1 // SPDX-License-Identifier: GPL-2.0-only <<
2 /* 1 /*
3 * C-Media CMI8788 driver - helper functions 2 * C-Media CMI8788 driver - helper functions
4 * 3 *
5 * Copyright (c) Clemens Ladisch <clemens@ladi 4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
>> 5 *
>> 6 *
>> 7 * This driver is free software; you can redistribute it and/or modify
>> 8 * it under the terms of the GNU General Public License, version 2.
>> 9 *
>> 10 * This driver is distributed in the hope that it will be useful,
>> 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 13 * GNU General Public License for more details.
>> 14 *
>> 15 * You should have received a copy of the GNU General Public License
>> 16 * along with this driver; if not, write to the Free Software
>> 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6 */ 18 */
7 19
8 #include <linux/delay.h> 20 #include <linux/delay.h>
9 #include <linux/sched.h> 21 #include <linux/sched.h>
10 #include <linux/export.h> 22 #include <linux/export.h>
11 #include <linux/io.h> 23 #include <linux/io.h>
12 #include <sound/core.h> 24 #include <sound/core.h>
13 #include <sound/mpu401.h> 25 #include <sound/mpu401.h>
14 #include "oxygen.h" 26 #include "oxygen.h"
15 27
16 u8 oxygen_read8(struct oxygen *chip, unsigned 28 u8 oxygen_read8(struct oxygen *chip, unsigned int reg)
17 { 29 {
18 return inb(chip->addr + reg); 30 return inb(chip->addr + reg);
19 } 31 }
20 EXPORT_SYMBOL(oxygen_read8); 32 EXPORT_SYMBOL(oxygen_read8);
21 33
22 u16 oxygen_read16(struct oxygen *chip, unsigne 34 u16 oxygen_read16(struct oxygen *chip, unsigned int reg)
23 { 35 {
24 return inw(chip->addr + reg); 36 return inw(chip->addr + reg);
25 } 37 }
26 EXPORT_SYMBOL(oxygen_read16); 38 EXPORT_SYMBOL(oxygen_read16);
27 39
28 u32 oxygen_read32(struct oxygen *chip, unsigne 40 u32 oxygen_read32(struct oxygen *chip, unsigned int reg)
29 { 41 {
30 return inl(chip->addr + reg); 42 return inl(chip->addr + reg);
31 } 43 }
32 EXPORT_SYMBOL(oxygen_read32); 44 EXPORT_SYMBOL(oxygen_read32);
33 45
34 void oxygen_write8(struct oxygen *chip, unsign 46 void oxygen_write8(struct oxygen *chip, unsigned int reg, u8 value)
35 { 47 {
36 outb(value, chip->addr + reg); 48 outb(value, chip->addr + reg);
37 chip->saved_registers._8[reg] = value; 49 chip->saved_registers._8[reg] = value;
38 } 50 }
39 EXPORT_SYMBOL(oxygen_write8); 51 EXPORT_SYMBOL(oxygen_write8);
40 52
41 void oxygen_write16(struct oxygen *chip, unsig 53 void oxygen_write16(struct oxygen *chip, unsigned int reg, u16 value)
42 { 54 {
43 outw(value, chip->addr + reg); 55 outw(value, chip->addr + reg);
44 chip->saved_registers._16[reg / 2] = c 56 chip->saved_registers._16[reg / 2] = cpu_to_le16(value);
45 } 57 }
46 EXPORT_SYMBOL(oxygen_write16); 58 EXPORT_SYMBOL(oxygen_write16);
47 59
48 void oxygen_write32(struct oxygen *chip, unsig 60 void oxygen_write32(struct oxygen *chip, unsigned int reg, u32 value)
49 { 61 {
50 outl(value, chip->addr + reg); 62 outl(value, chip->addr + reg);
51 chip->saved_registers._32[reg / 4] = c 63 chip->saved_registers._32[reg / 4] = cpu_to_le32(value);
52 } 64 }
53 EXPORT_SYMBOL(oxygen_write32); 65 EXPORT_SYMBOL(oxygen_write32);
54 66
55 void oxygen_write8_masked(struct oxygen *chip, 67 void oxygen_write8_masked(struct oxygen *chip, unsigned int reg,
56 u8 value, u8 mask) 68 u8 value, u8 mask)
57 { 69 {
58 u8 tmp = inb(chip->addr + reg); 70 u8 tmp = inb(chip->addr + reg);
59 tmp &= ~mask; 71 tmp &= ~mask;
60 tmp |= value & mask; 72 tmp |= value & mask;
61 outb(tmp, chip->addr + reg); 73 outb(tmp, chip->addr + reg);
62 chip->saved_registers._8[reg] = tmp; 74 chip->saved_registers._8[reg] = tmp;
63 } 75 }
64 EXPORT_SYMBOL(oxygen_write8_masked); 76 EXPORT_SYMBOL(oxygen_write8_masked);
65 77
66 void oxygen_write16_masked(struct oxygen *chip 78 void oxygen_write16_masked(struct oxygen *chip, unsigned int reg,
67 u16 value, u16 mask 79 u16 value, u16 mask)
68 { 80 {
69 u16 tmp = inw(chip->addr + reg); 81 u16 tmp = inw(chip->addr + reg);
70 tmp &= ~mask; 82 tmp &= ~mask;
71 tmp |= value & mask; 83 tmp |= value & mask;
72 outw(tmp, chip->addr + reg); 84 outw(tmp, chip->addr + reg);
73 chip->saved_registers._16[reg / 2] = c 85 chip->saved_registers._16[reg / 2] = cpu_to_le16(tmp);
74 } 86 }
75 EXPORT_SYMBOL(oxygen_write16_masked); 87 EXPORT_SYMBOL(oxygen_write16_masked);
76 88
77 void oxygen_write32_masked(struct oxygen *chip 89 void oxygen_write32_masked(struct oxygen *chip, unsigned int reg,
78 u32 value, u32 mask 90 u32 value, u32 mask)
79 { 91 {
80 u32 tmp = inl(chip->addr + reg); 92 u32 tmp = inl(chip->addr + reg);
81 tmp &= ~mask; 93 tmp &= ~mask;
82 tmp |= value & mask; 94 tmp |= value & mask;
83 outl(tmp, chip->addr + reg); 95 outl(tmp, chip->addr + reg);
84 chip->saved_registers._32[reg / 4] = c 96 chip->saved_registers._32[reg / 4] = cpu_to_le32(tmp);
85 } 97 }
86 EXPORT_SYMBOL(oxygen_write32_masked); 98 EXPORT_SYMBOL(oxygen_write32_masked);
87 99
88 static int oxygen_ac97_wait(struct oxygen *chi 100 static int oxygen_ac97_wait(struct oxygen *chip, unsigned int mask)
89 { 101 {
90 u8 status = 0; 102 u8 status = 0;
91 103
92 /* 104 /*
93 * Reading the status register also cl 105 * Reading the status register also clears the bits, so we have to save
94 * the read bits in status. 106 * the read bits in status.
95 */ 107 */
96 wait_event_timeout(chip->ac97_waitqueu 108 wait_event_timeout(chip->ac97_waitqueue,
97 ({ status |= oxygen 109 ({ status |= oxygen_read8(chip, OXYGEN_AC97_INTERRUPT_STATUS);
98 status & mask; } 110 status & mask; }),
99 msecs_to_jiffies(1) 111 msecs_to_jiffies(1) + 1);
100 /* 112 /*
101 * Check even after a timeout because 113 * Check even after a timeout because this function should not require
102 * the AC'97 interrupt to be enabled. 114 * the AC'97 interrupt to be enabled.
103 */ 115 */
104 status |= oxygen_read8(chip, OXYGEN_AC 116 status |= oxygen_read8(chip, OXYGEN_AC97_INTERRUPT_STATUS);
105 return status & mask ? 0 : -EIO; 117 return status & mask ? 0 : -EIO;
106 } 118 }
107 119
108 /* 120 /*
109 * About 10% of AC'97 register reads or writes 121 * About 10% of AC'97 register reads or writes fail to complete, but even those
110 * where the controller indicates completion a 122 * where the controller indicates completion aren't guaranteed to have actually
111 * happened. 123 * happened.
112 * 124 *
113 * It's hard to assign blame to either the con 125 * It's hard to assign blame to either the controller or the codec because both
114 * were made by C-Media ... 126 * were made by C-Media ...
115 */ 127 */
116 128
117 void oxygen_write_ac97(struct oxygen *chip, un 129 void oxygen_write_ac97(struct oxygen *chip, unsigned int codec,
118 unsigned int index, u16 130 unsigned int index, u16 data)
119 { 131 {
120 unsigned int count, succeeded; 132 unsigned int count, succeeded;
121 u32 reg; 133 u32 reg;
122 134
123 reg = data; 135 reg = data;
124 reg |= index << OXYGEN_AC97_REG_ADDR_S 136 reg |= index << OXYGEN_AC97_REG_ADDR_SHIFT;
125 reg |= OXYGEN_AC97_REG_DIR_WRITE; 137 reg |= OXYGEN_AC97_REG_DIR_WRITE;
126 reg |= codec << OXYGEN_AC97_REG_CODEC_ 138 reg |= codec << OXYGEN_AC97_REG_CODEC_SHIFT;
127 succeeded = 0; 139 succeeded = 0;
128 for (count = 5; count > 0; --count) { 140 for (count = 5; count > 0; --count) {
129 udelay(5); 141 udelay(5);
130 oxygen_write32(chip, OXYGEN_AC 142 oxygen_write32(chip, OXYGEN_AC97_REGS, reg);
131 /* require two "completed" wri 143 /* require two "completed" writes, just to be sure */
132 if (oxygen_ac97_wait(chip, OXY 144 if (oxygen_ac97_wait(chip, OXYGEN_AC97_INT_WRITE_DONE) >= 0 &&
133 ++succeeded >= 2) { 145 ++succeeded >= 2) {
134 chip->saved_ac97_regis 146 chip->saved_ac97_registers[codec][index / 2] = data;
135 return; 147 return;
136 } 148 }
137 } 149 }
138 dev_err(chip->card->dev, "AC'97 write 150 dev_err(chip->card->dev, "AC'97 write timeout\n");
139 } 151 }
140 EXPORT_SYMBOL(oxygen_write_ac97); 152 EXPORT_SYMBOL(oxygen_write_ac97);
141 153
142 u16 oxygen_read_ac97(struct oxygen *chip, unsi 154 u16 oxygen_read_ac97(struct oxygen *chip, unsigned int codec,
143 unsigned int index) 155 unsigned int index)
144 { 156 {
145 unsigned int count; 157 unsigned int count;
146 unsigned int last_read = UINT_MAX; 158 unsigned int last_read = UINT_MAX;
147 u32 reg; 159 u32 reg;
148 160
149 reg = index << OXYGEN_AC97_REG_ADDR_SH 161 reg = index << OXYGEN_AC97_REG_ADDR_SHIFT;
150 reg |= OXYGEN_AC97_REG_DIR_READ; 162 reg |= OXYGEN_AC97_REG_DIR_READ;
151 reg |= codec << OXYGEN_AC97_REG_CODEC_ 163 reg |= codec << OXYGEN_AC97_REG_CODEC_SHIFT;
152 for (count = 5; count > 0; --count) { 164 for (count = 5; count > 0; --count) {
153 udelay(5); 165 udelay(5);
154 oxygen_write32(chip, OXYGEN_AC 166 oxygen_write32(chip, OXYGEN_AC97_REGS, reg);
155 udelay(10); 167 udelay(10);
156 if (oxygen_ac97_wait(chip, OXY 168 if (oxygen_ac97_wait(chip, OXYGEN_AC97_INT_READ_DONE) >= 0) {
157 u16 value = oxygen_rea 169 u16 value = oxygen_read16(chip, OXYGEN_AC97_REGS);
158 /* we require two cons 170 /* we require two consecutive reads of the same value */
159 if (value == last_read 171 if (value == last_read)
160 return value; 172 return value;
161 last_read = value; 173 last_read = value;
162 /* 174 /*
163 * Invert the register 175 * Invert the register value bits to make sure that two
164 * consecutive unsucce 176 * consecutive unsuccessful reads do not return the same
165 * value. 177 * value.
166 */ 178 */
167 reg ^= 0xffff; 179 reg ^= 0xffff;
168 } 180 }
169 } 181 }
170 dev_err(chip->card->dev, "AC'97 read t 182 dev_err(chip->card->dev, "AC'97 read timeout on codec %u\n", codec);
171 return 0; 183 return 0;
172 } 184 }
173 EXPORT_SYMBOL(oxygen_read_ac97); 185 EXPORT_SYMBOL(oxygen_read_ac97);
174 186
175 void oxygen_write_ac97_masked(struct oxygen *c 187 void oxygen_write_ac97_masked(struct oxygen *chip, unsigned int codec,
176 unsigned int ind 188 unsigned int index, u16 data, u16 mask)
177 { 189 {
178 u16 value = oxygen_read_ac97(chip, cod 190 u16 value = oxygen_read_ac97(chip, codec, index);
179 value &= ~mask; 191 value &= ~mask;
180 value |= data & mask; 192 value |= data & mask;
181 oxygen_write_ac97(chip, codec, index, 193 oxygen_write_ac97(chip, codec, index, value);
182 } 194 }
183 EXPORT_SYMBOL(oxygen_write_ac97_masked); 195 EXPORT_SYMBOL(oxygen_write_ac97_masked);
184 196
185 static int oxygen_wait_spi(struct oxygen *chip 197 static int oxygen_wait_spi(struct oxygen *chip)
186 { 198 {
187 unsigned int count; 199 unsigned int count;
188 200
189 /* 201 /*
190 * Higher timeout to be sure: 200 us; 202 * Higher timeout to be sure: 200 us;
191 * actual transaction should not need 203 * actual transaction should not need more than 40 us.
192 */ 204 */
193 for (count = 50; count > 0; count--) { 205 for (count = 50; count > 0; count--) {
194 udelay(4); 206 udelay(4);
195 if ((oxygen_read8(chip, OXYGEN 207 if ((oxygen_read8(chip, OXYGEN_SPI_CONTROL) &
196 208 OXYGEN_SPI_BUSY) == 0)
197 return 0; 209 return 0;
198 } 210 }
199 dev_err(chip->card->dev, "oxygen: SPI 211 dev_err(chip->card->dev, "oxygen: SPI wait timeout\n");
200 return -EIO; 212 return -EIO;
201 } 213 }
202 214
203 int oxygen_write_spi(struct oxygen *chip, u8 c 215 int oxygen_write_spi(struct oxygen *chip, u8 control, unsigned int data)
204 { 216 {
205 /* 217 /*
206 * We need to wait AFTER initiating th 218 * We need to wait AFTER initiating the SPI transaction,
207 * otherwise read operations will not 219 * otherwise read operations will not work.
208 */ 220 */
209 oxygen_write8(chip, OXYGEN_SPI_DATA1, 221 oxygen_write8(chip, OXYGEN_SPI_DATA1, data);
210 oxygen_write8(chip, OXYGEN_SPI_DATA2, 222 oxygen_write8(chip, OXYGEN_SPI_DATA2, data >> 8);
211 if (control & OXYGEN_SPI_DATA_LENGTH_3 223 if (control & OXYGEN_SPI_DATA_LENGTH_3)
212 oxygen_write8(chip, OXYGEN_SPI 224 oxygen_write8(chip, OXYGEN_SPI_DATA3, data >> 16);
213 oxygen_write8(chip, OXYGEN_SPI_CONTROL 225 oxygen_write8(chip, OXYGEN_SPI_CONTROL, control);
214 return oxygen_wait_spi(chip); 226 return oxygen_wait_spi(chip);
215 } 227 }
216 EXPORT_SYMBOL(oxygen_write_spi); 228 EXPORT_SYMBOL(oxygen_write_spi);
217 229
218 void oxygen_write_i2c(struct oxygen *chip, u8 230 void oxygen_write_i2c(struct oxygen *chip, u8 device, u8 map, u8 data)
219 { 231 {
220 /* should not need more than about 300 232 /* should not need more than about 300 us */
221 msleep(1); 233 msleep(1);
222 234
223 oxygen_write8(chip, OXYGEN_2WIRE_MAP, 235 oxygen_write8(chip, OXYGEN_2WIRE_MAP, map);
224 oxygen_write8(chip, OXYGEN_2WIRE_DATA, 236 oxygen_write8(chip, OXYGEN_2WIRE_DATA, data);
225 oxygen_write8(chip, OXYGEN_2WIRE_CONTR 237 oxygen_write8(chip, OXYGEN_2WIRE_CONTROL,
226 device | OXYGEN_2WIRE_DI 238 device | OXYGEN_2WIRE_DIR_WRITE);
227 } 239 }
228 EXPORT_SYMBOL(oxygen_write_i2c); 240 EXPORT_SYMBOL(oxygen_write_i2c);
229 241
230 static void _write_uart(struct oxygen *chip, u 242 static void _write_uart(struct oxygen *chip, unsigned int port, u8 data)
231 { 243 {
232 if (oxygen_read8(chip, OXYGEN_MPU401 + 244 if (oxygen_read8(chip, OXYGEN_MPU401 + 1) & MPU401_TX_FULL)
233 msleep(1); 245 msleep(1);
234 oxygen_write8(chip, OXYGEN_MPU401 + po 246 oxygen_write8(chip, OXYGEN_MPU401 + port, data);
235 } 247 }
236 248
237 void oxygen_reset_uart(struct oxygen *chip) 249 void oxygen_reset_uart(struct oxygen *chip)
238 { 250 {
239 _write_uart(chip, 1, MPU401_RESET); 251 _write_uart(chip, 1, MPU401_RESET);
240 msleep(1); /* wait for ACK */ 252 msleep(1); /* wait for ACK */
241 _write_uart(chip, 1, MPU401_ENTER_UART 253 _write_uart(chip, 1, MPU401_ENTER_UART);
242 } 254 }
243 EXPORT_SYMBOL(oxygen_reset_uart); 255 EXPORT_SYMBOL(oxygen_reset_uart);
244 256
245 void oxygen_write_uart(struct oxygen *chip, u8 257 void oxygen_write_uart(struct oxygen *chip, u8 data)
246 { 258 {
247 _write_uart(chip, 0, data); 259 _write_uart(chip, 0, data);
248 } 260 }
249 EXPORT_SYMBOL(oxygen_write_uart); 261 EXPORT_SYMBOL(oxygen_write_uart);
250 262
251 u16 oxygen_read_eeprom(struct oxygen *chip, un 263 u16 oxygen_read_eeprom(struct oxygen *chip, unsigned int index)
252 { 264 {
253 unsigned int timeout; 265 unsigned int timeout;
254 266
255 oxygen_write8(chip, OXYGEN_EEPROM_CONT 267 oxygen_write8(chip, OXYGEN_EEPROM_CONTROL,
256 index | OXYGEN_EEPROM_DI 268 index | OXYGEN_EEPROM_DIR_READ);
257 for (timeout = 0; timeout < 100; ++tim 269 for (timeout = 0; timeout < 100; ++timeout) {
258 udelay(1); 270 udelay(1);
259 if (!(oxygen_read8(chip, OXYGE 271 if (!(oxygen_read8(chip, OXYGEN_EEPROM_STATUS)
260 & OXYGEN_EEPROM_BUSY)) 272 & OXYGEN_EEPROM_BUSY))
261 break; 273 break;
262 } 274 }
263 return oxygen_read16(chip, OXYGEN_EEPR 275 return oxygen_read16(chip, OXYGEN_EEPROM_DATA);
264 } 276 }
265 277
266 void oxygen_write_eeprom(struct oxygen *chip, 278 void oxygen_write_eeprom(struct oxygen *chip, unsigned int index, u16 value)
267 { 279 {
268 unsigned int timeout; 280 unsigned int timeout;
269 281
270 oxygen_write16(chip, OXYGEN_EEPROM_DAT 282 oxygen_write16(chip, OXYGEN_EEPROM_DATA, value);
271 oxygen_write8(chip, OXYGEN_EEPROM_CONT 283 oxygen_write8(chip, OXYGEN_EEPROM_CONTROL,
272 index | OXYGEN_EEPROM_DI 284 index | OXYGEN_EEPROM_DIR_WRITE);
273 for (timeout = 0; timeout < 10; ++time 285 for (timeout = 0; timeout < 10; ++timeout) {
274 msleep(1); 286 msleep(1);
275 if (!(oxygen_read8(chip, OXYGE 287 if (!(oxygen_read8(chip, OXYGEN_EEPROM_STATUS)
276 & OXYGEN_EEPROM_BUSY)) 288 & OXYGEN_EEPROM_BUSY))
277 return; 289 return;
278 } 290 }
279 dev_err(chip->card->dev, "EEPROM write 291 dev_err(chip->card->dev, "EEPROM write timeout\n");
280 } 292 }
281 293
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