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Linux/sound/pci/oxygen/wm8785.h

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Diff markup

Differences between /sound/pci/oxygen/wm8785.h (Version linux-6.12-rc7) and /sound/pci/oxygen/wm8785.h (Version linux-4.13.16)


  1 /* SPDX-License-Identifier: GPL-2.0 */         << 
  2 #ifndef WM8785_H_INCLUDED                           1 #ifndef WM8785_H_INCLUDED
  3 #define WM8785_H_INCLUDED                           2 #define WM8785_H_INCLUDED
  4                                                     3 
  5 #define WM8785_R0       0                           4 #define WM8785_R0       0
  6 #define WM8785_R1       1                           5 #define WM8785_R1       1
  7 #define WM8785_R2       2                           6 #define WM8785_R2       2
  8 #define WM8785_R7       7                           7 #define WM8785_R7       7
  9                                                     8 
 10 /* R0 */                                            9 /* R0 */
 11 #define WM8785_MCR_MASK         0x007              10 #define WM8785_MCR_MASK         0x007
 12 #define WM8785_MCR_SLAVE        0x000              11 #define WM8785_MCR_SLAVE        0x000
 13 #define WM8785_MCR_MASTER_128   0x001              12 #define WM8785_MCR_MASTER_128   0x001
 14 #define WM8785_MCR_MASTER_192   0x002              13 #define WM8785_MCR_MASTER_192   0x002
 15 #define WM8785_MCR_MASTER_256   0x003              14 #define WM8785_MCR_MASTER_256   0x003
 16 #define WM8785_MCR_MASTER_384   0x004              15 #define WM8785_MCR_MASTER_384   0x004
 17 #define WM8785_MCR_MASTER_512   0x005              16 #define WM8785_MCR_MASTER_512   0x005
 18 #define WM8785_MCR_MASTER_768   0x006              17 #define WM8785_MCR_MASTER_768   0x006
 19 #define WM8785_OSR_MASK         0x018              18 #define WM8785_OSR_MASK         0x018
 20 #define WM8785_OSR_SINGLE       0x000              19 #define WM8785_OSR_SINGLE       0x000
 21 #define WM8785_OSR_DOUBLE       0x008              20 #define WM8785_OSR_DOUBLE       0x008
 22 #define WM8785_OSR_QUAD         0x010              21 #define WM8785_OSR_QUAD         0x010
 23 #define WM8785_FORMAT_MASK      0x060              22 #define WM8785_FORMAT_MASK      0x060
 24 #define WM8785_FORMAT_RJUST     0x000              23 #define WM8785_FORMAT_RJUST     0x000
 25 #define WM8785_FORMAT_LJUST     0x020              24 #define WM8785_FORMAT_LJUST     0x020
 26 #define WM8785_FORMAT_I2S       0x040              25 #define WM8785_FORMAT_I2S       0x040
 27 #define WM8785_FORMAT_DSP       0x060              26 #define WM8785_FORMAT_DSP       0x060
 28 /* R1 */                                           27 /* R1 */
 29 #define WM8785_WL_MASK          0x003              28 #define WM8785_WL_MASK          0x003
 30 #define WM8785_WL_16            0x000              29 #define WM8785_WL_16            0x000
 31 #define WM8785_WL_20            0x001              30 #define WM8785_WL_20            0x001
 32 #define WM8785_WL_24            0x002              31 #define WM8785_WL_24            0x002
 33 #define WM8785_WL_32            0x003              32 #define WM8785_WL_32            0x003
 34 #define WM8785_LRP              0x004              33 #define WM8785_LRP              0x004
 35 #define WM8785_BCLKINV          0x008              34 #define WM8785_BCLKINV          0x008
 36 #define WM8785_LRSWAP           0x010              35 #define WM8785_LRSWAP           0x010
 37 #define WM8785_DEVNO_MASK       0x0e0              36 #define WM8785_DEVNO_MASK       0x0e0
 38 /* R2 */                                           37 /* R2 */
 39 #define WM8785_HPFR             0x001              38 #define WM8785_HPFR             0x001
 40 #define WM8785_HPFL             0x002              39 #define WM8785_HPFL             0x002
 41 #define WM8785_SDODIS           0x004              40 #define WM8785_SDODIS           0x004
 42 #define WM8785_PWRDNR           0x008              41 #define WM8785_PWRDNR           0x008
 43 #define WM8785_PWRDNL           0x010              42 #define WM8785_PWRDNL           0x010
 44 #define WM8785_TDM_MASK         0x1c0              43 #define WM8785_TDM_MASK         0x1c0
 45                                                    44 
 46 #endif                                             45 #endif
 47                                                    46 

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