1 /* SPDX-License-Identifier: GPL-2.0+ */ 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* 2 /*
3 * AMD ALSA SoC PCM Driver 3 * AMD ALSA SoC PCM Driver
4 * 4 *
5 * Copyright (C) 2021 Advanced Micro Devices, 5 * Copyright (C) 2021 Advanced Micro Devices, Inc. All rights reserved.
6 */ 6 */
7 7
8 #include "vg_chip_offset_byte.h" 8 #include "vg_chip_offset_byte.h"
9 #include <sound/pcm.h> 9 #include <sound/pcm.h>
10 10
11 #define ACP5x_PHY_BASE_ADDRESS 0x1240000 11 #define ACP5x_PHY_BASE_ADDRESS 0x1240000
12 #define ACP_DEVICE_ID 0x15E2 12 #define ACP_DEVICE_ID 0x15E2
13 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 13 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001
14 14
15 #define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01 15 #define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01
16 #define ACP_PGFSM_CNTL_POWER_OFF_MASK 0x00 16 #define ACP_PGFSM_CNTL_POWER_OFF_MASK 0x00
17 #define ACP_PGFSM_STATUS_MASK 0x03 17 #define ACP_PGFSM_STATUS_MASK 0x03
18 #define ACP_POWERED_ON 0x00 18 #define ACP_POWERED_ON 0x00
19 #define ACP_POWER_ON_IN_PROGRESS 0x01 19 #define ACP_POWER_ON_IN_PROGRESS 0x01
20 #define ACP_POWERED_OFF 0x02 20 #define ACP_POWERED_OFF 0x02
21 #define ACP_POWER_OFF_IN_PROGRESS 0x03 21 #define ACP_POWER_OFF_IN_PROGRESS 0x03
22 22
23 #define ACP_ERR_INTR_MASK 0x20000000 23 #define ACP_ERR_INTR_MASK 0x20000000
24 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFF 24 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
25 25
26 #define ACP5x_DEVS 4 26 #define ACP5x_DEVS 4
27 #define ACP5x_REG_START 0x1240000 27 #define ACP5x_REG_START 0x1240000
28 #define ACP5x_REG_END 0x1250200 28 #define ACP5x_REG_END 0x1250200
29 #define ACP5x_I2STDM_REG_START 0x1242400 29 #define ACP5x_I2STDM_REG_START 0x1242400
30 #define ACP5x_I2STDM_REG_END 0x1242410 30 #define ACP5x_I2STDM_REG_END 0x1242410
31 #define ACP5x_HS_TDM_REG_START 0x1242814 31 #define ACP5x_HS_TDM_REG_START 0x1242814
32 #define ACP5x_HS_TDM_REG_END 0x1242824 32 #define ACP5x_HS_TDM_REG_END 0x1242824
33 #define I2S_MODE 0 33 #define I2S_MODE 0
34 #define ACP5x_I2S_MODE 1 34 #define ACP5x_I2S_MODE 1
35 #define ACP5x_RES 4 35 #define ACP5x_RES 4
36 #define I2S_RX_THRESHOLD 27 36 #define I2S_RX_THRESHOLD 27
37 #define I2S_TX_THRESHOLD 28 37 #define I2S_TX_THRESHOLD 28
38 #define HS_TX_THRESHOLD 24 38 #define HS_TX_THRESHOLD 24
39 #define HS_RX_THRESHOLD 23 39 #define HS_RX_THRESHOLD 23
40 40
41 #define I2S_SP_INSTANCE 1 41 #define I2S_SP_INSTANCE 1
42 #define I2S_HS_INSTANCE 2 42 #define I2S_HS_INSTANCE 2
43 43
44 #define ACP_SRAM_PTE_OFFSET 0x02050000 44 #define ACP_SRAM_PTE_OFFSET 0x02050000
45 #define ACP_SRAM_SP_PB_PTE_OFFSET 0x0 45 #define ACP_SRAM_SP_PB_PTE_OFFSET 0x0
46 #define ACP_SRAM_SP_CP_PTE_OFFSET 0x100 46 #define ACP_SRAM_SP_CP_PTE_OFFSET 0x100
47 #define ACP_SRAM_HS_PB_PTE_OFFSET 0x200 47 #define ACP_SRAM_HS_PB_PTE_OFFSET 0x200
48 #define ACP_SRAM_HS_CP_PTE_OFFSET 0x300 48 #define ACP_SRAM_HS_CP_PTE_OFFSET 0x300
49 #define PAGE_SIZE_4K_ENABLE 0x2 49 #define PAGE_SIZE_4K_ENABLE 0x2
50 #define I2S_SP_TX_MEM_WINDOW_START 0x4000 50 #define I2S_SP_TX_MEM_WINDOW_START 0x4000000
51 #define I2S_SP_RX_MEM_WINDOW_START 0x4020 51 #define I2S_SP_RX_MEM_WINDOW_START 0x4020000
52 #define I2S_HS_TX_MEM_WINDOW_START 0x4040 52 #define I2S_HS_TX_MEM_WINDOW_START 0x4040000
53 #define I2S_HS_RX_MEM_WINDOW_START 0x4060 53 #define I2S_HS_RX_MEM_WINDOW_START 0x4060000
54 54
55 #define SP_PB_FIFO_ADDR_OFFSET 0x500 55 #define SP_PB_FIFO_ADDR_OFFSET 0x500
56 #define SP_CAPT_FIFO_ADDR_OFFSET 0x700 56 #define SP_CAPT_FIFO_ADDR_OFFSET 0x700
57 #define HS_PB_FIFO_ADDR_OFFSET 0x900 57 #define HS_PB_FIFO_ADDR_OFFSET 0x900
58 #define HS_CAPT_FIFO_ADDR_OFFSET 0xB00 58 #define HS_CAPT_FIFO_ADDR_OFFSET 0xB00
59 #define PLAYBACK_MIN_NUM_PERIODS 2 59 #define PLAYBACK_MIN_NUM_PERIODS 2
60 #define PLAYBACK_MAX_NUM_PERIODS 8 60 #define PLAYBACK_MAX_NUM_PERIODS 8
61 #define PLAYBACK_MAX_PERIOD_SIZE 8192 61 #define PLAYBACK_MAX_PERIOD_SIZE 8192
62 #define PLAYBACK_MIN_PERIOD_SIZE 1024 62 #define PLAYBACK_MIN_PERIOD_SIZE 1024
63 #define CAPTURE_MIN_NUM_PERIODS 2 63 #define CAPTURE_MIN_NUM_PERIODS 2
64 #define CAPTURE_MAX_NUM_PERIODS 8 64 #define CAPTURE_MAX_NUM_PERIODS 8
65 #define CAPTURE_MAX_PERIOD_SIZE 8192 65 #define CAPTURE_MAX_PERIOD_SIZE 8192
66 #define CAPTURE_MIN_PERIOD_SIZE 1024 66 #define CAPTURE_MIN_PERIOD_SIZE 1024
67 67
68 #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * 68 #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
69 #define MIN_BUFFER MAX_BUFFER 69 #define MIN_BUFFER MAX_BUFFER
70 #define FIFO_SIZE 0x100 70 #define FIFO_SIZE 0x100
71 #define DMA_SIZE 0x40 71 #define DMA_SIZE 0x40
72 #define FRM_LEN 0x100 72 #define FRM_LEN 0x100
73 73
74 #define I2S_MASTER_MODE_ENABLE 1 74 #define I2S_MASTER_MODE_ENABLE 1
75 #define I2S_MASTER_MODE_DISABLE 0 75 #define I2S_MASTER_MODE_DISABLE 0
76 76
77 #define SLOT_WIDTH_8 8 77 #define SLOT_WIDTH_8 8
78 #define SLOT_WIDTH_16 16 78 #define SLOT_WIDTH_16 16
79 #define SLOT_WIDTH_24 24 79 #define SLOT_WIDTH_24 24
80 #define SLOT_WIDTH_32 32 80 #define SLOT_WIDTH_32 32
81 #define TDM_ENABLE 1 81 #define TDM_ENABLE 1
82 #define TDM_DISABLE 0 82 #define TDM_DISABLE 0
83 #define ACP5x_ITER_IRER_SAMP_LEN_MASK 0x38 83 #define ACP5x_ITER_IRER_SAMP_LEN_MASK 0x38
84 84
85 struct i2s_dev_data { 85 struct i2s_dev_data {
86 bool tdm_mode; 86 bool tdm_mode;
87 bool master_mode; 87 bool master_mode;
88 int i2s_irq; 88 int i2s_irq;
89 u16 i2s_instance; 89 u16 i2s_instance;
90 u32 tdm_fmt; 90 u32 tdm_fmt;
91 void __iomem *acp5x_base; 91 void __iomem *acp5x_base;
92 struct snd_pcm_substream *play_stream; 92 struct snd_pcm_substream *play_stream;
93 struct snd_pcm_substream *capture_stre 93 struct snd_pcm_substream *capture_stream;
94 struct snd_pcm_substream *i2ssp_play_s 94 struct snd_pcm_substream *i2ssp_play_stream;
95 struct snd_pcm_substream *i2ssp_captur 95 struct snd_pcm_substream *i2ssp_capture_stream;
96 }; 96 };
97 97
98 struct i2s_stream_instance { 98 struct i2s_stream_instance {
99 u16 num_pages; 99 u16 num_pages;
100 u16 i2s_instance; 100 u16 i2s_instance;
101 u16 direction; 101 u16 direction;
102 u16 channels; 102 u16 channels;
103 u32 xfer_resolution; 103 u32 xfer_resolution;
104 u32 val; 104 u32 val;
105 dma_addr_t dma_addr; 105 dma_addr_t dma_addr;
106 u64 bytescount; 106 u64 bytescount;
107 void __iomem *acp5x_base; 107 void __iomem *acp5x_base;
108 u32 lrclk_div; 108 u32 lrclk_div;
109 u32 bclk_div; 109 u32 bclk_div;
110 }; 110 };
111 111
112 union acp_dma_count { 112 union acp_dma_count {
113 struct { 113 struct {
114 u32 low; 114 u32 low;
115 u32 high; 115 u32 high;
116 } bcount; 116 } bcount;
117 u64 bytescount; 117 u64 bytescount;
118 }; 118 };
119 119
120 struct acp5x_platform_info { 120 struct acp5x_platform_info {
121 u16 play_i2s_instance; 121 u16 play_i2s_instance;
122 u16 cap_i2s_instance; 122 u16 cap_i2s_instance;
123 }; 123 };
124 124
125 union acp_i2stdm_mstrclkgen { 125 union acp_i2stdm_mstrclkgen {
126 struct { 126 struct {
127 u32 i2stdm_master_mode : 1; 127 u32 i2stdm_master_mode : 1;
128 u32 i2stdm_format_mode : 1; 128 u32 i2stdm_format_mode : 1;
129 u32 i2stdm_lrclk_div_val : 9; 129 u32 i2stdm_lrclk_div_val : 9;
130 u32 i2stdm_bclk_div_val : 11; 130 u32 i2stdm_bclk_div_val : 11;
131 u32:10; 131 u32:10;
132 } bitfields, bits; 132 } bitfields, bits;
133 u32 u32_all; 133 u32 u32_all;
134 }; 134 };
135 135
136 /* common header file uses exact offset rather 136 /* common header file uses exact offset rather than relative
137 * offset which requires subtraction logic fro 137 * offset which requires subtraction logic from base_addr
138 * for accessing ACP5x MMIO space registers 138 * for accessing ACP5x MMIO space registers
139 */ 139 */
140 static inline u32 acp_readl(void __iomem *base 140 static inline u32 acp_readl(void __iomem *base_addr)
141 { 141 {
142 return readl(base_addr - ACP5x_PHY_BAS 142 return readl(base_addr - ACP5x_PHY_BASE_ADDRESS);
143 } 143 }
144 144
145 static inline void acp_writel(u32 val, void __ 145 static inline void acp_writel(u32 val, void __iomem *base_addr)
146 { 146 {
147 writel(val, base_addr - ACP5x_PHY_BASE 147 writel(val, base_addr - ACP5x_PHY_BASE_ADDRESS);
148 } 148 }
149 149
150 int snd_amd_acp_find_config(struct pci_dev *pc 150 int snd_amd_acp_find_config(struct pci_dev *pci);
151 151
152 static inline u64 acp_get_byte_count(struct i2 152 static inline u64 acp_get_byte_count(struct i2s_stream_instance *rtd,
153 int direc 153 int direction)
154 { 154 {
155 union acp_dma_count byte_count; 155 union acp_dma_count byte_count;
156 156
157 if (direction == SNDRV_PCM_STREAM_PLAY 157 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
158 switch (rtd->i2s_instance) { 158 switch (rtd->i2s_instance) {
159 case I2S_HS_INSTANCE: 159 case I2S_HS_INSTANCE:
160 byte_count.bcount.high 160 byte_count.bcount.high =
161 acp_readl(rtd- 161 acp_readl(rtd->acp5x_base +
162 ACP_ 162 ACP_HS_TX_LINEARPOSCNTR_HIGH);
163 byte_count.bcount.low 163 byte_count.bcount.low =
164 acp_readl(rtd- 164 acp_readl(rtd->acp5x_base +
165 ACP_ 165 ACP_HS_TX_LINEARPOSCNTR_LOW);
166 break; 166 break;
167 case I2S_SP_INSTANCE: 167 case I2S_SP_INSTANCE:
168 default: 168 default:
169 byte_count.bcount.high 169 byte_count.bcount.high =
170 acp_readl(rtd- 170 acp_readl(rtd->acp5x_base +
171 ACP_ 171 ACP_I2S_TX_LINEARPOSCNTR_HIGH);
172 byte_count.bcount.low 172 byte_count.bcount.low =
173 acp_readl(rtd- 173 acp_readl(rtd->acp5x_base +
174 ACP_ 174 ACP_I2S_TX_LINEARPOSCNTR_LOW);
175 } 175 }
176 } else { 176 } else {
177 switch (rtd->i2s_instance) { 177 switch (rtd->i2s_instance) {
178 case I2S_HS_INSTANCE: 178 case I2S_HS_INSTANCE:
179 byte_count.bcount.high 179 byte_count.bcount.high =
180 acp_readl(rtd- 180 acp_readl(rtd->acp5x_base +
181 ACP_ 181 ACP_HS_RX_LINEARPOSCNTR_HIGH);
182 byte_count.bcount.low 182 byte_count.bcount.low =
183 acp_readl(rtd- 183 acp_readl(rtd->acp5x_base +
184 ACP_ 184 ACP_HS_RX_LINEARPOSCNTR_LOW);
185 break; 185 break;
186 case I2S_SP_INSTANCE: 186 case I2S_SP_INSTANCE:
187 default: 187 default:
188 byte_count.bcount.high 188 byte_count.bcount.high =
189 acp_readl(rtd- 189 acp_readl(rtd->acp5x_base +
190 ACP_ 190 ACP_I2S_RX_LINEARPOSCNTR_HIGH);
191 byte_count.bcount.low 191 byte_count.bcount.low =
192 acp_readl(rtd- 192 acp_readl(rtd->acp5x_base +
193 ACP_ 193 ACP_I2S_RX_LINEARPOSCNTR_LOW);
194 } 194 }
195 } 195 }
196 return byte_count.bytescount; 196 return byte_count.bytescount;
197 } 197 }
198 198
199 static inline void acp5x_set_i2s_clk(struct i2 199 static inline void acp5x_set_i2s_clk(struct i2s_dev_data *adata,
200 struct i2 200 struct i2s_stream_instance *rtd)
201 { 201 {
202 union acp_i2stdm_mstrclkgen mclkgen; 202 union acp_i2stdm_mstrclkgen mclkgen;
203 u32 master_reg; 203 u32 master_reg;
204 204
205 switch (rtd->i2s_instance) { 205 switch (rtd->i2s_instance) {
206 case I2S_HS_INSTANCE: 206 case I2S_HS_INSTANCE:
207 master_reg = ACP_I2STDM2_MSTRC 207 master_reg = ACP_I2STDM2_MSTRCLKGEN;
208 break; 208 break;
209 case I2S_SP_INSTANCE: 209 case I2S_SP_INSTANCE:
210 default: 210 default:
211 master_reg = ACP_I2STDM0_MSTRC 211 master_reg = ACP_I2STDM0_MSTRCLKGEN;
212 break; 212 break;
213 } 213 }
214 214
215 mclkgen.bits.i2stdm_master_mode = 0x1; 215 mclkgen.bits.i2stdm_master_mode = 0x1;
216 if (adata->tdm_mode) 216 if (adata->tdm_mode)
217 mclkgen.bits.i2stdm_format_mod 217 mclkgen.bits.i2stdm_format_mode = 0x01;
218 else 218 else
219 mclkgen.bits.i2stdm_format_mod 219 mclkgen.bits.i2stdm_format_mode = 0x00;
220 220
221 mclkgen.bits.i2stdm_bclk_div_val = rtd 221 mclkgen.bits.i2stdm_bclk_div_val = rtd->bclk_div;
222 mclkgen.bits.i2stdm_lrclk_div_val = rt 222 mclkgen.bits.i2stdm_lrclk_div_val = rtd->lrclk_div;
223 acp_writel(mclkgen.u32_all, rtd->acp5x 223 acp_writel(mclkgen.u32_all, rtd->acp5x_base + master_reg);
224 } 224 }
225 225
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