1 /* SPDX-License-Identifier: GPL-2.0 */ << 2 #ifndef __ATMEL_PDMIC_H_ 1 #ifndef __ATMEL_PDMIC_H_ 3 #define __ATMEL_PDMIC_H_ 2 #define __ATMEL_PDMIC_H_ 4 3 5 #include <linux/bitops.h> 4 #include <linux/bitops.h> 6 5 7 #define PDMIC_CR 0x00000000 6 #define PDMIC_CR 0x00000000 8 7 9 #define PDMIC_CR_SWRST 0x1 8 #define PDMIC_CR_SWRST 0x1 10 #define PDMIC_CR_SWRST_MASK BIT(0) 9 #define PDMIC_CR_SWRST_MASK BIT(0) 11 #define PDMIC_CR_SWRST_SHIFT (0) 10 #define PDMIC_CR_SWRST_SHIFT (0) 12 11 13 #define PDMIC_CR_ENPDM_DIS 0x0 12 #define PDMIC_CR_ENPDM_DIS 0x0 14 #define PDMIC_CR_ENPDM_EN 0x1 13 #define PDMIC_CR_ENPDM_EN 0x1 15 #define PDMIC_CR_ENPDM_MASK BIT(4) 14 #define PDMIC_CR_ENPDM_MASK BIT(4) 16 #define PDMIC_CR_ENPDM_SHIFT (4) 15 #define PDMIC_CR_ENPDM_SHIFT (4) 17 16 18 #define PDMIC_MR 0x00000004 17 #define PDMIC_MR 0x00000004 19 18 20 #define PDMIC_MR_CLKS_PCK 0x0 19 #define PDMIC_MR_CLKS_PCK 0x0 21 #define PDMIC_MR_CLKS_GCK 0x1 20 #define PDMIC_MR_CLKS_GCK 0x1 22 #define PDMIC_MR_CLKS_MASK BIT(4) 21 #define PDMIC_MR_CLKS_MASK BIT(4) 23 #define PDMIC_MR_CLKS_SHIFT (4) 22 #define PDMIC_MR_CLKS_SHIFT (4) 24 23 25 #define PDMIC_MR_PRESCAL_MASK GENMASK(14, 8) 24 #define PDMIC_MR_PRESCAL_MASK GENMASK(14, 8) 26 #define PDMIC_MR_PRESCAL_SHIFT (8) 25 #define PDMIC_MR_PRESCAL_SHIFT (8) 27 26 28 #define PDMIC_CDR 0x00000014 27 #define PDMIC_CDR 0x00000014 29 28 30 #define PDMIC_IER 0x00000018 29 #define PDMIC_IER 0x00000018 31 #define PDMIC_IER_OVRE BIT(25 30 #define PDMIC_IER_OVRE BIT(25) 32 31 33 #define PDMIC_IDR 0x0000001c 32 #define PDMIC_IDR 0x0000001c 34 #define PDMIC_IDR_OVRE BIT(25 33 #define PDMIC_IDR_OVRE BIT(25) 35 34 36 #define PDMIC_IMR 0x00000020 35 #define PDMIC_IMR 0x00000020 37 36 38 #define PDMIC_ISR 0x00000024 37 #define PDMIC_ISR 0x00000024 39 #define PDMIC_ISR_OVRE BIT(25 38 #define PDMIC_ISR_OVRE BIT(25) 40 39 41 #define PDMIC_DSPR0 0x00000058 40 #define PDMIC_DSPR0 0x00000058 42 41 43 #define PDMIC_DSPR0_HPFBYP_DIS 0x1 42 #define PDMIC_DSPR0_HPFBYP_DIS 0x1 44 #define PDMIC_DSPR0_HPFBYP_EN 0x0 43 #define PDMIC_DSPR0_HPFBYP_EN 0x0 45 #define PDMIC_DSPR0_HPFBYP_MASK BIT(1) 44 #define PDMIC_DSPR0_HPFBYP_MASK BIT(1) 46 #define PDMIC_DSPR0_HPFBYP_SHIFT (1) 45 #define PDMIC_DSPR0_HPFBYP_SHIFT (1) 47 46 48 #define PDMIC_DSPR0_SINBYP_DIS 0x1 47 #define PDMIC_DSPR0_SINBYP_DIS 0x1 49 #define PDMIC_DSPR0_SINBYP_EN 0x0 48 #define PDMIC_DSPR0_SINBYP_EN 0x0 50 #define PDMIC_DSPR0_SINBYP_MASK BIT(2) 49 #define PDMIC_DSPR0_SINBYP_MASK BIT(2) 51 #define PDMIC_DSPR0_SINBYP_SHIFT (2) 50 #define PDMIC_DSPR0_SINBYP_SHIFT (2) 52 51 53 #define PDMIC_DSPR0_SIZE_16_BITS 0x0 52 #define PDMIC_DSPR0_SIZE_16_BITS 0x0 54 #define PDMIC_DSPR0_SIZE_32_BITS 0x1 53 #define PDMIC_DSPR0_SIZE_32_BITS 0x1 55 #define PDMIC_DSPR0_SIZE_MASK BIT(3) 54 #define PDMIC_DSPR0_SIZE_MASK BIT(3) 56 #define PDMIC_DSPR0_SIZE_SHIFT (3) 55 #define PDMIC_DSPR0_SIZE_SHIFT (3) 57 56 58 #define PDMIC_DSPR0_OSR_128 0x0 57 #define PDMIC_DSPR0_OSR_128 0x0 59 #define PDMIC_DSPR0_OSR_64 0x1 58 #define PDMIC_DSPR0_OSR_64 0x1 60 #define PDMIC_DSPR0_OSR_MASK GENMAS 59 #define PDMIC_DSPR0_OSR_MASK GENMASK(6, 4) 61 #define PDMIC_DSPR0_OSR_SHIFT (4) 60 #define PDMIC_DSPR0_OSR_SHIFT (4) 62 61 63 #define PDMIC_DSPR0_SCALE_MASK GENMAS 62 #define PDMIC_DSPR0_SCALE_MASK GENMASK(11, 8) 64 #define PDMIC_DSPR0_SCALE_SHIFT (8) 63 #define PDMIC_DSPR0_SCALE_SHIFT (8) 65 64 66 #define PDMIC_DSPR0_SHIFT_MASK GENMAS 65 #define PDMIC_DSPR0_SHIFT_MASK GENMASK(15, 12) 67 #define PDMIC_DSPR0_SHIFT_SHIFT (12) 66 #define PDMIC_DSPR0_SHIFT_SHIFT (12) 68 67 69 #define PDMIC_DSPR1 0x0000005c 68 #define PDMIC_DSPR1 0x0000005c 70 69 71 #define PDMIC_DSPR1_DGAIN_MASK GENMAS 70 #define PDMIC_DSPR1_DGAIN_MASK GENMASK(14, 0) 72 #define PDMIC_DSPR1_DGAIN_SHIFT (0) 71 #define PDMIC_DSPR1_DGAIN_SHIFT (0) 73 72 74 #define PDMIC_DSPR1_OFFSET_MASK GENMAS 73 #define PDMIC_DSPR1_OFFSET_MASK GENMASK(31, 16) 75 #define PDMIC_DSPR1_OFFSET_SHIFT (16) 74 #define PDMIC_DSPR1_OFFSET_SHIFT (16) 76 75 77 #define PDMIC_WPMR 0x000000e4 76 #define PDMIC_WPMR 0x000000e4 78 77 79 #define PDMIC_WPSR 0x000000e8 78 #define PDMIC_WPSR 0x000000e8 80 79 81 #endif 80 #endif 82 81
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