1 /* SPDX-License-Identifier: GPL-2.0-or-later * 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 2 /* 3 * File: sound/soc/codec/ad73311.h 3 * File: sound/soc/codec/ad73311.h 4 * Based on: 4 * Based on: 5 * Author: Cliff Cai <cliff.cai@analog.c 5 * Author: Cliff Cai <cliff.cai@analog.com> 6 * 6 * 7 * Created: Thur Sep 25, 2008 7 * Created: Thur Sep 25, 2008 8 * Description: definitions for AD73311 regis 8 * Description: definitions for AD73311 registers 9 * 9 * 10 * Modified: 10 * Modified: 11 * Copyright 2006 Analog Devices 11 * Copyright 2006 Analog Devices Inc. 12 * 12 * 13 * Bugs: Enter bugs at http://blackfin 13 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 14 */ 14 */ 15 15 16 #ifndef __AD73311_H__ 16 #ifndef __AD73311_H__ 17 #define __AD73311_H__ 17 #define __AD73311_H__ 18 18 19 #define AD_CONTROL 0x8000 19 #define AD_CONTROL 0x8000 20 #define AD_DATA 0x0000 20 #define AD_DATA 0x0000 21 #define AD_READ 0x4000 21 #define AD_READ 0x4000 22 #define AD_WRITE 0x0000 22 #define AD_WRITE 0x0000 23 23 24 /* Control register A */ 24 /* Control register A */ 25 #define CTRL_REG_A (0 << 8) 25 #define CTRL_REG_A (0 << 8) 26 26 27 #define REGA_MODE_PRO 0x00 27 #define REGA_MODE_PRO 0x00 28 #define REGA_MODE_DATA 0x01 28 #define REGA_MODE_DATA 0x01 29 #define REGA_MODE_MIXED 0x03 29 #define REGA_MODE_MIXED 0x03 30 #define REGA_DLB 0x04 30 #define REGA_DLB 0x04 31 #define REGA_SLB 0x08 31 #define REGA_SLB 0x08 32 #define REGA_DEVC(x) ((x & 0x7) << 32 #define REGA_DEVC(x) ((x & 0x7) << 4) 33 #define REGA_RESET 0x80 33 #define REGA_RESET 0x80 34 34 35 /* Control register B */ 35 /* Control register B */ 36 #define CTRL_REG_B (1 << 8) 36 #define CTRL_REG_B (1 << 8) 37 37 38 #define REGB_DIRATE(x) (x & 0x3) 38 #define REGB_DIRATE(x) (x & 0x3) 39 #define REGB_SCDIV(x) ((x & 0x3) << 2) 39 #define REGB_SCDIV(x) ((x & 0x3) << 2) 40 #define REGB_MCDIV(x) ((x & 0x7) << 4) 40 #define REGB_MCDIV(x) ((x & 0x7) << 4) 41 #define REGB_CEE (1 << 7) 41 #define REGB_CEE (1 << 7) 42 42 43 /* Control register C */ 43 /* Control register C */ 44 #define CTRL_REG_C (2 << 8) 44 #define CTRL_REG_C (2 << 8) 45 45 46 #define REGC_PUDEV (1 << 0) 46 #define REGC_PUDEV (1 << 0) 47 #define REGC_PUADC (1 << 3) 47 #define REGC_PUADC (1 << 3) 48 #define REGC_PUDAC (1 << 4) 48 #define REGC_PUDAC (1 << 4) 49 #define REGC_PUREF (1 << 5) 49 #define REGC_PUREF (1 << 5) 50 #define REGC_REFUSE (1 << 6) 50 #define REGC_REFUSE (1 << 6) 51 51 52 /* Control register D */ 52 /* Control register D */ 53 #define CTRL_REG_D (3 << 8) 53 #define CTRL_REG_D (3 << 8) 54 54 55 #define REGD_IGS(x) (x & 0x7) 55 #define REGD_IGS(x) (x & 0x7) 56 #define REGD_RMOD (1 << 3) 56 #define REGD_RMOD (1 << 3) 57 #define REGD_OGS(x) ((x & 0x7) << 57 #define REGD_OGS(x) ((x & 0x7) << 4) 58 #define REGD_MUTE (1 << 7) 58 #define REGD_MUTE (1 << 7) 59 59 60 /* Control register E */ 60 /* Control register E */ 61 #define CTRL_REG_E (4 << 8) 61 #define CTRL_REG_E (4 << 8) 62 62 63 #define REGE_DA(x) (x & 0x1f) 63 #define REGE_DA(x) (x & 0x1f) 64 #define REGE_IBYP (1 << 5) 64 #define REGE_IBYP (1 << 5) 65 65 66 /* Control register F */ 66 /* Control register F */ 67 #define CTRL_REG_F (5 << 8) 67 #define CTRL_REG_F (5 << 8) 68 68 69 #define REGF_SEEN (1 << 5) 69 #define REGF_SEEN (1 << 5) 70 #define REGF_INV (1 << 6) 70 #define REGF_INV (1 << 6) 71 #define REGF_ALB (1 << 7) 71 #define REGF_ALB (1 << 7) 72 72 73 #endif 73 #endif 74 74
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