1 // SPDX-License-Identifier: GPL-2.0-or-later 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* 2 /*
3 * ADAV80X Audio Codec driver supporting ADAV8 3 * ADAV80X Audio Codec driver supporting ADAV801, ADAV803
4 * 4 *
5 * Copyright 2011 Analog Devices Inc. 5 * Copyright 2011 Analog Devices Inc.
6 * Author: Yi Li <yi.li@analog.com> 6 * Author: Yi Li <yi.li@analog.com>
7 * Author: Lars-Peter Clausen <lars@metafoo.de 7 * Author: Lars-Peter Clausen <lars@metafoo.de>
8 */ 8 */
9 9
10 #include <linux/module.h> 10 #include <linux/module.h>
11 #include <linux/kernel.h> 11 #include <linux/kernel.h>
12 #include <linux/regmap.h> 12 #include <linux/regmap.h>
13 #include <linux/slab.h> 13 #include <linux/slab.h>
14 14
15 #include <sound/pcm.h> 15 #include <sound/pcm.h>
16 #include <sound/pcm_params.h> 16 #include <sound/pcm_params.h>
17 #include <sound/soc.h> 17 #include <sound/soc.h>
18 #include <sound/tlv.h> 18 #include <sound/tlv.h>
19 19
20 #include "adav80x.h" 20 #include "adav80x.h"
21 21
22 #define ADAV80X_PLAYBACK_CTRL 0x04 22 #define ADAV80X_PLAYBACK_CTRL 0x04
23 #define ADAV80X_AUX_IN_CTRL 0x05 23 #define ADAV80X_AUX_IN_CTRL 0x05
24 #define ADAV80X_REC_CTRL 0x06 24 #define ADAV80X_REC_CTRL 0x06
25 #define ADAV80X_AUX_OUT_CTRL 0x07 25 #define ADAV80X_AUX_OUT_CTRL 0x07
26 #define ADAV80X_DPATH_CTRL1 0x62 26 #define ADAV80X_DPATH_CTRL1 0x62
27 #define ADAV80X_DPATH_CTRL2 0x63 27 #define ADAV80X_DPATH_CTRL2 0x63
28 #define ADAV80X_DAC_CTRL1 0x64 28 #define ADAV80X_DAC_CTRL1 0x64
29 #define ADAV80X_DAC_CTRL2 0x65 29 #define ADAV80X_DAC_CTRL2 0x65
30 #define ADAV80X_DAC_CTRL3 0x66 30 #define ADAV80X_DAC_CTRL3 0x66
31 #define ADAV80X_DAC_L_VOL 0x68 31 #define ADAV80X_DAC_L_VOL 0x68
32 #define ADAV80X_DAC_R_VOL 0x69 32 #define ADAV80X_DAC_R_VOL 0x69
33 #define ADAV80X_PGA_L_VOL 0x6c 33 #define ADAV80X_PGA_L_VOL 0x6c
34 #define ADAV80X_PGA_R_VOL 0x6d 34 #define ADAV80X_PGA_R_VOL 0x6d
35 #define ADAV80X_ADC_CTRL1 0x6e 35 #define ADAV80X_ADC_CTRL1 0x6e
36 #define ADAV80X_ADC_CTRL2 0x6f 36 #define ADAV80X_ADC_CTRL2 0x6f
37 #define ADAV80X_ADC_L_VOL 0x70 37 #define ADAV80X_ADC_L_VOL 0x70
38 #define ADAV80X_ADC_R_VOL 0x71 38 #define ADAV80X_ADC_R_VOL 0x71
39 #define ADAV80X_PLL_CTRL1 0x74 39 #define ADAV80X_PLL_CTRL1 0x74
40 #define ADAV80X_PLL_CTRL2 0x75 40 #define ADAV80X_PLL_CTRL2 0x75
41 #define ADAV80X_ICLK_CTRL1 0x76 41 #define ADAV80X_ICLK_CTRL1 0x76
42 #define ADAV80X_ICLK_CTRL2 0x77 42 #define ADAV80X_ICLK_CTRL2 0x77
43 #define ADAV80X_PLL_CLK_SRC 0x78 43 #define ADAV80X_PLL_CLK_SRC 0x78
44 #define ADAV80X_PLL_OUTE 0x7a 44 #define ADAV80X_PLL_OUTE 0x7a
45 45
46 #define ADAV80X_PLL_CLK_SRC_PLL_XIN(pll) 46 #define ADAV80X_PLL_CLK_SRC_PLL_XIN(pll) 0x00
47 #define ADAV80X_PLL_CLK_SRC_PLL_MCLKI(pll) 47 #define ADAV80X_PLL_CLK_SRC_PLL_MCLKI(pll) (0x40 << (pll))
48 #define ADAV80X_PLL_CLK_SRC_PLL_MASK(pll) 48 #define ADAV80X_PLL_CLK_SRC_PLL_MASK(pll) (0x40 << (pll))
49 49
50 #define ADAV80X_ICLK_CTRL1_DAC_SRC(src) 50 #define ADAV80X_ICLK_CTRL1_DAC_SRC(src) ((src) << 5)
51 #define ADAV80X_ICLK_CTRL1_ADC_SRC(src) 51 #define ADAV80X_ICLK_CTRL1_ADC_SRC(src) ((src) << 2)
52 #define ADAV80X_ICLK_CTRL1_ICLK2_SRC(src) 52 #define ADAV80X_ICLK_CTRL1_ICLK2_SRC(src) (src)
53 #define ADAV80X_ICLK_CTRL2_ICLK1_SRC(src) 53 #define ADAV80X_ICLK_CTRL2_ICLK1_SRC(src) ((src) << 3)
54 54
55 #define ADAV80X_PLL_CTRL1_PLLDIV 55 #define ADAV80X_PLL_CTRL1_PLLDIV 0x10
56 #define ADAV80X_PLL_CTRL1_PLLPD(pll) 56 #define ADAV80X_PLL_CTRL1_PLLPD(pll) (0x04 << (pll))
57 #define ADAV80X_PLL_CTRL1_XTLPD 57 #define ADAV80X_PLL_CTRL1_XTLPD 0x02
58 58
59 #define ADAV80X_PLL_CTRL2_FIELD(pll, x) 59 #define ADAV80X_PLL_CTRL2_FIELD(pll, x) ((x) << ((pll) * 4))
60 60
61 #define ADAV80X_PLL_CTRL2_FS_48(pll) ADAV80 61 #define ADAV80X_PLL_CTRL2_FS_48(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x00)
62 #define ADAV80X_PLL_CTRL2_FS_32(pll) ADAV80 62 #define ADAV80X_PLL_CTRL2_FS_32(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x08)
63 #define ADAV80X_PLL_CTRL2_FS_44(pll) ADAV80 63 #define ADAV80X_PLL_CTRL2_FS_44(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x0c)
64 64
65 #define ADAV80X_PLL_CTRL2_SEL(pll) ADAV80 65 #define ADAV80X_PLL_CTRL2_SEL(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x02)
66 #define ADAV80X_PLL_CTRL2_DOUB(pll) ADAV80 66 #define ADAV80X_PLL_CTRL2_DOUB(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x01)
67 #define ADAV80X_PLL_CTRL2_PLL_MASK(pll) ADAV80 67 #define ADAV80X_PLL_CTRL2_PLL_MASK(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x0f)
68 68
69 #define ADAV80X_ADC_CTRL1_MODULATOR_MASK 69 #define ADAV80X_ADC_CTRL1_MODULATOR_MASK 0x80
70 #define ADAV80X_ADC_CTRL1_MODULATOR_128FS 70 #define ADAV80X_ADC_CTRL1_MODULATOR_128FS 0x00
71 #define ADAV80X_ADC_CTRL1_MODULATOR_64FS 71 #define ADAV80X_ADC_CTRL1_MODULATOR_64FS 0x80
72 72
73 #define ADAV80X_DAC_CTRL1_PD 73 #define ADAV80X_DAC_CTRL1_PD 0x80
74 74
75 #define ADAV80X_DAC_CTRL2_DIV1 75 #define ADAV80X_DAC_CTRL2_DIV1 0x00
76 #define ADAV80X_DAC_CTRL2_DIV1_5 76 #define ADAV80X_DAC_CTRL2_DIV1_5 0x10
77 #define ADAV80X_DAC_CTRL2_DIV2 77 #define ADAV80X_DAC_CTRL2_DIV2 0x20
78 #define ADAV80X_DAC_CTRL2_DIV3 78 #define ADAV80X_DAC_CTRL2_DIV3 0x30
79 #define ADAV80X_DAC_CTRL2_DIV_MASK 79 #define ADAV80X_DAC_CTRL2_DIV_MASK 0x30
80 80
81 #define ADAV80X_DAC_CTRL2_INTERPOL_256FS 81 #define ADAV80X_DAC_CTRL2_INTERPOL_256FS 0x00
82 #define ADAV80X_DAC_CTRL2_INTERPOL_128FS 82 #define ADAV80X_DAC_CTRL2_INTERPOL_128FS 0x40
83 #define ADAV80X_DAC_CTRL2_INTERPOL_64FS 83 #define ADAV80X_DAC_CTRL2_INTERPOL_64FS 0x80
84 #define ADAV80X_DAC_CTRL2_INTERPOL_MASK 84 #define ADAV80X_DAC_CTRL2_INTERPOL_MASK 0xc0
85 85
86 #define ADAV80X_DAC_CTRL2_DEEMPH_NONE 86 #define ADAV80X_DAC_CTRL2_DEEMPH_NONE 0x00
87 #define ADAV80X_DAC_CTRL2_DEEMPH_44 87 #define ADAV80X_DAC_CTRL2_DEEMPH_44 0x01
88 #define ADAV80X_DAC_CTRL2_DEEMPH_32 88 #define ADAV80X_DAC_CTRL2_DEEMPH_32 0x02
89 #define ADAV80X_DAC_CTRL2_DEEMPH_48 89 #define ADAV80X_DAC_CTRL2_DEEMPH_48 0x03
90 #define ADAV80X_DAC_CTRL2_DEEMPH_MASK 90 #define ADAV80X_DAC_CTRL2_DEEMPH_MASK 0x01
91 91
92 #define ADAV80X_CAPTURE_MODE_MASTER 92 #define ADAV80X_CAPTURE_MODE_MASTER 0x20
93 #define ADAV80X_CAPTURE_WORD_LEN24 93 #define ADAV80X_CAPTURE_WORD_LEN24 0x00
94 #define ADAV80X_CAPTURE_WORD_LEN20 94 #define ADAV80X_CAPTURE_WORD_LEN20 0x04
95 #define ADAV80X_CAPTRUE_WORD_LEN18 95 #define ADAV80X_CAPTRUE_WORD_LEN18 0x08
96 #define ADAV80X_CAPTURE_WORD_LEN16 96 #define ADAV80X_CAPTURE_WORD_LEN16 0x0c
97 #define ADAV80X_CAPTURE_WORD_LEN_MASK 97 #define ADAV80X_CAPTURE_WORD_LEN_MASK 0x0c
98 98
99 #define ADAV80X_CAPTURE_MODE_LEFT_J 99 #define ADAV80X_CAPTURE_MODE_LEFT_J 0x00
100 #define ADAV80X_CAPTURE_MODE_I2S 100 #define ADAV80X_CAPTURE_MODE_I2S 0x01
101 #define ADAV80X_CAPTURE_MODE_RIGHT_J 101 #define ADAV80X_CAPTURE_MODE_RIGHT_J 0x03
102 #define ADAV80X_CAPTURE_MODE_MASK 102 #define ADAV80X_CAPTURE_MODE_MASK 0x03
103 103
104 #define ADAV80X_PLAYBACK_MODE_MASTER 104 #define ADAV80X_PLAYBACK_MODE_MASTER 0x10
105 #define ADAV80X_PLAYBACK_MODE_LEFT_J 105 #define ADAV80X_PLAYBACK_MODE_LEFT_J 0x00
106 #define ADAV80X_PLAYBACK_MODE_I2S 106 #define ADAV80X_PLAYBACK_MODE_I2S 0x01
107 #define ADAV80X_PLAYBACK_MODE_RIGHT_J_24 107 #define ADAV80X_PLAYBACK_MODE_RIGHT_J_24 0x04
108 #define ADAV80X_PLAYBACK_MODE_RIGHT_J_20 108 #define ADAV80X_PLAYBACK_MODE_RIGHT_J_20 0x05
109 #define ADAV80X_PLAYBACK_MODE_RIGHT_J_18 109 #define ADAV80X_PLAYBACK_MODE_RIGHT_J_18 0x06
110 #define ADAV80X_PLAYBACK_MODE_RIGHT_J_16 110 #define ADAV80X_PLAYBACK_MODE_RIGHT_J_16 0x07
111 #define ADAV80X_PLAYBACK_MODE_MASK 111 #define ADAV80X_PLAYBACK_MODE_MASK 0x07
112 112
113 #define ADAV80X_PLL_OUTE_SYSCLKPD(x) 113 #define ADAV80X_PLL_OUTE_SYSCLKPD(x) BIT(2 - (x))
114 114
115 static const struct reg_default adav80x_reg_de 115 static const struct reg_default adav80x_reg_defaults[] = {
116 { ADAV80X_PLAYBACK_CTRL, 0x01 } 116 { ADAV80X_PLAYBACK_CTRL, 0x01 },
117 { ADAV80X_AUX_IN_CTRL, 0x01 } 117 { ADAV80X_AUX_IN_CTRL, 0x01 },
118 { ADAV80X_REC_CTRL, 0x02 } 118 { ADAV80X_REC_CTRL, 0x02 },
119 { ADAV80X_AUX_OUT_CTRL, 0x01 } 119 { ADAV80X_AUX_OUT_CTRL, 0x01 },
120 { ADAV80X_DPATH_CTRL1, 0xc0 } 120 { ADAV80X_DPATH_CTRL1, 0xc0 },
121 { ADAV80X_DPATH_CTRL2, 0x11 } 121 { ADAV80X_DPATH_CTRL2, 0x11 },
122 { ADAV80X_DAC_CTRL1, 0x00 } 122 { ADAV80X_DAC_CTRL1, 0x00 },
123 { ADAV80X_DAC_CTRL2, 0x00 } 123 { ADAV80X_DAC_CTRL2, 0x00 },
124 { ADAV80X_DAC_CTRL3, 0x00 } 124 { ADAV80X_DAC_CTRL3, 0x00 },
125 { ADAV80X_DAC_L_VOL, 0xff } 125 { ADAV80X_DAC_L_VOL, 0xff },
126 { ADAV80X_DAC_R_VOL, 0xff } 126 { ADAV80X_DAC_R_VOL, 0xff },
127 { ADAV80X_PGA_L_VOL, 0x00 } 127 { ADAV80X_PGA_L_VOL, 0x00 },
128 { ADAV80X_PGA_R_VOL, 0x00 } 128 { ADAV80X_PGA_R_VOL, 0x00 },
129 { ADAV80X_ADC_CTRL1, 0x00 } 129 { ADAV80X_ADC_CTRL1, 0x00 },
130 { ADAV80X_ADC_CTRL2, 0x00 } 130 { ADAV80X_ADC_CTRL2, 0x00 },
131 { ADAV80X_ADC_L_VOL, 0xff } 131 { ADAV80X_ADC_L_VOL, 0xff },
132 { ADAV80X_ADC_R_VOL, 0xff } 132 { ADAV80X_ADC_R_VOL, 0xff },
133 { ADAV80X_PLL_CTRL1, 0x00 } 133 { ADAV80X_PLL_CTRL1, 0x00 },
134 { ADAV80X_PLL_CTRL2, 0x00 } 134 { ADAV80X_PLL_CTRL2, 0x00 },
135 { ADAV80X_ICLK_CTRL1, 0x00 } 135 { ADAV80X_ICLK_CTRL1, 0x00 },
136 { ADAV80X_ICLK_CTRL2, 0x00 } 136 { ADAV80X_ICLK_CTRL2, 0x00 },
137 { ADAV80X_PLL_CLK_SRC, 0x00 } 137 { ADAV80X_PLL_CLK_SRC, 0x00 },
138 { ADAV80X_PLL_OUTE, 0x00 } 138 { ADAV80X_PLL_OUTE, 0x00 },
139 }; 139 };
140 140
141 struct adav80x { 141 struct adav80x {
142 struct regmap *regmap; 142 struct regmap *regmap;
143 143
144 enum adav80x_clk_src clk_src; 144 enum adav80x_clk_src clk_src;
145 unsigned int sysclk; 145 unsigned int sysclk;
146 enum adav80x_pll_src pll_src; 146 enum adav80x_pll_src pll_src;
147 147
148 unsigned int dai_fmt[2]; 148 unsigned int dai_fmt[2];
149 unsigned int rate; 149 unsigned int rate;
150 bool deemph; 150 bool deemph;
151 bool sysclk_pd[3]; 151 bool sysclk_pd[3];
152 }; 152 };
153 153
154 static const char *adav80x_mux_text[] = { 154 static const char *adav80x_mux_text[] = {
155 "ADC", 155 "ADC",
156 "Playback", 156 "Playback",
157 "Aux Playback", 157 "Aux Playback",
158 }; 158 };
159 159
160 static const unsigned int adav80x_mux_values[] 160 static const unsigned int adav80x_mux_values[] = {
161 0, 2, 3, 161 0, 2, 3,
162 }; 162 };
163 163
164 #define ADAV80X_MUX_ENUM_DECL(name, reg, shift 164 #define ADAV80X_MUX_ENUM_DECL(name, reg, shift) \
165 SOC_VALUE_ENUM_DOUBLE_DECL(name, reg, 165 SOC_VALUE_ENUM_DOUBLE_DECL(name, reg, shift, 7, \
166 ARRAY_SIZE(adav80x_mux_text), 166 ARRAY_SIZE(adav80x_mux_text), adav80x_mux_text, \
167 adav80x_mux_values) 167 adav80x_mux_values)
168 168
169 static ADAV80X_MUX_ENUM_DECL(adav80x_aux_captu 169 static ADAV80X_MUX_ENUM_DECL(adav80x_aux_capture_enum, ADAV80X_DPATH_CTRL1, 0);
170 static ADAV80X_MUX_ENUM_DECL(adav80x_capture_e 170 static ADAV80X_MUX_ENUM_DECL(adav80x_capture_enum, ADAV80X_DPATH_CTRL1, 3);
171 static ADAV80X_MUX_ENUM_DECL(adav80x_dac_enum, 171 static ADAV80X_MUX_ENUM_DECL(adav80x_dac_enum, ADAV80X_DPATH_CTRL2, 3);
172 172
173 static const struct snd_kcontrol_new adav80x_a 173 static const struct snd_kcontrol_new adav80x_aux_capture_mux_ctrl =
174 SOC_DAPM_ENUM("Route", adav80x_aux_cap 174 SOC_DAPM_ENUM("Route", adav80x_aux_capture_enum);
175 static const struct snd_kcontrol_new adav80x_c 175 static const struct snd_kcontrol_new adav80x_capture_mux_ctrl =
176 SOC_DAPM_ENUM("Route", adav80x_capture 176 SOC_DAPM_ENUM("Route", adav80x_capture_enum);
177 static const struct snd_kcontrol_new adav80x_d 177 static const struct snd_kcontrol_new adav80x_dac_mux_ctrl =
178 SOC_DAPM_ENUM("Route", adav80x_dac_enu 178 SOC_DAPM_ENUM("Route", adav80x_dac_enum);
179 179
180 #define ADAV80X_MUX(name, ctrl) \ 180 #define ADAV80X_MUX(name, ctrl) \
181 SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, 0 181 SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
182 182
183 static const struct snd_soc_dapm_widget adav80 183 static const struct snd_soc_dapm_widget adav80x_dapm_widgets[] = {
184 SND_SOC_DAPM_DAC("DAC", NULL, ADAV80X_ 184 SND_SOC_DAPM_DAC("DAC", NULL, ADAV80X_DAC_CTRL1, 7, 1),
185 SND_SOC_DAPM_ADC("ADC", NULL, ADAV80X_ 185 SND_SOC_DAPM_ADC("ADC", NULL, ADAV80X_ADC_CTRL1, 5, 1),
186 186
187 SND_SOC_DAPM_PGA("Right PGA", ADAV80X_ 187 SND_SOC_DAPM_PGA("Right PGA", ADAV80X_ADC_CTRL1, 0, 1, NULL, 0),
188 SND_SOC_DAPM_PGA("Left PGA", ADAV80X_A 188 SND_SOC_DAPM_PGA("Left PGA", ADAV80X_ADC_CTRL1, 1, 1, NULL, 0),
189 189
190 SND_SOC_DAPM_AIF_OUT("AIFOUT", "HiFi C 190 SND_SOC_DAPM_AIF_OUT("AIFOUT", "HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
191 SND_SOC_DAPM_AIF_IN("AIFIN", "HiFi Pla 191 SND_SOC_DAPM_AIF_IN("AIFIN", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
192 192
193 SND_SOC_DAPM_AIF_OUT("AIFAUXOUT", "Aux 193 SND_SOC_DAPM_AIF_OUT("AIFAUXOUT", "Aux Capture", 0, SND_SOC_NOPM, 0, 0),
194 SND_SOC_DAPM_AIF_IN("AIFAUXIN", "Aux P 194 SND_SOC_DAPM_AIF_IN("AIFAUXIN", "Aux Playback", 0, SND_SOC_NOPM, 0, 0),
195 195
196 ADAV80X_MUX("Aux Capture Select", &ada 196 ADAV80X_MUX("Aux Capture Select", &adav80x_aux_capture_mux_ctrl),
197 ADAV80X_MUX("Capture Select", &adav80x 197 ADAV80X_MUX("Capture Select", &adav80x_capture_mux_ctrl),
198 ADAV80X_MUX("DAC Select", &adav80x_dac 198 ADAV80X_MUX("DAC Select", &adav80x_dac_mux_ctrl),
199 199
200 SND_SOC_DAPM_INPUT("VINR"), 200 SND_SOC_DAPM_INPUT("VINR"),
201 SND_SOC_DAPM_INPUT("VINL"), 201 SND_SOC_DAPM_INPUT("VINL"),
202 SND_SOC_DAPM_OUTPUT("VOUTR"), 202 SND_SOC_DAPM_OUTPUT("VOUTR"),
203 SND_SOC_DAPM_OUTPUT("VOUTL"), 203 SND_SOC_DAPM_OUTPUT("VOUTL"),
204 204
205 SND_SOC_DAPM_SUPPLY("SYSCLK", SND_SOC_ 205 SND_SOC_DAPM_SUPPLY("SYSCLK", SND_SOC_NOPM, 0, 0, NULL, 0),
206 SND_SOC_DAPM_SUPPLY("PLL1", ADAV80X_PL 206 SND_SOC_DAPM_SUPPLY("PLL1", ADAV80X_PLL_CTRL1, 2, 1, NULL, 0),
207 SND_SOC_DAPM_SUPPLY("PLL2", ADAV80X_PL 207 SND_SOC_DAPM_SUPPLY("PLL2", ADAV80X_PLL_CTRL1, 3, 1, NULL, 0),
208 SND_SOC_DAPM_SUPPLY("OSC", ADAV80X_PLL 208 SND_SOC_DAPM_SUPPLY("OSC", ADAV80X_PLL_CTRL1, 1, 1, NULL, 0),
209 }; 209 };
210 210
211 static int adav80x_dapm_sysclk_check(struct sn 211 static int adav80x_dapm_sysclk_check(struct snd_soc_dapm_widget *source,
212 struct snd_soc_dapm_w 212 struct snd_soc_dapm_widget *sink)
213 { 213 {
214 struct snd_soc_component *component = 214 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
215 struct adav80x *adav80x = snd_soc_comp 215 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
216 const char *clk; 216 const char *clk;
217 217
218 switch (adav80x->clk_src) { 218 switch (adav80x->clk_src) {
219 case ADAV80X_CLK_PLL1: 219 case ADAV80X_CLK_PLL1:
220 clk = "PLL1"; 220 clk = "PLL1";
221 break; 221 break;
222 case ADAV80X_CLK_PLL2: 222 case ADAV80X_CLK_PLL2:
223 clk = "PLL2"; 223 clk = "PLL2";
224 break; 224 break;
225 case ADAV80X_CLK_XTAL: 225 case ADAV80X_CLK_XTAL:
226 clk = "OSC"; 226 clk = "OSC";
227 break; 227 break;
228 default: 228 default:
229 return 0; 229 return 0;
230 } 230 }
231 231
232 return snd_soc_dapm_widget_name_cmp(so !! 232 return strcmp(source->name, clk) == 0;
233 } 233 }
234 234
235 static int adav80x_dapm_pll_check(struct snd_s 235 static int adav80x_dapm_pll_check(struct snd_soc_dapm_widget *source,
236 struct snd_soc_dapm_w 236 struct snd_soc_dapm_widget *sink)
237 { 237 {
238 struct snd_soc_component *component = 238 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
239 struct adav80x *adav80x = snd_soc_comp 239 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
240 240
241 return adav80x->pll_src == ADAV80X_PLL 241 return adav80x->pll_src == ADAV80X_PLL_SRC_XTAL;
242 } 242 }
243 243
244 244
245 static const struct snd_soc_dapm_route adav80x 245 static const struct snd_soc_dapm_route adav80x_dapm_routes[] = {
246 { "DAC Select", "ADC", "ADC" }, 246 { "DAC Select", "ADC", "ADC" },
247 { "DAC Select", "Playback", "AIFIN" }, 247 { "DAC Select", "Playback", "AIFIN" },
248 { "DAC Select", "Aux Playback", "AIFAU 248 { "DAC Select", "Aux Playback", "AIFAUXIN" },
249 { "DAC", NULL, "DAC Select" }, 249 { "DAC", NULL, "DAC Select" },
250 250
251 { "Capture Select", "ADC", "ADC" }, 251 { "Capture Select", "ADC", "ADC" },
252 { "Capture Select", "Playback", "AIFIN 252 { "Capture Select", "Playback", "AIFIN" },
253 { "Capture Select", "Aux Playback", "A 253 { "Capture Select", "Aux Playback", "AIFAUXIN" },
254 { "AIFOUT", NULL, "Capture Select" }, 254 { "AIFOUT", NULL, "Capture Select" },
255 255
256 { "Aux Capture Select", "ADC", "ADC" } 256 { "Aux Capture Select", "ADC", "ADC" },
257 { "Aux Capture Select", "Playback", "A 257 { "Aux Capture Select", "Playback", "AIFIN" },
258 { "Aux Capture Select", "Aux Playback" 258 { "Aux Capture Select", "Aux Playback", "AIFAUXIN" },
259 { "AIFAUXOUT", NULL, "Aux Capture Sel 259 { "AIFAUXOUT", NULL, "Aux Capture Select" },
260 260
261 { "VOUTR", NULL, "DAC" }, 261 { "VOUTR", NULL, "DAC" },
262 { "VOUTL", NULL, "DAC" }, 262 { "VOUTL", NULL, "DAC" },
263 263
264 { "Left PGA", NULL, "VINL" }, 264 { "Left PGA", NULL, "VINL" },
265 { "Right PGA", NULL, "VINR" }, 265 { "Right PGA", NULL, "VINR" },
266 { "ADC", NULL, "Left PGA" }, 266 { "ADC", NULL, "Left PGA" },
267 { "ADC", NULL, "Right PGA" }, 267 { "ADC", NULL, "Right PGA" },
268 268
269 { "SYSCLK", NULL, "PLL1", adav80x_dapm 269 { "SYSCLK", NULL, "PLL1", adav80x_dapm_sysclk_check },
270 { "SYSCLK", NULL, "PLL2", adav80x_dapm 270 { "SYSCLK", NULL, "PLL2", adav80x_dapm_sysclk_check },
271 { "SYSCLK", NULL, "OSC", adav80x_dapm_ 271 { "SYSCLK", NULL, "OSC", adav80x_dapm_sysclk_check },
272 { "PLL1", NULL, "OSC", adav80x_dapm_pl 272 { "PLL1", NULL, "OSC", adav80x_dapm_pll_check },
273 { "PLL2", NULL, "OSC", adav80x_dapm_pl 273 { "PLL2", NULL, "OSC", adav80x_dapm_pll_check },
274 274
275 { "ADC", NULL, "SYSCLK" }, 275 { "ADC", NULL, "SYSCLK" },
276 { "DAC", NULL, "SYSCLK" }, 276 { "DAC", NULL, "SYSCLK" },
277 { "AIFOUT", NULL, "SYSCLK" }, 277 { "AIFOUT", NULL, "SYSCLK" },
278 { "AIFAUXOUT", NULL, "SYSCLK" }, 278 { "AIFAUXOUT", NULL, "SYSCLK" },
279 { "AIFIN", NULL, "SYSCLK" }, 279 { "AIFIN", NULL, "SYSCLK" },
280 { "AIFAUXIN", NULL, "SYSCLK" }, 280 { "AIFAUXIN", NULL, "SYSCLK" },
281 }; 281 };
282 282
283 static int adav80x_set_deemph(struct snd_soc_c 283 static int adav80x_set_deemph(struct snd_soc_component *component)
284 { 284 {
285 struct adav80x *adav80x = snd_soc_comp 285 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
286 unsigned int val; 286 unsigned int val;
287 287
288 if (adav80x->deemph) { 288 if (adav80x->deemph) {
289 switch (adav80x->rate) { 289 switch (adav80x->rate) {
290 case 32000: 290 case 32000:
291 val = ADAV80X_DAC_CTRL 291 val = ADAV80X_DAC_CTRL2_DEEMPH_32;
292 break; 292 break;
293 case 44100: 293 case 44100:
294 val = ADAV80X_DAC_CTRL 294 val = ADAV80X_DAC_CTRL2_DEEMPH_44;
295 break; 295 break;
296 case 48000: 296 case 48000:
297 case 64000: 297 case 64000:
298 case 88200: 298 case 88200:
299 case 96000: 299 case 96000:
300 val = ADAV80X_DAC_CTRL 300 val = ADAV80X_DAC_CTRL2_DEEMPH_48;
301 break; 301 break;
302 default: 302 default:
303 val = ADAV80X_DAC_CTRL 303 val = ADAV80X_DAC_CTRL2_DEEMPH_NONE;
304 break; 304 break;
305 } 305 }
306 } else { 306 } else {
307 val = ADAV80X_DAC_CTRL2_DEEMPH 307 val = ADAV80X_DAC_CTRL2_DEEMPH_NONE;
308 } 308 }
309 309
310 return regmap_update_bits(adav80x->reg 310 return regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL2,
311 ADAV80X_DAC_CTRL2_DEEMPH_MASK, 311 ADAV80X_DAC_CTRL2_DEEMPH_MASK, val);
312 } 312 }
313 313
314 static int adav80x_put_deemph(struct snd_kcont 314 static int adav80x_put_deemph(struct snd_kcontrol *kcontrol,
315 struct snd_ctl_elem_value *uco 315 struct snd_ctl_elem_value *ucontrol)
316 { 316 {
317 struct snd_soc_component *component = 317 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
318 struct adav80x *adav80x = snd_soc_comp 318 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
319 unsigned int deemph = ucontrol->value. 319 unsigned int deemph = ucontrol->value.integer.value[0];
320 320
321 if (deemph > 1) 321 if (deemph > 1)
322 return -EINVAL; 322 return -EINVAL;
323 323
324 adav80x->deemph = deemph; 324 adav80x->deemph = deemph;
325 325
326 return adav80x_set_deemph(component); 326 return adav80x_set_deemph(component);
327 } 327 }
328 328
329 static int adav80x_get_deemph(struct snd_kcont 329 static int adav80x_get_deemph(struct snd_kcontrol *kcontrol,
330 struct snd_ctl 330 struct snd_ctl_elem_value *ucontrol)
331 { 331 {
332 struct snd_soc_component *component = 332 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
333 struct adav80x *adav80x = snd_soc_comp 333 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
334 334
335 ucontrol->value.integer.value[0] = ada 335 ucontrol->value.integer.value[0] = adav80x->deemph;
336 return 0; 336 return 0;
337 }; 337 };
338 338
339 static const DECLARE_TLV_DB_SCALE(adav80x_inpg 339 static const DECLARE_TLV_DB_SCALE(adav80x_inpga_tlv, 0, 50, 0);
340 static const DECLARE_TLV_DB_MINMAX(adav80x_dig 340 static const DECLARE_TLV_DB_MINMAX(adav80x_digital_tlv, -9563, 0);
341 341
342 static const struct snd_kcontrol_new adav80x_c 342 static const struct snd_kcontrol_new adav80x_controls[] = {
343 SOC_DOUBLE_R_TLV("Master Playback Volu 343 SOC_DOUBLE_R_TLV("Master Playback Volume", ADAV80X_DAC_L_VOL,
344 ADAV80X_DAC_R_VOL, 0, 0xff, 0, 344 ADAV80X_DAC_R_VOL, 0, 0xff, 0, adav80x_digital_tlv),
345 SOC_DOUBLE_R_TLV("Master Capture Volum 345 SOC_DOUBLE_R_TLV("Master Capture Volume", ADAV80X_ADC_L_VOL,
346 ADAV80X_ADC_R_VOL, 0, 346 ADAV80X_ADC_R_VOL, 0, 0xff, 0, adav80x_digital_tlv),
347 347
348 SOC_DOUBLE_R_TLV("PGA Capture Volume", 348 SOC_DOUBLE_R_TLV("PGA Capture Volume", ADAV80X_PGA_L_VOL,
349 ADAV80X_PGA_R_VOL, 0, 349 ADAV80X_PGA_R_VOL, 0, 0x30, 0, adav80x_inpga_tlv),
350 350
351 SOC_DOUBLE("Master Playback Switch", A 351 SOC_DOUBLE("Master Playback Switch", ADAV80X_DAC_CTRL1, 0, 1, 1, 0),
352 SOC_DOUBLE("Master Capture Switch", AD 352 SOC_DOUBLE("Master Capture Switch", ADAV80X_ADC_CTRL1, 2, 3, 1, 1),
353 353
354 SOC_SINGLE("ADC High Pass Filter Switc 354 SOC_SINGLE("ADC High Pass Filter Switch", ADAV80X_ADC_CTRL1, 6, 1, 0),
355 355
356 SOC_SINGLE_BOOL_EXT("Playback De-empha 356 SOC_SINGLE_BOOL_EXT("Playback De-emphasis Switch", 0,
357 adav80x_get_deemph, ad 357 adav80x_get_deemph, adav80x_put_deemph),
358 }; 358 };
359 359
360 static unsigned int adav80x_port_ctrl_regs[2][ 360 static unsigned int adav80x_port_ctrl_regs[2][2] = {
361 { ADAV80X_REC_CTRL, ADAV80X_PLAYBACK_C 361 { ADAV80X_REC_CTRL, ADAV80X_PLAYBACK_CTRL, },
362 { ADAV80X_AUX_OUT_CTRL, ADAV80X_AUX_IN 362 { ADAV80X_AUX_OUT_CTRL, ADAV80X_AUX_IN_CTRL },
363 }; 363 };
364 364
365 static int adav80x_set_dai_fmt(struct snd_soc_ 365 static int adav80x_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
366 { 366 {
367 struct snd_soc_component *component = 367 struct snd_soc_component *component = dai->component;
368 struct adav80x *adav80x = snd_soc_comp 368 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
369 unsigned int capture = 0x00; 369 unsigned int capture = 0x00;
370 unsigned int playback = 0x00; 370 unsigned int playback = 0x00;
371 371
372 switch (fmt & SND_SOC_DAIFMT_CLOCK_PRO 372 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
373 case SND_SOC_DAIFMT_CBP_CFP: 373 case SND_SOC_DAIFMT_CBP_CFP:
374 capture |= ADAV80X_CAPTURE_MOD 374 capture |= ADAV80X_CAPTURE_MODE_MASTER;
375 playback |= ADAV80X_PLAYBACK_M 375 playback |= ADAV80X_PLAYBACK_MODE_MASTER;
376 break; 376 break;
377 case SND_SOC_DAIFMT_CBC_CFC: 377 case SND_SOC_DAIFMT_CBC_CFC:
378 break; 378 break;
379 default: 379 default:
380 return -EINVAL; 380 return -EINVAL;
381 } 381 }
382 382
383 switch (fmt & SND_SOC_DAIFMT_FORMAT_MA 383 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
384 case SND_SOC_DAIFMT_I2S: 384 case SND_SOC_DAIFMT_I2S:
385 capture |= ADAV80X_CAPTURE_MOD 385 capture |= ADAV80X_CAPTURE_MODE_I2S;
386 playback |= ADAV80X_PLAYBACK_M 386 playback |= ADAV80X_PLAYBACK_MODE_I2S;
387 break; 387 break;
388 case SND_SOC_DAIFMT_LEFT_J: 388 case SND_SOC_DAIFMT_LEFT_J:
389 capture |= ADAV80X_CAPTURE_MOD 389 capture |= ADAV80X_CAPTURE_MODE_LEFT_J;
390 playback |= ADAV80X_PLAYBACK_M 390 playback |= ADAV80X_PLAYBACK_MODE_LEFT_J;
391 break; 391 break;
392 case SND_SOC_DAIFMT_RIGHT_J: 392 case SND_SOC_DAIFMT_RIGHT_J:
393 capture |= ADAV80X_CAPTURE_MOD 393 capture |= ADAV80X_CAPTURE_MODE_RIGHT_J;
394 playback |= ADAV80X_PLAYBACK_M 394 playback |= ADAV80X_PLAYBACK_MODE_RIGHT_J_24;
395 break; 395 break;
396 default: 396 default:
397 return -EINVAL; 397 return -EINVAL;
398 } 398 }
399 399
400 switch (fmt & SND_SOC_DAIFMT_INV_MASK) 400 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
401 case SND_SOC_DAIFMT_NB_NF: 401 case SND_SOC_DAIFMT_NB_NF:
402 break; 402 break;
403 default: 403 default:
404 return -EINVAL; 404 return -EINVAL;
405 } 405 }
406 406
407 regmap_update_bits(adav80x->regmap, ad 407 regmap_update_bits(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][0],
408 ADAV80X_CAPTURE_MODE_MASK | AD 408 ADAV80X_CAPTURE_MODE_MASK | ADAV80X_CAPTURE_MODE_MASTER,
409 capture); 409 capture);
410 regmap_write(adav80x->regmap, adav80x_ 410 regmap_write(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][1],
411 playback); 411 playback);
412 412
413 adav80x->dai_fmt[dai->id] = fmt & SND_ 413 adav80x->dai_fmt[dai->id] = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
414 414
415 return 0; 415 return 0;
416 } 416 }
417 417
418 static int adav80x_set_adc_clock(struct snd_so 418 static int adav80x_set_adc_clock(struct snd_soc_component *component,
419 unsigned int sample_rate) 419 unsigned int sample_rate)
420 { 420 {
421 struct adav80x *adav80x = snd_soc_comp 421 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
422 unsigned int val; 422 unsigned int val;
423 423
424 if (sample_rate <= 48000) 424 if (sample_rate <= 48000)
425 val = ADAV80X_ADC_CTRL1_MODULA 425 val = ADAV80X_ADC_CTRL1_MODULATOR_128FS;
426 else 426 else
427 val = ADAV80X_ADC_CTRL1_MODULA 427 val = ADAV80X_ADC_CTRL1_MODULATOR_64FS;
428 428
429 regmap_update_bits(adav80x->regmap, AD 429 regmap_update_bits(adav80x->regmap, ADAV80X_ADC_CTRL1,
430 ADAV80X_ADC_CTRL1_MODULATOR_MA 430 ADAV80X_ADC_CTRL1_MODULATOR_MASK, val);
431 431
432 return 0; 432 return 0;
433 } 433 }
434 434
435 static int adav80x_set_dac_clock(struct snd_so 435 static int adav80x_set_dac_clock(struct snd_soc_component *component,
436 unsigned int sample_rate) 436 unsigned int sample_rate)
437 { 437 {
438 struct adav80x *adav80x = snd_soc_comp 438 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
439 unsigned int val; 439 unsigned int val;
440 440
441 if (sample_rate <= 48000) 441 if (sample_rate <= 48000)
442 val = ADAV80X_DAC_CTRL2_DIV1 | 442 val = ADAV80X_DAC_CTRL2_DIV1 | ADAV80X_DAC_CTRL2_INTERPOL_256FS;
443 else 443 else
444 val = ADAV80X_DAC_CTRL2_DIV2 | 444 val = ADAV80X_DAC_CTRL2_DIV2 | ADAV80X_DAC_CTRL2_INTERPOL_128FS;
445 445
446 regmap_update_bits(adav80x->regmap, AD 446 regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL2,
447 ADAV80X_DAC_CTRL2_DIV_MASK | A 447 ADAV80X_DAC_CTRL2_DIV_MASK | ADAV80X_DAC_CTRL2_INTERPOL_MASK,
448 val); 448 val);
449 449
450 return 0; 450 return 0;
451 } 451 }
452 452
453 static int adav80x_set_capture_pcm_format(stru 453 static int adav80x_set_capture_pcm_format(struct snd_soc_component *component,
454 struct snd_soc_dai *dai, struc 454 struct snd_soc_dai *dai, struct snd_pcm_hw_params *params)
455 { 455 {
456 struct adav80x *adav80x = snd_soc_comp 456 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
457 unsigned int val; 457 unsigned int val;
458 458
459 switch (params_width(params)) { 459 switch (params_width(params)) {
460 case 16: 460 case 16:
461 val = ADAV80X_CAPTURE_WORD_LEN 461 val = ADAV80X_CAPTURE_WORD_LEN16;
462 break; 462 break;
463 case 18: 463 case 18:
464 val = ADAV80X_CAPTRUE_WORD_LEN 464 val = ADAV80X_CAPTRUE_WORD_LEN18;
465 break; 465 break;
466 case 20: 466 case 20:
467 val = ADAV80X_CAPTURE_WORD_LEN 467 val = ADAV80X_CAPTURE_WORD_LEN20;
468 break; 468 break;
469 case 24: 469 case 24:
470 val = ADAV80X_CAPTURE_WORD_LEN 470 val = ADAV80X_CAPTURE_WORD_LEN24;
471 break; 471 break;
472 default: 472 default:
473 return -EINVAL; 473 return -EINVAL;
474 } 474 }
475 475
476 regmap_update_bits(adav80x->regmap, ad 476 regmap_update_bits(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][0],
477 ADAV80X_CAPTURE_WORD_LEN_MASK, 477 ADAV80X_CAPTURE_WORD_LEN_MASK, val);
478 478
479 return 0; 479 return 0;
480 } 480 }
481 481
482 static int adav80x_set_playback_pcm_format(str 482 static int adav80x_set_playback_pcm_format(struct snd_soc_component *component,
483 struct snd_soc_dai *dai, struc 483 struct snd_soc_dai *dai, struct snd_pcm_hw_params *params)
484 { 484 {
485 struct adav80x *adav80x = snd_soc_comp 485 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
486 unsigned int val; 486 unsigned int val;
487 487
488 if (adav80x->dai_fmt[dai->id] != SND_S 488 if (adav80x->dai_fmt[dai->id] != SND_SOC_DAIFMT_RIGHT_J)
489 return 0; 489 return 0;
490 490
491 switch (params_width(params)) { 491 switch (params_width(params)) {
492 case 16: 492 case 16:
493 val = ADAV80X_PLAYBACK_MODE_RI 493 val = ADAV80X_PLAYBACK_MODE_RIGHT_J_16;
494 break; 494 break;
495 case 18: 495 case 18:
496 val = ADAV80X_PLAYBACK_MODE_RI 496 val = ADAV80X_PLAYBACK_MODE_RIGHT_J_18;
497 break; 497 break;
498 case 20: 498 case 20:
499 val = ADAV80X_PLAYBACK_MODE_RI 499 val = ADAV80X_PLAYBACK_MODE_RIGHT_J_20;
500 break; 500 break;
501 case 24: 501 case 24:
502 val = ADAV80X_PLAYBACK_MODE_RI 502 val = ADAV80X_PLAYBACK_MODE_RIGHT_J_24;
503 break; 503 break;
504 default: 504 default:
505 return -EINVAL; 505 return -EINVAL;
506 } 506 }
507 507
508 regmap_update_bits(adav80x->regmap, ad 508 regmap_update_bits(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][1],
509 ADAV80X_PLAYBACK_MODE_MASK, va 509 ADAV80X_PLAYBACK_MODE_MASK, val);
510 510
511 return 0; 511 return 0;
512 } 512 }
513 513
514 static int adav80x_hw_params(struct snd_pcm_su 514 static int adav80x_hw_params(struct snd_pcm_substream *substream,
515 struct snd_pcm_hw_params *para 515 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
516 { 516 {
517 struct snd_soc_component *component = 517 struct snd_soc_component *component = dai->component;
518 struct adav80x *adav80x = snd_soc_comp 518 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
519 unsigned int rate = params_rate(params 519 unsigned int rate = params_rate(params);
520 520
521 if (rate * 256 != adav80x->sysclk) 521 if (rate * 256 != adav80x->sysclk)
522 return -EINVAL; 522 return -EINVAL;
523 523
524 if (substream->stream == SNDRV_PCM_STR 524 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
525 adav80x_set_playback_pcm_forma 525 adav80x_set_playback_pcm_format(component, dai, params);
526 adav80x_set_dac_clock(componen 526 adav80x_set_dac_clock(component, rate);
527 } else { 527 } else {
528 adav80x_set_capture_pcm_format 528 adav80x_set_capture_pcm_format(component, dai, params);
529 adav80x_set_adc_clock(componen 529 adav80x_set_adc_clock(component, rate);
530 } 530 }
531 adav80x->rate = rate; 531 adav80x->rate = rate;
532 adav80x_set_deemph(component); 532 adav80x_set_deemph(component);
533 533
534 return 0; 534 return 0;
535 } 535 }
536 536
537 static int adav80x_set_sysclk(struct snd_soc_c 537 static int adav80x_set_sysclk(struct snd_soc_component *component,
538 int clk_id, int 538 int clk_id, int source,
539 unsigned int fre 539 unsigned int freq, int dir)
540 { 540 {
541 struct adav80x *adav80x = snd_soc_comp 541 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
542 struct snd_soc_dapm_context *dapm = sn 542 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
543 543
544 if (dir == SND_SOC_CLOCK_IN) { 544 if (dir == SND_SOC_CLOCK_IN) {
545 switch (clk_id) { 545 switch (clk_id) {
546 case ADAV80X_CLK_XIN: 546 case ADAV80X_CLK_XIN:
547 case ADAV80X_CLK_XTAL: 547 case ADAV80X_CLK_XTAL:
548 case ADAV80X_CLK_MCLKI: 548 case ADAV80X_CLK_MCLKI:
549 case ADAV80X_CLK_PLL1: 549 case ADAV80X_CLK_PLL1:
550 case ADAV80X_CLK_PLL2: 550 case ADAV80X_CLK_PLL2:
551 break; 551 break;
552 default: 552 default:
553 return -EINVAL; 553 return -EINVAL;
554 } 554 }
555 555
556 adav80x->sysclk = freq; 556 adav80x->sysclk = freq;
557 557
558 if (adav80x->clk_src != clk_id 558 if (adav80x->clk_src != clk_id) {
559 unsigned int iclk_ctrl 559 unsigned int iclk_ctrl1, iclk_ctrl2;
560 560
561 adav80x->clk_src = clk 561 adav80x->clk_src = clk_id;
562 if (clk_id == ADAV80X_ 562 if (clk_id == ADAV80X_CLK_XTAL)
563 clk_id = ADAV8 563 clk_id = ADAV80X_CLK_XIN;
564 564
565 iclk_ctrl1 = ADAV80X_I 565 iclk_ctrl1 = ADAV80X_ICLK_CTRL1_DAC_SRC(clk_id) |
566 ADAV80 566 ADAV80X_ICLK_CTRL1_ADC_SRC(clk_id) |
567 ADAV80 567 ADAV80X_ICLK_CTRL1_ICLK2_SRC(clk_id);
568 iclk_ctrl2 = ADAV80X_I 568 iclk_ctrl2 = ADAV80X_ICLK_CTRL2_ICLK1_SRC(clk_id);
569 569
570 regmap_write(adav80x-> 570 regmap_write(adav80x->regmap, ADAV80X_ICLK_CTRL1,
571 iclk_ctrl1); 571 iclk_ctrl1);
572 regmap_write(adav80x-> 572 regmap_write(adav80x->regmap, ADAV80X_ICLK_CTRL2,
573 iclk_ctrl2); 573 iclk_ctrl2);
574 574
575 snd_soc_dapm_sync(dapm 575 snd_soc_dapm_sync(dapm);
576 } 576 }
577 } else { 577 } else {
578 unsigned int mask; 578 unsigned int mask;
579 579
580 switch (clk_id) { 580 switch (clk_id) {
581 case ADAV80X_CLK_SYSCLK1: 581 case ADAV80X_CLK_SYSCLK1:
582 case ADAV80X_CLK_SYSCLK2: 582 case ADAV80X_CLK_SYSCLK2:
583 case ADAV80X_CLK_SYSCLK3: 583 case ADAV80X_CLK_SYSCLK3:
584 break; 584 break;
585 default: 585 default:
586 return -EINVAL; 586 return -EINVAL;
587 } 587 }
588 588
589 clk_id -= ADAV80X_CLK_SYSCLK1; 589 clk_id -= ADAV80X_CLK_SYSCLK1;
590 mask = ADAV80X_PLL_OUTE_SYSCLK 590 mask = ADAV80X_PLL_OUTE_SYSCLKPD(clk_id);
591 591
592 if (freq == 0) { 592 if (freq == 0) {
593 regmap_update_bits(ada 593 regmap_update_bits(adav80x->regmap, ADAV80X_PLL_OUTE,
594 mask, mask); 594 mask, mask);
595 adav80x->sysclk_pd[clk 595 adav80x->sysclk_pd[clk_id] = true;
596 } else { 596 } else {
597 regmap_update_bits(ada 597 regmap_update_bits(adav80x->regmap, ADAV80X_PLL_OUTE,
598 mask, 0); 598 mask, 0);
599 adav80x->sysclk_pd[clk 599 adav80x->sysclk_pd[clk_id] = false;
600 } 600 }
601 601
602 snd_soc_dapm_mutex_lock(dapm); 602 snd_soc_dapm_mutex_lock(dapm);
603 603
604 if (adav80x->sysclk_pd[0]) 604 if (adav80x->sysclk_pd[0])
605 snd_soc_dapm_disable_p 605 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL1");
606 else 606 else
607 snd_soc_dapm_force_ena 607 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL1");
608 608
609 if (adav80x->sysclk_pd[1] || a 609 if (adav80x->sysclk_pd[1] || adav80x->sysclk_pd[2])
610 snd_soc_dapm_disable_p 610 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2");
611 else 611 else
612 snd_soc_dapm_force_ena 612 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2");
613 613
614 snd_soc_dapm_sync_unlocked(dap 614 snd_soc_dapm_sync_unlocked(dapm);
615 615
616 snd_soc_dapm_mutex_unlock(dapm 616 snd_soc_dapm_mutex_unlock(dapm);
617 } 617 }
618 618
619 return 0; 619 return 0;
620 } 620 }
621 621
622 static int adav80x_set_pll(struct snd_soc_comp 622 static int adav80x_set_pll(struct snd_soc_component *component, int pll_id,
623 int source, unsigned int freq_ 623 int source, unsigned int freq_in, unsigned int freq_out)
624 { 624 {
625 struct snd_soc_dapm_context *dapm = sn 625 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
626 struct adav80x *adav80x = snd_soc_comp 626 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
627 unsigned int pll_ctrl1 = 0; 627 unsigned int pll_ctrl1 = 0;
628 unsigned int pll_ctrl2 = 0; 628 unsigned int pll_ctrl2 = 0;
629 unsigned int pll_src; 629 unsigned int pll_src;
630 630
631 switch (source) { 631 switch (source) {
632 case ADAV80X_PLL_SRC_XTAL: 632 case ADAV80X_PLL_SRC_XTAL:
633 case ADAV80X_PLL_SRC_XIN: 633 case ADAV80X_PLL_SRC_XIN:
634 case ADAV80X_PLL_SRC_MCLKI: 634 case ADAV80X_PLL_SRC_MCLKI:
635 break; 635 break;
636 default: 636 default:
637 return -EINVAL; 637 return -EINVAL;
638 } 638 }
639 639
640 if (!freq_out) 640 if (!freq_out)
641 return 0; 641 return 0;
642 642
643 switch (freq_in) { 643 switch (freq_in) {
644 case 27000000: 644 case 27000000:
645 break; 645 break;
646 case 54000000: 646 case 54000000:
647 if (source == ADAV80X_PLL_SRC_ 647 if (source == ADAV80X_PLL_SRC_XIN) {
648 pll_ctrl1 |= ADAV80X_P 648 pll_ctrl1 |= ADAV80X_PLL_CTRL1_PLLDIV;
649 break; 649 break;
650 } 650 }
651 fallthrough; 651 fallthrough;
652 default: 652 default:
653 return -EINVAL; 653 return -EINVAL;
654 } 654 }
655 655
656 if (freq_out > 12288000) { 656 if (freq_out > 12288000) {
657 pll_ctrl2 |= ADAV80X_PLL_CTRL2 657 pll_ctrl2 |= ADAV80X_PLL_CTRL2_DOUB(pll_id);
658 freq_out /= 2; 658 freq_out /= 2;
659 } 659 }
660 660
661 /* freq_out = sample_rate * 256 */ 661 /* freq_out = sample_rate * 256 */
662 switch (freq_out) { 662 switch (freq_out) {
663 case 8192000: 663 case 8192000:
664 pll_ctrl2 |= ADAV80X_PLL_CTRL2 664 pll_ctrl2 |= ADAV80X_PLL_CTRL2_FS_32(pll_id);
665 break; 665 break;
666 case 11289600: 666 case 11289600:
667 pll_ctrl2 |= ADAV80X_PLL_CTRL2 667 pll_ctrl2 |= ADAV80X_PLL_CTRL2_FS_44(pll_id);
668 break; 668 break;
669 case 12288000: 669 case 12288000:
670 pll_ctrl2 |= ADAV80X_PLL_CTRL2 670 pll_ctrl2 |= ADAV80X_PLL_CTRL2_FS_48(pll_id);
671 break; 671 break;
672 default: 672 default:
673 return -EINVAL; 673 return -EINVAL;
674 } 674 }
675 675
676 regmap_update_bits(adav80x->regmap, AD 676 regmap_update_bits(adav80x->regmap, ADAV80X_PLL_CTRL1,
677 ADAV80X_PLL_CTRL1_PLLD 677 ADAV80X_PLL_CTRL1_PLLDIV, pll_ctrl1);
678 regmap_update_bits(adav80x->regmap, AD 678 regmap_update_bits(adav80x->regmap, ADAV80X_PLL_CTRL2,
679 ADAV80X_PLL_CTRL2_PLL_ 679 ADAV80X_PLL_CTRL2_PLL_MASK(pll_id), pll_ctrl2);
680 680
681 if (source != adav80x->pll_src) { 681 if (source != adav80x->pll_src) {
682 if (source == ADAV80X_PLL_SRC_ 682 if (source == ADAV80X_PLL_SRC_MCLKI)
683 pll_src = ADAV80X_PLL_ 683 pll_src = ADAV80X_PLL_CLK_SRC_PLL_MCLKI(pll_id);
684 else 684 else
685 pll_src = ADAV80X_PLL_ 685 pll_src = ADAV80X_PLL_CLK_SRC_PLL_XIN(pll_id);
686 686
687 regmap_update_bits(adav80x->re 687 regmap_update_bits(adav80x->regmap, ADAV80X_PLL_CLK_SRC,
688 ADAV80X_PLL_CL 688 ADAV80X_PLL_CLK_SRC_PLL_MASK(pll_id), pll_src);
689 689
690 adav80x->pll_src = source; 690 adav80x->pll_src = source;
691 691
692 snd_soc_dapm_sync(dapm); 692 snd_soc_dapm_sync(dapm);
693 } 693 }
694 694
695 return 0; 695 return 0;
696 } 696 }
697 697
698 static int adav80x_set_bias_level(struct snd_s 698 static int adav80x_set_bias_level(struct snd_soc_component *component,
699 enum snd_soc_bias_level level) 699 enum snd_soc_bias_level level)
700 { 700 {
701 struct adav80x *adav80x = snd_soc_comp 701 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
702 unsigned int mask = ADAV80X_DAC_CTRL1_ 702 unsigned int mask = ADAV80X_DAC_CTRL1_PD;
703 703
704 switch (level) { 704 switch (level) {
705 case SND_SOC_BIAS_ON: 705 case SND_SOC_BIAS_ON:
706 break; 706 break;
707 case SND_SOC_BIAS_PREPARE: 707 case SND_SOC_BIAS_PREPARE:
708 break; 708 break;
709 case SND_SOC_BIAS_STANDBY: 709 case SND_SOC_BIAS_STANDBY:
710 regmap_update_bits(adav80x->re 710 regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL1, mask,
711 0x00); 711 0x00);
712 break; 712 break;
713 case SND_SOC_BIAS_OFF: 713 case SND_SOC_BIAS_OFF:
714 regmap_update_bits(adav80x->re 714 regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL1, mask,
715 mask); 715 mask);
716 break; 716 break;
717 } 717 }
718 718
719 return 0; 719 return 0;
720 } 720 }
721 721
722 /* Enforce the same sample rate on all audio i 722 /* Enforce the same sample rate on all audio interfaces */
723 static int adav80x_dai_startup(struct snd_pcm_ 723 static int adav80x_dai_startup(struct snd_pcm_substream *substream,
724 struct snd_soc_dai *dai) 724 struct snd_soc_dai *dai)
725 { 725 {
726 struct snd_soc_component *component = 726 struct snd_soc_component *component = dai->component;
727 struct adav80x *adav80x = snd_soc_comp 727 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
728 728
729 if (!snd_soc_component_active(componen 729 if (!snd_soc_component_active(component) || !adav80x->rate)
730 return 0; 730 return 0;
731 731
732 return snd_pcm_hw_constraint_single(su 732 return snd_pcm_hw_constraint_single(substream->runtime,
733 SNDRV_PCM_HW_PARAM_RAT 733 SNDRV_PCM_HW_PARAM_RATE, adav80x->rate);
734 } 734 }
735 735
736 static void adav80x_dai_shutdown(struct snd_pc 736 static void adav80x_dai_shutdown(struct snd_pcm_substream *substream,
737 struct snd_soc_dai *dai) 737 struct snd_soc_dai *dai)
738 { 738 {
739 struct snd_soc_component *component = 739 struct snd_soc_component *component = dai->component;
740 struct adav80x *adav80x = snd_soc_comp 740 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
741 741
742 if (!snd_soc_component_active(componen 742 if (!snd_soc_component_active(component))
743 adav80x->rate = 0; 743 adav80x->rate = 0;
744 } 744 }
745 745
746 static const struct snd_soc_dai_ops adav80x_da 746 static const struct snd_soc_dai_ops adav80x_dai_ops = {
747 .set_fmt = adav80x_set_dai_fmt, 747 .set_fmt = adav80x_set_dai_fmt,
748 .hw_params = adav80x_hw_params, 748 .hw_params = adav80x_hw_params,
749 .startup = adav80x_dai_startup, 749 .startup = adav80x_dai_startup,
750 .shutdown = adav80x_dai_shutdown, 750 .shutdown = adav80x_dai_shutdown,
751 }; 751 };
752 752
753 #define ADAV80X_PLAYBACK_RATES (SNDRV_PCM_RATE 753 #define ADAV80X_PLAYBACK_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
754 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_ 754 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | \
755 SNDRV_PCM_RATE_96000) 755 SNDRV_PCM_RATE_96000)
756 756
757 #define ADAV80X_CAPTURE_RATES (SNDRV_PCM_RATE_ 757 #define ADAV80X_CAPTURE_RATES (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)
758 758
759 #define ADAV80X_FORMATS (SNDRV_PCM_FMTBIT_S16_ 759 #define ADAV80X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
760 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_F 760 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE)
761 761
762 static struct snd_soc_dai_driver adav80x_dais[ 762 static struct snd_soc_dai_driver adav80x_dais[] = {
763 { 763 {
764 .name = "adav80x-hifi", 764 .name = "adav80x-hifi",
765 .id = 0, 765 .id = 0,
766 .playback = { 766 .playback = {
767 .stream_name = "HiFi P 767 .stream_name = "HiFi Playback",
768 .channels_min = 2, 768 .channels_min = 2,
769 .channels_max = 2, 769 .channels_max = 2,
770 .rates = ADAV80X_PLAYB 770 .rates = ADAV80X_PLAYBACK_RATES,
771 .formats = ADAV80X_FOR 771 .formats = ADAV80X_FORMATS,
772 }, 772 },
773 .capture = { 773 .capture = {
774 .stream_name = "HiFi C 774 .stream_name = "HiFi Capture",
775 .channels_min = 2, 775 .channels_min = 2,
776 .channels_max = 2, 776 .channels_max = 2,
777 .rates = ADAV80X_CAPTU 777 .rates = ADAV80X_CAPTURE_RATES,
778 .formats = ADAV80X_FOR 778 .formats = ADAV80X_FORMATS,
779 }, 779 },
780 .ops = &adav80x_dai_ops, 780 .ops = &adav80x_dai_ops,
781 }, 781 },
782 { 782 {
783 .name = "adav80x-aux", 783 .name = "adav80x-aux",
784 .id = 1, 784 .id = 1,
785 .playback = { 785 .playback = {
786 .stream_name = "Aux Pl 786 .stream_name = "Aux Playback",
787 .channels_min = 2, 787 .channels_min = 2,
788 .channels_max = 2, 788 .channels_max = 2,
789 .rates = ADAV80X_PLAYB 789 .rates = ADAV80X_PLAYBACK_RATES,
790 .formats = ADAV80X_FOR 790 .formats = ADAV80X_FORMATS,
791 }, 791 },
792 .capture = { 792 .capture = {
793 .stream_name = "Aux Ca 793 .stream_name = "Aux Capture",
794 .channels_min = 2, 794 .channels_min = 2,
795 .channels_max = 2, 795 .channels_max = 2,
796 .rates = ADAV80X_CAPTU 796 .rates = ADAV80X_CAPTURE_RATES,
797 .formats = ADAV80X_FOR 797 .formats = ADAV80X_FORMATS,
798 }, 798 },
799 .ops = &adav80x_dai_ops, 799 .ops = &adav80x_dai_ops,
800 }, 800 },
801 }; 801 };
802 802
803 static int adav80x_probe(struct snd_soc_compon 803 static int adav80x_probe(struct snd_soc_component *component)
804 { 804 {
805 struct snd_soc_dapm_context *dapm = sn 805 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
806 struct adav80x *adav80x = snd_soc_comp 806 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
807 807
808 /* Force PLLs on for SYSCLK output */ 808 /* Force PLLs on for SYSCLK output */
809 snd_soc_dapm_force_enable_pin(dapm, "P 809 snd_soc_dapm_force_enable_pin(dapm, "PLL1");
810 snd_soc_dapm_force_enable_pin(dapm, "P 810 snd_soc_dapm_force_enable_pin(dapm, "PLL2");
811 811
812 /* Power down S/PDIF receiver, since i 812 /* Power down S/PDIF receiver, since it is currently not supported */
813 regmap_write(adav80x->regmap, ADAV80X_ 813 regmap_write(adav80x->regmap, ADAV80X_PLL_OUTE, 0x20);
814 /* Disable DAC zero flag */ 814 /* Disable DAC zero flag */
815 regmap_write(adav80x->regmap, ADAV80X_ 815 regmap_write(adav80x->regmap, ADAV80X_DAC_CTRL3, 0x6);
816 816
817 return 0; 817 return 0;
818 } 818 }
819 819
820 static int adav80x_resume(struct snd_soc_compo 820 static int adav80x_resume(struct snd_soc_component *component)
821 { 821 {
822 struct adav80x *adav80x = snd_soc_comp 822 struct adav80x *adav80x = snd_soc_component_get_drvdata(component);
823 823
824 regcache_sync(adav80x->regmap); 824 regcache_sync(adav80x->regmap);
825 825
826 return 0; 826 return 0;
827 } 827 }
828 828
829 static const struct snd_soc_component_driver a 829 static const struct snd_soc_component_driver adav80x_component_driver = {
830 .probe = adav80x_prob 830 .probe = adav80x_probe,
831 .resume = adav80x_resu 831 .resume = adav80x_resume,
832 .set_bias_level = adav80x_set_ 832 .set_bias_level = adav80x_set_bias_level,
833 .set_pll = adav80x_set_ 833 .set_pll = adav80x_set_pll,
834 .set_sysclk = adav80x_set_ 834 .set_sysclk = adav80x_set_sysclk,
835 .controls = adav80x_cont 835 .controls = adav80x_controls,
836 .num_controls = ARRAY_SIZE(a 836 .num_controls = ARRAY_SIZE(adav80x_controls),
837 .dapm_widgets = adav80x_dapm 837 .dapm_widgets = adav80x_dapm_widgets,
838 .num_dapm_widgets = ARRAY_SIZE(a 838 .num_dapm_widgets = ARRAY_SIZE(adav80x_dapm_widgets),
839 .dapm_routes = adav80x_dapm 839 .dapm_routes = adav80x_dapm_routes,
840 .num_dapm_routes = ARRAY_SIZE(a 840 .num_dapm_routes = ARRAY_SIZE(adav80x_dapm_routes),
841 .suspend_bias_off = 1, 841 .suspend_bias_off = 1,
842 .idle_bias_on = 1, 842 .idle_bias_on = 1,
843 .use_pmdown_time = 1, 843 .use_pmdown_time = 1,
844 .endianness = 1, 844 .endianness = 1,
>> 845 .non_legacy_dai_naming = 1,
845 }; 846 };
846 847
847 int adav80x_bus_probe(struct device *dev, stru 848 int adav80x_bus_probe(struct device *dev, struct regmap *regmap)
848 { 849 {
849 struct adav80x *adav80x; 850 struct adav80x *adav80x;
850 851
851 if (IS_ERR(regmap)) 852 if (IS_ERR(regmap))
852 return PTR_ERR(regmap); 853 return PTR_ERR(regmap);
853 854
854 adav80x = devm_kzalloc(dev, sizeof(*ad 855 adav80x = devm_kzalloc(dev, sizeof(*adav80x), GFP_KERNEL);
855 if (!adav80x) 856 if (!adav80x)
856 return -ENOMEM; 857 return -ENOMEM;
857 858
858 dev_set_drvdata(dev, adav80x); 859 dev_set_drvdata(dev, adav80x);
859 adav80x->regmap = regmap; 860 adav80x->regmap = regmap;
860 861
861 return devm_snd_soc_register_component 862 return devm_snd_soc_register_component(dev, &adav80x_component_driver,
862 adav80x_dais, ARRAY_SIZE(adav8 863 adav80x_dais, ARRAY_SIZE(adav80x_dais));
863 } 864 }
864 EXPORT_SYMBOL_GPL(adav80x_bus_probe); 865 EXPORT_SYMBOL_GPL(adav80x_bus_probe);
865 866
866 const struct regmap_config adav80x_regmap_conf 867 const struct regmap_config adav80x_regmap_config = {
867 .val_bits = 8, 868 .val_bits = 8,
868 .pad_bits = 1, 869 .pad_bits = 1,
869 .reg_bits = 7, 870 .reg_bits = 7,
870 871
871 .max_register = ADAV80X_PLL_OUTE, 872 .max_register = ADAV80X_PLL_OUTE,
872 873
873 .cache_type = REGCACHE_MAPLE, !! 874 .cache_type = REGCACHE_RBTREE,
874 .reg_defaults = adav80x_reg_defaults, 875 .reg_defaults = adav80x_reg_defaults,
875 .num_reg_defaults = ARRAY_SIZE(adav80x 876 .num_reg_defaults = ARRAY_SIZE(adav80x_reg_defaults),
876 }; 877 };
877 EXPORT_SYMBOL_GPL(adav80x_regmap_config); 878 EXPORT_SYMBOL_GPL(adav80x_regmap_config);
878 879
879 MODULE_DESCRIPTION("ASoC ADAV80x driver"); 880 MODULE_DESCRIPTION("ASoC ADAV80x driver");
880 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafo 881 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
881 MODULE_AUTHOR("Yi Li <yi.li@analog.com>>"); 882 MODULE_AUTHOR("Yi Li <yi.li@analog.com>>");
882 MODULE_LICENSE("GPL"); 883 MODULE_LICENSE("GPL");
883 884
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