1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 // 2 //
3 // Components shared between ASoC and HDA CS35 3 // Components shared between ASoC and HDA CS35L56 drivers
4 // 4 //
5 // Copyright (C) 2023 Cirrus Logic, Inc. and 5 // Copyright (C) 2023 Cirrus Logic, Inc. and
6 // Cirrus Logic Internation 6 // Cirrus Logic International Semiconductor Ltd.
7 7
8 #include <linux/array_size.h> 8 #include <linux/array_size.h>
9 #include <linux/firmware/cirrus/wmfw.h> 9 #include <linux/firmware/cirrus/wmfw.h>
10 #include <linux/gpio/consumer.h> 10 #include <linux/gpio/consumer.h>
11 #include <linux/regmap.h> 11 #include <linux/regmap.h>
12 #include <linux/regulator/consumer.h> 12 #include <linux/regulator/consumer.h>
13 #include <linux/types.h> 13 #include <linux/types.h>
14 #include <sound/cs-amp-lib.h> 14 #include <sound/cs-amp-lib.h>
15 15
16 #include "cs35l56.h" 16 #include "cs35l56.h"
17 17
18 static const struct reg_sequence cs35l56_patch 18 static const struct reg_sequence cs35l56_patch[] = {
19 /* 19 /*
20 * Firmware can change these to non-de 20 * Firmware can change these to non-defaults to satisfy SDCA.
21 * Ensure that they are at known defau 21 * Ensure that they are at known defaults.
22 */ 22 */
23 { CS35L56_ASP1_ENABLES1, 23 { CS35L56_ASP1_ENABLES1, 0x00000000 },
24 { CS35L56_ASP1_CONTROL1, 24 { CS35L56_ASP1_CONTROL1, 0x00000028 },
25 { CS35L56_ASP1_CONTROL2, 25 { CS35L56_ASP1_CONTROL2, 0x18180200 },
26 { CS35L56_ASP1_CONTROL3, 26 { CS35L56_ASP1_CONTROL3, 0x00000002 },
27 { CS35L56_ASP1_FRAME_CONTROL1, 27 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 },
28 { CS35L56_ASP1_FRAME_CONTROL5, 28 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 },
29 { CS35L56_ASP1_DATA_CONTROL1, 29 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 },
30 { CS35L56_ASP1_DATA_CONTROL5, 30 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 },
31 { CS35L56_ASP1TX1_INPUT, 31 { CS35L56_ASP1TX1_INPUT, 0x00000000 },
32 { CS35L56_ASP1TX2_INPUT, 32 { CS35L56_ASP1TX2_INPUT, 0x00000000 },
33 { CS35L56_ASP1TX3_INPUT, 33 { CS35L56_ASP1TX3_INPUT, 0x00000000 },
34 { CS35L56_ASP1TX4_INPUT, 34 { CS35L56_ASP1TX4_INPUT, 0x00000000 },
35 { CS35L56_SWIRE_DP3_CH1_INPUT, 35 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 },
36 { CS35L56_SWIRE_DP3_CH2_INPUT, 36 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 },
37 { CS35L56_SWIRE_DP3_CH3_INPUT, 37 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 },
38 { CS35L56_SWIRE_DP3_CH4_INPUT, 38 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 },
39 { CS35L56_IRQ1_MASK_18, 39 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff },
40 40
41 /* These are not reset by a soft-reset 41 /* These are not reset by a soft-reset, so patch to defaults. */
42 { CS35L56_MAIN_RENDER_USER_MUTE, 42 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 },
43 { CS35L56_MAIN_RENDER_USER_VOLUME, 43 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 },
44 { CS35L56_MAIN_POSTURE_NUMBER, 44 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 },
45 }; 45 };
46 46
47 int cs35l56_set_patch(struct cs35l56_base *cs3 47 int cs35l56_set_patch(struct cs35l56_base *cs35l56_base)
48 { 48 {
49 return regmap_register_patch(cs35l56_b 49 return regmap_register_patch(cs35l56_base->regmap, cs35l56_patch,
50 ARRAY_SIZ 50 ARRAY_SIZE(cs35l56_patch));
51 } 51 }
52 EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, SND_SO 52 EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, SND_SOC_CS35L56_SHARED);
53 53
54 static const struct reg_default cs35l56_reg_de 54 static const struct reg_default cs35l56_reg_defaults[] = {
55 /* no defaults for OTP_MEM - first rea 55 /* no defaults for OTP_MEM - first read populates cache */
56 56
57 { CS35L56_ASP1_ENABLES1, 57 { CS35L56_ASP1_ENABLES1, 0x00000000 },
58 { CS35L56_ASP1_CONTROL1, 58 { CS35L56_ASP1_CONTROL1, 0x00000028 },
59 { CS35L56_ASP1_CONTROL2, 59 { CS35L56_ASP1_CONTROL2, 0x18180200 },
60 { CS35L56_ASP1_CONTROL3, 60 { CS35L56_ASP1_CONTROL3, 0x00000002 },
61 { CS35L56_ASP1_FRAME_CONTROL1, 61 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 },
62 { CS35L56_ASP1_FRAME_CONTROL5, 62 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 },
63 { CS35L56_ASP1_DATA_CONTROL1, 63 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 },
64 { CS35L56_ASP1_DATA_CONTROL5, 64 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 },
65 { CS35L56_ASP1TX1_INPUT, 65 { CS35L56_ASP1TX1_INPUT, 0x00000000 },
66 { CS35L56_ASP1TX2_INPUT, 66 { CS35L56_ASP1TX2_INPUT, 0x00000000 },
67 { CS35L56_ASP1TX3_INPUT, 67 { CS35L56_ASP1TX3_INPUT, 0x00000000 },
68 { CS35L56_ASP1TX4_INPUT, 68 { CS35L56_ASP1TX4_INPUT, 0x00000000 },
69 { CS35L56_SWIRE_DP3_CH1_INPUT, 69 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 },
70 { CS35L56_SWIRE_DP3_CH2_INPUT, 70 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 },
71 { CS35L56_SWIRE_DP3_CH3_INPUT, 71 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 },
72 { CS35L56_SWIRE_DP3_CH4_INPUT, 72 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 },
73 { CS35L56_IRQ1_MASK_1, 73 { CS35L56_IRQ1_MASK_1, 0x83ffffff },
74 { CS35L56_IRQ1_MASK_2, 74 { CS35L56_IRQ1_MASK_2, 0xffff7fff },
75 { CS35L56_IRQ1_MASK_4, 75 { CS35L56_IRQ1_MASK_4, 0xe0ffffff },
76 { CS35L56_IRQ1_MASK_8, 76 { CS35L56_IRQ1_MASK_8, 0xfc000fff },
77 { CS35L56_IRQ1_MASK_18, 77 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff },
78 { CS35L56_IRQ1_MASK_20, 78 { CS35L56_IRQ1_MASK_20, 0x15c00000 },
79 { CS35L56_MAIN_RENDER_USER_MUTE, 79 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 },
80 { CS35L56_MAIN_RENDER_USER_VOLUME, 80 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 },
81 { CS35L56_MAIN_POSTURE_NUMBER, 81 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 },
82 }; 82 };
83 83
84 static bool cs35l56_is_dsp_memory(unsigned int 84 static bool cs35l56_is_dsp_memory(unsigned int reg)
85 { 85 {
86 switch (reg) { 86 switch (reg) {
87 case CS35L56_DSP1_XMEM_PACKED_0 ... CS 87 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143:
88 case CS35L56_DSP1_XMEM_UNPACKED32_0 .. 88 case CS35L56_DSP1_XMEM_UNPACKED32_0 ... CS35L56_DSP1_XMEM_UNPACKED32_4095:
89 case CS35L56_DSP1_XMEM_UNPACKED24_0 .. 89 case CS35L56_DSP1_XMEM_UNPACKED24_0 ... CS35L56_DSP1_XMEM_UNPACKED24_8191:
90 case CS35L56_DSP1_YMEM_PACKED_0 ... CS 90 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604:
91 case CS35L56_DSP1_YMEM_UNPACKED32_0 .. 91 case CS35L56_DSP1_YMEM_UNPACKED32_0 ... CS35L56_DSP1_YMEM_UNPACKED32_3070:
92 case CS35L56_DSP1_YMEM_UNPACKED24_0 .. 92 case CS35L56_DSP1_YMEM_UNPACKED24_0 ... CS35L56_DSP1_YMEM_UNPACKED24_6141:
93 case CS35L56_DSP1_PMEM_0 ... CS35L56_D 93 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114:
94 return true; 94 return true;
95 default: 95 default:
96 return false; 96 return false;
97 } 97 }
98 } 98 }
99 99
100 static bool cs35l56_readable_reg(struct device 100 static bool cs35l56_readable_reg(struct device *dev, unsigned int reg)
101 { 101 {
102 switch (reg) { 102 switch (reg) {
103 case CS35L56_DEVID: 103 case CS35L56_DEVID:
104 case CS35L56_REVID: 104 case CS35L56_REVID:
105 case CS35L56_RELID: 105 case CS35L56_RELID:
106 case CS35L56_OTPID: 106 case CS35L56_OTPID:
107 case CS35L56_SFT_RESET: 107 case CS35L56_SFT_RESET:
108 case CS35L56_GLOBAL_ENABLES: 108 case CS35L56_GLOBAL_ENABLES:
109 case CS35L56_BLOCK_ENABLES: 109 case CS35L56_BLOCK_ENABLES:
110 case CS35L56_BLOCK_ENABLES2: 110 case CS35L56_BLOCK_ENABLES2:
111 case CS35L56_REFCLK_INPUT: 111 case CS35L56_REFCLK_INPUT:
112 case CS35L56_GLOBAL_SAMPLE_RATE: 112 case CS35L56_GLOBAL_SAMPLE_RATE:
113 case CS35L56_OTP_MEM_53: 113 case CS35L56_OTP_MEM_53:
114 case CS35L56_OTP_MEM_54: 114 case CS35L56_OTP_MEM_54:
115 case CS35L56_OTP_MEM_55: 115 case CS35L56_OTP_MEM_55:
116 case CS35L56_ASP1_ENABLES1: 116 case CS35L56_ASP1_ENABLES1:
117 case CS35L56_ASP1_CONTROL1: 117 case CS35L56_ASP1_CONTROL1:
118 case CS35L56_ASP1_CONTROL2: 118 case CS35L56_ASP1_CONTROL2:
119 case CS35L56_ASP1_CONTROL3: 119 case CS35L56_ASP1_CONTROL3:
120 case CS35L56_ASP1_FRAME_CONTROL1: 120 case CS35L56_ASP1_FRAME_CONTROL1:
121 case CS35L56_ASP1_FRAME_CONTROL5: 121 case CS35L56_ASP1_FRAME_CONTROL5:
122 case CS35L56_ASP1_DATA_CONTROL1: 122 case CS35L56_ASP1_DATA_CONTROL1:
123 case CS35L56_ASP1_DATA_CONTROL5: 123 case CS35L56_ASP1_DATA_CONTROL5:
124 case CS35L56_DACPCM1_INPUT: 124 case CS35L56_DACPCM1_INPUT:
125 case CS35L56_DACPCM2_INPUT: 125 case CS35L56_DACPCM2_INPUT:
126 case CS35L56_ASP1TX1_INPUT: 126 case CS35L56_ASP1TX1_INPUT:
127 case CS35L56_ASP1TX2_INPUT: 127 case CS35L56_ASP1TX2_INPUT:
128 case CS35L56_ASP1TX3_INPUT: 128 case CS35L56_ASP1TX3_INPUT:
129 case CS35L56_ASP1TX4_INPUT: 129 case CS35L56_ASP1TX4_INPUT:
130 case CS35L56_DSP1RX1_INPUT: 130 case CS35L56_DSP1RX1_INPUT:
131 case CS35L56_DSP1RX2_INPUT: 131 case CS35L56_DSP1RX2_INPUT:
132 case CS35L56_SWIRE_DP3_CH1_INPUT: 132 case CS35L56_SWIRE_DP3_CH1_INPUT:
133 case CS35L56_SWIRE_DP3_CH2_INPUT: 133 case CS35L56_SWIRE_DP3_CH2_INPUT:
134 case CS35L56_SWIRE_DP3_CH3_INPUT: 134 case CS35L56_SWIRE_DP3_CH3_INPUT:
135 case CS35L56_SWIRE_DP3_CH4_INPUT: 135 case CS35L56_SWIRE_DP3_CH4_INPUT:
136 case CS35L56_IRQ1_CFG: 136 case CS35L56_IRQ1_CFG:
137 case CS35L56_IRQ1_STATUS: 137 case CS35L56_IRQ1_STATUS:
138 case CS35L56_IRQ1_EINT_1 ... CS35L56_I 138 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8:
139 case CS35L56_IRQ1_EINT_18: 139 case CS35L56_IRQ1_EINT_18:
140 case CS35L56_IRQ1_EINT_20: 140 case CS35L56_IRQ1_EINT_20:
141 case CS35L56_IRQ1_MASK_1: 141 case CS35L56_IRQ1_MASK_1:
142 case CS35L56_IRQ1_MASK_2: 142 case CS35L56_IRQ1_MASK_2:
143 case CS35L56_IRQ1_MASK_4: 143 case CS35L56_IRQ1_MASK_4:
144 case CS35L56_IRQ1_MASK_8: 144 case CS35L56_IRQ1_MASK_8:
145 case CS35L56_IRQ1_MASK_18: 145 case CS35L56_IRQ1_MASK_18:
146 case CS35L56_IRQ1_MASK_20: 146 case CS35L56_IRQ1_MASK_20:
147 case CS35L56_DSP_VIRTUAL1_MBOX_1: 147 case CS35L56_DSP_VIRTUAL1_MBOX_1:
148 case CS35L56_DSP_VIRTUAL1_MBOX_2: 148 case CS35L56_DSP_VIRTUAL1_MBOX_2:
149 case CS35L56_DSP_VIRTUAL1_MBOX_3: 149 case CS35L56_DSP_VIRTUAL1_MBOX_3:
150 case CS35L56_DSP_VIRTUAL1_MBOX_4: 150 case CS35L56_DSP_VIRTUAL1_MBOX_4:
151 case CS35L56_DSP_VIRTUAL1_MBOX_5: 151 case CS35L56_DSP_VIRTUAL1_MBOX_5:
152 case CS35L56_DSP_VIRTUAL1_MBOX_6: 152 case CS35L56_DSP_VIRTUAL1_MBOX_6:
153 case CS35L56_DSP_VIRTUAL1_MBOX_7: 153 case CS35L56_DSP_VIRTUAL1_MBOX_7:
154 case CS35L56_DSP_VIRTUAL1_MBOX_8: 154 case CS35L56_DSP_VIRTUAL1_MBOX_8:
155 case CS35L56_DSP_RESTRICT_STS1: 155 case CS35L56_DSP_RESTRICT_STS1:
156 case CS35L56_DSP1_SYS_INFO_ID ... CS35 156 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END:
157 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 157 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0:
158 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 158 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1:
159 case CS35L56_DSP1_SCRATCH1: 159 case CS35L56_DSP1_SCRATCH1:
160 case CS35L56_DSP1_SCRATCH2: 160 case CS35L56_DSP1_SCRATCH2:
161 case CS35L56_DSP1_SCRATCH3: 161 case CS35L56_DSP1_SCRATCH3:
162 case CS35L56_DSP1_SCRATCH4: 162 case CS35L56_DSP1_SCRATCH4:
163 return true; 163 return true;
164 default: 164 default:
165 return cs35l56_is_dsp_memory(r 165 return cs35l56_is_dsp_memory(reg);
166 } 166 }
167 } 167 }
168 168
169 static bool cs35l56_precious_reg(struct device 169 static bool cs35l56_precious_reg(struct device *dev, unsigned int reg)
170 { 170 {
171 switch (reg) { 171 switch (reg) {
172 case CS35L56_DSP1_XMEM_PACKED_0 ... CS 172 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143:
173 case CS35L56_DSP1_YMEM_PACKED_0 ... CS 173 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604:
174 case CS35L56_DSP1_PMEM_0 ... CS35L56_D 174 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114:
175 return true; 175 return true;
176 default: 176 default:
177 return false; 177 return false;
178 } 178 }
179 } 179 }
180 180
181 static bool cs35l56_volatile_reg(struct device 181 static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg)
182 { 182 {
183 switch (reg) { 183 switch (reg) {
184 case CS35L56_DEVID: 184 case CS35L56_DEVID:
185 case CS35L56_REVID: 185 case CS35L56_REVID:
186 case CS35L56_RELID: 186 case CS35L56_RELID:
187 case CS35L56_OTPID: 187 case CS35L56_OTPID:
188 case CS35L56_SFT_RESET: 188 case CS35L56_SFT_RESET:
189 case CS35L56_GLOBAL_ENABLES: 189 case CS35L56_GLOBAL_ENABLES: /* owned by firmware */
190 case CS35L56_BLOCK_ENABLES: 190 case CS35L56_BLOCK_ENABLES: /* owned by firmware */
191 case CS35L56_BLOCK_ENABLES2: 191 case CS35L56_BLOCK_ENABLES2: /* owned by firmware */
192 case CS35L56_REFCLK_INPUT: 192 case CS35L56_REFCLK_INPUT: /* owned by firmware */
193 case CS35L56_GLOBAL_SAMPLE_RATE: 193 case CS35L56_GLOBAL_SAMPLE_RATE: /* owned by firmware */
194 case CS35L56_DACPCM1_INPUT: 194 case CS35L56_DACPCM1_INPUT: /* owned by firmware */
195 case CS35L56_DACPCM2_INPUT: 195 case CS35L56_DACPCM2_INPUT: /* owned by firmware */
196 case CS35L56_DSP1RX1_INPUT: 196 case CS35L56_DSP1RX1_INPUT: /* owned by firmware */
197 case CS35L56_DSP1RX2_INPUT: 197 case CS35L56_DSP1RX2_INPUT: /* owned by firmware */
198 case CS35L56_IRQ1_STATUS: 198 case CS35L56_IRQ1_STATUS:
199 case CS35L56_IRQ1_EINT_1 ... CS35L56_I 199 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8:
200 case CS35L56_IRQ1_EINT_18: 200 case CS35L56_IRQ1_EINT_18:
201 case CS35L56_IRQ1_EINT_20: 201 case CS35L56_IRQ1_EINT_20:
202 case CS35L56_DSP_VIRTUAL1_MBOX_1: 202 case CS35L56_DSP_VIRTUAL1_MBOX_1:
203 case CS35L56_DSP_VIRTUAL1_MBOX_2: 203 case CS35L56_DSP_VIRTUAL1_MBOX_2:
204 case CS35L56_DSP_VIRTUAL1_MBOX_3: 204 case CS35L56_DSP_VIRTUAL1_MBOX_3:
205 case CS35L56_DSP_VIRTUAL1_MBOX_4: 205 case CS35L56_DSP_VIRTUAL1_MBOX_4:
206 case CS35L56_DSP_VIRTUAL1_MBOX_5: 206 case CS35L56_DSP_VIRTUAL1_MBOX_5:
207 case CS35L56_DSP_VIRTUAL1_MBOX_6: 207 case CS35L56_DSP_VIRTUAL1_MBOX_6:
208 case CS35L56_DSP_VIRTUAL1_MBOX_7: 208 case CS35L56_DSP_VIRTUAL1_MBOX_7:
209 case CS35L56_DSP_VIRTUAL1_MBOX_8: 209 case CS35L56_DSP_VIRTUAL1_MBOX_8:
210 case CS35L56_DSP_RESTRICT_STS1: 210 case CS35L56_DSP_RESTRICT_STS1:
211 case CS35L56_DSP1_SYS_INFO_ID ... CS35 211 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END:
212 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 212 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0:
213 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 213 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1:
214 case CS35L56_DSP1_SCRATCH1: 214 case CS35L56_DSP1_SCRATCH1:
215 case CS35L56_DSP1_SCRATCH2: 215 case CS35L56_DSP1_SCRATCH2:
216 case CS35L56_DSP1_SCRATCH3: 216 case CS35L56_DSP1_SCRATCH3:
217 case CS35L56_DSP1_SCRATCH4: 217 case CS35L56_DSP1_SCRATCH4:
218 return true; 218 return true;
219 case CS35L56_MAIN_RENDER_USER_MUTE: 219 case CS35L56_MAIN_RENDER_USER_MUTE:
220 case CS35L56_MAIN_RENDER_USER_VOLUME: 220 case CS35L56_MAIN_RENDER_USER_VOLUME:
221 case CS35L56_MAIN_POSTURE_NUMBER: 221 case CS35L56_MAIN_POSTURE_NUMBER:
222 return false; 222 return false;
223 default: 223 default:
224 return cs35l56_is_dsp_memory(r 224 return cs35l56_is_dsp_memory(reg);
225 } 225 }
226 } 226 }
227 227
228 int cs35l56_mbox_send(struct cs35l56_base *cs3 228 int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command)
229 { 229 {
230 unsigned int val; 230 unsigned int val;
231 int ret; 231 int ret;
232 232
233 regmap_write(cs35l56_base->regmap, CS3 233 regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command);
234 ret = regmap_read_poll_timeout(cs35l56 234 ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1,
235 val, (v 235 val, (val == 0),
236 CS35L56 236 CS35L56_MBOX_POLL_US, CS35L56_MBOX_TIMEOUT_US);
237 if (ret) { 237 if (ret) {
238 dev_warn(cs35l56_base->dev, "M 238 dev_warn(cs35l56_base->dev, "MBOX command %#x failed: %d\n", command, ret);
239 return ret; 239 return ret;
240 } 240 }
241 241
242 return 0; 242 return 0;
243 } 243 }
244 EXPORT_SYMBOL_NS_GPL(cs35l56_mbox_send, SND_SO 244 EXPORT_SYMBOL_NS_GPL(cs35l56_mbox_send, SND_SOC_CS35L56_SHARED);
245 245
246 int cs35l56_firmware_shutdown(struct cs35l56_b 246 int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base)
247 { 247 {
248 int ret; 248 int ret;
>> 249 unsigned int reg;
249 unsigned int val; 250 unsigned int val;
250 251
251 ret = cs35l56_mbox_send(cs35l56_base, 252 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_SHUTDOWN);
252 if (ret) 253 if (ret)
253 return ret; 254 return ret;
254 255
255 ret = regmap_read_poll_timeout(cs35l56 !! 256 if (cs35l56_base->rev < CS35L56_REVID_B0)
>> 257 reg = CS35L56_DSP1_PM_CUR_STATE_A1;
>> 258 else
>> 259 reg = CS35L56_DSP1_PM_CUR_STATE;
>> 260
>> 261 ret = regmap_read_poll_timeout(cs35l56_base->regmap, reg,
256 val, (v 262 val, (val == CS35L56_HALO_STATE_SHUTDOWN),
257 CS35L56 263 CS35L56_HALO_STATE_POLL_US,
258 CS35L56 264 CS35L56_HALO_STATE_TIMEOUT_US);
259 if (ret < 0) 265 if (ret < 0)
260 dev_err(cs35l56_base->dev, "Fa 266 dev_err(cs35l56_base->dev, "Failed to poll PM_CUR_STATE to 1 is %d (ret %d)\n",
261 val, ret); 267 val, ret);
262 return ret; 268 return ret;
263 } 269 }
264 EXPORT_SYMBOL_NS_GPL(cs35l56_firmware_shutdown 270 EXPORT_SYMBOL_NS_GPL(cs35l56_firmware_shutdown, SND_SOC_CS35L56_SHARED);
265 271
266 int cs35l56_wait_for_firmware_boot(struct cs35 272 int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base)
267 { 273 {
>> 274 unsigned int reg;
268 unsigned int val = 0; 275 unsigned int val = 0;
269 int read_ret, poll_ret; 276 int read_ret, poll_ret;
270 277
>> 278 if (cs35l56_base->rev < CS35L56_REVID_B0)
>> 279 reg = CS35L56_DSP1_HALO_STATE_A1;
>> 280 else
>> 281 reg = CS35L56_DSP1_HALO_STATE;
>> 282
271 /* 283 /*
272 * The regmap must remain in cache-onl 284 * The regmap must remain in cache-only until the chip has
273 * booted, so use a bypassed read of t 285 * booted, so use a bypassed read of the status register.
274 */ 286 */
275 poll_ret = read_poll_timeout(regmap_re 287 poll_ret = read_poll_timeout(regmap_read_bypassed, read_ret,
276 (val < 0x 288 (val < 0xFFFF) && (val >= CS35L56_HALO_STATE_BOOT_DONE),
277 CS35L56_H 289 CS35L56_HALO_STATE_POLL_US,
278 CS35L56_H 290 CS35L56_HALO_STATE_TIMEOUT_US,
279 false, 291 false,
280 cs35l56_b !! 292 cs35l56_base->regmap, reg, &val);
281 293
282 if (poll_ret) { 294 if (poll_ret) {
283 dev_err(cs35l56_base->dev, "Fi 295 dev_err(cs35l56_base->dev, "Firmware boot timed out(%d): HALO_STATE=%#x\n",
284 read_ret, val); 296 read_ret, val);
285 return -EIO; 297 return -EIO;
286 } 298 }
287 299
288 return 0; 300 return 0;
289 } 301 }
290 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_for_firmware 302 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_for_firmware_boot, SND_SOC_CS35L56_SHARED);
291 303
292 void cs35l56_wait_control_port_ready(void) 304 void cs35l56_wait_control_port_ready(void)
293 { 305 {
294 /* Wait for control port to be ready ( 306 /* Wait for control port to be ready (datasheet tIRS). */
295 usleep_range(CS35L56_CONTROL_PORT_READ 307 usleep_range(CS35L56_CONTROL_PORT_READY_US, 2 * CS35L56_CONTROL_PORT_READY_US);
296 } 308 }
297 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_control_port 309 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_control_port_ready, SND_SOC_CS35L56_SHARED);
298 310
299 void cs35l56_wait_min_reset_pulse(void) 311 void cs35l56_wait_min_reset_pulse(void)
300 { 312 {
301 /* Satisfy minimum reset pulse width s 313 /* Satisfy minimum reset pulse width spec */
302 usleep_range(CS35L56_RESET_PULSE_MIN_U 314 usleep_range(CS35L56_RESET_PULSE_MIN_US, 2 * CS35L56_RESET_PULSE_MIN_US);
303 } 315 }
304 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_min_reset_pu 316 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_min_reset_pulse, SND_SOC_CS35L56_SHARED);
305 317
306 static const struct reg_sequence cs35l56_syste 318 static const struct reg_sequence cs35l56_system_reset_seq[] = {
307 REG_SEQ0(CS35L56_DSP1_HALO_STATE, 0), 319 REG_SEQ0(CS35L56_DSP1_HALO_STATE, 0),
308 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, 320 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET),
309 }; 321 };
310 322
311 void cs35l56_system_reset(struct cs35l56_base 323 void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire)
312 { 324 {
313 /* 325 /*
314 * Must enter cache-only first so ther 326 * Must enter cache-only first so there can't be any more register
315 * accesses other than the controlled 327 * accesses other than the controlled system reset sequence below.
316 */ 328 */
317 regcache_cache_only(cs35l56_base->regm 329 regcache_cache_only(cs35l56_base->regmap, true);
318 regmap_multi_reg_write_bypassed(cs35l5 330 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
319 cs35l5 331 cs35l56_system_reset_seq,
320 ARRAY_ 332 ARRAY_SIZE(cs35l56_system_reset_seq));
321 333
322 /* On SoundWire the registers won't be 334 /* On SoundWire the registers won't be accessible until it re-enumerates. */
323 if (is_soundwire) 335 if (is_soundwire)
324 return; 336 return;
325 337
326 cs35l56_wait_control_port_ready(); 338 cs35l56_wait_control_port_ready();
327 339
328 /* Leave in cache-only. This will be r 340 /* Leave in cache-only. This will be revoked when the chip has rebooted. */
329 } 341 }
330 EXPORT_SYMBOL_NS_GPL(cs35l56_system_reset, SND 342 EXPORT_SYMBOL_NS_GPL(cs35l56_system_reset, SND_SOC_CS35L56_SHARED);
331 343
332 int cs35l56_irq_request(struct cs35l56_base *c 344 int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq)
333 { 345 {
334 int ret; 346 int ret;
335 347
336 if (irq < 1) 348 if (irq < 1)
337 return 0; 349 return 0;
338 350
339 ret = devm_request_threaded_irq(cs35l5 351 ret = devm_request_threaded_irq(cs35l56_base->dev, irq, NULL, cs35l56_irq,
340 IRQF_O 352 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW,
341 "cs35l 353 "cs35l56", cs35l56_base);
342 if (!ret) 354 if (!ret)
343 cs35l56_base->irq = irq; 355 cs35l56_base->irq = irq;
344 else 356 else
345 dev_err(cs35l56_base->dev, "Fa 357 dev_err(cs35l56_base->dev, "Failed to get IRQ: %d\n", ret);
346 358
347 return ret; 359 return ret;
348 } 360 }
349 EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, SND_ 361 EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, SND_SOC_CS35L56_SHARED);
350 362
351 irqreturn_t cs35l56_irq(int irq, void *data) 363 irqreturn_t cs35l56_irq(int irq, void *data)
352 { 364 {
353 struct cs35l56_base *cs35l56_base = da 365 struct cs35l56_base *cs35l56_base = data;
354 unsigned int status1 = 0, status8 = 0, 366 unsigned int status1 = 0, status8 = 0, status20 = 0;
355 unsigned int mask1, mask8, mask20; 367 unsigned int mask1, mask8, mask20;
356 unsigned int val; 368 unsigned int val;
357 int rv; 369 int rv;
358 370
359 irqreturn_t ret = IRQ_NONE; 371 irqreturn_t ret = IRQ_NONE;
360 372
361 if (!cs35l56_base->init_done) 373 if (!cs35l56_base->init_done)
362 return IRQ_NONE; 374 return IRQ_NONE;
363 375
364 mutex_lock(&cs35l56_base->irq_lock); 376 mutex_lock(&cs35l56_base->irq_lock);
365 377
366 rv = pm_runtime_resume_and_get(cs35l56 378 rv = pm_runtime_resume_and_get(cs35l56_base->dev);
367 if (rv < 0) { 379 if (rv < 0) {
368 dev_err(cs35l56_base->dev, "ir 380 dev_err(cs35l56_base->dev, "irq: failed to get pm_runtime: %d\n", rv);
369 goto err_unlock; 381 goto err_unlock;
370 } 382 }
371 383
372 regmap_read(cs35l56_base->regmap, CS35 384 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val);
373 if ((val & CS35L56_IRQ1_STS_MASK) == 0 385 if ((val & CS35L56_IRQ1_STS_MASK) == 0) {
374 dev_dbg(cs35l56_base->dev, "Sp 386 dev_dbg(cs35l56_base->dev, "Spurious IRQ: no pending interrupt\n");
375 goto err; 387 goto err;
376 } 388 }
377 389
378 /* Ack interrupts */ 390 /* Ack interrupts */
379 regmap_read(cs35l56_base->regmap, CS35 391 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, &status1);
380 regmap_read(cs35l56_base->regmap, CS35 392 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, &mask1);
381 status1 &= ~mask1; 393 status1 &= ~mask1;
382 regmap_write(cs35l56_base->regmap, CS3 394 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, status1);
383 395
384 regmap_read(cs35l56_base->regmap, CS35 396 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, &status8);
385 regmap_read(cs35l56_base->regmap, CS35 397 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, &mask8);
386 status8 &= ~mask8; 398 status8 &= ~mask8;
387 regmap_write(cs35l56_base->regmap, CS3 399 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, status8);
388 400
389 regmap_read(cs35l56_base->regmap, CS35 401 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_20, &status20);
390 regmap_read(cs35l56_base->regmap, CS35 402 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, &mask20);
391 status20 &= ~mask20; 403 status20 &= ~mask20;
392 /* We don't want EINT20 but they defau 404 /* We don't want EINT20 but they default to unmasked: force mask */
393 regmap_write(cs35l56_base->regmap, CS3 405 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff);
394 406
395 dev_dbg(cs35l56_base->dev, "%s: %#x %# 407 dev_dbg(cs35l56_base->dev, "%s: %#x %#x\n", __func__, status1, status8);
396 408
397 /* Check to see if unmasked bits are a 409 /* Check to see if unmasked bits are active */
398 if (!status1 && !status8 && !status20) 410 if (!status1 && !status8 && !status20)
399 goto err; 411 goto err;
400 412
401 if (status1 & CS35L56_AMP_SHORT_ERR_EI 413 if (status1 & CS35L56_AMP_SHORT_ERR_EINT1_MASK)
402 dev_crit(cs35l56_base->dev, "A 414 dev_crit(cs35l56_base->dev, "Amp short error\n");
403 415
404 if (status8 & CS35L56_TEMP_ERR_EINT1_M 416 if (status8 & CS35L56_TEMP_ERR_EINT1_MASK)
405 dev_crit(cs35l56_base->dev, "O 417 dev_crit(cs35l56_base->dev, "Overtemp error\n");
406 418
407 ret = IRQ_HANDLED; 419 ret = IRQ_HANDLED;
408 420
409 err: 421 err:
410 pm_runtime_put(cs35l56_base->dev); 422 pm_runtime_put(cs35l56_base->dev);
411 err_unlock: 423 err_unlock:
412 mutex_unlock(&cs35l56_base->irq_lock); 424 mutex_unlock(&cs35l56_base->irq_lock);
413 425
414 return ret; 426 return ret;
415 } 427 }
416 EXPORT_SYMBOL_NS_GPL(cs35l56_irq, SND_SOC_CS35 428 EXPORT_SYMBOL_NS_GPL(cs35l56_irq, SND_SOC_CS35L56_SHARED);
417 429
418 int cs35l56_is_fw_reload_needed(struct cs35l56 430 int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base)
419 { 431 {
420 unsigned int val; 432 unsigned int val;
421 int ret; 433 int ret;
422 434
423 /* 435 /*
424 * In secure mode FIRMWARE_MISSING is 436 * In secure mode FIRMWARE_MISSING is cleared by the BIOS loader so
425 * can't be used here to test for memo 437 * can't be used here to test for memory retention.
426 * Assume that tuning must be re-loade 438 * Assume that tuning must be re-loaded.
427 */ 439 */
428 if (cs35l56_base->secured) 440 if (cs35l56_base->secured)
429 return true; 441 return true;
430 442
431 ret = pm_runtime_resume_and_get(cs35l5 443 ret = pm_runtime_resume_and_get(cs35l56_base->dev);
432 if (ret) { 444 if (ret) {
433 dev_err(cs35l56_base->dev, "Fa 445 dev_err(cs35l56_base->dev, "Failed to runtime_get: %d\n", ret);
434 return ret; 446 return ret;
435 } 447 }
436 448
437 ret = regmap_read(cs35l56_base->regmap 449 ret = regmap_read(cs35l56_base->regmap, CS35L56_PROTECTION_STATUS, &val);
438 if (ret) 450 if (ret)
439 dev_err(cs35l56_base->dev, "Fa 451 dev_err(cs35l56_base->dev, "Failed to read PROTECTION_STATUS: %d\n", ret);
440 else 452 else
441 ret = !!(val & CS35L56_FIRMWAR 453 ret = !!(val & CS35L56_FIRMWARE_MISSING);
442 454
443 pm_runtime_put_autosuspend(cs35l56_bas 455 pm_runtime_put_autosuspend(cs35l56_base->dev);
444 456
445 return ret; 457 return ret;
446 } 458 }
447 EXPORT_SYMBOL_NS_GPL(cs35l56_is_fw_reload_need 459 EXPORT_SYMBOL_NS_GPL(cs35l56_is_fw_reload_needed, SND_SOC_CS35L56_SHARED);
448 460
449 static const struct reg_sequence cs35l56_hiber 461 static const struct reg_sequence cs35l56_hibernate_seq[] = {
450 /* This must be the last register acce 462 /* This must be the last register access */
451 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, 463 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE),
452 }; 464 };
453 465
>> 466 static const struct reg_sequence cs35l56_hibernate_wake_seq[] = {
>> 467 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_WAKEUP),
>> 468 };
>> 469
454 static void cs35l56_issue_wake_event(struct cs 470 static void cs35l56_issue_wake_event(struct cs35l56_base *cs35l56_base)
455 { 471 {
456 unsigned int val; <<
457 <<
458 /* 472 /*
459 * Dummy transactions to trigger I2C/S 473 * Dummy transactions to trigger I2C/SPI auto-wake. Issue two
460 * transactions to meet the minimum re 474 * transactions to meet the minimum required time from the rising edge
461 * to the last falling edge of wake. 475 * to the last falling edge of wake.
462 * 476 *
463 * It uses bypassed read because we mu !! 477 * It uses bypassed write because we must wake the chip before
464 * disabling regmap cache-only. 478 * disabling regmap cache-only.
>> 479 *
>> 480 * This can NAK on I2C which will terminate the write sequence so the
>> 481 * single-write sequence is issued twice.
465 */ 482 */
466 regmap_read_bypassed(cs35l56_base->reg !! 483 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
>> 484 cs35l56_hibernate_wake_seq,
>> 485 ARRAY_SIZE(cs35l56_hibernate_wake_seq));
467 486
468 usleep_range(CS35L56_WAKE_HOLD_TIME_US 487 usleep_range(CS35L56_WAKE_HOLD_TIME_US, 2 * CS35L56_WAKE_HOLD_TIME_US);
469 488
470 regmap_read_bypassed(cs35l56_base->reg !! 489 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
>> 490 cs35l56_hibernate_wake_seq,
>> 491 ARRAY_SIZE(cs35l56_hibernate_wake_seq));
471 492
472 cs35l56_wait_control_port_ready(); 493 cs35l56_wait_control_port_ready();
473 } 494 }
474 495
475 int cs35l56_runtime_suspend_common(struct cs35 496 int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base)
476 { 497 {
477 unsigned int val; 498 unsigned int val;
478 int ret; 499 int ret;
479 500
480 if (!cs35l56_base->init_done) 501 if (!cs35l56_base->init_done)
481 return 0; 502 return 0;
482 503
483 /* Firmware must have entered a power- 504 /* Firmware must have entered a power-save state */
484 ret = regmap_read_poll_timeout(cs35l56 505 ret = regmap_read_poll_timeout(cs35l56_base->regmap,
485 CS35L56 506 CS35L56_TRANSDUCER_ACTUAL_PS,
486 val, (v 507 val, (val >= CS35L56_PS3),
487 CS35L56 508 CS35L56_PS3_POLL_US,
488 CS35L56 509 CS35L56_PS3_TIMEOUT_US);
489 if (ret) 510 if (ret)
490 dev_warn(cs35l56_base->dev, "P 511 dev_warn(cs35l56_base->dev, "PS3 wait failed: %d\n", ret);
491 512
492 /* Clear BOOT_DONE so it can be used t 513 /* Clear BOOT_DONE so it can be used to detect a reboot */
493 regmap_write(cs35l56_base->regmap, CS3 514 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, CS35L56_OTP_BOOT_DONE_MASK);
494 515
495 if (!cs35l56_base->can_hibernate) { 516 if (!cs35l56_base->can_hibernate) {
496 regcache_cache_only(cs35l56_ba 517 regcache_cache_only(cs35l56_base->regmap, true);
497 dev_dbg(cs35l56_base->dev, "Su 518 dev_dbg(cs35l56_base->dev, "Suspended: no hibernate");
498 519
499 return 0; 520 return 0;
500 } 521 }
501 522
502 /* 523 /*
503 * Must enter cache-only first so ther 524 * Must enter cache-only first so there can't be any more register
504 * accesses other than the controlled 525 * accesses other than the controlled hibernate sequence below.
505 */ 526 */
506 regcache_cache_only(cs35l56_base->regm 527 regcache_cache_only(cs35l56_base->regmap, true);
507 528
508 regmap_multi_reg_write_bypassed(cs35l5 529 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
509 cs35l5 530 cs35l56_hibernate_seq,
510 ARRAY_ 531 ARRAY_SIZE(cs35l56_hibernate_seq));
511 532
512 dev_dbg(cs35l56_base->dev, "Suspended: 533 dev_dbg(cs35l56_base->dev, "Suspended: hibernate");
513 534
514 return 0; 535 return 0;
515 } 536 }
516 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend_c 537 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend_common, SND_SOC_CS35L56_SHARED);
517 538
518 int cs35l56_runtime_resume_common(struct cs35l 539 int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire)
519 { 540 {
520 unsigned int val; 541 unsigned int val;
521 int ret; 542 int ret;
522 543
523 if (!cs35l56_base->init_done) 544 if (!cs35l56_base->init_done)
524 return 0; 545 return 0;
525 546
526 if (!cs35l56_base->can_hibernate) 547 if (!cs35l56_base->can_hibernate)
527 goto out_sync; 548 goto out_sync;
528 549
529 /* Must be done before releasing cache 550 /* Must be done before releasing cache-only */
530 if (!is_soundwire) 551 if (!is_soundwire)
531 cs35l56_issue_wake_event(cs35l 552 cs35l56_issue_wake_event(cs35l56_base);
532 553
533 out_sync: 554 out_sync:
534 ret = cs35l56_wait_for_firmware_boot(c 555 ret = cs35l56_wait_for_firmware_boot(cs35l56_base);
535 if (ret) { 556 if (ret) {
536 dev_err(cs35l56_base->dev, "Hi 557 dev_err(cs35l56_base->dev, "Hibernate wake failed: %d\n", ret);
537 goto err; 558 goto err;
538 } 559 }
539 560
540 regcache_cache_only(cs35l56_base->regm 561 regcache_cache_only(cs35l56_base->regmap, false);
541 562
542 ret = cs35l56_mbox_send(cs35l56_base, 563 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE);
543 if (ret) 564 if (ret)
544 goto err; 565 goto err;
545 566
546 /* BOOT_DONE will be 1 if the amp rese 567 /* BOOT_DONE will be 1 if the amp reset */
547 regmap_read(cs35l56_base->regmap, CS35 568 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, &val);
548 if (val & CS35L56_OTP_BOOT_DONE_MASK) 569 if (val & CS35L56_OTP_BOOT_DONE_MASK) {
549 dev_dbg(cs35l56_base->dev, "Re 570 dev_dbg(cs35l56_base->dev, "Registers reset in suspend\n");
550 regcache_mark_dirty(cs35l56_ba 571 regcache_mark_dirty(cs35l56_base->regmap);
551 } 572 }
552 573
553 regcache_sync(cs35l56_base->regmap); 574 regcache_sync(cs35l56_base->regmap);
554 575
555 dev_dbg(cs35l56_base->dev, "Resumed"); 576 dev_dbg(cs35l56_base->dev, "Resumed");
556 577
557 return 0; 578 return 0;
558 579
559 err: 580 err:
560 regcache_cache_only(cs35l56_base->regm 581 regcache_cache_only(cs35l56_base->regmap, true);
561 582
562 regmap_multi_reg_write_bypassed(cs35l5 583 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
563 cs35l5 584 cs35l56_hibernate_seq,
564 ARRAY_ 585 ARRAY_SIZE(cs35l56_hibernate_seq));
565 586
566 return ret; 587 return ret;
567 } 588 }
568 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_co 589 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, SND_SOC_CS35L56_SHARED);
569 590
570 static const struct cs_dsp_region cs35l56_dsp1 591 static const struct cs_dsp_region cs35l56_dsp1_regions[] = {
571 { .type = WMFW_HALO_PM_PACKED, .base 592 { .type = WMFW_HALO_PM_PACKED, .base = CS35L56_DSP1_PMEM_0 },
572 { .type = WMFW_HALO_XM_PACKED, .base 593 { .type = WMFW_HALO_XM_PACKED, .base = CS35L56_DSP1_XMEM_PACKED_0 },
573 { .type = WMFW_HALO_YM_PACKED, .base 594 { .type = WMFW_HALO_YM_PACKED, .base = CS35L56_DSP1_YMEM_PACKED_0 },
574 { .type = WMFW_ADSP2_XM, .base 595 { .type = WMFW_ADSP2_XM, .base = CS35L56_DSP1_XMEM_UNPACKED24_0 },
575 { .type = WMFW_ADSP2_YM, .base 596 { .type = WMFW_ADSP2_YM, .base = CS35L56_DSP1_YMEM_UNPACKED24_0 },
576 }; 597 };
577 598
578 void cs35l56_init_cs_dsp(struct cs35l56_base * 599 void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp)
579 { 600 {
580 cs_dsp->num = 1; 601 cs_dsp->num = 1;
581 cs_dsp->type = WMFW_HALO; 602 cs_dsp->type = WMFW_HALO;
582 cs_dsp->rev = 0; 603 cs_dsp->rev = 0;
583 cs_dsp->dev = cs35l56_base->dev; 604 cs_dsp->dev = cs35l56_base->dev;
584 cs_dsp->regmap = cs35l56_base->regmap; 605 cs_dsp->regmap = cs35l56_base->regmap;
585 cs_dsp->base = CS35L56_DSP1_CORE_BASE; 606 cs_dsp->base = CS35L56_DSP1_CORE_BASE;
586 cs_dsp->base_sysinfo = CS35L56_DSP1_SY 607 cs_dsp->base_sysinfo = CS35L56_DSP1_SYS_INFO_ID;
587 cs_dsp->mem = cs35l56_dsp1_regions; 608 cs_dsp->mem = cs35l56_dsp1_regions;
588 cs_dsp->num_mems = ARRAY_SIZE(cs35l56_ 609 cs_dsp->num_mems = ARRAY_SIZE(cs35l56_dsp1_regions);
589 cs_dsp->no_core_startstop = true; 610 cs_dsp->no_core_startstop = true;
590 } 611 }
591 EXPORT_SYMBOL_NS_GPL(cs35l56_init_cs_dsp, SND_ 612 EXPORT_SYMBOL_NS_GPL(cs35l56_init_cs_dsp, SND_SOC_CS35L56_SHARED);
592 613
593 struct cs35l56_pte { 614 struct cs35l56_pte {
594 u8 x; 615 u8 x;
595 u8 wafer_id; 616 u8 wafer_id;
596 u8 pte[2]; 617 u8 pte[2];
597 u8 lot[3]; 618 u8 lot[3];
598 u8 y; 619 u8 y;
599 u8 unused[3]; 620 u8 unused[3];
600 u8 dvs; 621 u8 dvs;
601 } __packed; 622 } __packed;
602 static_assert((sizeof(struct cs35l56_pte) % si 623 static_assert((sizeof(struct cs35l56_pte) % sizeof(u32)) == 0);
603 624
604 static int cs35l56_read_silicon_uid(struct cs3 625 static int cs35l56_read_silicon_uid(struct cs35l56_base *cs35l56_base, u64 *uid)
605 { 626 {
606 struct cs35l56_pte pte; 627 struct cs35l56_pte pte;
607 u64 unique_id; 628 u64 unique_id;
608 int ret; 629 int ret;
609 630
610 ret = regmap_raw_read(cs35l56_base->re 631 ret = regmap_raw_read(cs35l56_base->regmap, CS35L56_OTP_MEM_53, &pte, sizeof(pte));
611 if (ret) { 632 if (ret) {
612 dev_err(cs35l56_base->dev, "Fa 633 dev_err(cs35l56_base->dev, "Failed to read OTP: %d\n", ret);
613 return ret; 634 return ret;
614 } 635 }
615 636
616 unique_id = (u32)pte.lot[2] | ((u32)pt 637 unique_id = (u32)pte.lot[2] | ((u32)pte.lot[1] << 8) | ((u32)pte.lot[0] << 16);
617 unique_id <<= 32; 638 unique_id <<= 32;
618 unique_id |= (u32)pte.x | ((u32)pte.y 639 unique_id |= (u32)pte.x | ((u32)pte.y << 8) | ((u32)pte.wafer_id << 16) |
619 ((u32)pte.dvs << 24); 640 ((u32)pte.dvs << 24);
620 641
621 dev_dbg(cs35l56_base->dev, "UniqueID = 642 dev_dbg(cs35l56_base->dev, "UniqueID = %#llx\n", unique_id);
622 643
623 *uid = unique_id; 644 *uid = unique_id;
624 645
625 return 0; 646 return 0;
626 } 647 }
627 648
628 /* Firmware calibration controls */ 649 /* Firmware calibration controls */
629 const struct cirrus_amp_cal_controls cs35l56_c 650 const struct cirrus_amp_cal_controls cs35l56_calibration_controls = {
630 .alg_id = 0x9f210, 651 .alg_id = 0x9f210,
631 .mem_region = WMFW_ADSP2_YM, 652 .mem_region = WMFW_ADSP2_YM,
632 .ambient = "CAL_AMBIENT", 653 .ambient = "CAL_AMBIENT",
633 .calr = "CAL_R", 654 .calr = "CAL_R",
634 .status = "CAL_STATUS", 655 .status = "CAL_STATUS",
635 .checksum = "CAL_CHECKSUM", 656 .checksum = "CAL_CHECKSUM",
636 }; 657 };
637 EXPORT_SYMBOL_NS_GPL(cs35l56_calibration_contr 658 EXPORT_SYMBOL_NS_GPL(cs35l56_calibration_controls, SND_SOC_CS35L56_SHARED);
638 659
639 int cs35l56_get_calibration(struct cs35l56_bas 660 int cs35l56_get_calibration(struct cs35l56_base *cs35l56_base)
640 { 661 {
641 u64 silicon_uid = 0; 662 u64 silicon_uid = 0;
642 int ret; 663 int ret;
643 664
644 /* Driver can't apply calibration to a 665 /* Driver can't apply calibration to a secured part, so skip */
645 if (cs35l56_base->secured) 666 if (cs35l56_base->secured)
646 return 0; 667 return 0;
647 668
648 ret = cs35l56_read_silicon_uid(cs35l56 669 ret = cs35l56_read_silicon_uid(cs35l56_base, &silicon_uid);
649 if (ret < 0) 670 if (ret < 0)
650 return ret; 671 return ret;
651 672
652 ret = cs_amp_get_efi_calibration_data( 673 ret = cs_amp_get_efi_calibration_data(cs35l56_base->dev, silicon_uid,
653 674 cs35l56_base->cal_index,
654 675 &cs35l56_base->cal_data);
655 676
656 /* Only return an error status if prob 677 /* Only return an error status if probe should be aborted */
657 if ((ret == -ENOENT) || (ret == -EOVER 678 if ((ret == -ENOENT) || (ret == -EOVERFLOW))
658 return 0; 679 return 0;
659 680
660 if (ret < 0) 681 if (ret < 0)
661 return ret; 682 return ret;
662 683
663 cs35l56_base->cal_data_valid = true; 684 cs35l56_base->cal_data_valid = true;
664 685
665 return 0; 686 return 0;
666 } 687 }
667 EXPORT_SYMBOL_NS_GPL(cs35l56_get_calibration, 688 EXPORT_SYMBOL_NS_GPL(cs35l56_get_calibration, SND_SOC_CS35L56_SHARED);
668 689
669 int cs35l56_read_prot_status(struct cs35l56_ba 690 int cs35l56_read_prot_status(struct cs35l56_base *cs35l56_base,
670 bool *fw_missing, 691 bool *fw_missing, unsigned int *fw_version)
671 { 692 {
672 unsigned int prot_status; 693 unsigned int prot_status;
673 int ret; 694 int ret;
674 695
675 ret = regmap_read(cs35l56_base->regmap 696 ret = regmap_read(cs35l56_base->regmap, CS35L56_PROTECTION_STATUS, &prot_status);
676 if (ret) { 697 if (ret) {
677 dev_err(cs35l56_base->dev, "Ge 698 dev_err(cs35l56_base->dev, "Get PROTECTION_STATUS failed: %d\n", ret);
678 return ret; 699 return ret;
679 } 700 }
680 701
681 *fw_missing = !!(prot_status & CS35L56 702 *fw_missing = !!(prot_status & CS35L56_FIRMWARE_MISSING);
682 703
683 ret = regmap_read(cs35l56_base->regmap 704 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP1_FW_VER, fw_version);
684 if (ret) { 705 if (ret) {
685 dev_err(cs35l56_base->dev, "Ge 706 dev_err(cs35l56_base->dev, "Get FW VER failed: %d\n", ret);
686 return ret; 707 return ret;
687 } 708 }
688 709
689 return 0; 710 return 0;
690 } 711 }
691 EXPORT_SYMBOL_NS_GPL(cs35l56_read_prot_status, 712 EXPORT_SYMBOL_NS_GPL(cs35l56_read_prot_status, SND_SOC_CS35L56_SHARED);
692 713
693 int cs35l56_hw_init(struct cs35l56_base *cs35l 714 int cs35l56_hw_init(struct cs35l56_base *cs35l56_base)
694 { 715 {
695 int ret; 716 int ret;
696 unsigned int devid, revid, otpid, secu 717 unsigned int devid, revid, otpid, secured, fw_ver;
697 bool fw_missing; 718 bool fw_missing;
698 719
699 /* 720 /*
700 * When the system is not using a rese 721 * When the system is not using a reset_gpio ensure the device is
701 * awake, otherwise the device has jus 722 * awake, otherwise the device has just been released from reset and
702 * the driver must wait for the contro 723 * the driver must wait for the control port to become usable.
703 */ 724 */
704 if (!cs35l56_base->reset_gpio) 725 if (!cs35l56_base->reset_gpio)
705 cs35l56_issue_wake_event(cs35l 726 cs35l56_issue_wake_event(cs35l56_base);
706 else 727 else
707 cs35l56_wait_control_port_read 728 cs35l56_wait_control_port_ready();
708 729
>> 730 /*
>> 731 * The HALO_STATE register is in different locations on Ax and B0
>> 732 * devices so the REVID needs to be determined before waiting for the
>> 733 * firmware to boot.
>> 734 */
709 ret = regmap_read_bypassed(cs35l56_bas 735 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_REVID, &revid);
710 if (ret < 0) { 736 if (ret < 0) {
711 dev_err(cs35l56_base->dev, "Ge 737 dev_err(cs35l56_base->dev, "Get Revision ID failed\n");
712 return ret; 738 return ret;
713 } 739 }
714 cs35l56_base->rev = revid & (CS35L56_A 740 cs35l56_base->rev = revid & (CS35L56_AREVID_MASK | CS35L56_MTLREVID_MASK);
715 741
716 ret = cs35l56_wait_for_firmware_boot(c 742 ret = cs35l56_wait_for_firmware_boot(cs35l56_base);
717 if (ret) 743 if (ret)
718 return ret; 744 return ret;
719 745
720 ret = regmap_read_bypassed(cs35l56_bas 746 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_DEVID, &devid);
721 if (ret < 0) { 747 if (ret < 0) {
722 dev_err(cs35l56_base->dev, "Ge 748 dev_err(cs35l56_base->dev, "Get Device ID failed\n");
723 return ret; 749 return ret;
724 } 750 }
725 devid &= CS35L56_DEVID_MASK; 751 devid &= CS35L56_DEVID_MASK;
726 752
727 switch (devid) { 753 switch (devid) {
728 case 0x35A54: 754 case 0x35A54:
729 case 0x35A56: 755 case 0x35A56:
730 case 0x35A57: 756 case 0x35A57:
731 break; 757 break;
732 default: 758 default:
733 dev_err(cs35l56_base->dev, "Un 759 dev_err(cs35l56_base->dev, "Unknown device %x\n", devid);
734 return ret; 760 return ret;
735 } 761 }
736 762
737 cs35l56_base->type = devid & 0xFF; 763 cs35l56_base->type = devid & 0xFF;
738 764
739 /* Silicon is now identified and boote 765 /* Silicon is now identified and booted so exit cache-only */
740 regcache_cache_only(cs35l56_base->regm 766 regcache_cache_only(cs35l56_base->regmap, false);
741 767
742 ret = regmap_read(cs35l56_base->regmap 768 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP_RESTRICT_STS1, &secured);
743 if (ret) { 769 if (ret) {
744 dev_err(cs35l56_base->dev, "Ge 770 dev_err(cs35l56_base->dev, "Get Secure status failed\n");
745 return ret; 771 return ret;
746 } 772 }
747 773
748 /* When any bus is restricted treat th 774 /* When any bus is restricted treat the device as secured */
749 if (secured & CS35L56_RESTRICTED_MASK) 775 if (secured & CS35L56_RESTRICTED_MASK)
750 cs35l56_base->secured = true; 776 cs35l56_base->secured = true;
751 777
752 ret = regmap_read(cs35l56_base->regmap 778 ret = regmap_read(cs35l56_base->regmap, CS35L56_OTPID, &otpid);
753 if (ret < 0) { 779 if (ret < 0) {
754 dev_err(cs35l56_base->dev, "Ge 780 dev_err(cs35l56_base->dev, "Get OTP ID failed\n");
755 return ret; 781 return ret;
756 } 782 }
757 783
758 ret = cs35l56_read_prot_status(cs35l56 784 ret = cs35l56_read_prot_status(cs35l56_base, &fw_missing, &fw_ver);
759 if (ret) 785 if (ret)
760 return ret; 786 return ret;
761 787
762 dev_info(cs35l56_base->dev, "Cirrus Lo 788 dev_info(cs35l56_base->dev, "Cirrus Logic CS35L%02X%s Rev %02X OTP%d fw:%d.%d.%d (patched=%u)\n",
763 cs35l56_base->type, cs35l56_b 789 cs35l56_base->type, cs35l56_base->secured ? "s" : "", cs35l56_base->rev, otpid,
764 fw_ver >> 16, (fw_ver >> 8) & 790 fw_ver >> 16, (fw_ver >> 8) & 0xff, fw_ver & 0xff, !fw_missing);
765 791
766 /* Wake source and *_BLOCKED interrupt 792 /* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */
767 regmap_write(cs35l56_base->regmap, CS3 793 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff);
768 regmap_update_bits(cs35l56_base->regma 794 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1,
769 CS35L56_AMP_SHORT_E 795 CS35L56_AMP_SHORT_ERR_EINT1_MASK,
770 0); 796 0);
771 regmap_update_bits(cs35l56_base->regma 797 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8,
772 CS35L56_TEMP_ERR_EI 798 CS35L56_TEMP_ERR_EINT1_MASK,
773 0); 799 0);
774 800
775 return 0; 801 return 0;
776 } 802 }
777 EXPORT_SYMBOL_NS_GPL(cs35l56_hw_init, SND_SOC_ 803 EXPORT_SYMBOL_NS_GPL(cs35l56_hw_init, SND_SOC_CS35L56_SHARED);
778 804
779 int cs35l56_get_speaker_id(struct cs35l56_base 805 int cs35l56_get_speaker_id(struct cs35l56_base *cs35l56_base)
780 { 806 {
781 struct gpio_descs *descs; 807 struct gpio_descs *descs;
782 u32 speaker_id; !! 808 int speaker_id;
783 int i, ret; 809 int i, ret;
784 810
785 /* Attempt to read the speaker type fr <<
786 ret = device_property_read_u32(cs35l56 <<
787 if (!ret) { <<
788 dev_dbg(cs35l56_base->dev, "Sp <<
789 return speaker_id; <<
790 } <<
791 <<
792 /* Read the speaker type qualifier fro 811 /* Read the speaker type qualifier from the motherboard GPIOs */
793 descs = gpiod_get_array_optional(cs35l 812 descs = gpiod_get_array_optional(cs35l56_base->dev, "spk-id", GPIOD_IN);
794 if (!descs) { 813 if (!descs) {
795 return -ENOENT; 814 return -ENOENT;
796 } else if (IS_ERR(descs)) { 815 } else if (IS_ERR(descs)) {
797 ret = PTR_ERR(descs); 816 ret = PTR_ERR(descs);
798 return dev_err_probe(cs35l56_b 817 return dev_err_probe(cs35l56_base->dev, ret, "Failed to get spk-id-gpios\n");
799 } 818 }
800 819
801 speaker_id = 0; 820 speaker_id = 0;
802 for (i = 0; i < descs->ndescs; i++) { 821 for (i = 0; i < descs->ndescs; i++) {
803 ret = gpiod_get_value_cansleep 822 ret = gpiod_get_value_cansleep(descs->desc[i]);
804 if (ret < 0) { 823 if (ret < 0) {
805 dev_err_probe(cs35l56_ 824 dev_err_probe(cs35l56_base->dev, ret, "Failed to read spk-id[%d]\n", i);
806 goto err; 825 goto err;
807 } 826 }
808 827
809 speaker_id |= (ret << i); 828 speaker_id |= (ret << i);
810 } 829 }
811 830
812 dev_dbg(cs35l56_base->dev, "Speaker ID 831 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id);
813 ret = speaker_id; 832 ret = speaker_id;
814 err: 833 err:
815 gpiod_put_array(descs); 834 gpiod_put_array(descs);
816 835
817 return ret; 836 return ret;
818 } 837 }
819 EXPORT_SYMBOL_NS_GPL(cs35l56_get_speaker_id, S 838 EXPORT_SYMBOL_NS_GPL(cs35l56_get_speaker_id, SND_SOC_CS35L56_SHARED);
820 839
821 static const u32 cs35l56_bclk_valid_for_pll_fr 840 static const u32 cs35l56_bclk_valid_for_pll_freq_table[] = {
822 [0x0C] = 128000, 841 [0x0C] = 128000,
823 [0x0F] = 256000, 842 [0x0F] = 256000,
824 [0x11] = 384000, 843 [0x11] = 384000,
825 [0x12] = 512000, 844 [0x12] = 512000,
826 [0x15] = 768000, 845 [0x15] = 768000,
827 [0x17] = 1024000, 846 [0x17] = 1024000,
828 [0x1A] = 1500000, 847 [0x1A] = 1500000,
829 [0x1B] = 1536000, 848 [0x1B] = 1536000,
830 [0x1C] = 2000000, 849 [0x1C] = 2000000,
831 [0x1D] = 2048000, 850 [0x1D] = 2048000,
832 [0x1E] = 2400000, 851 [0x1E] = 2400000,
833 [0x20] = 3000000, 852 [0x20] = 3000000,
834 [0x21] = 3072000, 853 [0x21] = 3072000,
835 [0x23] = 4000000, 854 [0x23] = 4000000,
836 [0x24] = 4096000, 855 [0x24] = 4096000,
837 [0x25] = 4800000, 856 [0x25] = 4800000,
838 [0x27] = 6000000, 857 [0x27] = 6000000,
839 [0x28] = 6144000, 858 [0x28] = 6144000,
840 [0x29] = 6250000, 859 [0x29] = 6250000,
841 [0x2A] = 6400000, 860 [0x2A] = 6400000,
842 [0x2E] = 8000000, 861 [0x2E] = 8000000,
843 [0x2F] = 8192000, 862 [0x2F] = 8192000,
844 [0x30] = 9600000, 863 [0x30] = 9600000,
845 [0x32] = 12000000, 864 [0x32] = 12000000,
846 [0x33] = 12288000, 865 [0x33] = 12288000,
847 [0x37] = 13500000, 866 [0x37] = 13500000,
848 [0x38] = 19200000, 867 [0x38] = 19200000,
849 [0x39] = 22579200, 868 [0x39] = 22579200,
850 [0x3B] = 24576000, 869 [0x3B] = 24576000,
851 }; 870 };
852 871
853 int cs35l56_get_bclk_freq_id(unsigned int freq 872 int cs35l56_get_bclk_freq_id(unsigned int freq)
854 { 873 {
855 int i; 874 int i;
856 875
857 if (freq == 0) 876 if (freq == 0)
858 return -EINVAL; 877 return -EINVAL;
859 878
860 /* The BCLK frequency must be a valid 879 /* The BCLK frequency must be a valid PLL REFCLK */
861 for (i = 0; i < ARRAY_SIZE(cs35l56_bcl 880 for (i = 0; i < ARRAY_SIZE(cs35l56_bclk_valid_for_pll_freq_table); ++i) {
862 if (cs35l56_bclk_valid_for_pll 881 if (cs35l56_bclk_valid_for_pll_freq_table[i] == freq)
863 return i; 882 return i;
864 } 883 }
865 884
866 return -EINVAL; 885 return -EINVAL;
867 } 886 }
868 EXPORT_SYMBOL_NS_GPL(cs35l56_get_bclk_freq_id, 887 EXPORT_SYMBOL_NS_GPL(cs35l56_get_bclk_freq_id, SND_SOC_CS35L56_SHARED);
869 888
870 static const char * const cs35l56_supplies[/* 889 static const char * const cs35l56_supplies[/* auto-sized */] = {
871 "VDD_P", 890 "VDD_P",
872 "VDD_IO", 891 "VDD_IO",
873 "VDD_A", 892 "VDD_A",
874 }; 893 };
875 894
876 void cs35l56_fill_supply_names(struct regulato 895 void cs35l56_fill_supply_names(struct regulator_bulk_data *data)
877 { 896 {
878 int i; 897 int i;
879 898
880 BUILD_BUG_ON(ARRAY_SIZE(cs35l56_suppli 899 BUILD_BUG_ON(ARRAY_SIZE(cs35l56_supplies) != CS35L56_NUM_BULK_SUPPLIES);
881 for (i = 0; i < ARRAY_SIZE(cs35l56_sup 900 for (i = 0; i < ARRAY_SIZE(cs35l56_supplies); i++)
882 data[i].supply = cs35l56_suppl 901 data[i].supply = cs35l56_supplies[i];
883 } 902 }
884 EXPORT_SYMBOL_NS_GPL(cs35l56_fill_supply_names 903 EXPORT_SYMBOL_NS_GPL(cs35l56_fill_supply_names, SND_SOC_CS35L56_SHARED);
885 904
886 const char * const cs35l56_tx_input_texts[] = 905 const char * const cs35l56_tx_input_texts[] = {
887 "None", "ASP1RX1", "ASP1RX2", "VMON", 906 "None", "ASP1RX1", "ASP1RX2", "VMON", "IMON", "ERRVOL", "CLASSH",
888 "VDDBMON", "VBSTMON", "DSP1TX1", "DSP1 907 "VDDBMON", "VBSTMON", "DSP1TX1", "DSP1TX2", "DSP1TX3", "DSP1TX4",
889 "DSP1TX5", "DSP1TX6", "DSP1TX7", "DSP1 908 "DSP1TX5", "DSP1TX6", "DSP1TX7", "DSP1TX8", "TEMPMON",
890 "INTERPOLATOR", "SDW1RX1", "SDW1RX2", 909 "INTERPOLATOR", "SDW1RX1", "SDW1RX2",
891 }; 910 };
892 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_texts, S 911 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_texts, SND_SOC_CS35L56_SHARED);
893 912
894 const unsigned int cs35l56_tx_input_values[] = 913 const unsigned int cs35l56_tx_input_values[] = {
895 CS35L56_INPUT_SRC_NONE, 914 CS35L56_INPUT_SRC_NONE,
896 CS35L56_INPUT_SRC_ASP1RX1, 915 CS35L56_INPUT_SRC_ASP1RX1,
897 CS35L56_INPUT_SRC_ASP1RX2, 916 CS35L56_INPUT_SRC_ASP1RX2,
898 CS35L56_INPUT_SRC_VMON, 917 CS35L56_INPUT_SRC_VMON,
899 CS35L56_INPUT_SRC_IMON, 918 CS35L56_INPUT_SRC_IMON,
900 CS35L56_INPUT_SRC_ERR_VOL, 919 CS35L56_INPUT_SRC_ERR_VOL,
901 CS35L56_INPUT_SRC_CLASSH, 920 CS35L56_INPUT_SRC_CLASSH,
902 CS35L56_INPUT_SRC_VDDBMON, 921 CS35L56_INPUT_SRC_VDDBMON,
903 CS35L56_INPUT_SRC_VBSTMON, 922 CS35L56_INPUT_SRC_VBSTMON,
904 CS35L56_INPUT_SRC_DSP1TX1, 923 CS35L56_INPUT_SRC_DSP1TX1,
905 CS35L56_INPUT_SRC_DSP1TX2, 924 CS35L56_INPUT_SRC_DSP1TX2,
906 CS35L56_INPUT_SRC_DSP1TX3, 925 CS35L56_INPUT_SRC_DSP1TX3,
907 CS35L56_INPUT_SRC_DSP1TX4, 926 CS35L56_INPUT_SRC_DSP1TX4,
908 CS35L56_INPUT_SRC_DSP1TX5, 927 CS35L56_INPUT_SRC_DSP1TX5,
909 CS35L56_INPUT_SRC_DSP1TX6, 928 CS35L56_INPUT_SRC_DSP1TX6,
910 CS35L56_INPUT_SRC_DSP1TX7, 929 CS35L56_INPUT_SRC_DSP1TX7,
911 CS35L56_INPUT_SRC_DSP1TX8, 930 CS35L56_INPUT_SRC_DSP1TX8,
912 CS35L56_INPUT_SRC_TEMPMON, 931 CS35L56_INPUT_SRC_TEMPMON,
913 CS35L56_INPUT_SRC_INTERPOLATOR, 932 CS35L56_INPUT_SRC_INTERPOLATOR,
914 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1, 933 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1,
915 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2, 934 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2,
916 }; 935 };
917 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_values, 936 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_values, SND_SOC_CS35L56_SHARED);
918 937
919 const struct regmap_config cs35l56_regmap_i2c !! 938 struct regmap_config cs35l56_regmap_i2c = {
920 .reg_bits = 32, 939 .reg_bits = 32,
921 .val_bits = 32, 940 .val_bits = 32,
922 .reg_stride = 4, 941 .reg_stride = 4,
923 .reg_format_endian = REGMAP_ENDIAN_BIG 942 .reg_format_endian = REGMAP_ENDIAN_BIG,
924 .val_format_endian = REGMAP_ENDIAN_BIG 943 .val_format_endian = REGMAP_ENDIAN_BIG,
925 .max_register = CS35L56_DSP1_PMEM_5114 944 .max_register = CS35L56_DSP1_PMEM_5114,
926 .reg_defaults = cs35l56_reg_defaults, 945 .reg_defaults = cs35l56_reg_defaults,
927 .num_reg_defaults = ARRAY_SIZE(cs35l56 946 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
928 .volatile_reg = cs35l56_volatile_reg, 947 .volatile_reg = cs35l56_volatile_reg,
929 .readable_reg = cs35l56_readable_reg, 948 .readable_reg = cs35l56_readable_reg,
930 .precious_reg = cs35l56_precious_reg, 949 .precious_reg = cs35l56_precious_reg,
931 .cache_type = REGCACHE_MAPLE, 950 .cache_type = REGCACHE_MAPLE,
932 }; 951 };
933 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_i2c, SND_S 952 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_i2c, SND_SOC_CS35L56_SHARED);
934 953
935 const struct regmap_config cs35l56_regmap_spi !! 954 struct regmap_config cs35l56_regmap_spi = {
936 .reg_bits = 32, 955 .reg_bits = 32,
937 .val_bits = 32, 956 .val_bits = 32,
938 .pad_bits = 16, 957 .pad_bits = 16,
939 .reg_stride = 4, 958 .reg_stride = 4,
940 .reg_format_endian = REGMAP_ENDIAN_BIG 959 .reg_format_endian = REGMAP_ENDIAN_BIG,
941 .val_format_endian = REGMAP_ENDIAN_BIG 960 .val_format_endian = REGMAP_ENDIAN_BIG,
942 .max_register = CS35L56_DSP1_PMEM_5114 961 .max_register = CS35L56_DSP1_PMEM_5114,
943 .reg_defaults = cs35l56_reg_defaults, 962 .reg_defaults = cs35l56_reg_defaults,
944 .num_reg_defaults = ARRAY_SIZE(cs35l56 963 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
945 .volatile_reg = cs35l56_volatile_reg, 964 .volatile_reg = cs35l56_volatile_reg,
946 .readable_reg = cs35l56_readable_reg, 965 .readable_reg = cs35l56_readable_reg,
947 .precious_reg = cs35l56_precious_reg, 966 .precious_reg = cs35l56_precious_reg,
948 .cache_type = REGCACHE_MAPLE, 967 .cache_type = REGCACHE_MAPLE,
949 }; 968 };
950 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_spi, SND_S 969 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_spi, SND_SOC_CS35L56_SHARED);
951 970
952 const struct regmap_config cs35l56_regmap_sdw !! 971 struct regmap_config cs35l56_regmap_sdw = {
953 .reg_bits = 32, 972 .reg_bits = 32,
954 .val_bits = 32, 973 .val_bits = 32,
955 .reg_stride = 4, 974 .reg_stride = 4,
956 .reg_format_endian = REGMAP_ENDIAN_LIT 975 .reg_format_endian = REGMAP_ENDIAN_LITTLE,
957 .val_format_endian = REGMAP_ENDIAN_BIG 976 .val_format_endian = REGMAP_ENDIAN_BIG,
958 .max_register = CS35L56_DSP1_PMEM_5114 977 .max_register = CS35L56_DSP1_PMEM_5114,
959 .reg_defaults = cs35l56_reg_defaults, 978 .reg_defaults = cs35l56_reg_defaults,
960 .num_reg_defaults = ARRAY_SIZE(cs35l56 979 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
961 .volatile_reg = cs35l56_volatile_reg, 980 .volatile_reg = cs35l56_volatile_reg,
962 .readable_reg = cs35l56_readable_reg, 981 .readable_reg = cs35l56_readable_reg,
963 .precious_reg = cs35l56_precious_reg, 982 .precious_reg = cs35l56_precious_reg,
964 .cache_type = REGCACHE_MAPLE, 983 .cache_type = REGCACHE_MAPLE,
965 }; 984 };
966 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_sdw, SND_S 985 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_sdw, SND_SOC_CS35L56_SHARED);
967 986
968 MODULE_DESCRIPTION("ASoC CS35L56 Shared"); 987 MODULE_DESCRIPTION("ASoC CS35L56 Shared");
969 MODULE_AUTHOR("Richard Fitzgerald <rf@opensour 988 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
970 MODULE_AUTHOR("Simon Trimmer <simont@opensourc 989 MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>");
971 MODULE_LICENSE("GPL"); 990 MODULE_LICENSE("GPL");
972 MODULE_IMPORT_NS(SND_SOC_CS_AMP_LIB); 991 MODULE_IMPORT_NS(SND_SOC_CS_AMP_LIB);
973 992
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