1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 2 /* 3 * cs42l52.h -- CS42L52 ALSA SoC audio driver 4 * 5 * Copyright 2012 CirrusLogic, Inc. 6 * 7 * Author: Georgi Vlaev <joe@nucleusys.com> 8 * Author: Brian Austin <brian.austin@cirrus.c 9 */ 10 11 #ifndef __CS42L52_H__ 12 #define __CS42L52_H__ 13 14 #define CS42L52_NAME 15 #define CS42L52_DEFAULT_CLK 16 #define CS42L52_MIN_CLK 17 #define CS42L52_MAX_CLK 18 #define CS42L52_DEFAULT_FORMAT 19 #define CS42L52_DEFAULT_MAX_CHANS 20 #define CS42L52_SYSCLK 21 22 #define CS42L52_CHIP_SWICTH 23 #define CS42L52_ALL_IN_ONE 24 #define CS42L52_CHIP_ONE 25 #define CS42L52_CHIP_TWO 26 #define CS42L52_CHIP_THR 27 #define CS42L52_CHIP_MASK 28 29 #define CS42L52_FIX_BITS_CTL 30 #define CS42L52_CHIP 31 #define CS42L52_CHIP_ID 32 #define CS42L52_CHIP_ID_MASK 33 #define CS42L52_CHIP_REV_A0 34 #define CS42L52_CHIP_REV_A1 35 #define CS42L52_CHIP_REV_B0 36 #define CS42L52_CHIP_REV_MASK 37 38 #define CS42L52_PWRCTL1 39 #define CS42L52_PWRCTL1_PDN_ALL 40 #define CS42L52_PWRCTL1_PDN_CHRG 41 #define CS42L52_PWRCTL1_PDN_PGAB 42 #define CS42L52_PWRCTL1_PDN_PGAA 43 #define CS42L52_PWRCTL1_PDN_ADCB 44 #define CS42L52_PWRCTL1_PDN_ADCA 45 #define CS42L52_PWRCTL1_PDN_CODEC 46 47 #define CS42L52_PWRCTL2 48 #define CS42L52_PWRCTL2_OVRDB 49 #define CS42L52_PWRCTL2_OVRDA 50 #define CS42L52_PWRCTL2_PDN_MICB 51 #define CS42L52_PWRCTL2_PDN_MICB_SHIFT 52 #define CS42L52_PWRCTL2_PDN_MICA 53 #define CS42L52_PWRCTL2_PDN_MICA_SHIFT 54 #define CS42L52_PWRCTL2_PDN_MICBIAS 55 #define CS42L52_PWRCTL2_PDN_MICBIAS_SHIFT 56 57 #define CS42L52_PWRCTL3 58 #define CS42L52_PWRCTL3_HPB_PDN_SHIFT 59 #define CS42L52_PWRCTL3_HPB_ON_LOW 60 #define CS42L52_PWRCTL3_HPB_ON_HIGH 61 #define CS42L52_PWRCTL3_HPB_ALWAYS_ON 62 #define CS42L52_PWRCTL3_HPB_ALWAYS_OFF 63 #define CS42L52_PWRCTL3_HPA_PDN_SHIFT 64 #define CS42L52_PWRCTL3_HPA_ON_LOW 65 #define CS42L52_PWRCTL3_HPA_ON_HIGH 66 #define CS42L52_PWRCTL3_HPA_ALWAYS_ON 67 #define CS42L52_PWRCTL3_HPA_ALWAYS_OFF 68 #define CS42L52_PWRCTL3_SPKB_PDN_SHIFT 69 #define CS42L52_PWRCTL3_SPKB_ON_LOW 70 #define CS42L52_PWRCTL3_SPKB_ON_HIGH 71 #define CS42L52_PWRCTL3_SPKB_ALWAYS_ON 72 #define CS42L52_PWRCTL3_PDN_SPKB 73 #define CS42L52_PWRCTL3_PDN_SPKA 74 #define CS42L52_PWRCTL3_SPKA_PDN_SHIFT 75 #define CS42L52_PWRCTL3_SPKA_ON_LOW 76 #define CS42L52_PWRCTL3_SPKA_ON_HIGH 77 #define CS42L52_PWRCTL3_SPKA_ALWAYS_ON 78 79 #define CS42L52_DEFAULT_OUTPUT_STATE 80 #define CS42L52_PWRCTL3_CONF_MASK 81 82 #define CS42L52_CLK_CTL 83 #define CLK_AUTODECT_ENABLE 84 #define CLK_SPEED_SHIFT 85 #define CLK_DS_MODE 86 #define CLK_SS_MODE 87 #define CLK_HS_MODE 88 #define CLK_QS_MODE 89 #define CLK_32K_SR_SHIFT 90 #define CLK_32K 91 #define CLK_NO_32K 92 #define CLK_27M_MCLK_SHIFT 93 #define CLK_27M_MCLK 94 #define CLK_NO_27M 95 #define CLK_RATIO_SHIFT 96 #define CLK_R_128 97 #define CLK_R_125 98 #define CLK_R_132 99 #define CLK_R_136 100 101 #define CS42L52_IFACE_CTL1 102 #define CS42L52_IFACE_CTL1_MASTER 103 #define CS42L52_IFACE_CTL1_SLAVE 104 #define CS42L52_IFACE_CTL1_INV_SCLK 105 #define CS42L52_IFACE_CTL1_ADC_FMT_I2S 106 #define CS42L52_IFACE_CTL1_ADC_FMT_LEFT_J 107 #define CS42L52_IFACE_CTL1_DSP_MODE_EN 108 #define CS42L52_IFACE_CTL1_DAC_FMT_LEFT_J 109 #define CS42L52_IFACE_CTL1_DAC_FMT_I2S 110 #define CS42L52_IFACE_CTL1_DAC_FMT_RIGHT_J 111 #define CS42L52_IFACE_CTL1_WL_32BIT 112 #define CS42L52_IFACE_CTL1_WL_24BIT 113 #define CS42L52_IFACE_CTL1_WL_20BIT 114 #define CS42L52_IFACE_CTL1_WL_16BIT 115 #define CS42L52_IFACE_CTL1_WL_MASK 116 117 #define CS42L52_IFACE_CTL2 118 #define CS42L52_IFACE_CTL2_SC_MC_EQ 119 #define CS42L52_IFACE_CTL2_LOOPBACK 120 #define CS42L52_IFACE_CTL2_S_MODE_OUTPUT_EN 121 #define CS42L52_IFACE_CTL2_S_MODE_OUTPUT_HIZ 122 #define CS42L52_IFACE_CTL2_HP_SW_INV 123 #define CS42L52_IFACE_CTL2_BIAS_LVL 124 125 #define CS42L52_ADC_PGA_A 126 #define CS42L52_ADC_PGA_B 127 #define CS42L52_ADC_SEL_SHIFT 128 #define CS42L52_ADC_SEL_AIN1 129 #define CS42L52_ADC_SEL_AIN2 130 #define CS42L52_ADC_SEL_AIN3 131 #define CS42L52_ADC_SEL_AIN4 132 #define CS42L52_ADC_SEL_PGA 133 134 #define CS42L52_ANALOG_HPF_CTL 135 #define CS42L52_HPF_CTL_ANLGSFTB 136 #define CS42L52_HPF_CTL_ANLGSFTA 137 138 #define CS42L52_ADC_HPF_FREQ 139 #define CS42L52_ADC_MISC_CTL 140 #define CS42L52_ADC_MISC_CTL_SOURCE_DSP 141 142 #define CS42L52_PB_CTL1 143 #define CS42L52_PB_CTL1_HP_GAIN_SHIFT 144 #define CS42L52_PB_CTL1_HP_GAIN_03959 145 #define CS42L52_PB_CTL1_HP_GAIN_04571 146 #define CS42L52_PB_CTL1_HP_GAIN_05111 147 #define CS42L52_PB_CTL1_HP_GAIN_06047 148 #define CS42L52_PB_CTL1_HP_GAIN_07099 149 #define CS42L52_PB_CTL1_HP_GAIN_08399 150 #define CS42L52_PB_CTL1_HP_GAIN_10000 151 #define CS42L52_PB_CTL1_HP_GAIN_11430 152 #define CS42L52_PB_CTL1_INV_PCMB 153 #define CS42L52_PB_CTL1_INV_PCMA 154 #define CS42L52_PB_CTL1_MSTB_MUTE 155 #define CS42L52_PB_CTL1_MSTA_MUTE 156 #define CS42L52_PB_CTL1_MUTE_MASK 157 #define CS42L52_PB_CTL1_MUTE 158 #define CS42L52_PB_CTL1_UNMUTE 159 160 #define CS42L52_MISC_CTL 161 #define CS42L52_MISC_CTL_DEEMPH 162 #define CS42L52_MISC_CTL_DIGSFT 163 #define CS42L52_MISC_CTL_DIGZC 164 165 #define CS42L52_PB_CTL2 166 #define CS42L52_PB_CTL2_HPB_MUTE 167 #define CS42L52_PB_CTL2_HPA_MUTE 168 #define CS42L52_PB_CTL2_SPKB_MUTE 169 #define CS42L52_PB_CTL2_SPKA_MUTE 170 #define CS42L52_PB_CTL2_SPK_SWAP 171 #define CS42L52_PB_CTL2_SPK_MONO 172 #define CS42L52_PB_CTL2_SPK_MUTE50 173 174 #define CS42L52_MICA_CTL 175 #define CS42L52_MICB_CTL 176 #define CS42L52_MIC_CTL_MIC_SEL_MASK 177 #define CS42L52_MIC_CTL_MIC_SEL_SHIFT 178 #define CS42L52_MIC_CTL_TYPE_MASK 179 #define CS42L52_MIC_CTL_TYPE_SHIFT 180 181 182 #define CS42L52_PGAA_CTL 183 #define CS42L52_PGAB_CTL 184 #define CS42L52_PGAX_CTL_VOL_12DB 185 #define CS42L52_PGAX_CTL_VOL_6DB 186 187 #define CS42L52_PASSTHRUA_VOL 188 #define CS42L52_PASSTHRUB_VOL 189 190 #define CS42L52_ADCA_VOL 191 #define CS42L52_ADCB_VOL 192 #define CS42L52_ADCX_VOL_24DB 193 #define CS42L52_ADCX_VOL_12DB 194 #define CS42L52_ADCX_VOL_6DB 195 196 #define CS42L52_ADCA_MIXER_VOL 197 #define CS42L52_ADCB_MIXER_VOL 198 #define CS42L52_ADC_MIXER_VOL_12DB 199 200 #define CS42L52_PCMA_MIXER_VOL 201 #define CS42L52_PCMB_MIXER_VOL 202 203 #define CS42L52_BEEP_FREQ 204 #define CS42L52_BEEP_VOL 205 #define CS42L52_BEEP_TONE_CTL 206 #define CS42L52_BEEP_RATE_SHIFT 207 #define CS42L52_BEEP_RATE_MASK 208 209 #define CS42L52_TONE_CTL 210 #define CS42L52_BEEP_EN_MASK 211 212 #define CS42L52_MASTERA_VOL 213 #define CS42L52_MASTERB_VOL 214 215 #define CS42L52_HPA_VOL 216 #define CS42L52_HPB_VOL 217 #define CS42L52_DEFAULT_HP_VOL 218 219 #define CS42L52_SPKA_VOL 220 #define CS42L52_SPKB_VOL 221 #define CS42L52_DEFAULT_SPK_VOL 222 223 #define CS42L52_ADC_PCM_MIXER 224 225 #define CS42L52_LIMITER_CTL1 226 #define CS42L52_LIMITER_CTL2 227 #define CS42L52_LIMITER_AT_RATE 228 229 #define CS42L52_ALC_CTL 230 #define CS42L52_ALC_CTL_ALCB_ENABLE_SHIFT 231 #define CS42L52_ALC_CTL_ALCA_ENABLE_SHIFT 232 #define CS42L52_ALC_CTL_FASTEST_ATTACK 233 234 #define CS42L52_ALC_RATE 235 #define CS42L52_ALC_SLOWEST_RELEASE 236 237 #define CS42L52_ALC_THRESHOLD 238 #define CS42L52_ALC_MAX_RATE_SHIFT 239 #define CS42L52_ALC_MIN_RATE_SHIFT 240 #define CS42L52_ALC_RATE_0DB 241 #define CS42L52_ALC_RATE_3DB 242 #define CS42L52_ALC_RATE_6DB 243 244 #define CS42L52_NOISE_GATE_CTL 245 #define CS42L52_NG_ENABLE_SHIFT 246 #define CS42L52_NG_THRESHOLD_SHIFT 247 #define CS42L52_NG_MIN_70DB 248 #define CS42L52_NG_DELAY_SHIFT 249 #define CS42L52_NG_DELAY_100MS 250 251 #define CS42L52_CLK_STATUS 252 #define CS42L52_BATT_COMPEN 253 254 #define CS42L52_BATT_LEVEL 255 #define CS42L52_SPK_STATUS 256 #define CS42L52_SPK_STATUS_PIN_SHIFT 257 #define CS42L52_SPK_STATUS_PIN_HIGH 258 259 #define CS42L52_TEM_CTL 260 #define CS42L52_TEM_CTL_SET 261 #define CS42L52_THE_FOLDBACK 262 #define CS42L52_CHARGE_PUMP 263 #define CS42L52_CHARGE_PUMP_MASK 264 #define CS42L52_CHARGE_PUMP_SHIFT 265 #define CS42L52_FIX_BITS1 266 #define CS42L52_FIX_BITS2 267 268 #define CS42L52_MAX_REGISTER 269 270 #endif 271
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