1 // SPDX-License-Identifier: GPL-2.0-only <<
2 /* 1 /*
3 * cs42l56.c -- CS42L56 ALSA SoC audio driver 2 * cs42l56.c -- CS42L56 ALSA SoC audio driver
4 * 3 *
5 * Copyright 2014 CirrusLogic, Inc. 4 * Copyright 2014 CirrusLogic, Inc.
6 * 5 *
7 * Author: Brian Austin <brian.austin@cirrus.c 6 * Author: Brian Austin <brian.austin@cirrus.com>
>> 7 *
>> 8 * This program is free software; you can redistribute it and/or modify
>> 9 * it under the terms of the GNU General Public License version 2 as
>> 10 * published by the Free Software Foundation.
>> 11 *
8 */ 12 */
9 13
10 #include <linux/module.h> 14 #include <linux/module.h>
11 #include <linux/moduleparam.h> 15 #include <linux/moduleparam.h>
12 #include <linux/kernel.h> 16 #include <linux/kernel.h>
13 #include <linux/init.h> 17 #include <linux/init.h>
14 #include <linux/delay.h> 18 #include <linux/delay.h>
15 #include <linux/pm.h> 19 #include <linux/pm.h>
16 #include <linux/i2c.h> 20 #include <linux/i2c.h>
17 #include <linux/input.h> 21 #include <linux/input.h>
18 #include <linux/regmap.h> 22 #include <linux/regmap.h>
19 #include <linux/slab.h> 23 #include <linux/slab.h>
20 #include <linux/workqueue.h> 24 #include <linux/workqueue.h>
21 #include <linux/platform_device.h> 25 #include <linux/platform_device.h>
22 #include <linux/regulator/consumer.h> 26 #include <linux/regulator/consumer.h>
23 #include <linux/of.h> !! 27 #include <linux/of_device.h>
24 #include <linux/of_gpio.h> 28 #include <linux/of_gpio.h>
25 #include <sound/core.h> 29 #include <sound/core.h>
26 #include <sound/pcm.h> 30 #include <sound/pcm.h>
27 #include <sound/pcm_params.h> 31 #include <sound/pcm_params.h>
28 #include <sound/soc.h> 32 #include <sound/soc.h>
29 #include <sound/soc-dapm.h> 33 #include <sound/soc-dapm.h>
30 #include <sound/initval.h> 34 #include <sound/initval.h>
31 #include <sound/tlv.h> 35 #include <sound/tlv.h>
32 #include <sound/cs42l56.h> 36 #include <sound/cs42l56.h>
33 #include "cs42l56.h" 37 #include "cs42l56.h"
34 38
35 #define CS42L56_NUM_SUPPLIES 3 39 #define CS42L56_NUM_SUPPLIES 3
36 static const char *const cs42l56_supply_names[ 40 static const char *const cs42l56_supply_names[CS42L56_NUM_SUPPLIES] = {
37 "VA", 41 "VA",
38 "VCP", 42 "VCP",
39 "VLDO", 43 "VLDO",
40 }; 44 };
41 45
42 struct cs42l56_private { 46 struct cs42l56_private {
43 struct regmap *regmap; 47 struct regmap *regmap;
44 struct snd_soc_component *component; !! 48 struct snd_soc_codec *codec;
45 struct device *dev; 49 struct device *dev;
46 struct cs42l56_platform_data pdata; 50 struct cs42l56_platform_data pdata;
47 struct regulator_bulk_data supplies[CS 51 struct regulator_bulk_data supplies[CS42L56_NUM_SUPPLIES];
48 u32 mclk; 52 u32 mclk;
49 u8 mclk_prediv; 53 u8 mclk_prediv;
50 u8 mclk_div2; 54 u8 mclk_div2;
51 u8 mclk_ratio; 55 u8 mclk_ratio;
52 u8 iface; 56 u8 iface;
53 u8 iface_fmt; 57 u8 iface_fmt;
54 u8 iface_inv; 58 u8 iface_inv;
55 #if IS_ENABLED(CONFIG_INPUT) 59 #if IS_ENABLED(CONFIG_INPUT)
56 struct input_dev *beep; 60 struct input_dev *beep;
57 struct work_struct beep_work; 61 struct work_struct beep_work;
58 int beep_rate; 62 int beep_rate;
59 #endif 63 #endif
60 }; 64 };
61 65
62 static const struct reg_default cs42l56_reg_de 66 static const struct reg_default cs42l56_reg_defaults[] = {
>> 67 { 1, 0x56 }, /* r01 - ID 1 */
>> 68 { 2, 0x04 }, /* r02 - ID 2 */
63 { 3, 0x7f }, /* r03 - Power Ctl 1 69 { 3, 0x7f }, /* r03 - Power Ctl 1 */
64 { 4, 0xff }, /* r04 - Power Ctl 2 70 { 4, 0xff }, /* r04 - Power Ctl 2 */
65 { 5, 0x00 }, /* ro5 - Clocking Ctl 71 { 5, 0x00 }, /* ro5 - Clocking Ctl 1 */
66 { 6, 0x0b }, /* r06 - Clocking Ctl 72 { 6, 0x0b }, /* r06 - Clocking Ctl 2 */
67 { 7, 0x00 }, /* r07 - Serial Forma 73 { 7, 0x00 }, /* r07 - Serial Format */
68 { 8, 0x05 }, /* r08 - Class H Ctl 74 { 8, 0x05 }, /* r08 - Class H Ctl */
69 { 9, 0x0c }, /* r09 - Misc Ctl */ 75 { 9, 0x0c }, /* r09 - Misc Ctl */
70 { 10, 0x80 }, /* r0a - INT Status * 76 { 10, 0x80 }, /* r0a - INT Status */
71 { 11, 0x00 }, /* r0b - Playback Ctl 77 { 11, 0x00 }, /* r0b - Playback Ctl */
72 { 12, 0x0c }, /* r0c - DSP Mute Ctl 78 { 12, 0x0c }, /* r0c - DSP Mute Ctl */
73 { 13, 0x00 }, /* r0d - ADCA Mixer V 79 { 13, 0x00 }, /* r0d - ADCA Mixer Volume */
74 { 14, 0x00 }, /* r0e - ADCB Mixer V 80 { 14, 0x00 }, /* r0e - ADCB Mixer Volume */
75 { 15, 0x00 }, /* r0f - PCMA Mixer V 81 { 15, 0x00 }, /* r0f - PCMA Mixer Volume */
76 { 16, 0x00 }, /* r10 - PCMB Mixer V 82 { 16, 0x00 }, /* r10 - PCMB Mixer Volume */
77 { 17, 0x00 }, /* r11 - Analog Input 83 { 17, 0x00 }, /* r11 - Analog Input Advisory Volume */
78 { 18, 0x00 }, /* r12 - Digital Inpu 84 { 18, 0x00 }, /* r12 - Digital Input Advisory Volume */
79 { 19, 0x00 }, /* r13 - Master A Vol 85 { 19, 0x00 }, /* r13 - Master A Volume */
80 { 20, 0x00 }, /* r14 - Master B Vol 86 { 20, 0x00 }, /* r14 - Master B Volume */
81 { 21, 0x00 }, /* r15 - Beep Freq / 87 { 21, 0x00 }, /* r15 - Beep Freq / On Time */
82 { 22, 0x00 }, /* r16 - Beep Volume 88 { 22, 0x00 }, /* r16 - Beep Volume / Off Time */
83 { 23, 0x00 }, /* r17 - Beep Tone Ct 89 { 23, 0x00 }, /* r17 - Beep Tone Ctl */
84 { 24, 0x88 }, /* r18 - Tone Ctl */ 90 { 24, 0x88 }, /* r18 - Tone Ctl */
85 { 25, 0x00 }, /* r19 - Channel Mixe 91 { 25, 0x00 }, /* r19 - Channel Mixer & Swap */
86 { 26, 0x00 }, /* r1a - AIN Ref Conf 92 { 26, 0x00 }, /* r1a - AIN Ref Config / ADC Mux */
87 { 27, 0xa0 }, /* r1b - High-Pass Fi 93 { 27, 0xa0 }, /* r1b - High-Pass Filter Ctl */
88 { 28, 0x00 }, /* r1c - Misc ADC Ctl 94 { 28, 0x00 }, /* r1c - Misc ADC Ctl */
89 { 29, 0x00 }, /* r1d - Gain & Bias 95 { 29, 0x00 }, /* r1d - Gain & Bias Ctl */
90 { 30, 0x00 }, /* r1e - PGAA Mux & V 96 { 30, 0x00 }, /* r1e - PGAA Mux & Volume */
91 { 31, 0x00 }, /* r1f - PGAB Mux & V 97 { 31, 0x00 }, /* r1f - PGAB Mux & Volume */
92 { 32, 0x00 }, /* r20 - ADCA Attenua 98 { 32, 0x00 }, /* r20 - ADCA Attenuator */
93 { 33, 0x00 }, /* r21 - ADCB Attenua 99 { 33, 0x00 }, /* r21 - ADCB Attenuator */
94 { 34, 0x00 }, /* r22 - ALC Enable & 100 { 34, 0x00 }, /* r22 - ALC Enable & Attack Rate */
95 { 35, 0xbf }, /* r23 - ALC Release 101 { 35, 0xbf }, /* r23 - ALC Release Rate */
96 { 36, 0x00 }, /* r24 - ALC Threshol 102 { 36, 0x00 }, /* r24 - ALC Threshold */
97 { 37, 0x00 }, /* r25 - Noise Gate C 103 { 37, 0x00 }, /* r25 - Noise Gate Ctl */
98 { 38, 0x00 }, /* r26 - ALC, Limiter 104 { 38, 0x00 }, /* r26 - ALC, Limiter, SFT, ZeroCross */
99 { 39, 0x00 }, /* r27 - Analog Mute, 105 { 39, 0x00 }, /* r27 - Analog Mute, LO & HP Mux */
100 { 40, 0x00 }, /* r28 - HP A Volume 106 { 40, 0x00 }, /* r28 - HP A Volume */
101 { 41, 0x00 }, /* r29 - HP B Volume 107 { 41, 0x00 }, /* r29 - HP B Volume */
102 { 42, 0x00 }, /* r2a - LINEOUT A Vo 108 { 42, 0x00 }, /* r2a - LINEOUT A Volume */
103 { 43, 0x00 }, /* r2b - LINEOUT B Vo 109 { 43, 0x00 }, /* r2b - LINEOUT B Volume */
104 { 44, 0x00 }, /* r2c - Limit Thresh 110 { 44, 0x00 }, /* r2c - Limit Threshold Ctl */
105 { 45, 0x7f }, /* r2d - Limiter Ctl 111 { 45, 0x7f }, /* r2d - Limiter Ctl & Release Rate */
106 { 46, 0x00 }, /* r2e - Limiter Atta 112 { 46, 0x00 }, /* r2e - Limiter Attack Rate */
107 }; 113 };
108 114
109 static bool cs42l56_readable_register(struct d 115 static bool cs42l56_readable_register(struct device *dev, unsigned int reg)
110 { 116 {
111 switch (reg) { 117 switch (reg) {
112 case CS42L56_CHIP_ID_1 ... CS42L56_LIM 118 case CS42L56_CHIP_ID_1 ... CS42L56_LIM_ATTACK_RATE:
113 return true; 119 return true;
114 default: 120 default:
115 return false; 121 return false;
116 } 122 }
117 } 123 }
118 124
119 static bool cs42l56_volatile_register(struct d 125 static bool cs42l56_volatile_register(struct device *dev, unsigned int reg)
120 { 126 {
121 switch (reg) { 127 switch (reg) {
122 case CS42L56_INT_STATUS: 128 case CS42L56_INT_STATUS:
123 return true; 129 return true;
124 default: 130 default:
125 return false; 131 return false;
126 } 132 }
127 } 133 }
128 134
129 static DECLARE_TLV_DB_SCALE(beep_tlv, -5000, 2 135 static DECLARE_TLV_DB_SCALE(beep_tlv, -5000, 200, 0);
130 static DECLARE_TLV_DB_SCALE(hl_tlv, -6000, 50, 136 static DECLARE_TLV_DB_SCALE(hl_tlv, -6000, 50, 0);
131 static DECLARE_TLV_DB_SCALE(adv_tlv, -10200, 5 137 static DECLARE_TLV_DB_SCALE(adv_tlv, -10200, 50, 0);
132 static DECLARE_TLV_DB_SCALE(adc_tlv, -9600, 10 138 static DECLARE_TLV_DB_SCALE(adc_tlv, -9600, 100, 0);
133 static DECLARE_TLV_DB_SCALE(tone_tlv, -1050, 1 139 static DECLARE_TLV_DB_SCALE(tone_tlv, -1050, 150, 0);
134 static DECLARE_TLV_DB_SCALE(preamp_tlv, 0, 100 140 static DECLARE_TLV_DB_SCALE(preamp_tlv, 0, 1000, 0);
135 static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 141 static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0);
136 142
137 static const DECLARE_TLV_DB_RANGE(ngnb_tlv, 143 static const DECLARE_TLV_DB_RANGE(ngnb_tlv,
138 0, 1, TLV_DB_SCALE_ITEM(-8200, 600, 0) 144 0, 1, TLV_DB_SCALE_ITEM(-8200, 600, 0),
139 2, 5, TLV_DB_SCALE_ITEM(-7600, 300, 0) 145 2, 5, TLV_DB_SCALE_ITEM(-7600, 300, 0)
140 ); 146 );
141 static const DECLARE_TLV_DB_RANGE(ngb_tlv, 147 static const DECLARE_TLV_DB_RANGE(ngb_tlv,
142 0, 2, TLV_DB_SCALE_ITEM(-6400, 600, 0) 148 0, 2, TLV_DB_SCALE_ITEM(-6400, 600, 0),
143 3, 7, TLV_DB_SCALE_ITEM(-4600, 300, 0) 149 3, 7, TLV_DB_SCALE_ITEM(-4600, 300, 0)
144 ); 150 );
145 static const DECLARE_TLV_DB_RANGE(alc_tlv, 151 static const DECLARE_TLV_DB_RANGE(alc_tlv,
146 0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0) 152 0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
147 3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0) 153 3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0)
148 ); 154 );
149 155
150 static const char * const beep_config_text[] = 156 static const char * const beep_config_text[] = {
151 "Off", "Single", "Multiple", "Continuo 157 "Off", "Single", "Multiple", "Continuous"
152 }; 158 };
153 159
154 static const struct soc_enum beep_config_enum 160 static const struct soc_enum beep_config_enum =
155 SOC_ENUM_SINGLE(CS42L56_BEEP_TONE_CFG, 161 SOC_ENUM_SINGLE(CS42L56_BEEP_TONE_CFG, 6,
156 ARRAY_SIZE(beep_config 162 ARRAY_SIZE(beep_config_text), beep_config_text);
157 163
158 static const char * const beep_pitch_text[] = 164 static const char * const beep_pitch_text[] = {
159 "C4", "C5", "D5", "E5", "F5", "G5", "A 165 "C4", "C5", "D5", "E5", "F5", "G5", "A5", "B5",
160 "C6", "D6", "E6", "F6", "G6", "A6", "B 166 "C6", "D6", "E6", "F6", "G6", "A6", "B6", "C7"
161 }; 167 };
162 168
163 static const struct soc_enum beep_pitch_enum = 169 static const struct soc_enum beep_pitch_enum =
164 SOC_ENUM_SINGLE(CS42L56_BEEP_FREQ_ONTI 170 SOC_ENUM_SINGLE(CS42L56_BEEP_FREQ_ONTIME, 4,
165 ARRAY_SIZE(beep_pitch_ 171 ARRAY_SIZE(beep_pitch_text), beep_pitch_text);
166 172
167 static const char * const beep_ontime_text[] = 173 static const char * const beep_ontime_text[] = {
168 "86 ms", "430 ms", "780 ms", "1.20 s", 174 "86 ms", "430 ms", "780 ms", "1.20 s", "1.50 s",
169 "1.80 s", "2.20 s", "2.50 s", "2.80 s" 175 "1.80 s", "2.20 s", "2.50 s", "2.80 s", "3.20 s",
170 "3.50 s", "3.80 s", "4.20 s", "4.50 s" 176 "3.50 s", "3.80 s", "4.20 s", "4.50 s", "4.80 s", "5.20 s"
171 }; 177 };
172 178
173 static const struct soc_enum beep_ontime_enum 179 static const struct soc_enum beep_ontime_enum =
174 SOC_ENUM_SINGLE(CS42L56_BEEP_FREQ_ONTI 180 SOC_ENUM_SINGLE(CS42L56_BEEP_FREQ_ONTIME, 0,
175 ARRAY_SIZE(beep_ontime 181 ARRAY_SIZE(beep_ontime_text), beep_ontime_text);
176 182
177 static const char * const beep_offtime_text[] 183 static const char * const beep_offtime_text[] = {
178 "1.23 s", "2.58 s", "3.90 s", "5.20 s" 184 "1.23 s", "2.58 s", "3.90 s", "5.20 s",
179 "6.60 s", "8.05 s", "9.35 s", "10.80 s 185 "6.60 s", "8.05 s", "9.35 s", "10.80 s"
180 }; 186 };
181 187
182 static const struct soc_enum beep_offtime_enum 188 static const struct soc_enum beep_offtime_enum =
183 SOC_ENUM_SINGLE(CS42L56_BEEP_FREQ_OFFT 189 SOC_ENUM_SINGLE(CS42L56_BEEP_FREQ_OFFTIME, 5,
184 ARRAY_SIZE(beep_offtim 190 ARRAY_SIZE(beep_offtime_text), beep_offtime_text);
185 191
186 static const char * const beep_treble_text[] = 192 static const char * const beep_treble_text[] = {
187 "5kHz", "7kHz", "10kHz", "15kHz" 193 "5kHz", "7kHz", "10kHz", "15kHz"
188 }; 194 };
189 195
190 static const struct soc_enum beep_treble_enum 196 static const struct soc_enum beep_treble_enum =
191 SOC_ENUM_SINGLE(CS42L56_BEEP_TONE_CFG, 197 SOC_ENUM_SINGLE(CS42L56_BEEP_TONE_CFG, 3,
192 ARRAY_SIZE(beep_treble 198 ARRAY_SIZE(beep_treble_text), beep_treble_text);
193 199
194 static const char * const beep_bass_text[] = { 200 static const char * const beep_bass_text[] = {
195 "50Hz", "100Hz", "200Hz", "250Hz" 201 "50Hz", "100Hz", "200Hz", "250Hz"
196 }; 202 };
197 203
198 static const struct soc_enum beep_bass_enum = 204 static const struct soc_enum beep_bass_enum =
199 SOC_ENUM_SINGLE(CS42L56_BEEP_TONE_CFG, 205 SOC_ENUM_SINGLE(CS42L56_BEEP_TONE_CFG, 1,
200 ARRAY_SIZE(beep_bass_t 206 ARRAY_SIZE(beep_bass_text), beep_bass_text);
201 207
>> 208 static const char * const adc_swap_text[] = {
>> 209 "None", "A+B/2", "A-B/2", "Swap"
>> 210 };
>> 211
>> 212 static const struct soc_enum adc_swap_enum =
>> 213 SOC_ENUM_SINGLE(CS42L56_MISC_ADC_CTL, 3,
>> 214 ARRAY_SIZE(adc_swap_text), adc_swap_text);
>> 215
202 static const char * const pgaa_mux_text[] = { 216 static const char * const pgaa_mux_text[] = {
203 "AIN1A", "AIN2A", "AIN3A"}; 217 "AIN1A", "AIN2A", "AIN3A"};
204 218
205 static const struct soc_enum pgaa_mux_enum = 219 static const struct soc_enum pgaa_mux_enum =
206 SOC_ENUM_SINGLE(CS42L56_PGAA_MUX_VOLUM 220 SOC_ENUM_SINGLE(CS42L56_PGAA_MUX_VOLUME, 0,
207 ARRAY_SIZE(pgaa_ 221 ARRAY_SIZE(pgaa_mux_text),
208 pgaa_mux_text); 222 pgaa_mux_text);
209 223
210 static const struct snd_kcontrol_new pgaa_mux 224 static const struct snd_kcontrol_new pgaa_mux =
211 SOC_DAPM_ENUM("Route", pgaa_mux_enum); 225 SOC_DAPM_ENUM("Route", pgaa_mux_enum);
212 226
213 static const char * const pgab_mux_text[] = { 227 static const char * const pgab_mux_text[] = {
214 "AIN1B", "AIN2B", "AIN3B"}; 228 "AIN1B", "AIN2B", "AIN3B"};
215 229
216 static const struct soc_enum pgab_mux_enum = 230 static const struct soc_enum pgab_mux_enum =
217 SOC_ENUM_SINGLE(CS42L56_PGAB_MUX_VOLUM 231 SOC_ENUM_SINGLE(CS42L56_PGAB_MUX_VOLUME, 0,
218 ARRAY_SIZE(pgab_ 232 ARRAY_SIZE(pgab_mux_text),
219 pgab_mux_text); 233 pgab_mux_text);
220 234
221 static const struct snd_kcontrol_new pgab_mux 235 static const struct snd_kcontrol_new pgab_mux =
222 SOC_DAPM_ENUM("Route", pgab_mux_enum); 236 SOC_DAPM_ENUM("Route", pgab_mux_enum);
223 237
224 static const char * const adca_mux_text[] = { 238 static const char * const adca_mux_text[] = {
225 "PGAA", "AIN1A", "AIN2A", "AIN3A"}; 239 "PGAA", "AIN1A", "AIN2A", "AIN3A"};
226 240
227 static const struct soc_enum adca_mux_enum = 241 static const struct soc_enum adca_mux_enum =
228 SOC_ENUM_SINGLE(CS42L56_AIN_REFCFG_ADC 242 SOC_ENUM_SINGLE(CS42L56_AIN_REFCFG_ADC_MUX, 0,
229 ARRAY_SIZE(adca_ 243 ARRAY_SIZE(adca_mux_text),
230 adca_mux_text); 244 adca_mux_text);
231 245
232 static const struct snd_kcontrol_new adca_mux 246 static const struct snd_kcontrol_new adca_mux =
233 SOC_DAPM_ENUM("Route", adca_mux_enum); 247 SOC_DAPM_ENUM("Route", adca_mux_enum);
234 248
235 static const char * const adcb_mux_text[] = { 249 static const char * const adcb_mux_text[] = {
236 "PGAB", "AIN1B", "AIN2B", "AIN3B"}; 250 "PGAB", "AIN1B", "AIN2B", "AIN3B"};
237 251
238 static const struct soc_enum adcb_mux_enum = 252 static const struct soc_enum adcb_mux_enum =
239 SOC_ENUM_SINGLE(CS42L56_AIN_REFCFG_ADC 253 SOC_ENUM_SINGLE(CS42L56_AIN_REFCFG_ADC_MUX, 2,
240 ARRAY_SIZE(adcb_ 254 ARRAY_SIZE(adcb_mux_text),
241 adcb_mux_text); 255 adcb_mux_text);
242 256
243 static const struct snd_kcontrol_new adcb_mux 257 static const struct snd_kcontrol_new adcb_mux =
244 SOC_DAPM_ENUM("Route", adcb_mux_enum); 258 SOC_DAPM_ENUM("Route", adcb_mux_enum);
245 259
246 static const char * const left_swap_text[] = { 260 static const char * const left_swap_text[] = {
247 "Left", "LR 2", "Right"}; 261 "Left", "LR 2", "Right"};
248 262
249 static const char * const right_swap_text[] = 263 static const char * const right_swap_text[] = {
250 "Right", "LR 2", "Left"}; 264 "Right", "LR 2", "Left"};
251 265
252 static const unsigned int swap_values[] = { 0, 266 static const unsigned int swap_values[] = { 0, 1, 3 };
253 267
254 static const struct soc_enum adca_swap_enum = 268 static const struct soc_enum adca_swap_enum =
255 SOC_VALUE_ENUM_SINGLE(CS42L56_CHAN_MIX 269 SOC_VALUE_ENUM_SINGLE(CS42L56_CHAN_MIX_SWAP, 0, 3,
256 ARRAY_SIZE(left_ 270 ARRAY_SIZE(left_swap_text),
257 left_swap_text, 271 left_swap_text,
258 swap_values); 272 swap_values);
259 static const struct snd_kcontrol_new adca_swap 273 static const struct snd_kcontrol_new adca_swap_mux =
260 SOC_DAPM_ENUM("Route", adca_swap_enum) 274 SOC_DAPM_ENUM("Route", adca_swap_enum);
261 275
262 static const struct soc_enum pcma_swap_enum = 276 static const struct soc_enum pcma_swap_enum =
263 SOC_VALUE_ENUM_SINGLE(CS42L56_CHAN_MIX 277 SOC_VALUE_ENUM_SINGLE(CS42L56_CHAN_MIX_SWAP, 4, 3,
264 ARRAY_SIZE(left_ 278 ARRAY_SIZE(left_swap_text),
265 left_swap_text, 279 left_swap_text,
266 swap_values); 280 swap_values);
267 static const struct snd_kcontrol_new pcma_swap 281 static const struct snd_kcontrol_new pcma_swap_mux =
268 SOC_DAPM_ENUM("Route", pcma_swap_enum) 282 SOC_DAPM_ENUM("Route", pcma_swap_enum);
269 283
270 static const struct soc_enum adcb_swap_enum = 284 static const struct soc_enum adcb_swap_enum =
271 SOC_VALUE_ENUM_SINGLE(CS42L56_CHAN_MIX 285 SOC_VALUE_ENUM_SINGLE(CS42L56_CHAN_MIX_SWAP, 2, 3,
272 ARRAY_SIZE(right 286 ARRAY_SIZE(right_swap_text),
273 right_swap_text, 287 right_swap_text,
274 swap_values); 288 swap_values);
275 static const struct snd_kcontrol_new adcb_swap 289 static const struct snd_kcontrol_new adcb_swap_mux =
276 SOC_DAPM_ENUM("Route", adcb_swap_enum) 290 SOC_DAPM_ENUM("Route", adcb_swap_enum);
277 291
278 static const struct soc_enum pcmb_swap_enum = 292 static const struct soc_enum pcmb_swap_enum =
279 SOC_VALUE_ENUM_SINGLE(CS42L56_CHAN_MIX 293 SOC_VALUE_ENUM_SINGLE(CS42L56_CHAN_MIX_SWAP, 6, 3,
280 ARRAY_SIZE(right 294 ARRAY_SIZE(right_swap_text),
281 right_swap_text, 295 right_swap_text,
282 swap_values); 296 swap_values);
283 static const struct snd_kcontrol_new pcmb_swap 297 static const struct snd_kcontrol_new pcmb_swap_mux =
284 SOC_DAPM_ENUM("Route", pcmb_swap_enum) 298 SOC_DAPM_ENUM("Route", pcmb_swap_enum);
285 299
286 static const struct snd_kcontrol_new hpa_switc 300 static const struct snd_kcontrol_new hpa_switch =
287 SOC_DAPM_SINGLE("Switch", CS42L56_PWRC 301 SOC_DAPM_SINGLE("Switch", CS42L56_PWRCTL_2, 6, 1, 1);
288 302
289 static const struct snd_kcontrol_new hpb_switc 303 static const struct snd_kcontrol_new hpb_switch =
290 SOC_DAPM_SINGLE("Switch", CS42L56_PWRC 304 SOC_DAPM_SINGLE("Switch", CS42L56_PWRCTL_2, 4, 1, 1);
291 305
292 static const struct snd_kcontrol_new loa_switc 306 static const struct snd_kcontrol_new loa_switch =
293 SOC_DAPM_SINGLE("Switch", CS42L56_PWRC 307 SOC_DAPM_SINGLE("Switch", CS42L56_PWRCTL_2, 2, 1, 1);
294 308
295 static const struct snd_kcontrol_new lob_switc 309 static const struct snd_kcontrol_new lob_switch =
296 SOC_DAPM_SINGLE("Switch", CS42L56_PWRC 310 SOC_DAPM_SINGLE("Switch", CS42L56_PWRCTL_2, 0, 1, 1);
297 311
298 static const char * const hploa_input_text[] = 312 static const char * const hploa_input_text[] = {
299 "DACA", "PGAA"}; 313 "DACA", "PGAA"};
300 314
301 static const struct soc_enum lineouta_input_en 315 static const struct soc_enum lineouta_input_enum =
302 SOC_ENUM_SINGLE(CS42L56_AMUTE_HPLO_MUX 316 SOC_ENUM_SINGLE(CS42L56_AMUTE_HPLO_MUX, 2,
303 ARRAY_SIZE(hploa 317 ARRAY_SIZE(hploa_input_text),
304 hploa_input_text 318 hploa_input_text);
305 319
306 static const struct snd_kcontrol_new lineouta_ 320 static const struct snd_kcontrol_new lineouta_input =
307 SOC_DAPM_ENUM("Route", lineouta_input_ 321 SOC_DAPM_ENUM("Route", lineouta_input_enum);
308 322
309 static const struct soc_enum hpa_input_enum = 323 static const struct soc_enum hpa_input_enum =
310 SOC_ENUM_SINGLE(CS42L56_AMUTE_HPLO_MUX 324 SOC_ENUM_SINGLE(CS42L56_AMUTE_HPLO_MUX, 0,
311 ARRAY_SIZE(hploa 325 ARRAY_SIZE(hploa_input_text),
312 hploa_input_text 326 hploa_input_text);
313 327
314 static const struct snd_kcontrol_new hpa_input 328 static const struct snd_kcontrol_new hpa_input =
315 SOC_DAPM_ENUM("Route", hpa_input_enum) 329 SOC_DAPM_ENUM("Route", hpa_input_enum);
316 330
317 static const char * const hplob_input_text[] = 331 static const char * const hplob_input_text[] = {
318 "DACB", "PGAB"}; 332 "DACB", "PGAB"};
319 333
320 static const struct soc_enum lineoutb_input_en 334 static const struct soc_enum lineoutb_input_enum =
321 SOC_ENUM_SINGLE(CS42L56_AMUTE_HPLO_MUX 335 SOC_ENUM_SINGLE(CS42L56_AMUTE_HPLO_MUX, 3,
322 ARRAY_SIZE(hplob 336 ARRAY_SIZE(hplob_input_text),
323 hplob_input_text 337 hplob_input_text);
324 338
325 static const struct snd_kcontrol_new lineoutb_ 339 static const struct snd_kcontrol_new lineoutb_input =
326 SOC_DAPM_ENUM("Route", lineoutb_input_ 340 SOC_DAPM_ENUM("Route", lineoutb_input_enum);
327 341
328 static const struct soc_enum hpb_input_enum = 342 static const struct soc_enum hpb_input_enum =
329 SOC_ENUM_SINGLE(CS42L56_AMUTE_HPLO_MUX 343 SOC_ENUM_SINGLE(CS42L56_AMUTE_HPLO_MUX, 1,
330 ARRAY_SIZE(hplob 344 ARRAY_SIZE(hplob_input_text),
331 hplob_input_text 345 hplob_input_text);
332 346
333 static const struct snd_kcontrol_new hpb_input 347 static const struct snd_kcontrol_new hpb_input =
334 SOC_DAPM_ENUM("Route", hpb_input_enum) 348 SOC_DAPM_ENUM("Route", hpb_input_enum);
335 349
336 static const char * const dig_mux_text[] = { 350 static const char * const dig_mux_text[] = {
337 "ADC", "DSP"}; 351 "ADC", "DSP"};
338 352
339 static const struct soc_enum dig_mux_enum = 353 static const struct soc_enum dig_mux_enum =
340 SOC_ENUM_SINGLE(CS42L56_MISC_CTL, 7, 354 SOC_ENUM_SINGLE(CS42L56_MISC_CTL, 7,
341 ARRAY_SIZE(dig_m 355 ARRAY_SIZE(dig_mux_text),
342 dig_mux_text); 356 dig_mux_text);
343 357
344 static const struct snd_kcontrol_new dig_mux = 358 static const struct snd_kcontrol_new dig_mux =
345 SOC_DAPM_ENUM("Route", dig_mux_enum); 359 SOC_DAPM_ENUM("Route", dig_mux_enum);
346 360
347 static const char * const hpf_freq_text[] = { 361 static const char * const hpf_freq_text[] = {
348 "1.8Hz", "119Hz", "236Hz", "464Hz" 362 "1.8Hz", "119Hz", "236Hz", "464Hz"
349 }; 363 };
350 364
351 static const struct soc_enum hpfa_freq_enum = 365 static const struct soc_enum hpfa_freq_enum =
352 SOC_ENUM_SINGLE(CS42L56_HPF_CTL, 0, 366 SOC_ENUM_SINGLE(CS42L56_HPF_CTL, 0,
353 ARRAY_SIZE(hpf_freq_te 367 ARRAY_SIZE(hpf_freq_text), hpf_freq_text);
354 368
355 static const struct soc_enum hpfb_freq_enum = 369 static const struct soc_enum hpfb_freq_enum =
356 SOC_ENUM_SINGLE(CS42L56_HPF_CTL, 2, 370 SOC_ENUM_SINGLE(CS42L56_HPF_CTL, 2,
357 ARRAY_SIZE(hpf_freq_te 371 ARRAY_SIZE(hpf_freq_text), hpf_freq_text);
358 372
359 static const char * const ng_delay_text[] = { 373 static const char * const ng_delay_text[] = {
360 "50ms", "100ms", "150ms", "200ms" 374 "50ms", "100ms", "150ms", "200ms"
361 }; 375 };
362 376
363 static const struct soc_enum ng_delay_enum = 377 static const struct soc_enum ng_delay_enum =
364 SOC_ENUM_SINGLE(CS42L56_NOISE_GATE_CTL 378 SOC_ENUM_SINGLE(CS42L56_NOISE_GATE_CTL, 0,
365 ARRAY_SIZE(ng_delay_te 379 ARRAY_SIZE(ng_delay_text), ng_delay_text);
366 380
367 static const struct snd_kcontrol_new cs42l56_s 381 static const struct snd_kcontrol_new cs42l56_snd_controls[] = {
368 382
369 SOC_DOUBLE_R_SX_TLV("Master Volume", C 383 SOC_DOUBLE_R_SX_TLV("Master Volume", CS42L56_MASTER_A_VOLUME,
370 CS42L56_MASTER_B 384 CS42L56_MASTER_B_VOLUME, 0, 0x34, 0xE4, adv_tlv),
371 SOC_DOUBLE("Master Mute Switch", CS42L 385 SOC_DOUBLE("Master Mute Switch", CS42L56_DSP_MUTE_CTL, 0, 1, 1, 1),
372 386
373 SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume" 387 SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume", CS42L56_ADCA_MIX_VOLUME,
374 CS42L56_ADCB_MIX 388 CS42L56_ADCB_MIX_VOLUME, 0, 0x88, 0x90, hl_tlv),
375 SOC_DOUBLE("ADC Mixer Mute Switch", CS 389 SOC_DOUBLE("ADC Mixer Mute Switch", CS42L56_DSP_MUTE_CTL, 6, 7, 1, 1),
376 390
377 SOC_DOUBLE_R_SX_TLV("PCM Mixer Volume" 391 SOC_DOUBLE_R_SX_TLV("PCM Mixer Volume", CS42L56_PCMA_MIX_VOLUME,
378 CS42L56_PCMB_MIX 392 CS42L56_PCMB_MIX_VOLUME, 0, 0x88, 0x90, hl_tlv),
379 SOC_DOUBLE("PCM Mixer Mute Switch", CS 393 SOC_DOUBLE("PCM Mixer Mute Switch", CS42L56_DSP_MUTE_CTL, 4, 5, 1, 1),
380 394
381 SOC_SINGLE_TLV("Analog Advisory Volume 395 SOC_SINGLE_TLV("Analog Advisory Volume",
382 CS42L56_ANAINPUT_ADV 396 CS42L56_ANAINPUT_ADV_VOLUME, 0, 0x00, 1, adv_tlv),
383 SOC_SINGLE_TLV("Digital Advisory Volum 397 SOC_SINGLE_TLV("Digital Advisory Volume",
384 CS42L56_DIGINPUT_ADV 398 CS42L56_DIGINPUT_ADV_VOLUME, 0, 0x00, 1, adv_tlv),
385 399
386 SOC_DOUBLE_R_SX_TLV("PGA Volume", CS42 400 SOC_DOUBLE_R_SX_TLV("PGA Volume", CS42L56_PGAA_MUX_VOLUME,
387 CS42L56_PGAB_MUX 401 CS42L56_PGAB_MUX_VOLUME, 0, 0x34, 0x24, pga_tlv),
388 SOC_DOUBLE_R_TLV("ADC Volume", CS42L56 402 SOC_DOUBLE_R_TLV("ADC Volume", CS42L56_ADCA_ATTENUATOR,
389 CS42L56_ADCB_ATT 403 CS42L56_ADCB_ATTENUATOR, 0, 0x00, 1, adc_tlv),
390 SOC_DOUBLE("ADC Mute Switch", CS42L56_ 404 SOC_DOUBLE("ADC Mute Switch", CS42L56_MISC_ADC_CTL, 2, 3, 1, 1),
391 SOC_DOUBLE("ADC Boost Switch", CS42L56 405 SOC_DOUBLE("ADC Boost Switch", CS42L56_GAIN_BIAS_CTL, 3, 2, 1, 1),
392 406
393 SOC_DOUBLE_R_SX_TLV("Headphone Volume" 407 SOC_DOUBLE_R_SX_TLV("Headphone Volume", CS42L56_HPA_VOLUME,
394 CS42L56_HPB_VOLU 408 CS42L56_HPB_VOLUME, 0, 0x44, 0x48, hl_tlv),
395 SOC_DOUBLE_R_SX_TLV("LineOut Volume", 409 SOC_DOUBLE_R_SX_TLV("LineOut Volume", CS42L56_LOA_VOLUME,
396 CS42L56_LOB_VOLU 410 CS42L56_LOB_VOLUME, 0, 0x44, 0x48, hl_tlv),
397 411
398 SOC_SINGLE_TLV("Bass Shelving Volume", 412 SOC_SINGLE_TLV("Bass Shelving Volume", CS42L56_TONE_CTL,
399 0, 0x00, 1, tone_tlv), 413 0, 0x00, 1, tone_tlv),
400 SOC_SINGLE_TLV("Treble Shelving Volume 414 SOC_SINGLE_TLV("Treble Shelving Volume", CS42L56_TONE_CTL,
401 4, 0x00, 1, tone_tlv), 415 4, 0x00, 1, tone_tlv),
402 416
403 SOC_DOUBLE_TLV("PGA Preamp Volume", CS 417 SOC_DOUBLE_TLV("PGA Preamp Volume", CS42L56_GAIN_BIAS_CTL,
404 4, 6, 0x02, 1, preamp_ 418 4, 6, 0x02, 1, preamp_tlv),
405 419
406 SOC_SINGLE("DSP Switch", CS42L56_PLAYB 420 SOC_SINGLE("DSP Switch", CS42L56_PLAYBACK_CTL, 7, 1, 1),
407 SOC_SINGLE("Gang Playback Switch", CS4 421 SOC_SINGLE("Gang Playback Switch", CS42L56_PLAYBACK_CTL, 4, 1, 1),
408 SOC_SINGLE("Gang ADC Switch", CS42L56_ 422 SOC_SINGLE("Gang ADC Switch", CS42L56_MISC_ADC_CTL, 7, 1, 1),
409 SOC_SINGLE("Gang PGA Switch", CS42L56_ 423 SOC_SINGLE("Gang PGA Switch", CS42L56_MISC_ADC_CTL, 6, 1, 1),
410 424
411 SOC_SINGLE("PCMA Invert", CS42L56_PLAY 425 SOC_SINGLE("PCMA Invert", CS42L56_PLAYBACK_CTL, 2, 1, 1),
412 SOC_SINGLE("PCMB Invert", CS42L56_PLAY 426 SOC_SINGLE("PCMB Invert", CS42L56_PLAYBACK_CTL, 3, 1, 1),
413 SOC_SINGLE("ADCA Invert", CS42L56_MISC 427 SOC_SINGLE("ADCA Invert", CS42L56_MISC_ADC_CTL, 2, 1, 1),
414 SOC_SINGLE("ADCB Invert", CS42L56_MISC 428 SOC_SINGLE("ADCB Invert", CS42L56_MISC_ADC_CTL, 3, 1, 1),
415 429
416 SOC_DOUBLE("HPF Switch", CS42L56_HPF_C 430 SOC_DOUBLE("HPF Switch", CS42L56_HPF_CTL, 5, 7, 1, 1),
417 SOC_DOUBLE("HPF Freeze Switch", CS42L5 431 SOC_DOUBLE("HPF Freeze Switch", CS42L56_HPF_CTL, 4, 6, 1, 1),
418 SOC_ENUM("HPFA Corner Freq", hpfa_freq 432 SOC_ENUM("HPFA Corner Freq", hpfa_freq_enum),
419 SOC_ENUM("HPFB Corner Freq", hpfb_freq 433 SOC_ENUM("HPFB Corner Freq", hpfb_freq_enum),
420 434
421 SOC_SINGLE("Analog Soft Ramp", CS42L56 435 SOC_SINGLE("Analog Soft Ramp", CS42L56_MISC_CTL, 4, 1, 1),
422 SOC_DOUBLE("Analog Soft Ramp Disable", 436 SOC_DOUBLE("Analog Soft Ramp Disable", CS42L56_ALC_LIM_SFT_ZC,
423 7, 5, 1, 1), 437 7, 5, 1, 1),
424 SOC_SINGLE("Analog Zero Cross", CS42L5 438 SOC_SINGLE("Analog Zero Cross", CS42L56_MISC_CTL, 3, 1, 1),
425 SOC_DOUBLE("Analog Zero Cross Disable" 439 SOC_DOUBLE("Analog Zero Cross Disable", CS42L56_ALC_LIM_SFT_ZC,
426 6, 4, 1, 1), 440 6, 4, 1, 1),
427 SOC_SINGLE("Digital Soft Ramp", CS42L5 441 SOC_SINGLE("Digital Soft Ramp", CS42L56_MISC_CTL, 2, 1, 1),
428 SOC_SINGLE("Digital Soft Ramp Disable" 442 SOC_SINGLE("Digital Soft Ramp Disable", CS42L56_ALC_LIM_SFT_ZC,
429 3, 1, 1), 443 3, 1, 1),
430 444
431 SOC_SINGLE("HL Deemphasis", CS42L56_PL 445 SOC_SINGLE("HL Deemphasis", CS42L56_PLAYBACK_CTL, 6, 1, 1),
432 446
433 SOC_SINGLE("ALC Switch", CS42L56_ALC_E 447 SOC_SINGLE("ALC Switch", CS42L56_ALC_EN_ATTACK_RATE, 6, 1, 1),
434 SOC_SINGLE("ALC Limit All Switch", CS4 448 SOC_SINGLE("ALC Limit All Switch", CS42L56_ALC_RELEASE_RATE, 7, 1, 1),
435 SOC_SINGLE_RANGE("ALC Attack", CS42L56 449 SOC_SINGLE_RANGE("ALC Attack", CS42L56_ALC_EN_ATTACK_RATE,
436 0, 0, 0x3f, 0), 450 0, 0, 0x3f, 0),
437 SOC_SINGLE_RANGE("ALC Release", CS42L5 451 SOC_SINGLE_RANGE("ALC Release", CS42L56_ALC_RELEASE_RATE,
438 0, 0x3f, 0, 0), 452 0, 0x3f, 0, 0),
439 SOC_SINGLE_TLV("ALC MAX", CS42L56_ALC_ 453 SOC_SINGLE_TLV("ALC MAX", CS42L56_ALC_THRESHOLD,
440 5, 0x07, 1, alc_tlv), 454 5, 0x07, 1, alc_tlv),
441 SOC_SINGLE_TLV("ALC MIN", CS42L56_ALC_ 455 SOC_SINGLE_TLV("ALC MIN", CS42L56_ALC_THRESHOLD,
442 2, 0x07, 1, alc_tlv), 456 2, 0x07, 1, alc_tlv),
443 457
444 SOC_SINGLE("Limiter Switch", CS42L56_L 458 SOC_SINGLE("Limiter Switch", CS42L56_LIM_CTL_RELEASE_RATE, 7, 1, 1),
445 SOC_SINGLE("Limit All Switch", CS42L56 459 SOC_SINGLE("Limit All Switch", CS42L56_LIM_CTL_RELEASE_RATE, 6, 1, 1),
446 SOC_SINGLE_RANGE("Limiter Attack", CS4 460 SOC_SINGLE_RANGE("Limiter Attack", CS42L56_LIM_ATTACK_RATE,
447 0, 0, 0x3f, 0), 461 0, 0, 0x3f, 0),
448 SOC_SINGLE_RANGE("Limiter Release", CS 462 SOC_SINGLE_RANGE("Limiter Release", CS42L56_LIM_CTL_RELEASE_RATE,
449 0, 0x3f, 0, 0), 463 0, 0x3f, 0, 0),
450 SOC_SINGLE_TLV("Limiter MAX", CS42L56_ 464 SOC_SINGLE_TLV("Limiter MAX", CS42L56_LIM_THRESHOLD_CTL,
451 5, 0x07, 1, alc_tlv), 465 5, 0x07, 1, alc_tlv),
452 SOC_SINGLE_TLV("Limiter Cushion", CS42 466 SOC_SINGLE_TLV("Limiter Cushion", CS42L56_ALC_THRESHOLD,
453 2, 0x07, 1, alc_tlv), 467 2, 0x07, 1, alc_tlv),
454 468
455 SOC_SINGLE("NG Switch", CS42L56_NOISE_ 469 SOC_SINGLE("NG Switch", CS42L56_NOISE_GATE_CTL, 6, 1, 1),
456 SOC_SINGLE("NG All Switch", CS42L56_NO 470 SOC_SINGLE("NG All Switch", CS42L56_NOISE_GATE_CTL, 7, 1, 1),
457 SOC_SINGLE("NG Boost Switch", CS42L56_ 471 SOC_SINGLE("NG Boost Switch", CS42L56_NOISE_GATE_CTL, 5, 1, 1),
458 SOC_SINGLE_TLV("NG Unboost Threshold", 472 SOC_SINGLE_TLV("NG Unboost Threshold", CS42L56_NOISE_GATE_CTL,
459 2, 0x07, 1, ngnb_tlv), 473 2, 0x07, 1, ngnb_tlv),
460 SOC_SINGLE_TLV("NG Boost Threshold", C 474 SOC_SINGLE_TLV("NG Boost Threshold", CS42L56_NOISE_GATE_CTL,
461 2, 0x07, 1, ngb_tlv), 475 2, 0x07, 1, ngb_tlv),
462 SOC_ENUM("NG Delay", ng_delay_enum), 476 SOC_ENUM("NG Delay", ng_delay_enum),
463 477
464 SOC_ENUM("Beep Config", beep_config_en 478 SOC_ENUM("Beep Config", beep_config_enum),
465 SOC_ENUM("Beep Pitch", beep_pitch_enum 479 SOC_ENUM("Beep Pitch", beep_pitch_enum),
466 SOC_ENUM("Beep on Time", beep_ontime_e 480 SOC_ENUM("Beep on Time", beep_ontime_enum),
467 SOC_ENUM("Beep off Time", beep_offtime 481 SOC_ENUM("Beep off Time", beep_offtime_enum),
468 SOC_SINGLE_SX_TLV("Beep Volume", CS42L 482 SOC_SINGLE_SX_TLV("Beep Volume", CS42L56_BEEP_FREQ_OFFTIME,
469 0, 0x07, 0x23, beep_tl 483 0, 0x07, 0x23, beep_tlv),
470 SOC_SINGLE("Beep Tone Ctl Switch", CS4 484 SOC_SINGLE("Beep Tone Ctl Switch", CS42L56_BEEP_TONE_CFG, 0, 1, 1),
471 SOC_ENUM("Beep Treble Corner Freq", be 485 SOC_ENUM("Beep Treble Corner Freq", beep_treble_enum),
472 SOC_ENUM("Beep Bass Corner Freq", beep 486 SOC_ENUM("Beep Bass Corner Freq", beep_bass_enum),
473 487
474 }; 488 };
475 489
476 static const struct snd_soc_dapm_widget cs42l5 490 static const struct snd_soc_dapm_widget cs42l56_dapm_widgets[] = {
477 491
478 SND_SOC_DAPM_SIGGEN("Beep"), 492 SND_SOC_DAPM_SIGGEN("Beep"),
479 SND_SOC_DAPM_SUPPLY("VBUF", CS42L56_PW 493 SND_SOC_DAPM_SUPPLY("VBUF", CS42L56_PWRCTL_1, 5, 1, NULL, 0),
480 SND_SOC_DAPM_MICBIAS("MIC1 Bias", CS42 494 SND_SOC_DAPM_MICBIAS("MIC1 Bias", CS42L56_PWRCTL_1, 4, 1),
481 SND_SOC_DAPM_SUPPLY("Charge Pump", CS4 495 SND_SOC_DAPM_SUPPLY("Charge Pump", CS42L56_PWRCTL_1, 3, 1, NULL, 0),
482 496
483 SND_SOC_DAPM_INPUT("AIN1A"), 497 SND_SOC_DAPM_INPUT("AIN1A"),
484 SND_SOC_DAPM_INPUT("AIN2A"), 498 SND_SOC_DAPM_INPUT("AIN2A"),
485 SND_SOC_DAPM_INPUT("AIN1B"), 499 SND_SOC_DAPM_INPUT("AIN1B"),
486 SND_SOC_DAPM_INPUT("AIN2B"), 500 SND_SOC_DAPM_INPUT("AIN2B"),
487 SND_SOC_DAPM_INPUT("AIN3A"), 501 SND_SOC_DAPM_INPUT("AIN3A"),
488 SND_SOC_DAPM_INPUT("AIN3B"), 502 SND_SOC_DAPM_INPUT("AIN3B"),
489 503
490 SND_SOC_DAPM_AIF_OUT("SDOUT", NULL, 0 504 SND_SOC_DAPM_AIF_OUT("SDOUT", NULL, 0,
491 SND_SOC_NOPM, 0, 0), 505 SND_SOC_NOPM, 0, 0),
492 506
493 SND_SOC_DAPM_AIF_IN("SDIN", NULL, 0, 507 SND_SOC_DAPM_AIF_IN("SDIN", NULL, 0,
494 SND_SOC_NOPM, 0, 0), 508 SND_SOC_NOPM, 0, 0),
495 509
496 SND_SOC_DAPM_MUX("Digital Output Mux", 510 SND_SOC_DAPM_MUX("Digital Output Mux", SND_SOC_NOPM,
497 0, 0, &dig_mux), 511 0, 0, &dig_mux),
498 512
499 SND_SOC_DAPM_PGA("PGAA", SND_SOC_NOPM, 513 SND_SOC_DAPM_PGA("PGAA", SND_SOC_NOPM, 0, 0, NULL, 0),
500 SND_SOC_DAPM_PGA("PGAB", SND_SOC_NOPM, 514 SND_SOC_DAPM_PGA("PGAB", SND_SOC_NOPM, 0, 0, NULL, 0),
501 SND_SOC_DAPM_MUX("PGAA Input Mux", 515 SND_SOC_DAPM_MUX("PGAA Input Mux",
502 SND_SOC_NOPM, 0, 0, &p 516 SND_SOC_NOPM, 0, 0, &pgaa_mux),
503 SND_SOC_DAPM_MUX("PGAB Input Mux", 517 SND_SOC_DAPM_MUX("PGAB Input Mux",
504 SND_SOC_NOPM, 0, 0, &p 518 SND_SOC_NOPM, 0, 0, &pgab_mux),
505 519
506 SND_SOC_DAPM_MUX("ADCA Mux", SND_SOC_N 520 SND_SOC_DAPM_MUX("ADCA Mux", SND_SOC_NOPM,
507 0, 0, &adca_mux), 521 0, 0, &adca_mux),
508 SND_SOC_DAPM_MUX("ADCB Mux", SND_SOC_N 522 SND_SOC_DAPM_MUX("ADCB Mux", SND_SOC_NOPM,
509 0, 0, &adcb_mux), 523 0, 0, &adcb_mux),
510 524
511 SND_SOC_DAPM_ADC("ADCA", NULL, CS42L56 525 SND_SOC_DAPM_ADC("ADCA", NULL, CS42L56_PWRCTL_1, 1, 1),
512 SND_SOC_DAPM_ADC("ADCB", NULL, CS42L56 526 SND_SOC_DAPM_ADC("ADCB", NULL, CS42L56_PWRCTL_1, 2, 1),
513 527
514 SND_SOC_DAPM_MUX("ADCA Swap Mux", SND_ 528 SND_SOC_DAPM_MUX("ADCA Swap Mux", SND_SOC_NOPM, 0, 0,
515 &adca_swap_mux), 529 &adca_swap_mux),
516 SND_SOC_DAPM_MUX("ADCB Swap Mux", SND_ 530 SND_SOC_DAPM_MUX("ADCB Swap Mux", SND_SOC_NOPM, 0, 0,
517 &adcb_swap_mux), 531 &adcb_swap_mux),
518 532
519 SND_SOC_DAPM_MUX("PCMA Swap Mux", SND_ 533 SND_SOC_DAPM_MUX("PCMA Swap Mux", SND_SOC_NOPM, 0, 0,
520 &pcma_swap_mux), 534 &pcma_swap_mux),
521 SND_SOC_DAPM_MUX("PCMB Swap Mux", SND_ 535 SND_SOC_DAPM_MUX("PCMB Swap Mux", SND_SOC_NOPM, 0, 0,
522 &pcmb_swap_mux), 536 &pcmb_swap_mux),
523 537
524 SND_SOC_DAPM_DAC("DACA", NULL, SND_SOC 538 SND_SOC_DAPM_DAC("DACA", NULL, SND_SOC_NOPM, 0, 0),
525 SND_SOC_DAPM_DAC("DACB", NULL, SND_SOC 539 SND_SOC_DAPM_DAC("DACB", NULL, SND_SOC_NOPM, 0, 0),
526 540
527 SND_SOC_DAPM_OUTPUT("HPA"), 541 SND_SOC_DAPM_OUTPUT("HPA"),
528 SND_SOC_DAPM_OUTPUT("LOA"), 542 SND_SOC_DAPM_OUTPUT("LOA"),
529 SND_SOC_DAPM_OUTPUT("HPB"), 543 SND_SOC_DAPM_OUTPUT("HPB"),
530 SND_SOC_DAPM_OUTPUT("LOB"), 544 SND_SOC_DAPM_OUTPUT("LOB"),
531 545
532 SND_SOC_DAPM_SWITCH("Headphone Right", 546 SND_SOC_DAPM_SWITCH("Headphone Right",
533 CS42L56_PWRCTL_2, 547 CS42L56_PWRCTL_2, 4, 1, &hpb_switch),
534 SND_SOC_DAPM_SWITCH("Headphone Left", 548 SND_SOC_DAPM_SWITCH("Headphone Left",
535 CS42L56_PWRCTL_2, 549 CS42L56_PWRCTL_2, 6, 1, &hpa_switch),
536 550
537 SND_SOC_DAPM_SWITCH("Lineout Right", 551 SND_SOC_DAPM_SWITCH("Lineout Right",
538 CS42L56_PWRCTL_2, 552 CS42L56_PWRCTL_2, 0, 1, &lob_switch),
539 SND_SOC_DAPM_SWITCH("Lineout Left", 553 SND_SOC_DAPM_SWITCH("Lineout Left",
540 CS42L56_PWRCTL_2, 554 CS42L56_PWRCTL_2, 2, 1, &loa_switch),
541 555
542 SND_SOC_DAPM_MUX("LINEOUTA Input Mux", 556 SND_SOC_DAPM_MUX("LINEOUTA Input Mux", SND_SOC_NOPM,
543 0, 0, &lineouta_input 557 0, 0, &lineouta_input),
544 SND_SOC_DAPM_MUX("LINEOUTB Input Mux", 558 SND_SOC_DAPM_MUX("LINEOUTB Input Mux", SND_SOC_NOPM,
545 0, 0, &lineoutb_input 559 0, 0, &lineoutb_input),
546 SND_SOC_DAPM_MUX("HPA Input Mux", SND_ 560 SND_SOC_DAPM_MUX("HPA Input Mux", SND_SOC_NOPM,
547 0, 0, &hpa_input), 561 0, 0, &hpa_input),
548 SND_SOC_DAPM_MUX("HPB Input Mux", SND_ 562 SND_SOC_DAPM_MUX("HPB Input Mux", SND_SOC_NOPM,
549 0, 0, &hpb_input), 563 0, 0, &hpb_input),
550 564
551 }; 565 };
552 566
553 static const struct snd_soc_dapm_route cs42l56 567 static const struct snd_soc_dapm_route cs42l56_audio_map[] = {
554 568
555 {"HiFi Capture", "DSP", "Digital Outpu 569 {"HiFi Capture", "DSP", "Digital Output Mux"},
556 {"HiFi Capture", "ADC", "Digital Outpu 570 {"HiFi Capture", "ADC", "Digital Output Mux"},
557 571
558 {"Digital Output Mux", NULL, "ADCA"}, 572 {"Digital Output Mux", NULL, "ADCA"},
559 {"Digital Output Mux", NULL, "ADCB"}, 573 {"Digital Output Mux", NULL, "ADCB"},
560 574
561 {"ADCB", NULL, "ADCB Swap Mux"}, 575 {"ADCB", NULL, "ADCB Swap Mux"},
562 {"ADCA", NULL, "ADCA Swap Mux"}, 576 {"ADCA", NULL, "ADCA Swap Mux"},
563 577
564 {"ADCA Swap Mux", NULL, "ADCA"}, 578 {"ADCA Swap Mux", NULL, "ADCA"},
565 {"ADCB Swap Mux", NULL, "ADCB"}, 579 {"ADCB Swap Mux", NULL, "ADCB"},
566 580
567 {"DACA", "Left", "ADCA Swap Mux"}, 581 {"DACA", "Left", "ADCA Swap Mux"},
568 {"DACA", "LR 2", "ADCA Swap Mux"}, 582 {"DACA", "LR 2", "ADCA Swap Mux"},
569 {"DACA", "Right", "ADCA Swap Mux"}, 583 {"DACA", "Right", "ADCA Swap Mux"},
570 584
571 {"DACB", "Left", "ADCB Swap Mux"}, 585 {"DACB", "Left", "ADCB Swap Mux"},
572 {"DACB", "LR 2", "ADCB Swap Mux"}, 586 {"DACB", "LR 2", "ADCB Swap Mux"},
573 {"DACB", "Right", "ADCB Swap Mux"}, 587 {"DACB", "Right", "ADCB Swap Mux"},
574 588
575 {"ADCA Mux", NULL, "AIN3A"}, 589 {"ADCA Mux", NULL, "AIN3A"},
576 {"ADCA Mux", NULL, "AIN2A"}, 590 {"ADCA Mux", NULL, "AIN2A"},
577 {"ADCA Mux", NULL, "AIN1A"}, 591 {"ADCA Mux", NULL, "AIN1A"},
578 {"ADCA Mux", NULL, "PGAA"}, 592 {"ADCA Mux", NULL, "PGAA"},
579 {"ADCB Mux", NULL, "AIN3B"}, 593 {"ADCB Mux", NULL, "AIN3B"},
580 {"ADCB Mux", NULL, "AIN2B"}, 594 {"ADCB Mux", NULL, "AIN2B"},
581 {"ADCB Mux", NULL, "AIN1B"}, 595 {"ADCB Mux", NULL, "AIN1B"},
582 {"ADCB Mux", NULL, "PGAB"}, 596 {"ADCB Mux", NULL, "PGAB"},
583 597
584 {"PGAA", "AIN1A", "PGAA Input Mux"}, 598 {"PGAA", "AIN1A", "PGAA Input Mux"},
585 {"PGAA", "AIN2A", "PGAA Input Mux"}, 599 {"PGAA", "AIN2A", "PGAA Input Mux"},
586 {"PGAA", "AIN3A", "PGAA Input Mux"}, 600 {"PGAA", "AIN3A", "PGAA Input Mux"},
587 {"PGAB", "AIN1B", "PGAB Input Mux"}, 601 {"PGAB", "AIN1B", "PGAB Input Mux"},
588 {"PGAB", "AIN2B", "PGAB Input Mux"}, 602 {"PGAB", "AIN2B", "PGAB Input Mux"},
589 {"PGAB", "AIN3B", "PGAB Input Mux"}, 603 {"PGAB", "AIN3B", "PGAB Input Mux"},
590 604
591 {"PGAA Input Mux", NULL, "AIN1A"}, 605 {"PGAA Input Mux", NULL, "AIN1A"},
592 {"PGAA Input Mux", NULL, "AIN2A"}, 606 {"PGAA Input Mux", NULL, "AIN2A"},
593 {"PGAA Input Mux", NULL, "AIN3A"}, 607 {"PGAA Input Mux", NULL, "AIN3A"},
594 {"PGAB Input Mux", NULL, "AIN1B"}, 608 {"PGAB Input Mux", NULL, "AIN1B"},
595 {"PGAB Input Mux", NULL, "AIN2B"}, 609 {"PGAB Input Mux", NULL, "AIN2B"},
596 {"PGAB Input Mux", NULL, "AIN3B"}, 610 {"PGAB Input Mux", NULL, "AIN3B"},
597 611
598 {"LOB", "Switch", "LINEOUTB Input Mux" 612 {"LOB", "Switch", "LINEOUTB Input Mux"},
599 {"LOA", "Switch", "LINEOUTA Input Mux" 613 {"LOA", "Switch", "LINEOUTA Input Mux"},
600 614
601 {"LINEOUTA Input Mux", "PGAA", "PGAA"} 615 {"LINEOUTA Input Mux", "PGAA", "PGAA"},
602 {"LINEOUTB Input Mux", "PGAB", "PGAB"} 616 {"LINEOUTB Input Mux", "PGAB", "PGAB"},
603 {"LINEOUTA Input Mux", "DACA", "DACA"} 617 {"LINEOUTA Input Mux", "DACA", "DACA"},
604 {"LINEOUTB Input Mux", "DACB", "DACB"} 618 {"LINEOUTB Input Mux", "DACB", "DACB"},
605 619
606 {"HPA", "Switch", "HPB Input Mux"}, 620 {"HPA", "Switch", "HPB Input Mux"},
607 {"HPB", "Switch", "HPA Input Mux"}, 621 {"HPB", "Switch", "HPA Input Mux"},
608 622
609 {"HPA Input Mux", "PGAA", "PGAA"}, 623 {"HPA Input Mux", "PGAA", "PGAA"},
610 {"HPB Input Mux", "PGAB", "PGAB"}, 624 {"HPB Input Mux", "PGAB", "PGAB"},
611 {"HPA Input Mux", "DACA", "DACA"}, 625 {"HPA Input Mux", "DACA", "DACA"},
612 {"HPB Input Mux", "DACB", "DACB"}, 626 {"HPB Input Mux", "DACB", "DACB"},
613 627
614 {"DACA", NULL, "PCMA Swap Mux"}, 628 {"DACA", NULL, "PCMA Swap Mux"},
615 {"DACB", NULL, "PCMB Swap Mux"}, 629 {"DACB", NULL, "PCMB Swap Mux"},
616 630
617 {"PCMB Swap Mux", "Left", "HiFi Playba 631 {"PCMB Swap Mux", "Left", "HiFi Playback"},
618 {"PCMB Swap Mux", "LR 2", "HiFi Playba 632 {"PCMB Swap Mux", "LR 2", "HiFi Playback"},
619 {"PCMB Swap Mux", "Right", "HiFi Playb 633 {"PCMB Swap Mux", "Right", "HiFi Playback"},
620 634
621 {"PCMA Swap Mux", "Left", "HiFi Playba 635 {"PCMA Swap Mux", "Left", "HiFi Playback"},
622 {"PCMA Swap Mux", "LR 2", "HiFi Playba 636 {"PCMA Swap Mux", "LR 2", "HiFi Playback"},
623 {"PCMA Swap Mux", "Right", "HiFi Playb 637 {"PCMA Swap Mux", "Right", "HiFi Playback"},
624 638
625 }; 639 };
626 640
627 struct cs42l56_clk_para { 641 struct cs42l56_clk_para {
628 u32 mclk; 642 u32 mclk;
629 u32 srate; 643 u32 srate;
630 u8 ratio; 644 u8 ratio;
631 }; 645 };
632 646
633 static const struct cs42l56_clk_para clk_ratio 647 static const struct cs42l56_clk_para clk_ratio_table[] = {
634 /* 8k */ 648 /* 8k */
635 { 6000000, 8000, CS42L56_MCLK_LRCLK_76 649 { 6000000, 8000, CS42L56_MCLK_LRCLK_768 },
636 { 6144000, 8000, CS42L56_MCLK_LRCLK_75 650 { 6144000, 8000, CS42L56_MCLK_LRCLK_750 },
637 { 12000000, 8000, CS42L56_MCLK_LRCLK_7 651 { 12000000, 8000, CS42L56_MCLK_LRCLK_768 },
638 { 12288000, 8000, CS42L56_MCLK_LRCLK_7 652 { 12288000, 8000, CS42L56_MCLK_LRCLK_750 },
639 { 24000000, 8000, CS42L56_MCLK_LRCLK_7 653 { 24000000, 8000, CS42L56_MCLK_LRCLK_768 },
640 { 24576000, 8000, CS42L56_MCLK_LRCLK_7 654 { 24576000, 8000, CS42L56_MCLK_LRCLK_750 },
641 /* 11.025k */ 655 /* 11.025k */
642 { 5644800, 11025, CS42L56_MCLK_LRCLK_5 656 { 5644800, 11025, CS42L56_MCLK_LRCLK_512},
643 { 11289600, 11025, CS42L56_MCLK_LRCLK_ 657 { 11289600, 11025, CS42L56_MCLK_LRCLK_512},
644 { 22579200, 11025, CS42L56_MCLK_LRCLK_ 658 { 22579200, 11025, CS42L56_MCLK_LRCLK_512 },
645 /* 11.0294k */ 659 /* 11.0294k */
646 { 6000000, 110294, CS42L56_MCLK_LRCLK_ 660 { 6000000, 110294, CS42L56_MCLK_LRCLK_544 },
647 { 12000000, 110294, CS42L56_MCLK_LRCLK 661 { 12000000, 110294, CS42L56_MCLK_LRCLK_544 },
648 { 24000000, 110294, CS42L56_MCLK_LRCLK 662 { 24000000, 110294, CS42L56_MCLK_LRCLK_544 },
649 /* 12k */ 663 /* 12k */
650 { 6000000, 12000, CS42L56_MCLK_LRCLK_5 664 { 6000000, 12000, CS42L56_MCLK_LRCLK_500 },
651 { 6144000, 12000, CS42L56_MCLK_LRCLK_5 665 { 6144000, 12000, CS42L56_MCLK_LRCLK_512 },
652 { 12000000, 12000, CS42L56_MCLK_LRCLK_ 666 { 12000000, 12000, CS42L56_MCLK_LRCLK_500 },
653 { 12288000, 12000, CS42L56_MCLK_LRCLK_ 667 { 12288000, 12000, CS42L56_MCLK_LRCLK_512 },
654 { 24000000, 12000, CS42L56_MCLK_LRCLK_ 668 { 24000000, 12000, CS42L56_MCLK_LRCLK_500 },
655 { 24576000, 12000, CS42L56_MCLK_LRCLK_ 669 { 24576000, 12000, CS42L56_MCLK_LRCLK_512 },
656 /* 16k */ 670 /* 16k */
657 { 6000000, 16000, CS42L56_MCLK_LRCLK_3 671 { 6000000, 16000, CS42L56_MCLK_LRCLK_375 },
658 { 6144000, 16000, CS42L56_MCLK_LRCLK_3 672 { 6144000, 16000, CS42L56_MCLK_LRCLK_384 },
659 { 12000000, 16000, CS42L56_MCLK_LRCLK_ 673 { 12000000, 16000, CS42L56_MCLK_LRCLK_375 },
660 { 12288000, 16000, CS42L56_MCLK_LRCLK_ 674 { 12288000, 16000, CS42L56_MCLK_LRCLK_384 },
661 { 24000000, 16000, CS42L56_MCLK_LRCLK_ 675 { 24000000, 16000, CS42L56_MCLK_LRCLK_375 },
662 { 24576000, 16000, CS42L56_MCLK_LRCLK_ 676 { 24576000, 16000, CS42L56_MCLK_LRCLK_384 },
663 /* 22.050k */ 677 /* 22.050k */
664 { 5644800, 22050, CS42L56_MCLK_LRCLK_2 678 { 5644800, 22050, CS42L56_MCLK_LRCLK_256 },
665 { 11289600, 22050, CS42L56_MCLK_LRCLK_ 679 { 11289600, 22050, CS42L56_MCLK_LRCLK_256 },
666 { 22579200, 22050, CS42L56_MCLK_LRCLK_ 680 { 22579200, 22050, CS42L56_MCLK_LRCLK_256 },
667 /* 22.0588k */ 681 /* 22.0588k */
668 { 6000000, 220588, CS42L56_MCLK_LRCLK_ 682 { 6000000, 220588, CS42L56_MCLK_LRCLK_272 },
669 { 12000000, 220588, CS42L56_MCLK_LRCLK 683 { 12000000, 220588, CS42L56_MCLK_LRCLK_272 },
670 { 24000000, 220588, CS42L56_MCLK_LRCLK 684 { 24000000, 220588, CS42L56_MCLK_LRCLK_272 },
671 /* 24k */ 685 /* 24k */
672 { 6000000, 24000, CS42L56_MCLK_LRCLK_2 686 { 6000000, 24000, CS42L56_MCLK_LRCLK_250 },
673 { 6144000, 24000, CS42L56_MCLK_LRCLK_2 687 { 6144000, 24000, CS42L56_MCLK_LRCLK_256 },
674 { 12000000, 24000, CS42L56_MCLK_LRCLK_ 688 { 12000000, 24000, CS42L56_MCLK_LRCLK_250 },
675 { 12288000, 24000, CS42L56_MCLK_LRCLK_ 689 { 12288000, 24000, CS42L56_MCLK_LRCLK_256 },
676 { 24000000, 24000, CS42L56_MCLK_LRCLK_ 690 { 24000000, 24000, CS42L56_MCLK_LRCLK_250 },
677 { 24576000, 24000, CS42L56_MCLK_LRCLK_ 691 { 24576000, 24000, CS42L56_MCLK_LRCLK_256 },
678 /* 32k */ 692 /* 32k */
679 { 6000000, 32000, CS42L56_MCLK_LRCLK_1 693 { 6000000, 32000, CS42L56_MCLK_LRCLK_187P5 },
680 { 6144000, 32000, CS42L56_MCLK_LRCLK_1 694 { 6144000, 32000, CS42L56_MCLK_LRCLK_192 },
681 { 12000000, 32000, CS42L56_MCLK_LRCLK_ 695 { 12000000, 32000, CS42L56_MCLK_LRCLK_187P5 },
682 { 12288000, 32000, CS42L56_MCLK_LRCLK_ 696 { 12288000, 32000, CS42L56_MCLK_LRCLK_192 },
683 { 24000000, 32000, CS42L56_MCLK_LRCLK_ 697 { 24000000, 32000, CS42L56_MCLK_LRCLK_187P5 },
684 { 24576000, 32000, CS42L56_MCLK_LRCLK_ 698 { 24576000, 32000, CS42L56_MCLK_LRCLK_192 },
685 /* 44.118k */ 699 /* 44.118k */
686 { 6000000, 44118, CS42L56_MCLK_LRCLK_1 700 { 6000000, 44118, CS42L56_MCLK_LRCLK_136 },
687 { 12000000, 44118, CS42L56_MCLK_LRCLK_ 701 { 12000000, 44118, CS42L56_MCLK_LRCLK_136 },
688 { 24000000, 44118, CS42L56_MCLK_LRCLK_ 702 { 24000000, 44118, CS42L56_MCLK_LRCLK_136 },
689 /* 44.1k */ 703 /* 44.1k */
690 { 5644800, 44100, CS42L56_MCLK_LRCLK_1 704 { 5644800, 44100, CS42L56_MCLK_LRCLK_128 },
691 { 11289600, 44100, CS42L56_MCLK_LRCLK_ 705 { 11289600, 44100, CS42L56_MCLK_LRCLK_128 },
692 { 22579200, 44100, CS42L56_MCLK_LRCLK_ 706 { 22579200, 44100, CS42L56_MCLK_LRCLK_128 },
693 /* 48k */ 707 /* 48k */
694 { 6000000, 48000, CS42L56_MCLK_LRCLK_1 708 { 6000000, 48000, CS42L56_MCLK_LRCLK_125 },
695 { 6144000, 48000, CS42L56_MCLK_LRCLK_1 709 { 6144000, 48000, CS42L56_MCLK_LRCLK_128 },
696 { 12000000, 48000, CS42L56_MCLK_LRCLK_ 710 { 12000000, 48000, CS42L56_MCLK_LRCLK_125 },
697 { 12288000, 48000, CS42L56_MCLK_LRCLK_ 711 { 12288000, 48000, CS42L56_MCLK_LRCLK_128 },
698 { 24000000, 48000, CS42L56_MCLK_LRCLK_ 712 { 24000000, 48000, CS42L56_MCLK_LRCLK_125 },
699 { 24576000, 48000, CS42L56_MCLK_LRCLK_ 713 { 24576000, 48000, CS42L56_MCLK_LRCLK_128 },
700 }; 714 };
701 715
702 static int cs42l56_get_mclk_ratio(int mclk, in 716 static int cs42l56_get_mclk_ratio(int mclk, int rate)
703 { 717 {
704 int i; 718 int i;
705 719
706 for (i = 0; i < ARRAY_SIZE(clk_ratio_t 720 for (i = 0; i < ARRAY_SIZE(clk_ratio_table); i++) {
707 if (clk_ratio_table[i].mclk == 721 if (clk_ratio_table[i].mclk == mclk &&
708 clk_ratio_table[i].srate = 722 clk_ratio_table[i].srate == rate)
709 return clk_ratio_table 723 return clk_ratio_table[i].ratio;
710 } 724 }
711 return -EINVAL; 725 return -EINVAL;
712 } 726 }
713 727
714 static int cs42l56_set_sysclk(struct snd_soc_d 728 static int cs42l56_set_sysclk(struct snd_soc_dai *codec_dai,
715 int clk_id, unsigned i 729 int clk_id, unsigned int freq, int dir)
716 { 730 {
717 struct snd_soc_component *component = !! 731 struct snd_soc_codec *codec = codec_dai->codec;
718 struct cs42l56_private *cs42l56 = snd_ !! 732 struct cs42l56_private *cs42l56 = snd_soc_codec_get_drvdata(codec);
719 733
720 switch (freq) { 734 switch (freq) {
721 case CS42L56_MCLK_5P6448MHZ: 735 case CS42L56_MCLK_5P6448MHZ:
722 case CS42L56_MCLK_6MHZ: 736 case CS42L56_MCLK_6MHZ:
723 case CS42L56_MCLK_6P144MHZ: 737 case CS42L56_MCLK_6P144MHZ:
724 cs42l56->mclk_div2 = 0; 738 cs42l56->mclk_div2 = 0;
725 cs42l56->mclk_prediv = 0; 739 cs42l56->mclk_prediv = 0;
726 break; 740 break;
727 case CS42L56_MCLK_11P2896MHZ: 741 case CS42L56_MCLK_11P2896MHZ:
728 case CS42L56_MCLK_12MHZ: 742 case CS42L56_MCLK_12MHZ:
729 case CS42L56_MCLK_12P288MHZ: 743 case CS42L56_MCLK_12P288MHZ:
730 cs42l56->mclk_div2 = CS42L56_M 744 cs42l56->mclk_div2 = CS42L56_MCLK_DIV2;
731 cs42l56->mclk_prediv = 0; 745 cs42l56->mclk_prediv = 0;
732 break; 746 break;
733 case CS42L56_MCLK_22P5792MHZ: 747 case CS42L56_MCLK_22P5792MHZ:
734 case CS42L56_MCLK_24MHZ: 748 case CS42L56_MCLK_24MHZ:
735 case CS42L56_MCLK_24P576MHZ: 749 case CS42L56_MCLK_24P576MHZ:
736 cs42l56->mclk_div2 = CS42L56_M 750 cs42l56->mclk_div2 = CS42L56_MCLK_DIV2;
737 cs42l56->mclk_prediv = CS42L56 751 cs42l56->mclk_prediv = CS42L56_MCLK_PREDIV;
738 break; 752 break;
739 default: 753 default:
740 return -EINVAL; 754 return -EINVAL;
741 } 755 }
742 cs42l56->mclk = freq; 756 cs42l56->mclk = freq;
743 757
744 snd_soc_component_update_bits(componen !! 758 snd_soc_update_bits(codec, CS42L56_CLKCTL_1,
745 CS42L56_MCLK_PREDI 759 CS42L56_MCLK_PREDIV_MASK,
746 cs42l56->mclk_ 760 cs42l56->mclk_prediv);
747 snd_soc_component_update_bits(componen !! 761 snd_soc_update_bits(codec, CS42L56_CLKCTL_1,
748 CS42L56_MCLK_DIV2_ 762 CS42L56_MCLK_DIV2_MASK,
749 cs42l56->mclk_ 763 cs42l56->mclk_div2);
750 764
751 return 0; 765 return 0;
752 } 766 }
753 767
754 static int cs42l56_set_dai_fmt(struct snd_soc_ 768 static int cs42l56_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
755 { 769 {
756 struct snd_soc_component *component = !! 770 struct snd_soc_codec *codec = codec_dai->codec;
757 struct cs42l56_private *cs42l56 = snd_ !! 771 struct cs42l56_private *cs42l56 = snd_soc_codec_get_drvdata(codec);
758 772
759 switch (fmt & SND_SOC_DAIFMT_MASTER_MA 773 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
760 case SND_SOC_DAIFMT_CBM_CFM: 774 case SND_SOC_DAIFMT_CBM_CFM:
761 cs42l56->iface = CS42L56_MASTE 775 cs42l56->iface = CS42L56_MASTER_MODE;
762 break; 776 break;
763 case SND_SOC_DAIFMT_CBS_CFS: 777 case SND_SOC_DAIFMT_CBS_CFS:
764 cs42l56->iface = CS42L56_SLAVE 778 cs42l56->iface = CS42L56_SLAVE_MODE;
765 break; 779 break;
766 default: 780 default:
767 return -EINVAL; 781 return -EINVAL;
768 } 782 }
769 783
770 /* interface format */ 784 /* interface format */
771 switch (fmt & SND_SOC_DAIFMT_FORMAT_MA 785 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
772 case SND_SOC_DAIFMT_I2S: 786 case SND_SOC_DAIFMT_I2S:
773 cs42l56->iface_fmt = CS42L56_D 787 cs42l56->iface_fmt = CS42L56_DIG_FMT_I2S;
774 break; 788 break;
775 case SND_SOC_DAIFMT_LEFT_J: 789 case SND_SOC_DAIFMT_LEFT_J:
776 cs42l56->iface_fmt = CS42L56_D 790 cs42l56->iface_fmt = CS42L56_DIG_FMT_LEFT_J;
777 break; 791 break;
778 default: 792 default:
779 return -EINVAL; 793 return -EINVAL;
780 } 794 }
781 795
782 /* sclk inversion */ 796 /* sclk inversion */
783 switch (fmt & SND_SOC_DAIFMT_INV_MASK) 797 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
784 case SND_SOC_DAIFMT_NB_NF: 798 case SND_SOC_DAIFMT_NB_NF:
785 cs42l56->iface_inv = 0; 799 cs42l56->iface_inv = 0;
786 break; 800 break;
787 case SND_SOC_DAIFMT_IB_NF: 801 case SND_SOC_DAIFMT_IB_NF:
788 cs42l56->iface_inv = CS42L56_S 802 cs42l56->iface_inv = CS42L56_SCLK_INV;
789 break; 803 break;
790 default: 804 default:
791 return -EINVAL; 805 return -EINVAL;
792 } 806 }
793 807
794 snd_soc_component_update_bits(componen !! 808 snd_soc_update_bits(codec, CS42L56_CLKCTL_1,
795 CS42L56_MS_MODE_MA 809 CS42L56_MS_MODE_MASK, cs42l56->iface);
796 snd_soc_component_update_bits(componen !! 810 snd_soc_update_bits(codec, CS42L56_SERIAL_FMT,
797 CS42L56_DIG_FMT_MA 811 CS42L56_DIG_FMT_MASK, cs42l56->iface_fmt);
798 snd_soc_component_update_bits(componen !! 812 snd_soc_update_bits(codec, CS42L56_CLKCTL_1,
799 CS42L56_SCLK_INV_M 813 CS42L56_SCLK_INV_MASK, cs42l56->iface_inv);
800 return 0; 814 return 0;
801 } 815 }
802 816
803 static int cs42l56_mute(struct snd_soc_dai *da !! 817 static int cs42l56_digital_mute(struct snd_soc_dai *dai, int mute)
804 { 818 {
805 struct snd_soc_component *component = !! 819 struct snd_soc_codec *codec = dai->codec;
806 820
807 if (mute) { 821 if (mute) {
808 /* Hit the DSP Mixer first */ 822 /* Hit the DSP Mixer first */
809 snd_soc_component_update_bits( !! 823 snd_soc_update_bits(codec, CS42L56_DSP_MUTE_CTL,
810 CS42L56_AD 824 CS42L56_ADCAMIX_MUTE_MASK |
811 CS42L56_AD 825 CS42L56_ADCBMIX_MUTE_MASK |
812 CS42L56_PC 826 CS42L56_PCMAMIX_MUTE_MASK |
813 CS42L56_PC 827 CS42L56_PCMBMIX_MUTE_MASK |
814 CS42L56_MS 828 CS42L56_MSTB_MUTE_MASK |
815 CS42L56_MS 829 CS42L56_MSTA_MUTE_MASK,
816 CS42L56_MU 830 CS42L56_MUTE_ALL);
817 /* Mute ADC's */ 831 /* Mute ADC's */
818 snd_soc_component_update_bits( !! 832 snd_soc_update_bits(codec, CS42L56_MISC_ADC_CTL,
819 CS42L56_AD 833 CS42L56_ADCA_MUTE_MASK |
820 CS42L56_AD 834 CS42L56_ADCB_MUTE_MASK,
821 CS42L56_MU 835 CS42L56_MUTE_ALL);
822 /* HP And LO */ 836 /* HP And LO */
823 snd_soc_component_update_bits( !! 837 snd_soc_update_bits(codec, CS42L56_HPA_VOLUME,
824 CS42L56_HP 838 CS42L56_HP_MUTE_MASK, CS42L56_MUTE_ALL);
825 snd_soc_component_update_bits( !! 839 snd_soc_update_bits(codec, CS42L56_HPB_VOLUME,
826 CS42L56_HP 840 CS42L56_HP_MUTE_MASK, CS42L56_MUTE_ALL);
827 snd_soc_component_update_bits( !! 841 snd_soc_update_bits(codec, CS42L56_LOA_VOLUME,
828 CS42L56_LO 842 CS42L56_LO_MUTE_MASK, CS42L56_MUTE_ALL);
829 snd_soc_component_update_bits( !! 843 snd_soc_update_bits(codec, CS42L56_LOB_VOLUME,
830 CS42L56_LO 844 CS42L56_LO_MUTE_MASK, CS42L56_MUTE_ALL);
831 } else { 845 } else {
832 snd_soc_component_update_bits( !! 846 snd_soc_update_bits(codec, CS42L56_DSP_MUTE_CTL,
833 CS42L56_AD 847 CS42L56_ADCAMIX_MUTE_MASK |
834 CS42L56_AD 848 CS42L56_ADCBMIX_MUTE_MASK |
835 CS42L56_PC 849 CS42L56_PCMAMIX_MUTE_MASK |
836 CS42L56_PC 850 CS42L56_PCMBMIX_MUTE_MASK |
837 CS42L56_MS 851 CS42L56_MSTB_MUTE_MASK |
838 CS42L56_MS 852 CS42L56_MSTA_MUTE_MASK,
839 CS42L56_UN 853 CS42L56_UNMUTE);
840 854
841 snd_soc_component_update_bits( !! 855 snd_soc_update_bits(codec, CS42L56_MISC_ADC_CTL,
842 CS42L56_AD 856 CS42L56_ADCA_MUTE_MASK |
843 CS42L56_AD 857 CS42L56_ADCB_MUTE_MASK,
844 CS42L56_UN 858 CS42L56_UNMUTE);
845 859
846 snd_soc_component_update_bits( !! 860 snd_soc_update_bits(codec, CS42L56_HPA_VOLUME,
847 CS42L56_HP 861 CS42L56_HP_MUTE_MASK, CS42L56_UNMUTE);
848 snd_soc_component_update_bits( !! 862 snd_soc_update_bits(codec, CS42L56_HPB_VOLUME,
849 CS42L56_HP 863 CS42L56_HP_MUTE_MASK, CS42L56_UNMUTE);
850 snd_soc_component_update_bits( !! 864 snd_soc_update_bits(codec, CS42L56_LOA_VOLUME,
851 CS42L56_LO 865 CS42L56_LO_MUTE_MASK, CS42L56_UNMUTE);
852 snd_soc_component_update_bits( !! 866 snd_soc_update_bits(codec, CS42L56_LOB_VOLUME,
853 CS42L56_LO 867 CS42L56_LO_MUTE_MASK, CS42L56_UNMUTE);
854 } 868 }
855 return 0; 869 return 0;
856 } 870 }
857 871
858 static int cs42l56_pcm_hw_params(struct snd_pc 872 static int cs42l56_pcm_hw_params(struct snd_pcm_substream *substream,
859 struct sn 873 struct snd_pcm_hw_params *params,
860 struct sn 874 struct snd_soc_dai *dai)
861 { 875 {
862 struct snd_soc_component *component = !! 876 struct snd_soc_codec *codec = dai->codec;
863 struct cs42l56_private *cs42l56 = snd_ !! 877 struct cs42l56_private *cs42l56 = snd_soc_codec_get_drvdata(codec);
864 int ratio; 878 int ratio;
865 879
866 ratio = cs42l56_get_mclk_ratio(cs42l56 880 ratio = cs42l56_get_mclk_ratio(cs42l56->mclk, params_rate(params));
867 if (ratio >= 0) { 881 if (ratio >= 0) {
868 snd_soc_component_update_bits( !! 882 snd_soc_update_bits(codec, CS42L56_CLKCTL_2,
869 CS42L56_CL 883 CS42L56_CLK_RATIO_MASK, ratio);
870 } else { 884 } else {
871 dev_err(component->dev, "unsup !! 885 dev_err(codec->dev, "unsupported mclk/sclk/lrclk ratio\n");
872 return -EINVAL; 886 return -EINVAL;
873 } 887 }
874 888
875 return 0; 889 return 0;
876 } 890 }
877 891
878 static int cs42l56_set_bias_level(struct snd_s !! 892 static int cs42l56_set_bias_level(struct snd_soc_codec *codec,
879 enum s 893 enum snd_soc_bias_level level)
880 { 894 {
881 struct cs42l56_private *cs42l56 = snd_ !! 895 struct cs42l56_private *cs42l56 = snd_soc_codec_get_drvdata(codec);
882 int ret; 896 int ret;
883 897
884 switch (level) { 898 switch (level) {
885 case SND_SOC_BIAS_ON: 899 case SND_SOC_BIAS_ON:
886 break; 900 break;
887 case SND_SOC_BIAS_PREPARE: 901 case SND_SOC_BIAS_PREPARE:
888 snd_soc_component_update_bits( !! 902 snd_soc_update_bits(codec, CS42L56_CLKCTL_1,
889 CS42L56_MC 903 CS42L56_MCLK_DIS_MASK, 0);
890 snd_soc_component_update_bits( !! 904 snd_soc_update_bits(codec, CS42L56_PWRCTL_1,
891 CS42L56_PD 905 CS42L56_PDN_ALL_MASK, 0);
892 break; 906 break;
893 case SND_SOC_BIAS_STANDBY: 907 case SND_SOC_BIAS_STANDBY:
894 if (snd_soc_component_get_bias !! 908 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
895 regcache_cache_only(cs 909 regcache_cache_only(cs42l56->regmap, false);
896 regcache_sync(cs42l56- 910 regcache_sync(cs42l56->regmap);
897 ret = regulator_bulk_e 911 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l56->supplies),
898 912 cs42l56->supplies);
899 if (ret != 0) { 913 if (ret != 0) {
900 dev_err(cs42l5 914 dev_err(cs42l56->dev,
901 "Faile 915 "Failed to enable regulators: %d\n",
902 ret); 916 ret);
903 return ret; 917 return ret;
904 } 918 }
905 } 919 }
906 snd_soc_component_update_bits( !! 920 snd_soc_update_bits(codec, CS42L56_PWRCTL_1,
907 CS42L56_PD 921 CS42L56_PDN_ALL_MASK, 1);
908 break; 922 break;
909 case SND_SOC_BIAS_OFF: 923 case SND_SOC_BIAS_OFF:
910 snd_soc_component_update_bits( !! 924 snd_soc_update_bits(codec, CS42L56_PWRCTL_1,
911 CS42L56_PD 925 CS42L56_PDN_ALL_MASK, 1);
912 snd_soc_component_update_bits( !! 926 snd_soc_update_bits(codec, CS42L56_CLKCTL_1,
913 CS42L56_MC 927 CS42L56_MCLK_DIS_MASK, 1);
914 regcache_cache_only(cs42l56->r 928 regcache_cache_only(cs42l56->regmap, true);
915 regulator_bulk_disable(ARRAY_S 929 regulator_bulk_disable(ARRAY_SIZE(cs42l56->supplies),
916 930 cs42l56->supplies);
917 break; 931 break;
918 } 932 }
919 933
920 return 0; 934 return 0;
921 } 935 }
922 936
923 #define CS42L56_RATES (SNDRV_PCM_RATE_8000_480 937 #define CS42L56_RATES (SNDRV_PCM_RATE_8000_48000)
924 938
925 #define CS42L56_FORMATS (SNDRV_PCM_FMTBIT_S16_ 939 #define CS42L56_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
926 SNDRV_PCM_FMTBIT_S20_3 940 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
927 SNDRV_PCM_FMTBIT_S32_L 941 SNDRV_PCM_FMTBIT_S32_LE)
928 942
929 943
930 static const struct snd_soc_dai_ops cs42l56_op 944 static const struct snd_soc_dai_ops cs42l56_ops = {
931 .hw_params = cs42l56_pcm_hw_param 945 .hw_params = cs42l56_pcm_hw_params,
932 .mute_stream = cs42l56_mute, !! 946 .digital_mute = cs42l56_digital_mute,
933 .set_fmt = cs42l56_set_dai_fmt, 947 .set_fmt = cs42l56_set_dai_fmt,
934 .set_sysclk = cs42l56_set_sysclk, 948 .set_sysclk = cs42l56_set_sysclk,
935 .no_capture_mute = 1, <<
936 }; 949 };
937 950
938 static struct snd_soc_dai_driver cs42l56_dai = 951 static struct snd_soc_dai_driver cs42l56_dai = {
939 .name = "cs42l56", 952 .name = "cs42l56",
940 .playback = { 953 .playback = {
941 .stream_name = "HiFi P 954 .stream_name = "HiFi Playback",
942 .channels_min = 1, 955 .channels_min = 1,
943 .channels_max = 2, 956 .channels_max = 2,
944 .rates = CS42L56_RATES 957 .rates = CS42L56_RATES,
945 .formats = CS42L56_FOR 958 .formats = CS42L56_FORMATS,
946 }, 959 },
947 .capture = { 960 .capture = {
948 .stream_name = "HiFi C 961 .stream_name = "HiFi Capture",
949 .channels_min = 1, 962 .channels_min = 1,
950 .channels_max = 2, 963 .channels_max = 2,
951 .rates = CS42L56_RATES 964 .rates = CS42L56_RATES,
952 .formats = CS42L56_FOR 965 .formats = CS42L56_FORMATS,
953 }, 966 },
954 .ops = &cs42l56_ops, 967 .ops = &cs42l56_ops,
955 }; 968 };
956 969
957 static int beep_freq[] = { 970 static int beep_freq[] = {
958 261, 522, 585, 667, 706, 774, 889, 100 971 261, 522, 585, 667, 706, 774, 889, 1000,
959 1043, 1200, 1333, 1412, 1600, 1714, 20 972 1043, 1200, 1333, 1412, 1600, 1714, 2000, 2182
960 }; 973 };
961 974
962 static void cs42l56_beep_work(struct work_stru 975 static void cs42l56_beep_work(struct work_struct *work)
963 { 976 {
964 struct cs42l56_private *cs42l56 = 977 struct cs42l56_private *cs42l56 =
965 container_of(work, struct cs42 978 container_of(work, struct cs42l56_private, beep_work);
966 struct snd_soc_component *component = !! 979 struct snd_soc_codec *codec = cs42l56->codec;
967 struct snd_soc_dapm_context *dapm = sn !! 980 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
968 int i; 981 int i;
969 int val = 0; 982 int val = 0;
970 int best = 0; 983 int best = 0;
971 984
972 if (cs42l56->beep_rate) { 985 if (cs42l56->beep_rate) {
973 for (i = 0; i < ARRAY_SIZE(bee 986 for (i = 0; i < ARRAY_SIZE(beep_freq); i++) {
974 if (abs(cs42l56->beep_ 987 if (abs(cs42l56->beep_rate - beep_freq[i]) <
975 abs(cs42l56->beep_ 988 abs(cs42l56->beep_rate - beep_freq[best]))
976 best = i; 989 best = i;
977 } 990 }
978 991
979 dev_dbg(component->dev, "Set b !! 992 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
980 beep_freq[best], cs42l 993 beep_freq[best], cs42l56->beep_rate);
981 994
982 val = (best << CS42L56_BEEP_RA 995 val = (best << CS42L56_BEEP_RATE_SHIFT);
983 996
984 snd_soc_dapm_enable_pin(dapm, 997 snd_soc_dapm_enable_pin(dapm, "Beep");
985 } else { 998 } else {
986 dev_dbg(component->dev, "Disab !! 999 dev_dbg(codec->dev, "Disabling beep\n");
987 snd_soc_dapm_disable_pin(dapm, 1000 snd_soc_dapm_disable_pin(dapm, "Beep");
988 } 1001 }
989 1002
990 snd_soc_component_update_bits(componen !! 1003 snd_soc_update_bits(codec, CS42L56_BEEP_FREQ_ONTIME,
991 CS42L56_BEEP_FREQ_ 1004 CS42L56_BEEP_FREQ_MASK, val);
992 1005
993 snd_soc_dapm_sync(dapm); 1006 snd_soc_dapm_sync(dapm);
994 } 1007 }
995 1008
996 /* For usability define a way of injecting bee 1009 /* For usability define a way of injecting beep events for the device -
997 * many systems will not have a keyboard. 1010 * many systems will not have a keyboard.
998 */ 1011 */
999 static int cs42l56_beep_event(struct input_dev 1012 static int cs42l56_beep_event(struct input_dev *dev, unsigned int type,
1000 unsigned int cod 1013 unsigned int code, int hz)
1001 { 1014 {
1002 struct snd_soc_component *component = !! 1015 struct snd_soc_codec *codec = input_get_drvdata(dev);
1003 struct cs42l56_private *cs42l56 = snd !! 1016 struct cs42l56_private *cs42l56 = snd_soc_codec_get_drvdata(codec);
1004 1017
1005 dev_dbg(component->dev, "Beep event % !! 1018 dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
1006 1019
1007 switch (code) { 1020 switch (code) {
1008 case SND_BELL: 1021 case SND_BELL:
1009 if (hz) 1022 if (hz)
1010 hz = 261; 1023 hz = 261;
1011 break; <<
1012 case SND_TONE: 1024 case SND_TONE:
1013 break; 1025 break;
1014 default: 1026 default:
1015 return -1; 1027 return -1;
1016 } 1028 }
1017 1029
1018 /* Kick the beep from a workqueue */ 1030 /* Kick the beep from a workqueue */
1019 cs42l56->beep_rate = hz; 1031 cs42l56->beep_rate = hz;
1020 schedule_work(&cs42l56->beep_work); 1032 schedule_work(&cs42l56->beep_work);
1021 return 0; 1033 return 0;
1022 } 1034 }
1023 1035
1024 static ssize_t beep_store(struct device *dev, !! 1036 static ssize_t cs42l56_beep_set(struct device *dev,
1025 const char *buf, si !! 1037 struct device_attribute *attr,
>> 1038 const char *buf, size_t count)
1026 { 1039 {
1027 struct cs42l56_private *cs42l56 = dev 1040 struct cs42l56_private *cs42l56 = dev_get_drvdata(dev);
1028 long int time; 1041 long int time;
1029 int ret; 1042 int ret;
1030 1043
1031 ret = kstrtol(buf, 10, &time); 1044 ret = kstrtol(buf, 10, &time);
1032 if (ret != 0) 1045 if (ret != 0)
1033 return ret; 1046 return ret;
1034 1047
1035 input_event(cs42l56->beep, EV_SND, SN 1048 input_event(cs42l56->beep, EV_SND, SND_TONE, time);
1036 1049
1037 return count; 1050 return count;
1038 } 1051 }
1039 1052
1040 static DEVICE_ATTR_WO(beep); !! 1053 static DEVICE_ATTR(beep, 0200, NULL, cs42l56_beep_set);
1041 1054
1042 static void cs42l56_init_beep(struct snd_soc_ !! 1055 static void cs42l56_init_beep(struct snd_soc_codec *codec)
1043 { 1056 {
1044 struct cs42l56_private *cs42l56 = snd !! 1057 struct cs42l56_private *cs42l56 = snd_soc_codec_get_drvdata(codec);
1045 int ret; 1058 int ret;
1046 1059
1047 cs42l56->beep = devm_input_allocate_d !! 1060 cs42l56->beep = devm_input_allocate_device(codec->dev);
1048 if (!cs42l56->beep) { 1061 if (!cs42l56->beep) {
1049 dev_err(component->dev, "Fail !! 1062 dev_err(codec->dev, "Failed to allocate beep device\n");
1050 return; 1063 return;
1051 } 1064 }
1052 1065
1053 INIT_WORK(&cs42l56->beep_work, cs42l5 1066 INIT_WORK(&cs42l56->beep_work, cs42l56_beep_work);
1054 cs42l56->beep_rate = 0; 1067 cs42l56->beep_rate = 0;
1055 1068
1056 cs42l56->beep->name = "CS42L56 Beep G 1069 cs42l56->beep->name = "CS42L56 Beep Generator";
1057 cs42l56->beep->phys = dev_name(compon !! 1070 cs42l56->beep->phys = dev_name(codec->dev);
1058 cs42l56->beep->id.bustype = BUS_I2C; 1071 cs42l56->beep->id.bustype = BUS_I2C;
1059 1072
1060 cs42l56->beep->evbit[0] = BIT_MASK(EV 1073 cs42l56->beep->evbit[0] = BIT_MASK(EV_SND);
1061 cs42l56->beep->sndbit[0] = BIT_MASK(S 1074 cs42l56->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
1062 cs42l56->beep->event = cs42l56_beep_e 1075 cs42l56->beep->event = cs42l56_beep_event;
1063 cs42l56->beep->dev.parent = component !! 1076 cs42l56->beep->dev.parent = codec->dev;
1064 input_set_drvdata(cs42l56->beep, comp !! 1077 input_set_drvdata(cs42l56->beep, codec);
1065 1078
1066 ret = input_register_device(cs42l56-> 1079 ret = input_register_device(cs42l56->beep);
1067 if (ret != 0) { 1080 if (ret != 0) {
1068 cs42l56->beep = NULL; 1081 cs42l56->beep = NULL;
1069 dev_err(component->dev, "Fail !! 1082 dev_err(codec->dev, "Failed to register beep device\n");
1070 } 1083 }
1071 1084
1072 ret = device_create_file(component->d !! 1085 ret = device_create_file(codec->dev, &dev_attr_beep);
1073 if (ret != 0) { 1086 if (ret != 0) {
1074 dev_err(component->dev, "Fail !! 1087 dev_err(codec->dev, "Failed to create keyclick file: %d\n",
1075 ret); 1088 ret);
1076 } 1089 }
1077 } 1090 }
1078 1091
1079 static void cs42l56_free_beep(struct snd_soc_ !! 1092 static void cs42l56_free_beep(struct snd_soc_codec *codec)
1080 { 1093 {
1081 struct cs42l56_private *cs42l56 = snd !! 1094 struct cs42l56_private *cs42l56 = snd_soc_codec_get_drvdata(codec);
1082 1095
1083 device_remove_file(component->dev, &d !! 1096 device_remove_file(codec->dev, &dev_attr_beep);
1084 cancel_work_sync(&cs42l56->beep_work) 1097 cancel_work_sync(&cs42l56->beep_work);
1085 cs42l56->beep = NULL; 1098 cs42l56->beep = NULL;
1086 1099
1087 snd_soc_component_update_bits(compone !! 1100 snd_soc_update_bits(codec, CS42L56_BEEP_TONE_CFG,
1088 CS42L56_BEEP_EN_M 1101 CS42L56_BEEP_EN_MASK, 0);
1089 } 1102 }
1090 1103
1091 static int cs42l56_probe(struct snd_soc_compo !! 1104 static int cs42l56_probe(struct snd_soc_codec *codec)
1092 { 1105 {
1093 cs42l56_init_beep(component); !! 1106 cs42l56_init_beep(codec);
1094 1107
1095 return 0; 1108 return 0;
1096 } 1109 }
1097 1110
1098 static void cs42l56_remove(struct snd_soc_com !! 1111 static int cs42l56_remove(struct snd_soc_codec *codec)
1099 { 1112 {
1100 cs42l56_free_beep(component); !! 1113 cs42l56_free_beep(codec);
>> 1114
>> 1115 return 0;
1101 } 1116 }
1102 1117
1103 static const struct snd_soc_component_driver !! 1118 static const struct snd_soc_codec_driver soc_codec_dev_cs42l56 = {
1104 .probe = cs42l56_pro !! 1119 .probe = cs42l56_probe,
1105 .remove = cs42l56_rem !! 1120 .remove = cs42l56_remove,
1106 .set_bias_level = cs42l56_set !! 1121 .set_bias_level = cs42l56_set_bias_level,
1107 .controls = cs42l56_snd !! 1122 .suspend_bias_off = true,
1108 .num_controls = ARRAY_SIZE( !! 1123
1109 .dapm_widgets = cs42l56_dap !! 1124 .component_driver = {
1110 .num_dapm_widgets = ARRAY_SIZE( !! 1125 .controls = cs42l56_snd_controls,
1111 .dapm_routes = cs42l56_aud !! 1126 .num_controls = ARRAY_SIZE(cs42l56_snd_controls),
1112 .num_dapm_routes = ARRAY_SIZE( !! 1127 .dapm_widgets = cs42l56_dapm_widgets,
1113 .suspend_bias_off = 1, !! 1128 .num_dapm_widgets = ARRAY_SIZE(cs42l56_dapm_widgets),
1114 .idle_bias_on = 1, !! 1129 .dapm_routes = cs42l56_audio_map,
1115 .use_pmdown_time = 1, !! 1130 .num_dapm_routes = ARRAY_SIZE(cs42l56_audio_map),
1116 .endianness = 1, !! 1131 },
1117 }; 1132 };
1118 1133
1119 static const struct regmap_config cs42l56_reg 1134 static const struct regmap_config cs42l56_regmap = {
1120 .reg_bits = 8, 1135 .reg_bits = 8,
1121 .val_bits = 8, 1136 .val_bits = 8,
1122 1137
1123 .max_register = CS42L56_MAX_REGISTER, 1138 .max_register = CS42L56_MAX_REGISTER,
1124 .reg_defaults = cs42l56_reg_defaults, 1139 .reg_defaults = cs42l56_reg_defaults,
1125 .num_reg_defaults = ARRAY_SIZE(cs42l5 1140 .num_reg_defaults = ARRAY_SIZE(cs42l56_reg_defaults),
1126 .readable_reg = cs42l56_readable_regi 1141 .readable_reg = cs42l56_readable_register,
1127 .volatile_reg = cs42l56_volatile_regi 1142 .volatile_reg = cs42l56_volatile_register,
1128 .cache_type = REGCACHE_MAPLE, !! 1143 .cache_type = REGCACHE_RBTREE,
1129 }; 1144 };
1130 1145
1131 static int cs42l56_handle_of_data(struct i2c_ 1146 static int cs42l56_handle_of_data(struct i2c_client *i2c_client,
1132 struct cs 1147 struct cs42l56_platform_data *pdata)
1133 { 1148 {
1134 struct device_node *np = i2c_client-> 1149 struct device_node *np = i2c_client->dev.of_node;
1135 u32 val32; 1150 u32 val32;
1136 1151
1137 if (of_property_read_bool(np, "cirrus 1152 if (of_property_read_bool(np, "cirrus,ain1a-reference-cfg"))
1138 pdata->ain1a_ref_cfg = true; 1153 pdata->ain1a_ref_cfg = true;
1139 1154
1140 if (of_property_read_bool(np, "cirrus 1155 if (of_property_read_bool(np, "cirrus,ain2a-reference-cfg"))
1141 pdata->ain2a_ref_cfg = true; 1156 pdata->ain2a_ref_cfg = true;
1142 1157
1143 if (of_property_read_bool(np, "cirrus 1158 if (of_property_read_bool(np, "cirrus,ain1b-reference-cfg"))
1144 pdata->ain1b_ref_cfg = true; 1159 pdata->ain1b_ref_cfg = true;
1145 1160
1146 if (of_property_read_bool(np, "cirrus 1161 if (of_property_read_bool(np, "cirrus,ain2b-reference-cfg"))
1147 pdata->ain2b_ref_cfg = true; 1162 pdata->ain2b_ref_cfg = true;
1148 1163
1149 if (of_property_read_u32(np, "cirrus, 1164 if (of_property_read_u32(np, "cirrus,micbias-lvl", &val32) >= 0)
1150 pdata->micbias_lvl = val32; 1165 pdata->micbias_lvl = val32;
1151 1166
1152 if (of_property_read_u32(np, "cirrus, 1167 if (of_property_read_u32(np, "cirrus,chgfreq-divisor", &val32) >= 0)
1153 pdata->chgfreq = val32; 1168 pdata->chgfreq = val32;
1154 1169
1155 if (of_property_read_u32(np, "cirrus, 1170 if (of_property_read_u32(np, "cirrus,adaptive-pwr-cfg", &val32) >= 0)
1156 pdata->adaptive_pwr = val32; 1171 pdata->adaptive_pwr = val32;
1157 1172
1158 if (of_property_read_u32(np, "cirrus, 1173 if (of_property_read_u32(np, "cirrus,hpf-left-freq", &val32) >= 0)
1159 pdata->hpfa_freq = val32; 1174 pdata->hpfa_freq = val32;
1160 1175
1161 if (of_property_read_u32(np, "cirrus, 1176 if (of_property_read_u32(np, "cirrus,hpf-left-freq", &val32) >= 0)
1162 pdata->hpfb_freq = val32; 1177 pdata->hpfb_freq = val32;
1163 1178
1164 pdata->gpio_nreset = of_get_named_gpi 1179 pdata->gpio_nreset = of_get_named_gpio(np, "cirrus,gpio-nreset", 0);
1165 1180
1166 return 0; 1181 return 0;
1167 } 1182 }
1168 1183
1169 static int cs42l56_i2c_probe(struct i2c_clien !! 1184 static int cs42l56_i2c_probe(struct i2c_client *i2c_client,
>> 1185 const struct i2c_device_id *id)
1170 { 1186 {
1171 struct cs42l56_private *cs42l56; 1187 struct cs42l56_private *cs42l56;
1172 struct cs42l56_platform_data *pdata = 1188 struct cs42l56_platform_data *pdata =
1173 dev_get_platdata(&i2c_client- 1189 dev_get_platdata(&i2c_client->dev);
1174 int ret, i; 1190 int ret, i;
1175 unsigned int devid; !! 1191 unsigned int devid = 0;
1176 unsigned int alpha_rev, metal_rev; 1192 unsigned int alpha_rev, metal_rev;
1177 unsigned int reg; 1193 unsigned int reg;
1178 1194
1179 cs42l56 = devm_kzalloc(&i2c_client->d !! 1195 cs42l56 = devm_kzalloc(&i2c_client->dev,
>> 1196 sizeof(struct cs42l56_private),
>> 1197 GFP_KERNEL);
1180 if (cs42l56 == NULL) 1198 if (cs42l56 == NULL)
1181 return -ENOMEM; 1199 return -ENOMEM;
1182 cs42l56->dev = &i2c_client->dev; 1200 cs42l56->dev = &i2c_client->dev;
1183 1201
1184 cs42l56->regmap = devm_regmap_init_i2 1202 cs42l56->regmap = devm_regmap_init_i2c(i2c_client, &cs42l56_regmap);
1185 if (IS_ERR(cs42l56->regmap)) { 1203 if (IS_ERR(cs42l56->regmap)) {
1186 ret = PTR_ERR(cs42l56->regmap 1204 ret = PTR_ERR(cs42l56->regmap);
1187 dev_err(&i2c_client->dev, "re 1205 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1188 return ret; 1206 return ret;
1189 } 1207 }
1190 1208
1191 if (pdata) { 1209 if (pdata) {
1192 cs42l56->pdata = *pdata; 1210 cs42l56->pdata = *pdata;
1193 } else { 1211 } else {
>> 1212 pdata = devm_kzalloc(&i2c_client->dev,
>> 1213 sizeof(struct cs42l56_platform_data),
>> 1214 GFP_KERNEL);
>> 1215 if (!pdata) {
>> 1216 dev_err(&i2c_client->dev,
>> 1217 "could not allocate pdata\n");
>> 1218 return -ENOMEM;
>> 1219 }
1194 if (i2c_client->dev.of_node) 1220 if (i2c_client->dev.of_node) {
1195 ret = cs42l56_handle_ 1221 ret = cs42l56_handle_of_data(i2c_client,
1196 1222 &cs42l56->pdata);
1197 if (ret != 0) 1223 if (ret != 0)
1198 return ret; 1224 return ret;
1199 } 1225 }
>> 1226 cs42l56->pdata = *pdata;
1200 } 1227 }
1201 1228
1202 if (cs42l56->pdata.gpio_nreset) { 1229 if (cs42l56->pdata.gpio_nreset) {
1203 ret = gpio_request_one(cs42l5 1230 ret = gpio_request_one(cs42l56->pdata.gpio_nreset,
1204 GPIOF_ 1231 GPIOF_OUT_INIT_HIGH, "CS42L56 /RST");
1205 if (ret < 0) { 1232 if (ret < 0) {
1206 dev_err(&i2c_client-> 1233 dev_err(&i2c_client->dev,
1207 "Failed to re 1234 "Failed to request /RST %d: %d\n",
1208 cs42l56->pdat 1235 cs42l56->pdata.gpio_nreset, ret);
1209 return ret; 1236 return ret;
1210 } 1237 }
1211 gpio_set_value_cansleep(cs42l 1238 gpio_set_value_cansleep(cs42l56->pdata.gpio_nreset, 0);
1212 gpio_set_value_cansleep(cs42l 1239 gpio_set_value_cansleep(cs42l56->pdata.gpio_nreset, 1);
1213 } 1240 }
1214 1241
1215 1242
1216 i2c_set_clientdata(i2c_client, cs42l5 1243 i2c_set_clientdata(i2c_client, cs42l56);
1217 1244
1218 for (i = 0; i < ARRAY_SIZE(cs42l56->s 1245 for (i = 0; i < ARRAY_SIZE(cs42l56->supplies); i++)
1219 cs42l56->supplies[i].supply = 1246 cs42l56->supplies[i].supply = cs42l56_supply_names[i];
1220 1247
1221 ret = devm_regulator_bulk_get(&i2c_cl 1248 ret = devm_regulator_bulk_get(&i2c_client->dev,
1222 ARRAY_S 1249 ARRAY_SIZE(cs42l56->supplies),
1223 cs42l56 1250 cs42l56->supplies);
1224 if (ret != 0) { 1251 if (ret != 0) {
1225 dev_err(&i2c_client->dev, 1252 dev_err(&i2c_client->dev,
1226 "Failed to request su 1253 "Failed to request supplies: %d\n", ret);
1227 return ret; 1254 return ret;
1228 } 1255 }
1229 1256
1230 ret = regulator_bulk_enable(ARRAY_SIZ 1257 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l56->supplies),
1231 cs42l56-> 1258 cs42l56->supplies);
1232 if (ret != 0) { 1259 if (ret != 0) {
1233 dev_err(&i2c_client->dev, 1260 dev_err(&i2c_client->dev,
1234 "Failed to enable sup 1261 "Failed to enable supplies: %d\n", ret);
1235 return ret; 1262 return ret;
1236 } 1263 }
1237 1264
1238 ret = regmap_read(cs42l56->regmap, CS !! 1265 regcache_cache_bypass(cs42l56->regmap, true);
1239 if (ret) { <<
1240 dev_err(&i2c_client->dev, "Fa <<
1241 goto err_enable; <<
1242 } <<
1243 1266
>> 1267 ret = regmap_read(cs42l56->regmap, CS42L56_CHIP_ID_1, ®);
1244 devid = reg & CS42L56_CHIP_ID_MASK; 1268 devid = reg & CS42L56_CHIP_ID_MASK;
1245 if (devid != CS42L56_DEVID) { 1269 if (devid != CS42L56_DEVID) {
1246 dev_err(&i2c_client->dev, 1270 dev_err(&i2c_client->dev,
1247 "CS42L56 Device ID (% 1271 "CS42L56 Device ID (%X). Expected %X\n",
1248 devid, CS42L56_DEVID) 1272 devid, CS42L56_DEVID);
1249 ret = -EINVAL; 1273 ret = -EINVAL;
1250 goto err_enable; 1274 goto err_enable;
1251 } 1275 }
1252 alpha_rev = reg & CS42L56_AREV_MASK; 1276 alpha_rev = reg & CS42L56_AREV_MASK;
1253 metal_rev = reg & CS42L56_MTLREV_MASK 1277 metal_rev = reg & CS42L56_MTLREV_MASK;
1254 1278
1255 dev_info(&i2c_client->dev, "Cirrus Lo 1279 dev_info(&i2c_client->dev, "Cirrus Logic CS42L56 ");
1256 dev_info(&i2c_client->dev, "Alpha Rev 1280 dev_info(&i2c_client->dev, "Alpha Rev %X Metal Rev %X\n",
1257 alpha_rev, metal_rev); 1281 alpha_rev, metal_rev);
1258 1282
>> 1283 regcache_cache_bypass(cs42l56->regmap, false);
>> 1284
1259 if (cs42l56->pdata.ain1a_ref_cfg) 1285 if (cs42l56->pdata.ain1a_ref_cfg)
1260 regmap_update_bits(cs42l56->r 1286 regmap_update_bits(cs42l56->regmap, CS42L56_AIN_REFCFG_ADC_MUX,
1261 CS42L56_AI !! 1287 CS42L56_AIN1A_REF_MASK, 1);
1262 CS42L56_AI <<
1263 1288
1264 if (cs42l56->pdata.ain1b_ref_cfg) 1289 if (cs42l56->pdata.ain1b_ref_cfg)
1265 regmap_update_bits(cs42l56->r 1290 regmap_update_bits(cs42l56->regmap, CS42L56_AIN_REFCFG_ADC_MUX,
1266 CS42L56_AI !! 1291 CS42L56_AIN1B_REF_MASK, 1);
1267 CS42L56_AI <<
1268 1292
1269 if (cs42l56->pdata.ain2a_ref_cfg) 1293 if (cs42l56->pdata.ain2a_ref_cfg)
1270 regmap_update_bits(cs42l56->r 1294 regmap_update_bits(cs42l56->regmap, CS42L56_AIN_REFCFG_ADC_MUX,
1271 CS42L56_AI !! 1295 CS42L56_AIN2A_REF_MASK, 1);
1272 CS42L56_AI <<
1273 1296
1274 if (cs42l56->pdata.ain2b_ref_cfg) 1297 if (cs42l56->pdata.ain2b_ref_cfg)
1275 regmap_update_bits(cs42l56->r 1298 regmap_update_bits(cs42l56->regmap, CS42L56_AIN_REFCFG_ADC_MUX,
1276 CS42L56_AI !! 1299 CS42L56_AIN2B_REF_MASK, 1);
1277 CS42L56_AI <<
1278 1300
1279 if (cs42l56->pdata.micbias_lvl) 1301 if (cs42l56->pdata.micbias_lvl)
1280 regmap_update_bits(cs42l56->r 1302 regmap_update_bits(cs42l56->regmap, CS42L56_GAIN_BIAS_CTL,
1281 CS42L56_MI 1303 CS42L56_MIC_BIAS_MASK,
1282 cs42l56->pdat 1304 cs42l56->pdata.micbias_lvl);
1283 1305
1284 if (cs42l56->pdata.chgfreq) 1306 if (cs42l56->pdata.chgfreq)
1285 regmap_update_bits(cs42l56->r 1307 regmap_update_bits(cs42l56->regmap, CS42L56_CLASSH_CTL,
1286 CS42L56_CH 1308 CS42L56_CHRG_FREQ_MASK,
1287 cs42l56->pdat 1309 cs42l56->pdata.chgfreq);
1288 1310
1289 if (cs42l56->pdata.hpfb_freq) 1311 if (cs42l56->pdata.hpfb_freq)
1290 regmap_update_bits(cs42l56->r 1312 regmap_update_bits(cs42l56->regmap, CS42L56_HPF_CTL,
1291 CS42L56_HP 1313 CS42L56_HPFB_FREQ_MASK,
1292 cs42l56->pdat 1314 cs42l56->pdata.hpfb_freq);
1293 1315
1294 if (cs42l56->pdata.hpfa_freq) 1316 if (cs42l56->pdata.hpfa_freq)
1295 regmap_update_bits(cs42l56->r 1317 regmap_update_bits(cs42l56->regmap, CS42L56_HPF_CTL,
1296 CS42L56_HP 1318 CS42L56_HPFA_FREQ_MASK,
1297 cs42l56->pdat 1319 cs42l56->pdata.hpfa_freq);
1298 1320
1299 if (cs42l56->pdata.adaptive_pwr) 1321 if (cs42l56->pdata.adaptive_pwr)
1300 regmap_update_bits(cs42l56->r 1322 regmap_update_bits(cs42l56->regmap, CS42L56_CLASSH_CTL,
1301 CS42L56_AD 1323 CS42L56_ADAPT_PWR_MASK,
1302 cs42l56->pdat 1324 cs42l56->pdata.adaptive_pwr);
1303 1325
1304 ret = devm_snd_soc_register_componen !! 1326 ret = snd_soc_register_codec(&i2c_client->dev,
1305 &soc_component_dev_cs !! 1327 &soc_codec_dev_cs42l56, &cs42l56_dai, 1);
1306 if (ret < 0) 1328 if (ret < 0)
1307 goto err_enable; 1329 goto err_enable;
1308 1330
1309 return 0; 1331 return 0;
1310 1332
1311 err_enable: 1333 err_enable:
1312 regulator_bulk_disable(ARRAY_SIZE(cs4 1334 regulator_bulk_disable(ARRAY_SIZE(cs42l56->supplies),
1313 cs42l56->suppl 1335 cs42l56->supplies);
1314 return ret; 1336 return ret;
1315 } 1337 }
1316 1338
1317 static void cs42l56_i2c_remove(struct i2c_cli !! 1339 static int cs42l56_i2c_remove(struct i2c_client *client)
1318 { 1340 {
1319 struct cs42l56_private *cs42l56 = i2c 1341 struct cs42l56_private *cs42l56 = i2c_get_clientdata(client);
1320 1342
>> 1343 snd_soc_unregister_codec(&client->dev);
1321 regulator_bulk_disable(ARRAY_SIZE(cs4 1344 regulator_bulk_disable(ARRAY_SIZE(cs42l56->supplies),
1322 cs42l56->suppl 1345 cs42l56->supplies);
>> 1346 return 0;
1323 } 1347 }
1324 1348
1325 static const struct of_device_id cs42l56_of_m 1349 static const struct of_device_id cs42l56_of_match[] = {
1326 { .compatible = "cirrus,cs42l56", }, 1350 { .compatible = "cirrus,cs42l56", },
1327 { } 1351 { }
1328 }; 1352 };
1329 MODULE_DEVICE_TABLE(of, cs42l56_of_match); 1353 MODULE_DEVICE_TABLE(of, cs42l56_of_match);
1330 1354
1331 1355
1332 static const struct i2c_device_id cs42l56_id[ 1356 static const struct i2c_device_id cs42l56_id[] = {
1333 { "cs42l56" }, !! 1357 { "cs42l56", 0 },
1334 { } 1358 { }
1335 }; 1359 };
1336 MODULE_DEVICE_TABLE(i2c, cs42l56_id); 1360 MODULE_DEVICE_TABLE(i2c, cs42l56_id);
1337 1361
1338 static struct i2c_driver cs42l56_i2c_driver = 1362 static struct i2c_driver cs42l56_i2c_driver = {
1339 .driver = { 1363 .driver = {
1340 .name = "cs42l56", 1364 .name = "cs42l56",
1341 .of_match_table = cs42l56_of_ 1365 .of_match_table = cs42l56_of_match,
1342 }, 1366 },
1343 .id_table = cs42l56_id, 1367 .id_table = cs42l56_id,
1344 .probe = cs42l56_i2c_probe, 1368 .probe = cs42l56_i2c_probe,
1345 .remove = cs42l56_i2c_remove, 1369 .remove = cs42l56_i2c_remove,
1346 }; 1370 };
1347 1371
1348 module_i2c_driver(cs42l56_i2c_driver); 1372 module_i2c_driver(cs42l56_i2c_driver);
1349 1373
1350 MODULE_DESCRIPTION("ASoC CS42L56 driver"); 1374 MODULE_DESCRIPTION("ASoC CS42L56 driver");
1351 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc 1375 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1352 MODULE_LICENSE("GPL"); 1376 MODULE_LICENSE("GPL");
1353 1377
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