1 // SPDX-License-Identifier: GPL-2.0-only 1
2 /*
3 * cs42l56.c -- CS42L56 ALSA SoC audio driver
4 *
5 * Copyright 2014 CirrusLogic, Inc.
6 *
7 * Author: Brian Austin <brian.austin@cirrus.c
8 */
9
10 #include <linux/module.h>
11 #include <linux/moduleparam.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/pm.h>
16 #include <linux/i2c.h>
17 #include <linux/input.h>
18 #include <linux/regmap.h>
19 #include <linux/slab.h>
20 #include <linux/workqueue.h>
21 #include <linux/platform_device.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/of.h>
24 #include <linux/of_gpio.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/soc-dapm.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
32 #include <sound/cs42l56.h>
33 #include "cs42l56.h"
34
35 #define CS42L56_NUM_SUPPLIES 3
36 static const char *const cs42l56_supply_names[
37 "VA",
38 "VCP",
39 "VLDO",
40 };
41
42 struct cs42l56_private {
43 struct regmap *regmap;
44 struct snd_soc_component *component;
45 struct device *dev;
46 struct cs42l56_platform_data pdata;
47 struct regulator_bulk_data supplies[CS
48 u32 mclk;
49 u8 mclk_prediv;
50 u8 mclk_div2;
51 u8 mclk_ratio;
52 u8 iface;
53 u8 iface_fmt;
54 u8 iface_inv;
55 #if IS_ENABLED(CONFIG_INPUT)
56 struct input_dev *beep;
57 struct work_struct beep_work;
58 int beep_rate;
59 #endif
60 };
61
62 static const struct reg_default cs42l56_reg_de
63 { 3, 0x7f }, /* r03 - Power Ctl 1
64 { 4, 0xff }, /* r04 - Power Ctl 2
65 { 5, 0x00 }, /* ro5 - Clocking Ctl
66 { 6, 0x0b }, /* r06 - Clocking Ctl
67 { 7, 0x00 }, /* r07 - Serial Forma
68 { 8, 0x05 }, /* r08 - Class H Ctl
69 { 9, 0x0c }, /* r09 - Misc Ctl */
70 { 10, 0x80 }, /* r0a - INT Status *
71 { 11, 0x00 }, /* r0b - Playback Ctl
72 { 12, 0x0c }, /* r0c - DSP Mute Ctl
73 { 13, 0x00 }, /* r0d - ADCA Mixer V
74 { 14, 0x00 }, /* r0e - ADCB Mixer V
75 { 15, 0x00 }, /* r0f - PCMA Mixer V
76 { 16, 0x00 }, /* r10 - PCMB Mixer V
77 { 17, 0x00 }, /* r11 - Analog Input
78 { 18, 0x00 }, /* r12 - Digital Inpu
79 { 19, 0x00 }, /* r13 - Master A Vol
80 { 20, 0x00 }, /* r14 - Master B Vol
81 { 21, 0x00 }, /* r15 - Beep Freq /
82 { 22, 0x00 }, /* r16 - Beep Volume
83 { 23, 0x00 }, /* r17 - Beep Tone Ct
84 { 24, 0x88 }, /* r18 - Tone Ctl */
85 { 25, 0x00 }, /* r19 - Channel Mixe
86 { 26, 0x00 }, /* r1a - AIN Ref Conf
87 { 27, 0xa0 }, /* r1b - High-Pass Fi
88 { 28, 0x00 }, /* r1c - Misc ADC Ctl
89 { 29, 0x00 }, /* r1d - Gain & Bias
90 { 30, 0x00 }, /* r1e - PGAA Mux & V
91 { 31, 0x00 }, /* r1f - PGAB Mux & V
92 { 32, 0x00 }, /* r20 - ADCA Attenua
93 { 33, 0x00 }, /* r21 - ADCB Attenua
94 { 34, 0x00 }, /* r22 - ALC Enable &
95 { 35, 0xbf }, /* r23 - ALC Release
96 { 36, 0x00 }, /* r24 - ALC Threshol
97 { 37, 0x00 }, /* r25 - Noise Gate C
98 { 38, 0x00 }, /* r26 - ALC, Limiter
99 { 39, 0x00 }, /* r27 - Analog Mute,
100 { 40, 0x00 }, /* r28 - HP A Volume
101 { 41, 0x00 }, /* r29 - HP B Volume
102 { 42, 0x00 }, /* r2a - LINEOUT A Vo
103 { 43, 0x00 }, /* r2b - LINEOUT B Vo
104 { 44, 0x00 }, /* r2c - Limit Thresh
105 { 45, 0x7f }, /* r2d - Limiter Ctl
106 { 46, 0x00 }, /* r2e - Limiter Atta
107 };
108
109 static bool cs42l56_readable_register(struct d
110 {
111 switch (reg) {
112 case CS42L56_CHIP_ID_1 ... CS42L56_LIM
113 return true;
114 default:
115 return false;
116 }
117 }
118
119 static bool cs42l56_volatile_register(struct d
120 {
121 switch (reg) {
122 case CS42L56_INT_STATUS:
123 return true;
124 default:
125 return false;
126 }
127 }
128
129 static DECLARE_TLV_DB_SCALE(beep_tlv, -5000, 2
130 static DECLARE_TLV_DB_SCALE(hl_tlv, -6000, 50,
131 static DECLARE_TLV_DB_SCALE(adv_tlv, -10200, 5
132 static DECLARE_TLV_DB_SCALE(adc_tlv, -9600, 10
133 static DECLARE_TLV_DB_SCALE(tone_tlv, -1050, 1
134 static DECLARE_TLV_DB_SCALE(preamp_tlv, 0, 100
135 static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50,
136
137 static const DECLARE_TLV_DB_RANGE(ngnb_tlv,
138 0, 1, TLV_DB_SCALE_ITEM(-8200, 600, 0)
139 2, 5, TLV_DB_SCALE_ITEM(-7600, 300, 0)
140 );
141 static const DECLARE_TLV_DB_RANGE(ngb_tlv,
142 0, 2, TLV_DB_SCALE_ITEM(-6400, 600, 0)
143 3, 7, TLV_DB_SCALE_ITEM(-4600, 300, 0)
144 );
145 static const DECLARE_TLV_DB_RANGE(alc_tlv,
146 0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0)
147 3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0)
148 );
149
150 static const char * const beep_config_text[] =
151 "Off", "Single", "Multiple", "Continuo
152 };
153
154 static const struct soc_enum beep_config_enum
155 SOC_ENUM_SINGLE(CS42L56_BEEP_TONE_CFG,
156 ARRAY_SIZE(beep_config
157
158 static const char * const beep_pitch_text[] =
159 "C4", "C5", "D5", "E5", "F5", "G5", "A
160 "C6", "D6", "E6", "F6", "G6", "A6", "B
161 };
162
163 static const struct soc_enum beep_pitch_enum =
164 SOC_ENUM_SINGLE(CS42L56_BEEP_FREQ_ONTI
165 ARRAY_SIZE(beep_pitch_
166
167 static const char * const beep_ontime_text[] =
168 "86 ms", "430 ms", "780 ms", "1.20 s",
169 "1.80 s", "2.20 s", "2.50 s", "2.80 s"
170 "3.50 s", "3.80 s", "4.20 s", "4.50 s"
171 };
172
173 static const struct soc_enum beep_ontime_enum
174 SOC_ENUM_SINGLE(CS42L56_BEEP_FREQ_ONTI
175 ARRAY_SIZE(beep_ontime
176
177 static const char * const beep_offtime_text[]
178 "1.23 s", "2.58 s", "3.90 s", "5.20 s"
179 "6.60 s", "8.05 s", "9.35 s", "10.80 s
180 };
181
182 static const struct soc_enum beep_offtime_enum
183 SOC_ENUM_SINGLE(CS42L56_BEEP_FREQ_OFFT
184 ARRAY_SIZE(beep_offtim
185
186 static const char * const beep_treble_text[] =
187 "5kHz", "7kHz", "10kHz", "15kHz"
188 };
189
190 static const struct soc_enum beep_treble_enum
191 SOC_ENUM_SINGLE(CS42L56_BEEP_TONE_CFG,
192 ARRAY_SIZE(beep_treble
193
194 static const char * const beep_bass_text[] = {
195 "50Hz", "100Hz", "200Hz", "250Hz"
196 };
197
198 static const struct soc_enum beep_bass_enum =
199 SOC_ENUM_SINGLE(CS42L56_BEEP_TONE_CFG,
200 ARRAY_SIZE(beep_bass_t
201
202 static const char * const pgaa_mux_text[] = {
203 "AIN1A", "AIN2A", "AIN3A"};
204
205 static const struct soc_enum pgaa_mux_enum =
206 SOC_ENUM_SINGLE(CS42L56_PGAA_MUX_VOLUM
207 ARRAY_SIZE(pgaa_
208 pgaa_mux_text);
209
210 static const struct snd_kcontrol_new pgaa_mux
211 SOC_DAPM_ENUM("Route", pgaa_mux_enum);
212
213 static const char * const pgab_mux_text[] = {
214 "AIN1B", "AIN2B", "AIN3B"};
215
216 static const struct soc_enum pgab_mux_enum =
217 SOC_ENUM_SINGLE(CS42L56_PGAB_MUX_VOLUM
218 ARRAY_SIZE(pgab_
219 pgab_mux_text);
220
221 static const struct snd_kcontrol_new pgab_mux
222 SOC_DAPM_ENUM("Route", pgab_mux_enum);
223
224 static const char * const adca_mux_text[] = {
225 "PGAA", "AIN1A", "AIN2A", "AIN3A"};
226
227 static const struct soc_enum adca_mux_enum =
228 SOC_ENUM_SINGLE(CS42L56_AIN_REFCFG_ADC
229 ARRAY_SIZE(adca_
230 adca_mux_text);
231
232 static const struct snd_kcontrol_new adca_mux
233 SOC_DAPM_ENUM("Route", adca_mux_enum);
234
235 static const char * const adcb_mux_text[] = {
236 "PGAB", "AIN1B", "AIN2B", "AIN3B"};
237
238 static const struct soc_enum adcb_mux_enum =
239 SOC_ENUM_SINGLE(CS42L56_AIN_REFCFG_ADC
240 ARRAY_SIZE(adcb_
241 adcb_mux_text);
242
243 static const struct snd_kcontrol_new adcb_mux
244 SOC_DAPM_ENUM("Route", adcb_mux_enum);
245
246 static const char * const left_swap_text[] = {
247 "Left", "LR 2", "Right"};
248
249 static const char * const right_swap_text[] =
250 "Right", "LR 2", "Left"};
251
252 static const unsigned int swap_values[] = { 0,
253
254 static const struct soc_enum adca_swap_enum =
255 SOC_VALUE_ENUM_SINGLE(CS42L56_CHAN_MIX
256 ARRAY_SIZE(left_
257 left_swap_text,
258 swap_values);
259 static const struct snd_kcontrol_new adca_swap
260 SOC_DAPM_ENUM("Route", adca_swap_enum)
261
262 static const struct soc_enum pcma_swap_enum =
263 SOC_VALUE_ENUM_SINGLE(CS42L56_CHAN_MIX
264 ARRAY_SIZE(left_
265 left_swap_text,
266 swap_values);
267 static const struct snd_kcontrol_new pcma_swap
268 SOC_DAPM_ENUM("Route", pcma_swap_enum)
269
270 static const struct soc_enum adcb_swap_enum =
271 SOC_VALUE_ENUM_SINGLE(CS42L56_CHAN_MIX
272 ARRAY_SIZE(right
273 right_swap_text,
274 swap_values);
275 static const struct snd_kcontrol_new adcb_swap
276 SOC_DAPM_ENUM("Route", adcb_swap_enum)
277
278 static const struct soc_enum pcmb_swap_enum =
279 SOC_VALUE_ENUM_SINGLE(CS42L56_CHAN_MIX
280 ARRAY_SIZE(right
281 right_swap_text,
282 swap_values);
283 static const struct snd_kcontrol_new pcmb_swap
284 SOC_DAPM_ENUM("Route", pcmb_swap_enum)
285
286 static const struct snd_kcontrol_new hpa_switc
287 SOC_DAPM_SINGLE("Switch", CS42L56_PWRC
288
289 static const struct snd_kcontrol_new hpb_switc
290 SOC_DAPM_SINGLE("Switch", CS42L56_PWRC
291
292 static const struct snd_kcontrol_new loa_switc
293 SOC_DAPM_SINGLE("Switch", CS42L56_PWRC
294
295 static const struct snd_kcontrol_new lob_switc
296 SOC_DAPM_SINGLE("Switch", CS42L56_PWRC
297
298 static const char * const hploa_input_text[] =
299 "DACA", "PGAA"};
300
301 static const struct soc_enum lineouta_input_en
302 SOC_ENUM_SINGLE(CS42L56_AMUTE_HPLO_MUX
303 ARRAY_SIZE(hploa
304 hploa_input_text
305
306 static const struct snd_kcontrol_new lineouta_
307 SOC_DAPM_ENUM("Route", lineouta_input_
308
309 static const struct soc_enum hpa_input_enum =
310 SOC_ENUM_SINGLE(CS42L56_AMUTE_HPLO_MUX
311 ARRAY_SIZE(hploa
312 hploa_input_text
313
314 static const struct snd_kcontrol_new hpa_input
315 SOC_DAPM_ENUM("Route", hpa_input_enum)
316
317 static const char * const hplob_input_text[] =
318 "DACB", "PGAB"};
319
320 static const struct soc_enum lineoutb_input_en
321 SOC_ENUM_SINGLE(CS42L56_AMUTE_HPLO_MUX
322 ARRAY_SIZE(hplob
323 hplob_input_text
324
325 static const struct snd_kcontrol_new lineoutb_
326 SOC_DAPM_ENUM("Route", lineoutb_input_
327
328 static const struct soc_enum hpb_input_enum =
329 SOC_ENUM_SINGLE(CS42L56_AMUTE_HPLO_MUX
330 ARRAY_SIZE(hplob
331 hplob_input_text
332
333 static const struct snd_kcontrol_new hpb_input
334 SOC_DAPM_ENUM("Route", hpb_input_enum)
335
336 static const char * const dig_mux_text[] = {
337 "ADC", "DSP"};
338
339 static const struct soc_enum dig_mux_enum =
340 SOC_ENUM_SINGLE(CS42L56_MISC_CTL, 7,
341 ARRAY_SIZE(dig_m
342 dig_mux_text);
343
344 static const struct snd_kcontrol_new dig_mux =
345 SOC_DAPM_ENUM("Route", dig_mux_enum);
346
347 static const char * const hpf_freq_text[] = {
348 "1.8Hz", "119Hz", "236Hz", "464Hz"
349 };
350
351 static const struct soc_enum hpfa_freq_enum =
352 SOC_ENUM_SINGLE(CS42L56_HPF_CTL, 0,
353 ARRAY_SIZE(hpf_freq_te
354
355 static const struct soc_enum hpfb_freq_enum =
356 SOC_ENUM_SINGLE(CS42L56_HPF_CTL, 2,
357 ARRAY_SIZE(hpf_freq_te
358
359 static const char * const ng_delay_text[] = {
360 "50ms", "100ms", "150ms", "200ms"
361 };
362
363 static const struct soc_enum ng_delay_enum =
364 SOC_ENUM_SINGLE(CS42L56_NOISE_GATE_CTL
365 ARRAY_SIZE(ng_delay_te
366
367 static const struct snd_kcontrol_new cs42l56_s
368
369 SOC_DOUBLE_R_SX_TLV("Master Volume", C
370 CS42L56_MASTER_B
371 SOC_DOUBLE("Master Mute Switch", CS42L
372
373 SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume"
374 CS42L56_ADCB_MIX
375 SOC_DOUBLE("ADC Mixer Mute Switch", CS
376
377 SOC_DOUBLE_R_SX_TLV("PCM Mixer Volume"
378 CS42L56_PCMB_MIX
379 SOC_DOUBLE("PCM Mixer Mute Switch", CS
380
381 SOC_SINGLE_TLV("Analog Advisory Volume
382 CS42L56_ANAINPUT_ADV
383 SOC_SINGLE_TLV("Digital Advisory Volum
384 CS42L56_DIGINPUT_ADV
385
386 SOC_DOUBLE_R_SX_TLV("PGA Volume", CS42
387 CS42L56_PGAB_MUX
388 SOC_DOUBLE_R_TLV("ADC Volume", CS42L56
389 CS42L56_ADCB_ATT
390 SOC_DOUBLE("ADC Mute Switch", CS42L56_
391 SOC_DOUBLE("ADC Boost Switch", CS42L56
392
393 SOC_DOUBLE_R_SX_TLV("Headphone Volume"
394 CS42L56_HPB_VOLU
395 SOC_DOUBLE_R_SX_TLV("LineOut Volume",
396 CS42L56_LOB_VOLU
397
398 SOC_SINGLE_TLV("Bass Shelving Volume",
399 0, 0x00, 1, tone_tlv),
400 SOC_SINGLE_TLV("Treble Shelving Volume
401 4, 0x00, 1, tone_tlv),
402
403 SOC_DOUBLE_TLV("PGA Preamp Volume", CS
404 4, 6, 0x02, 1, preamp_
405
406 SOC_SINGLE("DSP Switch", CS42L56_PLAYB
407 SOC_SINGLE("Gang Playback Switch", CS4
408 SOC_SINGLE("Gang ADC Switch", CS42L56_
409 SOC_SINGLE("Gang PGA Switch", CS42L56_
410
411 SOC_SINGLE("PCMA Invert", CS42L56_PLAY
412 SOC_SINGLE("PCMB Invert", CS42L56_PLAY
413 SOC_SINGLE("ADCA Invert", CS42L56_MISC
414 SOC_SINGLE("ADCB Invert", CS42L56_MISC
415
416 SOC_DOUBLE("HPF Switch", CS42L56_HPF_C
417 SOC_DOUBLE("HPF Freeze Switch", CS42L5
418 SOC_ENUM("HPFA Corner Freq", hpfa_freq
419 SOC_ENUM("HPFB Corner Freq", hpfb_freq
420
421 SOC_SINGLE("Analog Soft Ramp", CS42L56
422 SOC_DOUBLE("Analog Soft Ramp Disable",
423 7, 5, 1, 1),
424 SOC_SINGLE("Analog Zero Cross", CS42L5
425 SOC_DOUBLE("Analog Zero Cross Disable"
426 6, 4, 1, 1),
427 SOC_SINGLE("Digital Soft Ramp", CS42L5
428 SOC_SINGLE("Digital Soft Ramp Disable"
429 3, 1, 1),
430
431 SOC_SINGLE("HL Deemphasis", CS42L56_PL
432
433 SOC_SINGLE("ALC Switch", CS42L56_ALC_E
434 SOC_SINGLE("ALC Limit All Switch", CS4
435 SOC_SINGLE_RANGE("ALC Attack", CS42L56
436 0, 0, 0x3f, 0),
437 SOC_SINGLE_RANGE("ALC Release", CS42L5
438 0, 0x3f, 0, 0),
439 SOC_SINGLE_TLV("ALC MAX", CS42L56_ALC_
440 5, 0x07, 1, alc_tlv),
441 SOC_SINGLE_TLV("ALC MIN", CS42L56_ALC_
442 2, 0x07, 1, alc_tlv),
443
444 SOC_SINGLE("Limiter Switch", CS42L56_L
445 SOC_SINGLE("Limit All Switch", CS42L56
446 SOC_SINGLE_RANGE("Limiter Attack", CS4
447 0, 0, 0x3f, 0),
448 SOC_SINGLE_RANGE("Limiter Release", CS
449 0, 0x3f, 0, 0),
450 SOC_SINGLE_TLV("Limiter MAX", CS42L56_
451 5, 0x07, 1, alc_tlv),
452 SOC_SINGLE_TLV("Limiter Cushion", CS42
453 2, 0x07, 1, alc_tlv),
454
455 SOC_SINGLE("NG Switch", CS42L56_NOISE_
456 SOC_SINGLE("NG All Switch", CS42L56_NO
457 SOC_SINGLE("NG Boost Switch", CS42L56_
458 SOC_SINGLE_TLV("NG Unboost Threshold",
459 2, 0x07, 1, ngnb_tlv),
460 SOC_SINGLE_TLV("NG Boost Threshold", C
461 2, 0x07, 1, ngb_tlv),
462 SOC_ENUM("NG Delay", ng_delay_enum),
463
464 SOC_ENUM("Beep Config", beep_config_en
465 SOC_ENUM("Beep Pitch", beep_pitch_enum
466 SOC_ENUM("Beep on Time", beep_ontime_e
467 SOC_ENUM("Beep off Time", beep_offtime
468 SOC_SINGLE_SX_TLV("Beep Volume", CS42L
469 0, 0x07, 0x23, beep_tl
470 SOC_SINGLE("Beep Tone Ctl Switch", CS4
471 SOC_ENUM("Beep Treble Corner Freq", be
472 SOC_ENUM("Beep Bass Corner Freq", beep
473
474 };
475
476 static const struct snd_soc_dapm_widget cs42l5
477
478 SND_SOC_DAPM_SIGGEN("Beep"),
479 SND_SOC_DAPM_SUPPLY("VBUF", CS42L56_PW
480 SND_SOC_DAPM_MICBIAS("MIC1 Bias", CS42
481 SND_SOC_DAPM_SUPPLY("Charge Pump", CS4
482
483 SND_SOC_DAPM_INPUT("AIN1A"),
484 SND_SOC_DAPM_INPUT("AIN2A"),
485 SND_SOC_DAPM_INPUT("AIN1B"),
486 SND_SOC_DAPM_INPUT("AIN2B"),
487 SND_SOC_DAPM_INPUT("AIN3A"),
488 SND_SOC_DAPM_INPUT("AIN3B"),
489
490 SND_SOC_DAPM_AIF_OUT("SDOUT", NULL, 0
491 SND_SOC_NOPM, 0, 0),
492
493 SND_SOC_DAPM_AIF_IN("SDIN", NULL, 0,
494 SND_SOC_NOPM, 0, 0),
495
496 SND_SOC_DAPM_MUX("Digital Output Mux",
497 0, 0, &dig_mux),
498
499 SND_SOC_DAPM_PGA("PGAA", SND_SOC_NOPM,
500 SND_SOC_DAPM_PGA("PGAB", SND_SOC_NOPM,
501 SND_SOC_DAPM_MUX("PGAA Input Mux",
502 SND_SOC_NOPM, 0, 0, &p
503 SND_SOC_DAPM_MUX("PGAB Input Mux",
504 SND_SOC_NOPM, 0, 0, &p
505
506 SND_SOC_DAPM_MUX("ADCA Mux", SND_SOC_N
507 0, 0, &adca_mux),
508 SND_SOC_DAPM_MUX("ADCB Mux", SND_SOC_N
509 0, 0, &adcb_mux),
510
511 SND_SOC_DAPM_ADC("ADCA", NULL, CS42L56
512 SND_SOC_DAPM_ADC("ADCB", NULL, CS42L56
513
514 SND_SOC_DAPM_MUX("ADCA Swap Mux", SND_
515 &adca_swap_mux),
516 SND_SOC_DAPM_MUX("ADCB Swap Mux", SND_
517 &adcb_swap_mux),
518
519 SND_SOC_DAPM_MUX("PCMA Swap Mux", SND_
520 &pcma_swap_mux),
521 SND_SOC_DAPM_MUX("PCMB Swap Mux", SND_
522 &pcmb_swap_mux),
523
524 SND_SOC_DAPM_DAC("DACA", NULL, SND_SOC
525 SND_SOC_DAPM_DAC("DACB", NULL, SND_SOC
526
527 SND_SOC_DAPM_OUTPUT("HPA"),
528 SND_SOC_DAPM_OUTPUT("LOA"),
529 SND_SOC_DAPM_OUTPUT("HPB"),
530 SND_SOC_DAPM_OUTPUT("LOB"),
531
532 SND_SOC_DAPM_SWITCH("Headphone Right",
533 CS42L56_PWRCTL_2,
534 SND_SOC_DAPM_SWITCH("Headphone Left",
535 CS42L56_PWRCTL_2,
536
537 SND_SOC_DAPM_SWITCH("Lineout Right",
538 CS42L56_PWRCTL_2,
539 SND_SOC_DAPM_SWITCH("Lineout Left",
540 CS42L56_PWRCTL_2,
541
542 SND_SOC_DAPM_MUX("LINEOUTA Input Mux",
543 0, 0, &lineouta_input
544 SND_SOC_DAPM_MUX("LINEOUTB Input Mux",
545 0, 0, &lineoutb_input
546 SND_SOC_DAPM_MUX("HPA Input Mux", SND_
547 0, 0, &hpa_input),
548 SND_SOC_DAPM_MUX("HPB Input Mux", SND_
549 0, 0, &hpb_input),
550
551 };
552
553 static const struct snd_soc_dapm_route cs42l56
554
555 {"HiFi Capture", "DSP", "Digital Outpu
556 {"HiFi Capture", "ADC", "Digital Outpu
557
558 {"Digital Output Mux", NULL, "ADCA"},
559 {"Digital Output Mux", NULL, "ADCB"},
560
561 {"ADCB", NULL, "ADCB Swap Mux"},
562 {"ADCA", NULL, "ADCA Swap Mux"},
563
564 {"ADCA Swap Mux", NULL, "ADCA"},
565 {"ADCB Swap Mux", NULL, "ADCB"},
566
567 {"DACA", "Left", "ADCA Swap Mux"},
568 {"DACA", "LR 2", "ADCA Swap Mux"},
569 {"DACA", "Right", "ADCA Swap Mux"},
570
571 {"DACB", "Left", "ADCB Swap Mux"},
572 {"DACB", "LR 2", "ADCB Swap Mux"},
573 {"DACB", "Right", "ADCB Swap Mux"},
574
575 {"ADCA Mux", NULL, "AIN3A"},
576 {"ADCA Mux", NULL, "AIN2A"},
577 {"ADCA Mux", NULL, "AIN1A"},
578 {"ADCA Mux", NULL, "PGAA"},
579 {"ADCB Mux", NULL, "AIN3B"},
580 {"ADCB Mux", NULL, "AIN2B"},
581 {"ADCB Mux", NULL, "AIN1B"},
582 {"ADCB Mux", NULL, "PGAB"},
583
584 {"PGAA", "AIN1A", "PGAA Input Mux"},
585 {"PGAA", "AIN2A", "PGAA Input Mux"},
586 {"PGAA", "AIN3A", "PGAA Input Mux"},
587 {"PGAB", "AIN1B", "PGAB Input Mux"},
588 {"PGAB", "AIN2B", "PGAB Input Mux"},
589 {"PGAB", "AIN3B", "PGAB Input Mux"},
590
591 {"PGAA Input Mux", NULL, "AIN1A"},
592 {"PGAA Input Mux", NULL, "AIN2A"},
593 {"PGAA Input Mux", NULL, "AIN3A"},
594 {"PGAB Input Mux", NULL, "AIN1B"},
595 {"PGAB Input Mux", NULL, "AIN2B"},
596 {"PGAB Input Mux", NULL, "AIN3B"},
597
598 {"LOB", "Switch", "LINEOUTB Input Mux"
599 {"LOA", "Switch", "LINEOUTA Input Mux"
600
601 {"LINEOUTA Input Mux", "PGAA", "PGAA"}
602 {"LINEOUTB Input Mux", "PGAB", "PGAB"}
603 {"LINEOUTA Input Mux", "DACA", "DACA"}
604 {"LINEOUTB Input Mux", "DACB", "DACB"}
605
606 {"HPA", "Switch", "HPB Input Mux"},
607 {"HPB", "Switch", "HPA Input Mux"},
608
609 {"HPA Input Mux", "PGAA", "PGAA"},
610 {"HPB Input Mux", "PGAB", "PGAB"},
611 {"HPA Input Mux", "DACA", "DACA"},
612 {"HPB Input Mux", "DACB", "DACB"},
613
614 {"DACA", NULL, "PCMA Swap Mux"},
615 {"DACB", NULL, "PCMB Swap Mux"},
616
617 {"PCMB Swap Mux", "Left", "HiFi Playba
618 {"PCMB Swap Mux", "LR 2", "HiFi Playba
619 {"PCMB Swap Mux", "Right", "HiFi Playb
620
621 {"PCMA Swap Mux", "Left", "HiFi Playba
622 {"PCMA Swap Mux", "LR 2", "HiFi Playba
623 {"PCMA Swap Mux", "Right", "HiFi Playb
624
625 };
626
627 struct cs42l56_clk_para {
628 u32 mclk;
629 u32 srate;
630 u8 ratio;
631 };
632
633 static const struct cs42l56_clk_para clk_ratio
634 /* 8k */
635 { 6000000, 8000, CS42L56_MCLK_LRCLK_76
636 { 6144000, 8000, CS42L56_MCLK_LRCLK_75
637 { 12000000, 8000, CS42L56_MCLK_LRCLK_7
638 { 12288000, 8000, CS42L56_MCLK_LRCLK_7
639 { 24000000, 8000, CS42L56_MCLK_LRCLK_7
640 { 24576000, 8000, CS42L56_MCLK_LRCLK_7
641 /* 11.025k */
642 { 5644800, 11025, CS42L56_MCLK_LRCLK_5
643 { 11289600, 11025, CS42L56_MCLK_LRCLK_
644 { 22579200, 11025, CS42L56_MCLK_LRCLK_
645 /* 11.0294k */
646 { 6000000, 110294, CS42L56_MCLK_LRCLK_
647 { 12000000, 110294, CS42L56_MCLK_LRCLK
648 { 24000000, 110294, CS42L56_MCLK_LRCLK
649 /* 12k */
650 { 6000000, 12000, CS42L56_MCLK_LRCLK_5
651 { 6144000, 12000, CS42L56_MCLK_LRCLK_5
652 { 12000000, 12000, CS42L56_MCLK_LRCLK_
653 { 12288000, 12000, CS42L56_MCLK_LRCLK_
654 { 24000000, 12000, CS42L56_MCLK_LRCLK_
655 { 24576000, 12000, CS42L56_MCLK_LRCLK_
656 /* 16k */
657 { 6000000, 16000, CS42L56_MCLK_LRCLK_3
658 { 6144000, 16000, CS42L56_MCLK_LRCLK_3
659 { 12000000, 16000, CS42L56_MCLK_LRCLK_
660 { 12288000, 16000, CS42L56_MCLK_LRCLK_
661 { 24000000, 16000, CS42L56_MCLK_LRCLK_
662 { 24576000, 16000, CS42L56_MCLK_LRCLK_
663 /* 22.050k */
664 { 5644800, 22050, CS42L56_MCLK_LRCLK_2
665 { 11289600, 22050, CS42L56_MCLK_LRCLK_
666 { 22579200, 22050, CS42L56_MCLK_LRCLK_
667 /* 22.0588k */
668 { 6000000, 220588, CS42L56_MCLK_LRCLK_
669 { 12000000, 220588, CS42L56_MCLK_LRCLK
670 { 24000000, 220588, CS42L56_MCLK_LRCLK
671 /* 24k */
672 { 6000000, 24000, CS42L56_MCLK_LRCLK_2
673 { 6144000, 24000, CS42L56_MCLK_LRCLK_2
674 { 12000000, 24000, CS42L56_MCLK_LRCLK_
675 { 12288000, 24000, CS42L56_MCLK_LRCLK_
676 { 24000000, 24000, CS42L56_MCLK_LRCLK_
677 { 24576000, 24000, CS42L56_MCLK_LRCLK_
678 /* 32k */
679 { 6000000, 32000, CS42L56_MCLK_LRCLK_1
680 { 6144000, 32000, CS42L56_MCLK_LRCLK_1
681 { 12000000, 32000, CS42L56_MCLK_LRCLK_
682 { 12288000, 32000, CS42L56_MCLK_LRCLK_
683 { 24000000, 32000, CS42L56_MCLK_LRCLK_
684 { 24576000, 32000, CS42L56_MCLK_LRCLK_
685 /* 44.118k */
686 { 6000000, 44118, CS42L56_MCLK_LRCLK_1
687 { 12000000, 44118, CS42L56_MCLK_LRCLK_
688 { 24000000, 44118, CS42L56_MCLK_LRCLK_
689 /* 44.1k */
690 { 5644800, 44100, CS42L56_MCLK_LRCLK_1
691 { 11289600, 44100, CS42L56_MCLK_LRCLK_
692 { 22579200, 44100, CS42L56_MCLK_LRCLK_
693 /* 48k */
694 { 6000000, 48000, CS42L56_MCLK_LRCLK_1
695 { 6144000, 48000, CS42L56_MCLK_LRCLK_1
696 { 12000000, 48000, CS42L56_MCLK_LRCLK_
697 { 12288000, 48000, CS42L56_MCLK_LRCLK_
698 { 24000000, 48000, CS42L56_MCLK_LRCLK_
699 { 24576000, 48000, CS42L56_MCLK_LRCLK_
700 };
701
702 static int cs42l56_get_mclk_ratio(int mclk, in
703 {
704 int i;
705
706 for (i = 0; i < ARRAY_SIZE(clk_ratio_t
707 if (clk_ratio_table[i].mclk ==
708 clk_ratio_table[i].srate =
709 return clk_ratio_table
710 }
711 return -EINVAL;
712 }
713
714 static int cs42l56_set_sysclk(struct snd_soc_d
715 int clk_id, unsigned i
716 {
717 struct snd_soc_component *component =
718 struct cs42l56_private *cs42l56 = snd_
719
720 switch (freq) {
721 case CS42L56_MCLK_5P6448MHZ:
722 case CS42L56_MCLK_6MHZ:
723 case CS42L56_MCLK_6P144MHZ:
724 cs42l56->mclk_div2 = 0;
725 cs42l56->mclk_prediv = 0;
726 break;
727 case CS42L56_MCLK_11P2896MHZ:
728 case CS42L56_MCLK_12MHZ:
729 case CS42L56_MCLK_12P288MHZ:
730 cs42l56->mclk_div2 = CS42L56_M
731 cs42l56->mclk_prediv = 0;
732 break;
733 case CS42L56_MCLK_22P5792MHZ:
734 case CS42L56_MCLK_24MHZ:
735 case CS42L56_MCLK_24P576MHZ:
736 cs42l56->mclk_div2 = CS42L56_M
737 cs42l56->mclk_prediv = CS42L56
738 break;
739 default:
740 return -EINVAL;
741 }
742 cs42l56->mclk = freq;
743
744 snd_soc_component_update_bits(componen
745 CS42L56_MCLK_PREDI
746 cs42l56->mclk_
747 snd_soc_component_update_bits(componen
748 CS42L56_MCLK_DIV2_
749 cs42l56->mclk_
750
751 return 0;
752 }
753
754 static int cs42l56_set_dai_fmt(struct snd_soc_
755 {
756 struct snd_soc_component *component =
757 struct cs42l56_private *cs42l56 = snd_
758
759 switch (fmt & SND_SOC_DAIFMT_MASTER_MA
760 case SND_SOC_DAIFMT_CBM_CFM:
761 cs42l56->iface = CS42L56_MASTE
762 break;
763 case SND_SOC_DAIFMT_CBS_CFS:
764 cs42l56->iface = CS42L56_SLAVE
765 break;
766 default:
767 return -EINVAL;
768 }
769
770 /* interface format */
771 switch (fmt & SND_SOC_DAIFMT_FORMAT_MA
772 case SND_SOC_DAIFMT_I2S:
773 cs42l56->iface_fmt = CS42L56_D
774 break;
775 case SND_SOC_DAIFMT_LEFT_J:
776 cs42l56->iface_fmt = CS42L56_D
777 break;
778 default:
779 return -EINVAL;
780 }
781
782 /* sclk inversion */
783 switch (fmt & SND_SOC_DAIFMT_INV_MASK)
784 case SND_SOC_DAIFMT_NB_NF:
785 cs42l56->iface_inv = 0;
786 break;
787 case SND_SOC_DAIFMT_IB_NF:
788 cs42l56->iface_inv = CS42L56_S
789 break;
790 default:
791 return -EINVAL;
792 }
793
794 snd_soc_component_update_bits(componen
795 CS42L56_MS_MODE_MA
796 snd_soc_component_update_bits(componen
797 CS42L56_DIG_FMT_MA
798 snd_soc_component_update_bits(componen
799 CS42L56_SCLK_INV_M
800 return 0;
801 }
802
803 static int cs42l56_mute(struct snd_soc_dai *da
804 {
805 struct snd_soc_component *component =
806
807 if (mute) {
808 /* Hit the DSP Mixer first */
809 snd_soc_component_update_bits(
810 CS42L56_AD
811 CS42L56_AD
812 CS42L56_PC
813 CS42L56_PC
814 CS42L56_MS
815 CS42L56_MS
816 CS42L56_MU
817 /* Mute ADC's */
818 snd_soc_component_update_bits(
819 CS42L56_AD
820 CS42L56_AD
821 CS42L56_MU
822 /* HP And LO */
823 snd_soc_component_update_bits(
824 CS42L56_HP
825 snd_soc_component_update_bits(
826 CS42L56_HP
827 snd_soc_component_update_bits(
828 CS42L56_LO
829 snd_soc_component_update_bits(
830 CS42L56_LO
831 } else {
832 snd_soc_component_update_bits(
833 CS42L56_AD
834 CS42L56_AD
835 CS42L56_PC
836 CS42L56_PC
837 CS42L56_MS
838 CS42L56_MS
839 CS42L56_UN
840
841 snd_soc_component_update_bits(
842 CS42L56_AD
843 CS42L56_AD
844 CS42L56_UN
845
846 snd_soc_component_update_bits(
847 CS42L56_HP
848 snd_soc_component_update_bits(
849 CS42L56_HP
850 snd_soc_component_update_bits(
851 CS42L56_LO
852 snd_soc_component_update_bits(
853 CS42L56_LO
854 }
855 return 0;
856 }
857
858 static int cs42l56_pcm_hw_params(struct snd_pc
859 struct sn
860 struct sn
861 {
862 struct snd_soc_component *component =
863 struct cs42l56_private *cs42l56 = snd_
864 int ratio;
865
866 ratio = cs42l56_get_mclk_ratio(cs42l56
867 if (ratio >= 0) {
868 snd_soc_component_update_bits(
869 CS42L56_CL
870 } else {
871 dev_err(component->dev, "unsup
872 return -EINVAL;
873 }
874
875 return 0;
876 }
877
878 static int cs42l56_set_bias_level(struct snd_s
879 enum s
880 {
881 struct cs42l56_private *cs42l56 = snd_
882 int ret;
883
884 switch (level) {
885 case SND_SOC_BIAS_ON:
886 break;
887 case SND_SOC_BIAS_PREPARE:
888 snd_soc_component_update_bits(
889 CS42L56_MC
890 snd_soc_component_update_bits(
891 CS42L56_PD
892 break;
893 case SND_SOC_BIAS_STANDBY:
894 if (snd_soc_component_get_bias
895 regcache_cache_only(cs
896 regcache_sync(cs42l56-
897 ret = regulator_bulk_e
898
899 if (ret != 0) {
900 dev_err(cs42l5
901 "Faile
902 ret);
903 return ret;
904 }
905 }
906 snd_soc_component_update_bits(
907 CS42L56_PD
908 break;
909 case SND_SOC_BIAS_OFF:
910 snd_soc_component_update_bits(
911 CS42L56_PD
912 snd_soc_component_update_bits(
913 CS42L56_MC
914 regcache_cache_only(cs42l56->r
915 regulator_bulk_disable(ARRAY_S
916
917 break;
918 }
919
920 return 0;
921 }
922
923 #define CS42L56_RATES (SNDRV_PCM_RATE_8000_480
924
925 #define CS42L56_FORMATS (SNDRV_PCM_FMTBIT_S16_
926 SNDRV_PCM_FMTBIT_S20_3
927 SNDRV_PCM_FMTBIT_S32_L
928
929
930 static const struct snd_soc_dai_ops cs42l56_op
931 .hw_params = cs42l56_pcm_hw_param
932 .mute_stream = cs42l56_mute,
933 .set_fmt = cs42l56_set_dai_fmt,
934 .set_sysclk = cs42l56_set_sysclk,
935 .no_capture_mute = 1,
936 };
937
938 static struct snd_soc_dai_driver cs42l56_dai =
939 .name = "cs42l56",
940 .playback = {
941 .stream_name = "HiFi P
942 .channels_min = 1,
943 .channels_max = 2,
944 .rates = CS42L56_RATES
945 .formats = CS42L56_FOR
946 },
947 .capture = {
948 .stream_name = "HiFi C
949 .channels_min = 1,
950 .channels_max = 2,
951 .rates = CS42L56_RATES
952 .formats = CS42L56_FOR
953 },
954 .ops = &cs42l56_ops,
955 };
956
957 static int beep_freq[] = {
958 261, 522, 585, 667, 706, 774, 889, 100
959 1043, 1200, 1333, 1412, 1600, 1714, 20
960 };
961
962 static void cs42l56_beep_work(struct work_stru
963 {
964 struct cs42l56_private *cs42l56 =
965 container_of(work, struct cs42
966 struct snd_soc_component *component =
967 struct snd_soc_dapm_context *dapm = sn
968 int i;
969 int val = 0;
970 int best = 0;
971
972 if (cs42l56->beep_rate) {
973 for (i = 0; i < ARRAY_SIZE(bee
974 if (abs(cs42l56->beep_
975 abs(cs42l56->beep_
976 best = i;
977 }
978
979 dev_dbg(component->dev, "Set b
980 beep_freq[best], cs42l
981
982 val = (best << CS42L56_BEEP_RA
983
984 snd_soc_dapm_enable_pin(dapm,
985 } else {
986 dev_dbg(component->dev, "Disab
987 snd_soc_dapm_disable_pin(dapm,
988 }
989
990 snd_soc_component_update_bits(componen
991 CS42L56_BEEP_FREQ_
992
993 snd_soc_dapm_sync(dapm);
994 }
995
996 /* For usability define a way of injecting bee
997 * many systems will not have a keyboard.
998 */
999 static int cs42l56_beep_event(struct input_dev
1000 unsigned int cod
1001 {
1002 struct snd_soc_component *component =
1003 struct cs42l56_private *cs42l56 = snd
1004
1005 dev_dbg(component->dev, "Beep event %
1006
1007 switch (code) {
1008 case SND_BELL:
1009 if (hz)
1010 hz = 261;
1011 break;
1012 case SND_TONE:
1013 break;
1014 default:
1015 return -1;
1016 }
1017
1018 /* Kick the beep from a workqueue */
1019 cs42l56->beep_rate = hz;
1020 schedule_work(&cs42l56->beep_work);
1021 return 0;
1022 }
1023
1024 static ssize_t beep_store(struct device *dev,
1025 const char *buf, si
1026 {
1027 struct cs42l56_private *cs42l56 = dev
1028 long int time;
1029 int ret;
1030
1031 ret = kstrtol(buf, 10, &time);
1032 if (ret != 0)
1033 return ret;
1034
1035 input_event(cs42l56->beep, EV_SND, SN
1036
1037 return count;
1038 }
1039
1040 static DEVICE_ATTR_WO(beep);
1041
1042 static void cs42l56_init_beep(struct snd_soc_
1043 {
1044 struct cs42l56_private *cs42l56 = snd
1045 int ret;
1046
1047 cs42l56->beep = devm_input_allocate_d
1048 if (!cs42l56->beep) {
1049 dev_err(component->dev, "Fail
1050 return;
1051 }
1052
1053 INIT_WORK(&cs42l56->beep_work, cs42l5
1054 cs42l56->beep_rate = 0;
1055
1056 cs42l56->beep->name = "CS42L56 Beep G
1057 cs42l56->beep->phys = dev_name(compon
1058 cs42l56->beep->id.bustype = BUS_I2C;
1059
1060 cs42l56->beep->evbit[0] = BIT_MASK(EV
1061 cs42l56->beep->sndbit[0] = BIT_MASK(S
1062 cs42l56->beep->event = cs42l56_beep_e
1063 cs42l56->beep->dev.parent = component
1064 input_set_drvdata(cs42l56->beep, comp
1065
1066 ret = input_register_device(cs42l56->
1067 if (ret != 0) {
1068 cs42l56->beep = NULL;
1069 dev_err(component->dev, "Fail
1070 }
1071
1072 ret = device_create_file(component->d
1073 if (ret != 0) {
1074 dev_err(component->dev, "Fail
1075 ret);
1076 }
1077 }
1078
1079 static void cs42l56_free_beep(struct snd_soc_
1080 {
1081 struct cs42l56_private *cs42l56 = snd
1082
1083 device_remove_file(component->dev, &d
1084 cancel_work_sync(&cs42l56->beep_work)
1085 cs42l56->beep = NULL;
1086
1087 snd_soc_component_update_bits(compone
1088 CS42L56_BEEP_EN_M
1089 }
1090
1091 static int cs42l56_probe(struct snd_soc_compo
1092 {
1093 cs42l56_init_beep(component);
1094
1095 return 0;
1096 }
1097
1098 static void cs42l56_remove(struct snd_soc_com
1099 {
1100 cs42l56_free_beep(component);
1101 }
1102
1103 static const struct snd_soc_component_driver
1104 .probe = cs42l56_pro
1105 .remove = cs42l56_rem
1106 .set_bias_level = cs42l56_set
1107 .controls = cs42l56_snd
1108 .num_controls = ARRAY_SIZE(
1109 .dapm_widgets = cs42l56_dap
1110 .num_dapm_widgets = ARRAY_SIZE(
1111 .dapm_routes = cs42l56_aud
1112 .num_dapm_routes = ARRAY_SIZE(
1113 .suspend_bias_off = 1,
1114 .idle_bias_on = 1,
1115 .use_pmdown_time = 1,
1116 .endianness = 1,
1117 };
1118
1119 static const struct regmap_config cs42l56_reg
1120 .reg_bits = 8,
1121 .val_bits = 8,
1122
1123 .max_register = CS42L56_MAX_REGISTER,
1124 .reg_defaults = cs42l56_reg_defaults,
1125 .num_reg_defaults = ARRAY_SIZE(cs42l5
1126 .readable_reg = cs42l56_readable_regi
1127 .volatile_reg = cs42l56_volatile_regi
1128 .cache_type = REGCACHE_MAPLE,
1129 };
1130
1131 static int cs42l56_handle_of_data(struct i2c_
1132 struct cs
1133 {
1134 struct device_node *np = i2c_client->
1135 u32 val32;
1136
1137 if (of_property_read_bool(np, "cirrus
1138 pdata->ain1a_ref_cfg = true;
1139
1140 if (of_property_read_bool(np, "cirrus
1141 pdata->ain2a_ref_cfg = true;
1142
1143 if (of_property_read_bool(np, "cirrus
1144 pdata->ain1b_ref_cfg = true;
1145
1146 if (of_property_read_bool(np, "cirrus
1147 pdata->ain2b_ref_cfg = true;
1148
1149 if (of_property_read_u32(np, "cirrus,
1150 pdata->micbias_lvl = val32;
1151
1152 if (of_property_read_u32(np, "cirrus,
1153 pdata->chgfreq = val32;
1154
1155 if (of_property_read_u32(np, "cirrus,
1156 pdata->adaptive_pwr = val32;
1157
1158 if (of_property_read_u32(np, "cirrus,
1159 pdata->hpfa_freq = val32;
1160
1161 if (of_property_read_u32(np, "cirrus,
1162 pdata->hpfb_freq = val32;
1163
1164 pdata->gpio_nreset = of_get_named_gpi
1165
1166 return 0;
1167 }
1168
1169 static int cs42l56_i2c_probe(struct i2c_clien
1170 {
1171 struct cs42l56_private *cs42l56;
1172 struct cs42l56_platform_data *pdata =
1173 dev_get_platdata(&i2c_client-
1174 int ret, i;
1175 unsigned int devid;
1176 unsigned int alpha_rev, metal_rev;
1177 unsigned int reg;
1178
1179 cs42l56 = devm_kzalloc(&i2c_client->d
1180 if (cs42l56 == NULL)
1181 return -ENOMEM;
1182 cs42l56->dev = &i2c_client->dev;
1183
1184 cs42l56->regmap = devm_regmap_init_i2
1185 if (IS_ERR(cs42l56->regmap)) {
1186 ret = PTR_ERR(cs42l56->regmap
1187 dev_err(&i2c_client->dev, "re
1188 return ret;
1189 }
1190
1191 if (pdata) {
1192 cs42l56->pdata = *pdata;
1193 } else {
1194 if (i2c_client->dev.of_node)
1195 ret = cs42l56_handle_
1196
1197 if (ret != 0)
1198 return ret;
1199 }
1200 }
1201
1202 if (cs42l56->pdata.gpio_nreset) {
1203 ret = gpio_request_one(cs42l5
1204 GPIOF_
1205 if (ret < 0) {
1206 dev_err(&i2c_client->
1207 "Failed to re
1208 cs42l56->pdat
1209 return ret;
1210 }
1211 gpio_set_value_cansleep(cs42l
1212 gpio_set_value_cansleep(cs42l
1213 }
1214
1215
1216 i2c_set_clientdata(i2c_client, cs42l5
1217
1218 for (i = 0; i < ARRAY_SIZE(cs42l56->s
1219 cs42l56->supplies[i].supply =
1220
1221 ret = devm_regulator_bulk_get(&i2c_cl
1222 ARRAY_S
1223 cs42l56
1224 if (ret != 0) {
1225 dev_err(&i2c_client->dev,
1226 "Failed to request su
1227 return ret;
1228 }
1229
1230 ret = regulator_bulk_enable(ARRAY_SIZ
1231 cs42l56->
1232 if (ret != 0) {
1233 dev_err(&i2c_client->dev,
1234 "Failed to enable sup
1235 return ret;
1236 }
1237
1238 ret = regmap_read(cs42l56->regmap, CS
1239 if (ret) {
1240 dev_err(&i2c_client->dev, "Fa
1241 goto err_enable;
1242 }
1243
1244 devid = reg & CS42L56_CHIP_ID_MASK;
1245 if (devid != CS42L56_DEVID) {
1246 dev_err(&i2c_client->dev,
1247 "CS42L56 Device ID (%
1248 devid, CS42L56_DEVID)
1249 ret = -EINVAL;
1250 goto err_enable;
1251 }
1252 alpha_rev = reg & CS42L56_AREV_MASK;
1253 metal_rev = reg & CS42L56_MTLREV_MASK
1254
1255 dev_info(&i2c_client->dev, "Cirrus Lo
1256 dev_info(&i2c_client->dev, "Alpha Rev
1257 alpha_rev, metal_rev);
1258
1259 if (cs42l56->pdata.ain1a_ref_cfg)
1260 regmap_update_bits(cs42l56->r
1261 CS42L56_AI
1262 CS42L56_AI
1263
1264 if (cs42l56->pdata.ain1b_ref_cfg)
1265 regmap_update_bits(cs42l56->r
1266 CS42L56_AI
1267 CS42L56_AI
1268
1269 if (cs42l56->pdata.ain2a_ref_cfg)
1270 regmap_update_bits(cs42l56->r
1271 CS42L56_AI
1272 CS42L56_AI
1273
1274 if (cs42l56->pdata.ain2b_ref_cfg)
1275 regmap_update_bits(cs42l56->r
1276 CS42L56_AI
1277 CS42L56_AI
1278
1279 if (cs42l56->pdata.micbias_lvl)
1280 regmap_update_bits(cs42l56->r
1281 CS42L56_MI
1282 cs42l56->pdat
1283
1284 if (cs42l56->pdata.chgfreq)
1285 regmap_update_bits(cs42l56->r
1286 CS42L56_CH
1287 cs42l56->pdat
1288
1289 if (cs42l56->pdata.hpfb_freq)
1290 regmap_update_bits(cs42l56->r
1291 CS42L56_HP
1292 cs42l56->pdat
1293
1294 if (cs42l56->pdata.hpfa_freq)
1295 regmap_update_bits(cs42l56->r
1296 CS42L56_HP
1297 cs42l56->pdat
1298
1299 if (cs42l56->pdata.adaptive_pwr)
1300 regmap_update_bits(cs42l56->r
1301 CS42L56_AD
1302 cs42l56->pdat
1303
1304 ret = devm_snd_soc_register_componen
1305 &soc_component_dev_cs
1306 if (ret < 0)
1307 goto err_enable;
1308
1309 return 0;
1310
1311 err_enable:
1312 regulator_bulk_disable(ARRAY_SIZE(cs4
1313 cs42l56->suppl
1314 return ret;
1315 }
1316
1317 static void cs42l56_i2c_remove(struct i2c_cli
1318 {
1319 struct cs42l56_private *cs42l56 = i2c
1320
1321 regulator_bulk_disable(ARRAY_SIZE(cs4
1322 cs42l56->suppl
1323 }
1324
1325 static const struct of_device_id cs42l56_of_m
1326 { .compatible = "cirrus,cs42l56", },
1327 { }
1328 };
1329 MODULE_DEVICE_TABLE(of, cs42l56_of_match);
1330
1331
1332 static const struct i2c_device_id cs42l56_id[
1333 { "cs42l56" },
1334 { }
1335 };
1336 MODULE_DEVICE_TABLE(i2c, cs42l56_id);
1337
1338 static struct i2c_driver cs42l56_i2c_driver =
1339 .driver = {
1340 .name = "cs42l56",
1341 .of_match_table = cs42l56_of_
1342 },
1343 .id_table = cs42l56_id,
1344 .probe = cs42l56_i2c_probe,
1345 .remove = cs42l56_i2c_remove,
1346 };
1347
1348 module_i2c_driver(cs42l56_i2c_driver);
1349
1350 MODULE_DESCRIPTION("ASoC CS42L56 driver");
1351 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc
1352 MODULE_LICENSE("GPL");
1353
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