1 /* SPDX-License-Identifier: GPL-2.0-only */ <<
2 /* 1 /*
3 * lm49453.h - LM49453 ALSA Soc Audio drive 2 * lm49453.h - LM49453 ALSA Soc Audio drive
4 * 3 *
5 * Copyright (c) 2012 Texas Instruments, Inc 4 * Copyright (c) 2012 Texas Instruments, Inc
>> 5 *
>> 6 * This program is free software; you can redistribute it and/or modify
>> 7 * it under the terms of the GNU General Public License as published by
>> 8 * the Free Software Foundation; version 2 of the License.
>> 9 *
6 */ 10 */
7 11
8 #ifndef _LM49453_H 12 #ifndef _LM49453_H
9 #define _LM49453_H 13 #define _LM49453_H
10 14
11 #include <linux/bitops.h> 15 #include <linux/bitops.h>
12 16
13 /* LM49453_P0 register space for page0 */ 17 /* LM49453_P0 register space for page0 */
14 #define LM49453_P0_PMC_SETUP_REG 18 #define LM49453_P0_PMC_SETUP_REG 0x00
15 #define LM49453_P0_PLL_CLK_SEL1_REG 19 #define LM49453_P0_PLL_CLK_SEL1_REG 0x01
16 #define LM49453_P0_PLL_CLK_SEL2_REG 20 #define LM49453_P0_PLL_CLK_SEL2_REG 0x02
17 #define LM49453_P0_PMC_CLK_DIV_REG 21 #define LM49453_P0_PMC_CLK_DIV_REG 0x03
18 #define LM49453_P0_HSDET_CLK_DIV_REG 22 #define LM49453_P0_HSDET_CLK_DIV_REG 0x04
19 #define LM49453_P0_DMIC_CLK_DIV_REG 23 #define LM49453_P0_DMIC_CLK_DIV_REG 0x05
20 #define LM49453_P0_ADC_CLK_DIV_REG 24 #define LM49453_P0_ADC_CLK_DIV_REG 0x06
21 #define LM49453_P0_DAC_OT_CLK_DIV_REG 25 #define LM49453_P0_DAC_OT_CLK_DIV_REG 0x07
22 #define LM49453_P0_PLL_HF_M_REG 26 #define LM49453_P0_PLL_HF_M_REG 0x08
23 #define LM49453_P0_PLL_LF_M_REG 27 #define LM49453_P0_PLL_LF_M_REG 0x09
24 #define LM49453_P0_PLL_NL_REG 28 #define LM49453_P0_PLL_NL_REG 0x0A
25 #define LM49453_P0_PLL_N_MODL_REG 29 #define LM49453_P0_PLL_N_MODL_REG 0x0B
26 #define LM49453_P0_PLL_N_MODH_REG 30 #define LM49453_P0_PLL_N_MODH_REG 0x0C
27 #define LM49453_P0_PLL_P1_REG 31 #define LM49453_P0_PLL_P1_REG 0x0D
28 #define LM49453_P0_PLL_P2_REG 32 #define LM49453_P0_PLL_P2_REG 0x0E
29 #define LM49453_P0_FLL_REF_FREQL_REG 33 #define LM49453_P0_FLL_REF_FREQL_REG 0x0F
30 #define LM49453_P0_FLL_REF_FREQH_REG 34 #define LM49453_P0_FLL_REF_FREQH_REG 0x10
31 #define LM49453_P0_VCO_TARGETLL_REG 35 #define LM49453_P0_VCO_TARGETLL_REG 0x11
32 #define LM49453_P0_VCO_TARGETLH_REG 36 #define LM49453_P0_VCO_TARGETLH_REG 0x12
33 #define LM49453_P0_VCO_TARGETHL_REG 37 #define LM49453_P0_VCO_TARGETHL_REG 0x13
34 #define LM49453_P0_VCO_TARGETHH_REG 38 #define LM49453_P0_VCO_TARGETHH_REG 0x14
35 #define LM49453_P0_PLL_CONFIG_REG 39 #define LM49453_P0_PLL_CONFIG_REG 0x15
36 #define LM49453_P0_DAC_CLK_SEL_REG 40 #define LM49453_P0_DAC_CLK_SEL_REG 0x16
37 #define LM49453_P0_DAC_HP_CLK_DIV_REG 41 #define LM49453_P0_DAC_HP_CLK_DIV_REG 0x17
38 42
39 /* Analog Mixer Input Stages */ 43 /* Analog Mixer Input Stages */
40 #define LM49453_P0_MICL_REG 44 #define LM49453_P0_MICL_REG 0x20
41 #define LM49453_P0_MICR_REG 45 #define LM49453_P0_MICR_REG 0x21
42 #define LM49453_P0_EP_REG 46 #define LM49453_P0_EP_REG 0x24
43 #define LM49453_P0_DIS_PKVL_FB_REG 47 #define LM49453_P0_DIS_PKVL_FB_REG 0x25
44 48
45 /* Analog Mixer Output Stages */ 49 /* Analog Mixer Output Stages */
46 #define LM49453_P0_ANALOG_MIXER_ADC_REG 50 #define LM49453_P0_ANALOG_MIXER_ADC_REG 0x2E
47 51
48 /*ADC or DAC */ 52 /*ADC or DAC */
49 #define LM49453_P0_ADC_DSP_REG 53 #define LM49453_P0_ADC_DSP_REG 0x30
50 #define LM49453_P0_DAC_DSP_REG 54 #define LM49453_P0_DAC_DSP_REG 0x31
51 55
52 /* EFFECTS ENABLES */ 56 /* EFFECTS ENABLES */
53 #define LM49453_P0_ADC_FX_ENABLES_REG 57 #define LM49453_P0_ADC_FX_ENABLES_REG 0x33
54 58
55 /* GPIO */ 59 /* GPIO */
56 #define LM49453_P0_GPIO1_REG 60 #define LM49453_P0_GPIO1_REG 0x38
57 #define LM49453_P0_GPIO2_REG 61 #define LM49453_P0_GPIO2_REG 0x39
58 #define LM49453_P0_GPIO3_REG 62 #define LM49453_P0_GPIO3_REG 0x3A
59 #define LM49453_P0_HAP_CTL_REG 63 #define LM49453_P0_HAP_CTL_REG 0x3B
60 #define LM49453_P0_HAP_FREQ_PROG_LEFTL_REG 64 #define LM49453_P0_HAP_FREQ_PROG_LEFTL_REG 0x3C
61 #define LM49453_P0_HAP_FREQ_PROG_LEFTH_REG 65 #define LM49453_P0_HAP_FREQ_PROG_LEFTH_REG 0x3D
62 #define LM49453_P0_HAP_FREQ_PROG_RIGHTL_REG 66 #define LM49453_P0_HAP_FREQ_PROG_RIGHTL_REG 0x3E
63 #define LM49453_P0_HAP_FREQ_PROG_RIGHTH_REG 67 #define LM49453_P0_HAP_FREQ_PROG_RIGHTH_REG 0x3F
64 68
65 /* DIGITAL MIXER */ 69 /* DIGITAL MIXER */
66 #define LM49453_P0_DMIX_CLK_SEL_REG 70 #define LM49453_P0_DMIX_CLK_SEL_REG 0x40
67 #define LM49453_P0_PORT1_RX_LVL1_REG 71 #define LM49453_P0_PORT1_RX_LVL1_REG 0x41
68 #define LM49453_P0_PORT1_RX_LVL2_REG 72 #define LM49453_P0_PORT1_RX_LVL2_REG 0x42
69 #define LM49453_P0_PORT2_RX_LVL_REG 73 #define LM49453_P0_PORT2_RX_LVL_REG 0x43
70 #define LM49453_P0_PORT1_TX1_REG 74 #define LM49453_P0_PORT1_TX1_REG 0x44
71 #define LM49453_P0_PORT1_TX2_REG 75 #define LM49453_P0_PORT1_TX2_REG 0x45
72 #define LM49453_P0_PORT1_TX3_REG 76 #define LM49453_P0_PORT1_TX3_REG 0x46
73 #define LM49453_P0_PORT1_TX4_REG 77 #define LM49453_P0_PORT1_TX4_REG 0x47
74 #define LM49453_P0_PORT1_TX5_REG 78 #define LM49453_P0_PORT1_TX5_REG 0x48
75 #define LM49453_P0_PORT1_TX6_REG 79 #define LM49453_P0_PORT1_TX6_REG 0x49
76 #define LM49453_P0_PORT1_TX7_REG 80 #define LM49453_P0_PORT1_TX7_REG 0x4A
77 #define LM49453_P0_PORT1_TX8_REG 81 #define LM49453_P0_PORT1_TX8_REG 0x4B
78 #define LM49453_P0_PORT2_TX1_REG 82 #define LM49453_P0_PORT2_TX1_REG 0x4C
79 #define LM49453_P0_PORT2_TX2_REG 83 #define LM49453_P0_PORT2_TX2_REG 0x4D
80 #define LM49453_P0_STN_SEL_REG 84 #define LM49453_P0_STN_SEL_REG 0x4F
81 #define LM49453_P0_DACHPL1_REG 85 #define LM49453_P0_DACHPL1_REG 0x50
82 #define LM49453_P0_DACHPL2_REG 86 #define LM49453_P0_DACHPL2_REG 0x51
83 #define LM49453_P0_DACHPR1_REG 87 #define LM49453_P0_DACHPR1_REG 0x52
84 #define LM49453_P0_DACHPR2_REG 88 #define LM49453_P0_DACHPR2_REG 0x53
85 #define LM49453_P0_DACLOL1_REG 89 #define LM49453_P0_DACLOL1_REG 0x54
86 #define LM49453_P0_DACLOL2_REG 90 #define LM49453_P0_DACLOL2_REG 0x55
87 #define LM49453_P0_DACLOR1_REG 91 #define LM49453_P0_DACLOR1_REG 0x56
88 #define LM49453_P0_DACLOR2_REG 92 #define LM49453_P0_DACLOR2_REG 0x57
89 #define LM49453_P0_DACLSL1_REG 93 #define LM49453_P0_DACLSL1_REG 0x58
90 #define LM49453_P0_DACLSL2_REG 94 #define LM49453_P0_DACLSL2_REG 0x59
91 #define LM49453_P0_DACLSR1_REG 95 #define LM49453_P0_DACLSR1_REG 0x5A
92 #define LM49453_P0_DACLSR2_REG 96 #define LM49453_P0_DACLSR2_REG 0x5B
93 #define LM49453_P0_DACHAL1_REG 97 #define LM49453_P0_DACHAL1_REG 0x5C
94 #define LM49453_P0_DACHAL2_REG 98 #define LM49453_P0_DACHAL2_REG 0x5D
95 #define LM49453_P0_DACHAR1_REG 99 #define LM49453_P0_DACHAR1_REG 0x5E
96 #define LM49453_P0_DACHAR2_REG 100 #define LM49453_P0_DACHAR2_REG 0x5F
97 101
98 /* AUDIO PORT 1 (TDM) */ 102 /* AUDIO PORT 1 (TDM) */
99 #define LM49453_P0_AUDIO_PORT1_BASIC_REG 103 #define LM49453_P0_AUDIO_PORT1_BASIC_REG 0x60
100 #define LM49453_P0_AUDIO_PORT1_CLK_GEN1_REG 104 #define LM49453_P0_AUDIO_PORT1_CLK_GEN1_REG 0x61
101 #define LM49453_P0_AUDIO_PORT1_CLK_GEN2_REG 105 #define LM49453_P0_AUDIO_PORT1_CLK_GEN2_REG 0x62
102 #define LM49453_P0_AUDIO_PORT1_CLK_GEN3_REG 106 #define LM49453_P0_AUDIO_PORT1_CLK_GEN3_REG 0x63
103 #define LM49453_P0_AUDIO_PORT1_SYNC_RATE_REG 107 #define LM49453_P0_AUDIO_PORT1_SYNC_RATE_REG 0x64
104 #define LM49453_P0_AUDIO_PORT1_SYNC_SDO_SETUP_ 108 #define LM49453_P0_AUDIO_PORT1_SYNC_SDO_SETUP_REG 0x65
105 #define LM49453_P0_AUDIO_PORT1_DATA_WIDTH_REG 109 #define LM49453_P0_AUDIO_PORT1_DATA_WIDTH_REG 0x66
106 #define LM49453_P0_AUDIO_PORT1_RX_MSB_REG 110 #define LM49453_P0_AUDIO_PORT1_RX_MSB_REG 0x67
107 #define LM49453_P0_AUDIO_PORT1_TX_MSB_REG 111 #define LM49453_P0_AUDIO_PORT1_TX_MSB_REG 0x68
108 #define LM49453_P0_AUDIO_PORT1_TDM_CHANNELS_RE 112 #define LM49453_P0_AUDIO_PORT1_TDM_CHANNELS_REG 0x69
109 113
110 /* AUDIO PORT 2 */ 114 /* AUDIO PORT 2 */
111 #define LM49453_P0_AUDIO_PORT2_BASIC_REG 115 #define LM49453_P0_AUDIO_PORT2_BASIC_REG 0x6A
112 #define LM49453_P0_AUDIO_PORT2_CLK_GEN1_REG 116 #define LM49453_P0_AUDIO_PORT2_CLK_GEN1_REG 0x6B
113 #define LM49453_P0_AUDIO_PORT2_CLK_GEN2_REG 117 #define LM49453_P0_AUDIO_PORT2_CLK_GEN2_REG 0x6C
114 #define LM49453_P0_AUDIO_PORT2_SYNC_GEN_REG 118 #define LM49453_P0_AUDIO_PORT2_SYNC_GEN_REG 0x6D
115 #define LM49453_P0_AUDIO_PORT2_DATA_WIDTH_REG 119 #define LM49453_P0_AUDIO_PORT2_DATA_WIDTH_REG 0x6E
116 #define LM49453_P0_AUDIO_PORT2_RX_MODE_REG 120 #define LM49453_P0_AUDIO_PORT2_RX_MODE_REG 0x6F
117 #define LM49453_P0_AUDIO_PORT2_TX_MODE_REG 121 #define LM49453_P0_AUDIO_PORT2_TX_MODE_REG 0x70
118 122
119 /* SAMPLE RATE */ 123 /* SAMPLE RATE */
120 #define LM49453_P0_PORT1_SR_LSB_REG 124 #define LM49453_P0_PORT1_SR_LSB_REG 0x79
121 #define LM49453_P0_PORT1_SR_MSB_REG 125 #define LM49453_P0_PORT1_SR_MSB_REG 0x7A
122 #define LM49453_P0_PORT2_SR_LSB_REG 126 #define LM49453_P0_PORT2_SR_LSB_REG 0x7B
123 #define LM49453_P0_PORT2_SR_MSB_REG 127 #define LM49453_P0_PORT2_SR_MSB_REG 0x7C
124 128
125 /* EFFECTS - HPFs */ 129 /* EFFECTS - HPFs */
126 #define LM49453_P0_HPF_REG 130 #define LM49453_P0_HPF_REG 0x80
127 131
128 /* EFFECTS ADC ALC */ 132 /* EFFECTS ADC ALC */
129 #define LM49453_P0_ADC_ALC1_REG 133 #define LM49453_P0_ADC_ALC1_REG 0x82
130 #define LM49453_P0_ADC_ALC2_REG 134 #define LM49453_P0_ADC_ALC2_REG 0x83
131 #define LM49453_P0_ADC_ALC3_REG 135 #define LM49453_P0_ADC_ALC3_REG 0x84
132 #define LM49453_P0_ADC_ALC4_REG 136 #define LM49453_P0_ADC_ALC4_REG 0x85
133 #define LM49453_P0_ADC_ALC5_REG 137 #define LM49453_P0_ADC_ALC5_REG 0x86
134 #define LM49453_P0_ADC_ALC6_REG 138 #define LM49453_P0_ADC_ALC6_REG 0x87
135 #define LM49453_P0_ADC_ALC7_REG 139 #define LM49453_P0_ADC_ALC7_REG 0x88
136 #define LM49453_P0_ADC_ALC8_REG 140 #define LM49453_P0_ADC_ALC8_REG 0x89
137 #define LM49453_P0_DMIC1_LEVELL_REG 141 #define LM49453_P0_DMIC1_LEVELL_REG 0x8A
138 #define LM49453_P0_DMIC1_LEVELR_REG 142 #define LM49453_P0_DMIC1_LEVELR_REG 0x8B
139 #define LM49453_P0_DMIC2_LEVELL_REG 143 #define LM49453_P0_DMIC2_LEVELL_REG 0x8C
140 #define LM49453_P0_DMIC2_LEVELR_REG 144 #define LM49453_P0_DMIC2_LEVELR_REG 0x8D
141 #define LM49453_P0_ADC_LEVELL_REG 145 #define LM49453_P0_ADC_LEVELL_REG 0x8E
142 #define LM49453_P0_ADC_LEVELR_REG 146 #define LM49453_P0_ADC_LEVELR_REG 0x8F
143 #define LM49453_P0_DAC_HP_LEVELL_REG 147 #define LM49453_P0_DAC_HP_LEVELL_REG 0x90
144 #define LM49453_P0_DAC_HP_LEVELR_REG 148 #define LM49453_P0_DAC_HP_LEVELR_REG 0x91
145 #define LM49453_P0_DAC_LO_LEVELL_REG 149 #define LM49453_P0_DAC_LO_LEVELL_REG 0x92
146 #define LM49453_P0_DAC_LO_LEVELR_REG 150 #define LM49453_P0_DAC_LO_LEVELR_REG 0x93
147 #define LM49453_P0_DAC_LS_LEVELL_REG 151 #define LM49453_P0_DAC_LS_LEVELL_REG 0x94
148 #define LM49453_P0_DAC_LS_LEVELR_REG 152 #define LM49453_P0_DAC_LS_LEVELR_REG 0x95
149 #define LM49453_P0_DAC_HA_LEVELL_REG 153 #define LM49453_P0_DAC_HA_LEVELL_REG 0x96
150 #define LM49453_P0_DAC_HA_LEVELR_REG 154 #define LM49453_P0_DAC_HA_LEVELR_REG 0x97
151 #define LM49453_P0_SOFT_MUTE_REG 155 #define LM49453_P0_SOFT_MUTE_REG 0x98
152 #define LM49453_P0_DMIC_MUTE_CFG_REG 156 #define LM49453_P0_DMIC_MUTE_CFG_REG 0x99
153 #define LM49453_P0_ADC_MUTE_CFG_REG 157 #define LM49453_P0_ADC_MUTE_CFG_REG 0x9A
154 #define LM49453_P0_DAC_MUTE_CFG_REG 158 #define LM49453_P0_DAC_MUTE_CFG_REG 0x9B
155 159
156 /*DIGITAL MIC1 */ 160 /*DIGITAL MIC1 */
157 #define LM49453_P0_DIGITAL_MIC1_CONFIG_REG 161 #define LM49453_P0_DIGITAL_MIC1_CONFIG_REG 0xB0
158 #define LM49453_P0_DIGITAL_MIC1_DATA_DELAYL_RE 162 #define LM49453_P0_DIGITAL_MIC1_DATA_DELAYL_REG 0xB1
159 #define LM49453_P0_DIGITAL_MIC1_DATA_DELAYR_RE 163 #define LM49453_P0_DIGITAL_MIC1_DATA_DELAYR_REG 0xB2
160 164
161 /*DIGITAL MIC2 */ 165 /*DIGITAL MIC2 */
162 #define LM49453_P0_DIGITAL_MIC2_CONFIG_REG 166 #define LM49453_P0_DIGITAL_MIC2_CONFIG_REG 0xB3
163 #define LM49453_P0_DIGITAL_MIC2_DATA_DELAYL_RE 167 #define LM49453_P0_DIGITAL_MIC2_DATA_DELAYL_REG 0xB4
164 #define LM49453_P0_DIGITAL_MIC2_DATA_DELAYR_RE 168 #define LM49453_P0_DIGITAL_MIC2_DATA_DELAYR_REG 0xB5
165 169
166 /* ADC DECIMATOR */ 170 /* ADC DECIMATOR */
167 #define LM49453_P0_ADC_DECIMATOR_REG 171 #define LM49453_P0_ADC_DECIMATOR_REG 0xB6
168 172
169 /* DAC CONFIGURE */ 173 /* DAC CONFIGURE */
170 #define LM49453_P0_DAC_CONFIG_REG 174 #define LM49453_P0_DAC_CONFIG_REG 0xB7
171 175
172 /* SIDETONE */ 176 /* SIDETONE */
173 #define LM49453_P0_STN_VOL_ADCL_REG 177 #define LM49453_P0_STN_VOL_ADCL_REG 0xB8
174 #define LM49453_P0_STN_VOL_ADCR_REG 178 #define LM49453_P0_STN_VOL_ADCR_REG 0xB9
175 #define LM49453_P0_STN_VOL_DMIC1L_REG 179 #define LM49453_P0_STN_VOL_DMIC1L_REG 0xBA
176 #define LM49453_P0_STN_VOL_DMIC1R_REG 180 #define LM49453_P0_STN_VOL_DMIC1R_REG 0xBB
177 #define LM49453_P0_STN_VOL_DMIC2L_REG 181 #define LM49453_P0_STN_VOL_DMIC2L_REG 0xBC
178 #define LM49453_P0_STN_VOL_DMIC2R_REG 182 #define LM49453_P0_STN_VOL_DMIC2R_REG 0xBD
179 183
180 /* ADC/DAC CLIPPING MONITORS (Read Only/Write 184 /* ADC/DAC CLIPPING MONITORS (Read Only/Write to Clear) */
181 #define LM49453_P0_ADC_DEC_CLIP_REG 185 #define LM49453_P0_ADC_DEC_CLIP_REG 0xC2
182 #define LM49453_P0_ADC_HPF_CLIP_REG 186 #define LM49453_P0_ADC_HPF_CLIP_REG 0xC3
183 #define LM49453_P0_ADC_LVL_CLIP_REG 187 #define LM49453_P0_ADC_LVL_CLIP_REG 0xC4
184 #define LM49453_P0_DAC_LVL_CLIP_REG 188 #define LM49453_P0_DAC_LVL_CLIP_REG 0xC5
185 189
186 /* ADC ALC EFFECT MONITORS (Read Only) */ 190 /* ADC ALC EFFECT MONITORS (Read Only) */
187 #define LM49453_P0_ADC_LVLMONL_REG 191 #define LM49453_P0_ADC_LVLMONL_REG 0xC8
188 #define LM49453_P0_ADC_LVLMONR_REG 192 #define LM49453_P0_ADC_LVLMONR_REG 0xC9
189 #define LM49453_P0_ADC_ALCMONL_REG 193 #define LM49453_P0_ADC_ALCMONL_REG 0xCA
190 #define LM49453_P0_ADC_ALCMONR_REG 194 #define LM49453_P0_ADC_ALCMONR_REG 0xCB
191 #define LM49453_P0_ADC_MUTED_REG 195 #define LM49453_P0_ADC_MUTED_REG 0xCC
192 #define LM49453_P0_DAC_MUTED_REG 196 #define LM49453_P0_DAC_MUTED_REG 0xCD
193 197
194 /* HEADSET DETECT */ 198 /* HEADSET DETECT */
195 #define LM49453_P0_HSD_PPB_LONG_CNT_LIMITL_REG 199 #define LM49453_P0_HSD_PPB_LONG_CNT_LIMITL_REG 0xD0
196 #define LM49453_P0_HSD_PPB_LONG_CNT_LIMITR_REG 200 #define LM49453_P0_HSD_PPB_LONG_CNT_LIMITR_REG 0xD1
197 #define LM49453_P0_HSD_PIN3_4_EX_LOOP_CNT_LIMI 201 #define LM49453_P0_HSD_PIN3_4_EX_LOOP_CNT_LIMITL_REG 0xD2
198 #define LM49453_P0_HSD_PIN3_4_EX_LOOP_CNT_LIMI 202 #define LM49453_P0_HSD_PIN3_4_EX_LOOP_CNT_LIMITH_REG 0xD3
199 #define LM49453_P0_HSD_TIMEOUT1_REG 203 #define LM49453_P0_HSD_TIMEOUT1_REG 0xD4
200 #define LM49453_P0_HSD_TIMEOUT2_REG 204 #define LM49453_P0_HSD_TIMEOUT2_REG 0xD5
201 #define LM49453_P0_HSD_TIMEOUT3_REG 205 #define LM49453_P0_HSD_TIMEOUT3_REG 0xD6
202 #define LM49453_P0_HSD_PIN3_4_CFG_REG 206 #define LM49453_P0_HSD_PIN3_4_CFG_REG 0xD7
203 #define LM49453_P0_HSD_IRQ1_REG 207 #define LM49453_P0_HSD_IRQ1_REG 0xD8
204 #define LM49453_P0_HSD_IRQ2_REG 208 #define LM49453_P0_HSD_IRQ2_REG 0xD9
205 #define LM49453_P0_HSD_IRQ3_REG 209 #define LM49453_P0_HSD_IRQ3_REG 0xDA
206 #define LM49453_P0_HSD_IRQ4_REG 210 #define LM49453_P0_HSD_IRQ4_REG 0xDB
207 #define LM49453_P0_HSD_IRQ_MASK1_REG 211 #define LM49453_P0_HSD_IRQ_MASK1_REG 0xDC
208 #define LM49453_P0_HSD_IRQ_MASK2_REG 212 #define LM49453_P0_HSD_IRQ_MASK2_REG 0xDD
209 #define LM49453_P0_HSD_IRQ_MASK3_REG 213 #define LM49453_P0_HSD_IRQ_MASK3_REG 0xDE
210 #define LM49453_P0_HSD_R_HPLL_REG 214 #define LM49453_P0_HSD_R_HPLL_REG 0xE0
211 #define LM49453_P0_HSD_R_HPLH_REG 215 #define LM49453_P0_HSD_R_HPLH_REG 0xE1
212 #define LM49453_P0_HSD_R_HPLU_REG 216 #define LM49453_P0_HSD_R_HPLU_REG 0xE2
213 #define LM49453_P0_HSD_R_HPRL_REG 217 #define LM49453_P0_HSD_R_HPRL_REG 0xE3
214 #define LM49453_P0_HSD_R_HPRH_REG 218 #define LM49453_P0_HSD_R_HPRH_REG 0xE4
215 #define LM49453_P0_HSD_R_HPRU_REG 219 #define LM49453_P0_HSD_R_HPRU_REG 0xE5
216 #define LM49453_P0_HSD_VEL_L_FINALL_REG 220 #define LM49453_P0_HSD_VEL_L_FINALL_REG 0xE6
217 #define LM49453_P0_HSD_VEL_L_FINALH_REG 221 #define LM49453_P0_HSD_VEL_L_FINALH_REG 0xE7
218 #define LM49453_P0_HSD_VEL_L_FINALU_REG 222 #define LM49453_P0_HSD_VEL_L_FINALU_REG 0xE8
219 #define LM49453_P0_HSD_RO_FINALL_REG 223 #define LM49453_P0_HSD_RO_FINALL_REG 0xE9
220 #define LM49453_P0_HSD_RO_FINALH_REG 224 #define LM49453_P0_HSD_RO_FINALH_REG 0xEA
221 #define LM49453_P0_HSD_RO_FINALU_REG 225 #define LM49453_P0_HSD_RO_FINALU_REG 0xEB
222 #define LM49453_P0_HSD_VMIC_BIAS_FINALL_REG 226 #define LM49453_P0_HSD_VMIC_BIAS_FINALL_REG 0xEC
223 #define LM49453_P0_HSD_VMIC_BIAS_FINALH_REG 227 #define LM49453_P0_HSD_VMIC_BIAS_FINALH_REG 0xED
224 #define LM49453_P0_HSD_VMIC_BIAS_FINALU_REG 228 #define LM49453_P0_HSD_VMIC_BIAS_FINALU_REG 0xEE
225 #define LM49453_P0_HSD_PIN_CONFIG_REG 229 #define LM49453_P0_HSD_PIN_CONFIG_REG 0xEF
226 #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STAT 230 #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATUS1_REG 0xF1
227 #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STAT 231 #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATUS2_REG 0xF2
228 #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STAT 232 #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATUS3_REG 0xF3
229 #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STAT 233 #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATEL_REG 0xF4
230 #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STAT 234 #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATEH_REG 0xF5
231 235
232 /* I/O PULLDOWN CONFIG */ 236 /* I/O PULLDOWN CONFIG */
233 #define LM49453_P0_PULL_CONFIG1_REG 237 #define LM49453_P0_PULL_CONFIG1_REG 0xF8
234 #define LM49453_P0_PULL_CONFIG2_REG 238 #define LM49453_P0_PULL_CONFIG2_REG 0xF9
235 #define LM49453_P0_PULL_CONFIG3_REG 239 #define LM49453_P0_PULL_CONFIG3_REG 0xFA
236 240
237 /* RESET */ 241 /* RESET */
238 #define LM49453_P0_RESET_REG 242 #define LM49453_P0_RESET_REG 0xFE
239 243
240 /* PAGE */ 244 /* PAGE */
241 #define LM49453_PAGE_REG 245 #define LM49453_PAGE_REG 0xFF
242 246
243 #define LM49453_MAX_REGISTER 247 #define LM49453_MAX_REGISTER (0xFF+1)
244 248
245 /* LM49453_P0_PMC_SETUP_REG (0x00h) */ 249 /* LM49453_P0_PMC_SETUP_REG (0x00h) */
246 #define LM49453_PMC_SETUP_CHIP_EN 250 #define LM49453_PMC_SETUP_CHIP_EN (BIT(1)|BIT(0))
247 #define LM49453_PMC_SETUP_PLL_EN 251 #define LM49453_PMC_SETUP_PLL_EN BIT(2)
248 #define LM49453_PMC_SETUP_PLL_P2_EN 252 #define LM49453_PMC_SETUP_PLL_P2_EN BIT(3)
249 #define LM49453_PMC_SETUP_PLL_FLL 253 #define LM49453_PMC_SETUP_PLL_FLL BIT(4)
250 #define LM49453_PMC_SETUP_MCLK_OVER 254 #define LM49453_PMC_SETUP_MCLK_OVER BIT(5)
251 #define LM49453_PMC_SETUP_RTC_CLK_OVER 255 #define LM49453_PMC_SETUP_RTC_CLK_OVER BIT(6)
252 #define LM49453_PMC_SETUP_CHIP_ACTIVE 256 #define LM49453_PMC_SETUP_CHIP_ACTIVE BIT(7)
253 257
254 /* Chip Enable bits */ 258 /* Chip Enable bits */
255 #define LM49453_CHIP_EN_SHUTDOWN 259 #define LM49453_CHIP_EN_SHUTDOWN 0x00
256 #define LM49453_CHIP_EN 260 #define LM49453_CHIP_EN 0x01
257 #define LM49453_CHIP_EN_HSD_DETECT 261 #define LM49453_CHIP_EN_HSD_DETECT 0x02
258 #define LM49453_CHIP_EN_INVALID_HSD 262 #define LM49453_CHIP_EN_INVALID_HSD 0x03
259 263
260 /* LM49453_P0_PLL_CLK_SEL1_REG (0x01h) */ 264 /* LM49453_P0_PLL_CLK_SEL1_REG (0x01h) */
261 #define LM49453_CLK_SEL1_MCLK_SEL 265 #define LM49453_CLK_SEL1_MCLK_SEL 0x11
262 #define LM49453_CLK_SEL1_RTC_SEL 266 #define LM49453_CLK_SEL1_RTC_SEL 0x11
263 #define LM49453_CLK_SEL1_PORT1_SEL 267 #define LM49453_CLK_SEL1_PORT1_SEL 0x10
264 #define LM49453_CLK_SEL1_PORT2_SEL 268 #define LM49453_CLK_SEL1_PORT2_SEL 0x11
265 269
266 /* LM49453_P0_PLL_CLK_SEL2_REG (0x02h) */ 270 /* LM49453_P0_PLL_CLK_SEL2_REG (0x02h) */
267 #define LM49453_CLK_SEL2_ADC_CLK_SEL 271 #define LM49453_CLK_SEL2_ADC_CLK_SEL 0x38
268 272
269 /* LM49453_P0_FLL_REF_FREQL_REG (0x0F) */ 273 /* LM49453_P0_FLL_REF_FREQL_REG (0x0F) */
270 #define LM49453_FLL_REF_FREQ_VAL 274 #define LM49453_FLL_REF_FREQ_VAL 0x8ca0001
271 275
272 /* LM49453_P0_VCO_TARGETLL_REG (0x11) */ 276 /* LM49453_P0_VCO_TARGETLL_REG (0x11) */
273 #define LM49453_VCO_TARGET_VAL 277 #define LM49453_VCO_TARGET_VAL 0x8ca0001
274 278
275 /* LM49453_P0_ADC_DSP_REG (0x30h) */ 279 /* LM49453_P0_ADC_DSP_REG (0x30h) */
276 #define LM49453_ADC_DSP_ADC_MUTEL 280 #define LM49453_ADC_DSP_ADC_MUTEL BIT(0)
277 #define LM49453_ADC_DSP_ADC_MUTER 281 #define LM49453_ADC_DSP_ADC_MUTER BIT(1)
278 #define LM49453_ADC_DSP_DMIC1_MUTEL 282 #define LM49453_ADC_DSP_DMIC1_MUTEL BIT(2)
279 #define LM49453_ADC_DSP_DMIC1_MUTER 283 #define LM49453_ADC_DSP_DMIC1_MUTER BIT(3)
280 #define LM49453_ADC_DSP_DMIC2_MUTEL 284 #define LM49453_ADC_DSP_DMIC2_MUTEL BIT(4)
281 #define LM49453_ADC_DSP_DMIC2_MUTER 285 #define LM49453_ADC_DSP_DMIC2_MUTER BIT(5)
282 #define LM49453_ADC_DSP_MUTE_ALL 286 #define LM49453_ADC_DSP_MUTE_ALL 0x3F
283 287
284 /* LM49453_P0_DAC_DSP_REG (0x31h) */ 288 /* LM49453_P0_DAC_DSP_REG (0x31h) */
285 #define LM49453_DAC_DSP_MUTE_ALL 289 #define LM49453_DAC_DSP_MUTE_ALL 0xFF
286 290
287 /* LM49453_P0_AUDIO_PORT1_BASIC_REG (0x60h) */ 291 /* LM49453_P0_AUDIO_PORT1_BASIC_REG (0x60h) */
288 #define LM49453_AUDIO_PORT1_BASIC_FMT_MASK 292 #define LM49453_AUDIO_PORT1_BASIC_FMT_MASK (BIT(4)|BIT(3))
289 #define LM49453_AUDIO_PORT1_BASIC_CLK_MS 293 #define LM49453_AUDIO_PORT1_BASIC_CLK_MS BIT(3)
290 #define LM49453_AUDIO_PORT1_BASIC_SYNC_MS 294 #define LM49453_AUDIO_PORT1_BASIC_SYNC_MS BIT(4)
291 295
292 /* LM49453_P0_RESET_REG (0xFEh) */ 296 /* LM49453_P0_RESET_REG (0xFEh) */
293 #define LM49453_RESET_REG_RST 297 #define LM49453_RESET_REG_RST BIT(0)
294 298
295 /* Page select register bits (0xFF) */ 299 /* Page select register bits (0xFF) */
296 #define LM49453_PAGE0_SELECT 300 #define LM49453_PAGE0_SELECT 0x0
297 #define LM49453_PAGE1_SELECT 301 #define LM49453_PAGE1_SELECT 0x1
298 302
299 /* LM49453_P0_HSD_PIN3_4_CFG_REG (Jack Pin con 303 /* LM49453_P0_HSD_PIN3_4_CFG_REG (Jack Pin config - 0xD7) */
300 #define LM49453_JACK_DISABLE 304 #define LM49453_JACK_DISABLE 0x00
301 #define LM49453_JACK_CONFIG1 305 #define LM49453_JACK_CONFIG1 0x01
302 #define LM49453_JACK_CONFIG2 306 #define LM49453_JACK_CONFIG2 0x02
303 #define LM49453_JACK_CONFIG3 307 #define LM49453_JACK_CONFIG3 0x03
304 #define LM49453_JACK_CONFIG4 308 #define LM49453_JACK_CONFIG4 0x04
305 #define LM49453_JACK_CONFIG5 309 #define LM49453_JACK_CONFIG5 0x05
306 310
307 /* Page 1 REGISTERS */ 311 /* Page 1 REGISTERS */
308 312
309 /* SIDETONE */ 313 /* SIDETONE */
310 #define LM49453_P1_SIDETONE_SA0L_REG 314 #define LM49453_P1_SIDETONE_SA0L_REG 0x80
311 #define LM49453_P1_SIDETONE_SA0H_REG 315 #define LM49453_P1_SIDETONE_SA0H_REG 0x81
312 #define LM49453_P1_SIDETONE_SAB0U_REG 316 #define LM49453_P1_SIDETONE_SAB0U_REG 0x82
313 #define LM49453_P1_SIDETONE_SB0L_REG 317 #define LM49453_P1_SIDETONE_SB0L_REG 0x83
314 #define LM49453_P1_SIDETONE_SB0H_REG 318 #define LM49453_P1_SIDETONE_SB0H_REG 0x84
315 #define LM49453_P1_SIDETONE_SH0L_REG 319 #define LM49453_P1_SIDETONE_SH0L_REG 0x85
316 #define LM49453_P1_SIDETONE_SH0H_REG 320 #define LM49453_P1_SIDETONE_SH0H_REG 0x86
317 #define LM49453_P1_SIDETONE_SH0U_REG 321 #define LM49453_P1_SIDETONE_SH0U_REG 0x87
318 #define LM49453_P1_SIDETONE_SA1L_REG 322 #define LM49453_P1_SIDETONE_SA1L_REG 0x88
319 #define LM49453_P1_SIDETONE_SA1H_REG 323 #define LM49453_P1_SIDETONE_SA1H_REG 0x89
320 #define LM49453_P1_SIDETONE_SAB1U_REG 324 #define LM49453_P1_SIDETONE_SAB1U_REG 0x8A
321 #define LM49453_P1_SIDETONE_SB1L_REG 325 #define LM49453_P1_SIDETONE_SB1L_REG 0x8B
322 #define LM49453_P1_SIDETONE_SB1H_REG 326 #define LM49453_P1_SIDETONE_SB1H_REG 0x8C
323 #define LM49453_P1_SIDETONE_SH1L_REG 327 #define LM49453_P1_SIDETONE_SH1L_REG 0x8D
324 #define LM49453_P1_SIDETONE_SH1H_REG 328 #define LM49453_P1_SIDETONE_SH1H_REG 0x8E
325 #define LM49453_P1_SIDETONE_SH1U_REG 329 #define LM49453_P1_SIDETONE_SH1U_REG 0x8F
326 #define LM49453_P1_SIDETONE_SA2L_REG 330 #define LM49453_P1_SIDETONE_SA2L_REG 0x90
327 #define LM49453_P1_SIDETONE_SA2H_REG 331 #define LM49453_P1_SIDETONE_SA2H_REG 0x91
328 #define LM49453_P1_SIDETONE_SAB2U_REG 332 #define LM49453_P1_SIDETONE_SAB2U_REG 0x92
329 #define LM49453_P1_SIDETONE_SB2L_REG 333 #define LM49453_P1_SIDETONE_SB2L_REG 0x93
330 #define LM49453_P1_SIDETONE_SB2H_REG 334 #define LM49453_P1_SIDETONE_SB2H_REG 0x94
331 #define LM49453_P1_SIDETONE_SH2L_REG 335 #define LM49453_P1_SIDETONE_SH2L_REG 0x95
332 #define LM49453_P1_SIDETONE_SH2H_REG 336 #define LM49453_P1_SIDETONE_SH2H_REG 0x96
333 #define LM49453_P1_SIDETONE_SH2U_REG 337 #define LM49453_P1_SIDETONE_SH2U_REG 0x97
334 #define LM49453_P1_SIDETONE_SA3L_REG 338 #define LM49453_P1_SIDETONE_SA3L_REG 0x98
335 #define LM49453_P1_SIDETONE_SA3H_REG 339 #define LM49453_P1_SIDETONE_SA3H_REG 0x99
336 #define LM49453_P1_SIDETONE_SAB3U_REG 340 #define LM49453_P1_SIDETONE_SAB3U_REG 0x9A
337 #define LM49453_P1_SIDETONE_SB3L_REG 341 #define LM49453_P1_SIDETONE_SB3L_REG 0x9B
338 #define LM49453_P1_SIDETONE_SB3H_REG 342 #define LM49453_P1_SIDETONE_SB3H_REG 0x9C
339 #define LM49453_P1_SIDETONE_SH3L_REG 343 #define LM49453_P1_SIDETONE_SH3L_REG 0x9D
340 #define LM49453_P1_SIDETONE_SH3H_REG 344 #define LM49453_P1_SIDETONE_SH3H_REG 0x9E
341 #define LM49453_P1_SIDETONE_SH3U_REG 345 #define LM49453_P1_SIDETONE_SH3U_REG 0x9F
342 #define LM49453_P1_SIDETONE_SA4L_REG 346 #define LM49453_P1_SIDETONE_SA4L_REG 0xA0
343 #define LM49453_P1_SIDETONE_SA4H_REG 347 #define LM49453_P1_SIDETONE_SA4H_REG 0xA1
344 #define LM49453_P1_SIDETONE_SAB4U_REG 348 #define LM49453_P1_SIDETONE_SAB4U_REG 0xA2
345 #define LM49453_P1_SIDETONE_SB4L_REG 349 #define LM49453_P1_SIDETONE_SB4L_REG 0xA3
346 #define LM49453_P1_SIDETONE_SB4H_REG 350 #define LM49453_P1_SIDETONE_SB4H_REG 0xA4
347 #define LM49453_P1_SIDETONE_SH4L_REG 351 #define LM49453_P1_SIDETONE_SH4L_REG 0xA5
348 #define LM49453_P1_SIDETONE_SH4H_REG 352 #define LM49453_P1_SIDETONE_SH4H_REG 0xA6
349 #define LM49453_P1_SIDETONE_SH4U_REG 353 #define LM49453_P1_SIDETONE_SH4U_REG 0xA7
350 #define LM49453_P1_SIDETONE_SA5L_REG 354 #define LM49453_P1_SIDETONE_SA5L_REG 0xA8
351 #define LM49453_P1_SIDETONE_SA5H_REG 355 #define LM49453_P1_SIDETONE_SA5H_REG 0xA9
352 #define LM49453_P1_SIDETONE_SAB5U_REG 356 #define LM49453_P1_SIDETONE_SAB5U_REG 0xAA
353 #define LM49453_P1_SIDETONE_SB5L_REG 357 #define LM49453_P1_SIDETONE_SB5L_REG 0xAB
354 #define LM49453_P1_SIDETONE_SB5H_REG 358 #define LM49453_P1_SIDETONE_SB5H_REG 0xAC
355 #define LM49453_P1_SIDETONE_SH5L_REG 359 #define LM49453_P1_SIDETONE_SH5L_REG 0xAD
356 #define LM49453_P1_SIDETONE_SH5H_REG 360 #define LM49453_P1_SIDETONE_SH5H_REG 0xAE
357 #define LM49453_P1_SIDETONE_SH5U_REG 361 #define LM49453_P1_SIDETONE_SH5U_REG 0xAF
358 362
359 /* CHARGE PUMP CONFIG */ 363 /* CHARGE PUMP CONFIG */
360 #define LM49453_P1_CP_CONFIG1_REG 364 #define LM49453_P1_CP_CONFIG1_REG 0xB0
361 #define LM49453_P1_CP_CONFIG2_REG 365 #define LM49453_P1_CP_CONFIG2_REG 0xB1
362 #define LM49453_P1_CP_CONFIG3_REG 366 #define LM49453_P1_CP_CONFIG3_REG 0xB2
363 #define LM49453_P1_CP_CONFIG4_REG 367 #define LM49453_P1_CP_CONFIG4_REG 0xB3
364 #define LM49453_P1_CP_LA_VTH1L_REG 368 #define LM49453_P1_CP_LA_VTH1L_REG 0xB4
365 #define LM49453_P1_CP_LA_VTH1M_REG 369 #define LM49453_P1_CP_LA_VTH1M_REG 0xB5
366 #define LM49453_P1_CP_LA_VTH2L_REG 370 #define LM49453_P1_CP_LA_VTH2L_REG 0xB6
367 #define LM49453_P1_CP_LA_VTH2M_REG 371 #define LM49453_P1_CP_LA_VTH2M_REG 0xB7
368 #define LM49453_P1_CP_LA_VTH3L_REG 372 #define LM49453_P1_CP_LA_VTH3L_REG 0xB8
369 #define LM49453_P1_CP_LA_VTH3H_REG 373 #define LM49453_P1_CP_LA_VTH3H_REG 0xB9
370 #define LM49453_P1_CP_CLK_DIV_REG 374 #define LM49453_P1_CP_CLK_DIV_REG 0xBA
371 375
372 /* DAC */ 376 /* DAC */
373 #define LM49453_P1_DAC_CHOP_REG 377 #define LM49453_P1_DAC_CHOP_REG 0xC0
374 378
375 #define LM49453_CLK_SRC_MCLK 379 #define LM49453_CLK_SRC_MCLK 1
376 #endif 380 #endif
377 381
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