1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2018-2020, The Linux Foundati 2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
3 3
4 #include <linux/clk.h> 4 #include <linux/clk.h>
5 #include <linux/clk-provider.h> 5 #include <linux/clk-provider.h>
6 #include <linux/init.h> 6 #include <linux/init.h>
7 #include <linux/io.h> 7 #include <linux/io.h>
8 #include <linux/module.h> 8 #include <linux/module.h>
9 #include <linux/of_clk.h> 9 #include <linux/of_clk.h>
10 #include <linux/of_platform.h> 10 #include <linux/of_platform.h>
11 #include <linux/platform_device.h> 11 #include <linux/platform_device.h>
12 #include <linux/pm_runtime.h> 12 #include <linux/pm_runtime.h>
13 #include <linux/regmap.h> 13 #include <linux/regmap.h>
14 #include <linux/regulator/consumer.h> 14 #include <linux/regulator/consumer.h>
15 #include <sound/soc.h> 15 #include <sound/soc.h>
16 #include <sound/soc-dapm.h> 16 #include <sound/soc-dapm.h>
17 #include <sound/tlv.h> 17 #include <sound/tlv.h>
18 18
19 #include "lpass-macro-common.h" 19 #include "lpass-macro-common.h"
20 20
21 /* VA macro registers */ 21 /* VA macro registers */
22 #define CDC_VA_CLK_RST_CTRL_MCLK_CONTROL 22 #define CDC_VA_CLK_RST_CTRL_MCLK_CONTROL (0x0000)
23 #define CDC_VA_MCLK_CONTROL_EN 23 #define CDC_VA_MCLK_CONTROL_EN BIT(0)
24 #define CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL 24 #define CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004)
25 #define CDC_VA_FS_CONTROL_EN 25 #define CDC_VA_FS_CONTROL_EN BIT(0)
26 #define CDC_VA_FS_COUNTER_CLR <<
27 #define CDC_VA_CLK_RST_CTRL_SWR_CONTROL 26 #define CDC_VA_CLK_RST_CTRL_SWR_CONTROL (0x0008)
28 #define CDC_VA_SWR_RESET_MASK BIT(1) <<
29 #define CDC_VA_SWR_RESET_ENABLE BIT(1) <<
30 #define CDC_VA_SWR_CLK_EN_MASK BIT(0) <<
31 #define CDC_VA_SWR_CLK_ENABLE BIT(0) <<
32 #define CDC_VA_TOP_CSR_TOP_CFG0 27 #define CDC_VA_TOP_CSR_TOP_CFG0 (0x0080)
33 #define CDC_VA_FS_BROADCAST_EN 28 #define CDC_VA_FS_BROADCAST_EN BIT(1)
34 #define CDC_VA_TOP_CSR_DMIC0_CTL 29 #define CDC_VA_TOP_CSR_DMIC0_CTL (0x0084)
35 #define CDC_VA_TOP_CSR_DMIC1_CTL 30 #define CDC_VA_TOP_CSR_DMIC1_CTL (0x0088)
36 #define CDC_VA_TOP_CSR_DMIC2_CTL 31 #define CDC_VA_TOP_CSR_DMIC2_CTL (0x008C)
37 #define CDC_VA_TOP_CSR_DMIC3_CTL 32 #define CDC_VA_TOP_CSR_DMIC3_CTL (0x0090)
38 #define CDC_VA_DMIC_EN_MASK 33 #define CDC_VA_DMIC_EN_MASK BIT(0)
39 #define CDC_VA_DMIC_ENABLE 34 #define CDC_VA_DMIC_ENABLE BIT(0)
40 #define CDC_VA_DMIC_CLK_SEL_MASK 35 #define CDC_VA_DMIC_CLK_SEL_MASK GENMASK(3, 1)
41 #define CDC_VA_DMIC_CLK_SEL_SHFT 36 #define CDC_VA_DMIC_CLK_SEL_SHFT 1
42 #define CDC_VA_DMIC_CLK_SEL_DIV0 37 #define CDC_VA_DMIC_CLK_SEL_DIV0 0x0
43 #define CDC_VA_DMIC_CLK_SEL_DIV1 38 #define CDC_VA_DMIC_CLK_SEL_DIV1 0x2
44 #define CDC_VA_DMIC_CLK_SEL_DIV2 39 #define CDC_VA_DMIC_CLK_SEL_DIV2 0x4
45 #define CDC_VA_DMIC_CLK_SEL_DIV3 40 #define CDC_VA_DMIC_CLK_SEL_DIV3 0x6
46 #define CDC_VA_DMIC_CLK_SEL_DIV4 41 #define CDC_VA_DMIC_CLK_SEL_DIV4 0x8
47 #define CDC_VA_DMIC_CLK_SEL_DIV5 42 #define CDC_VA_DMIC_CLK_SEL_DIV5 0xa
48 #define CDC_VA_TOP_CSR_DMIC_CFG 43 #define CDC_VA_TOP_CSR_DMIC_CFG (0x0094)
49 #define CDC_VA_RESET_ALL_DMICS_MASK 44 #define CDC_VA_RESET_ALL_DMICS_MASK BIT(7)
50 #define CDC_VA_RESET_ALL_DMICS_RESET 45 #define CDC_VA_RESET_ALL_DMICS_RESET BIT(7)
51 #define CDC_VA_RESET_ALL_DMICS_DISABLE 46 #define CDC_VA_RESET_ALL_DMICS_DISABLE 0
52 #define CDC_VA_DMIC3_FREQ_CHANGE_MASK 47 #define CDC_VA_DMIC3_FREQ_CHANGE_MASK BIT(3)
53 #define CDC_VA_DMIC3_FREQ_CHANGE_EN 48 #define CDC_VA_DMIC3_FREQ_CHANGE_EN BIT(3)
54 #define CDC_VA_DMIC2_FREQ_CHANGE_MASK 49 #define CDC_VA_DMIC2_FREQ_CHANGE_MASK BIT(2)
55 #define CDC_VA_DMIC2_FREQ_CHANGE_EN 50 #define CDC_VA_DMIC2_FREQ_CHANGE_EN BIT(2)
56 #define CDC_VA_DMIC1_FREQ_CHANGE_MASK 51 #define CDC_VA_DMIC1_FREQ_CHANGE_MASK BIT(1)
57 #define CDC_VA_DMIC1_FREQ_CHANGE_EN 52 #define CDC_VA_DMIC1_FREQ_CHANGE_EN BIT(1)
58 #define CDC_VA_DMIC0_FREQ_CHANGE_MASK 53 #define CDC_VA_DMIC0_FREQ_CHANGE_MASK BIT(0)
59 #define CDC_VA_DMIC0_FREQ_CHANGE_EN 54 #define CDC_VA_DMIC0_FREQ_CHANGE_EN BIT(0)
60 #define CDC_VA_DMIC_FREQ_CHANGE_DISABLE 55 #define CDC_VA_DMIC_FREQ_CHANGE_DISABLE 0
61 #define CDC_VA_TOP_CSR_DEBUG_BUS 56 #define CDC_VA_TOP_CSR_DEBUG_BUS (0x009C)
62 #define CDC_VA_TOP_CSR_DEBUG_EN 57 #define CDC_VA_TOP_CSR_DEBUG_EN (0x00A0)
63 #define CDC_VA_TOP_CSR_TX_I2S_CTL 58 #define CDC_VA_TOP_CSR_TX_I2S_CTL (0x00A4)
64 #define CDC_VA_TOP_CSR_I2S_CLK 59 #define CDC_VA_TOP_CSR_I2S_CLK (0x00A8)
65 #define CDC_VA_TOP_CSR_I2S_RESET 60 #define CDC_VA_TOP_CSR_I2S_RESET (0x00AC)
66 #define CDC_VA_TOP_CSR_CORE_ID_0 61 #define CDC_VA_TOP_CSR_CORE_ID_0 (0x00C0)
67 #define CDC_VA_TOP_CSR_CORE_ID_1 62 #define CDC_VA_TOP_CSR_CORE_ID_1 (0x00C4)
68 #define CDC_VA_TOP_CSR_CORE_ID_2 63 #define CDC_VA_TOP_CSR_CORE_ID_2 (0x00C8)
69 #define CDC_VA_TOP_CSR_CORE_ID_3 64 #define CDC_VA_TOP_CSR_CORE_ID_3 (0x00CC)
70 #define CDC_VA_TOP_CSR_SWR_MIC_CTL0 65 #define CDC_VA_TOP_CSR_SWR_MIC_CTL0 (0x00D0)
71 #define CDC_VA_TOP_CSR_SWR_MIC_CTL1 66 #define CDC_VA_TOP_CSR_SWR_MIC_CTL1 (0x00D4)
72 #define CDC_VA_TOP_CSR_SWR_MIC_CTL2 67 #define CDC_VA_TOP_CSR_SWR_MIC_CTL2 (0x00D8)
73 #define CDC_VA_SWR_MIC_CLK_SEL_0_1_MASK <<
74 #define CDC_VA_SWR_MIC_CLK_SEL_0_1_DIV1 <<
75 #define CDC_VA_TOP_CSR_SWR_CTRL 68 #define CDC_VA_TOP_CSR_SWR_CTRL (0x00DC)
76 #define CDC_VA_INP_MUX_ADC_MUX0_CFG0 69 #define CDC_VA_INP_MUX_ADC_MUX0_CFG0 (0x0100)
77 #define CDC_VA_INP_MUX_ADC_MUX0_CFG1 70 #define CDC_VA_INP_MUX_ADC_MUX0_CFG1 (0x0104)
78 #define CDC_VA_INP_MUX_ADC_MUX1_CFG0 71 #define CDC_VA_INP_MUX_ADC_MUX1_CFG0 (0x0108)
79 #define CDC_VA_INP_MUX_ADC_MUX1_CFG1 72 #define CDC_VA_INP_MUX_ADC_MUX1_CFG1 (0x010C)
80 #define CDC_VA_INP_MUX_ADC_MUX2_CFG0 73 #define CDC_VA_INP_MUX_ADC_MUX2_CFG0 (0x0110)
81 #define CDC_VA_INP_MUX_ADC_MUX2_CFG1 74 #define CDC_VA_INP_MUX_ADC_MUX2_CFG1 (0x0114)
82 #define CDC_VA_INP_MUX_ADC_MUX3_CFG0 75 #define CDC_VA_INP_MUX_ADC_MUX3_CFG0 (0x0118)
83 #define CDC_VA_INP_MUX_ADC_MUX3_CFG1 76 #define CDC_VA_INP_MUX_ADC_MUX3_CFG1 (0x011C)
84 #define CDC_VA_TX0_TX_PATH_CTL 77 #define CDC_VA_TX0_TX_PATH_CTL (0x0400)
85 #define CDC_VA_TX_PATH_CLK_EN_MASK 78 #define CDC_VA_TX_PATH_CLK_EN_MASK BIT(5)
86 #define CDC_VA_TX_PATH_CLK_EN 79 #define CDC_VA_TX_PATH_CLK_EN BIT(5)
87 #define CDC_VA_TX_PATH_CLK_DISABLE 80 #define CDC_VA_TX_PATH_CLK_DISABLE 0
88 #define CDC_VA_TX_PATH_PGA_MUTE_EN_MASK 81 #define CDC_VA_TX_PATH_PGA_MUTE_EN_MASK BIT(4)
89 #define CDC_VA_TX_PATH_PGA_MUTE_EN 82 #define CDC_VA_TX_PATH_PGA_MUTE_EN BIT(4)
90 #define CDC_VA_TX_PATH_PGA_MUTE_DISABLE 83 #define CDC_VA_TX_PATH_PGA_MUTE_DISABLE 0
91 #define CDC_VA_TX0_TX_PATH_CFG0 84 #define CDC_VA_TX0_TX_PATH_CFG0 (0x0404)
92 #define CDC_VA_ADC_MODE_MASK 85 #define CDC_VA_ADC_MODE_MASK GENMASK(2, 1)
93 #define CDC_VA_ADC_MODE_SHIFT 86 #define CDC_VA_ADC_MODE_SHIFT 1
94 #define TX_HPF_CUT_OFF_FREQ_MASK 87 #define TX_HPF_CUT_OFF_FREQ_MASK GENMASK(6, 5)
95 #define CF_MIN_3DB_4HZ 0x0 88 #define CF_MIN_3DB_4HZ 0x0
96 #define CF_MIN_3DB_75HZ 0x1 89 #define CF_MIN_3DB_75HZ 0x1
97 #define CF_MIN_3DB_150HZ 0x2 90 #define CF_MIN_3DB_150HZ 0x2
98 #define CDC_VA_TX0_TX_PATH_CFG1 91 #define CDC_VA_TX0_TX_PATH_CFG1 (0x0408)
99 #define CDC_VA_TX0_TX_VOL_CTL 92 #define CDC_VA_TX0_TX_VOL_CTL (0x040C)
100 #define CDC_VA_TX0_TX_PATH_SEC0 93 #define CDC_VA_TX0_TX_PATH_SEC0 (0x0410)
101 #define CDC_VA_TX0_TX_PATH_SEC1 94 #define CDC_VA_TX0_TX_PATH_SEC1 (0x0414)
102 #define CDC_VA_TX0_TX_PATH_SEC2 95 #define CDC_VA_TX0_TX_PATH_SEC2 (0x0418)
103 #define CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK 96 #define CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK BIT(1)
104 #define CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_REQ 97 #define CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_REQ BIT(1)
105 #define CDC_VA_TX_HPF_ZERO_GATE_MASK 98 #define CDC_VA_TX_HPF_ZERO_GATE_MASK BIT(0)
106 #define CDC_VA_TX_HPF_ZERO_NO_GATE 99 #define CDC_VA_TX_HPF_ZERO_NO_GATE BIT(0)
107 #define CDC_VA_TX_HPF_ZERO_GATE 100 #define CDC_VA_TX_HPF_ZERO_GATE 0
108 #define CDC_VA_TX0_TX_PATH_SEC3 101 #define CDC_VA_TX0_TX_PATH_SEC3 (0x041C)
109 #define CDC_VA_TX0_TX_PATH_SEC4 102 #define CDC_VA_TX0_TX_PATH_SEC4 (0x0420)
110 #define CDC_VA_TX0_TX_PATH_SEC5 103 #define CDC_VA_TX0_TX_PATH_SEC5 (0x0424)
111 #define CDC_VA_TX0_TX_PATH_SEC6 104 #define CDC_VA_TX0_TX_PATH_SEC6 (0x0428)
112 #define CDC_VA_TX0_TX_PATH_SEC7 105 #define CDC_VA_TX0_TX_PATH_SEC7 (0x042C)
113 #define CDC_VA_TX1_TX_PATH_CTL 106 #define CDC_VA_TX1_TX_PATH_CTL (0x0480)
114 #define CDC_VA_TX1_TX_PATH_CFG0 107 #define CDC_VA_TX1_TX_PATH_CFG0 (0x0484)
115 #define CDC_VA_TX1_TX_PATH_CFG1 108 #define CDC_VA_TX1_TX_PATH_CFG1 (0x0488)
116 #define CDC_VA_TX1_TX_VOL_CTL 109 #define CDC_VA_TX1_TX_VOL_CTL (0x048C)
117 #define CDC_VA_TX1_TX_PATH_SEC0 110 #define CDC_VA_TX1_TX_PATH_SEC0 (0x0490)
118 #define CDC_VA_TX1_TX_PATH_SEC1 111 #define CDC_VA_TX1_TX_PATH_SEC1 (0x0494)
119 #define CDC_VA_TX1_TX_PATH_SEC2 112 #define CDC_VA_TX1_TX_PATH_SEC2 (0x0498)
120 #define CDC_VA_TX1_TX_PATH_SEC3 113 #define CDC_VA_TX1_TX_PATH_SEC3 (0x049C)
121 #define CDC_VA_TX1_TX_PATH_SEC4 114 #define CDC_VA_TX1_TX_PATH_SEC4 (0x04A0)
122 #define CDC_VA_TX1_TX_PATH_SEC5 115 #define CDC_VA_TX1_TX_PATH_SEC5 (0x04A4)
123 #define CDC_VA_TX1_TX_PATH_SEC6 116 #define CDC_VA_TX1_TX_PATH_SEC6 (0x04A8)
124 #define CDC_VA_TX2_TX_PATH_CTL 117 #define CDC_VA_TX2_TX_PATH_CTL (0x0500)
125 #define CDC_VA_TX2_TX_PATH_CFG0 118 #define CDC_VA_TX2_TX_PATH_CFG0 (0x0504)
126 #define CDC_VA_TX2_TX_PATH_CFG1 119 #define CDC_VA_TX2_TX_PATH_CFG1 (0x0508)
127 #define CDC_VA_TX2_TX_VOL_CTL 120 #define CDC_VA_TX2_TX_VOL_CTL (0x050C)
128 #define CDC_VA_TX2_TX_PATH_SEC0 121 #define CDC_VA_TX2_TX_PATH_SEC0 (0x0510)
129 #define CDC_VA_TX2_TX_PATH_SEC1 122 #define CDC_VA_TX2_TX_PATH_SEC1 (0x0514)
130 #define CDC_VA_TX2_TX_PATH_SEC2 123 #define CDC_VA_TX2_TX_PATH_SEC2 (0x0518)
131 #define CDC_VA_TX2_TX_PATH_SEC3 124 #define CDC_VA_TX2_TX_PATH_SEC3 (0x051C)
132 #define CDC_VA_TX2_TX_PATH_SEC4 125 #define CDC_VA_TX2_TX_PATH_SEC4 (0x0520)
133 #define CDC_VA_TX2_TX_PATH_SEC5 126 #define CDC_VA_TX2_TX_PATH_SEC5 (0x0524)
134 #define CDC_VA_TX2_TX_PATH_SEC6 127 #define CDC_VA_TX2_TX_PATH_SEC6 (0x0528)
135 #define CDC_VA_TX3_TX_PATH_CTL 128 #define CDC_VA_TX3_TX_PATH_CTL (0x0580)
136 #define CDC_VA_TX3_TX_PATH_CFG0 129 #define CDC_VA_TX3_TX_PATH_CFG0 (0x0584)
137 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK 130 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK BIT(7)
138 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC 131 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC BIT(7)
139 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_ADC 132 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_ADC 0
140 #define CDC_VA_TX3_TX_PATH_CFG1 133 #define CDC_VA_TX3_TX_PATH_CFG1 (0x0588)
141 #define CDC_VA_TX3_TX_VOL_CTL 134 #define CDC_VA_TX3_TX_VOL_CTL (0x058C)
142 #define CDC_VA_TX3_TX_PATH_SEC0 135 #define CDC_VA_TX3_TX_PATH_SEC0 (0x0590)
143 #define CDC_VA_TX3_TX_PATH_SEC1 136 #define CDC_VA_TX3_TX_PATH_SEC1 (0x0594)
144 #define CDC_VA_TX3_TX_PATH_SEC2 137 #define CDC_VA_TX3_TX_PATH_SEC2 (0x0598)
145 #define CDC_VA_TX3_TX_PATH_SEC3 138 #define CDC_VA_TX3_TX_PATH_SEC3 (0x059C)
146 #define CDC_VA_TX3_TX_PATH_SEC4 139 #define CDC_VA_TX3_TX_PATH_SEC4 (0x05A0)
147 #define CDC_VA_TX3_TX_PATH_SEC5 140 #define CDC_VA_TX3_TX_PATH_SEC5 (0x05A4)
148 #define CDC_VA_TX3_TX_PATH_SEC6 141 #define CDC_VA_TX3_TX_PATH_SEC6 (0x05A8)
149 142
150 #define VA_MAX_OFFSET 143 #define VA_MAX_OFFSET (0x07A8)
151 144
152 #define VA_MACRO_NUM_DECIMATORS 4 145 #define VA_MACRO_NUM_DECIMATORS 4
153 #define VA_MACRO_RATES (SNDRV_PCM_RATE_8000 | 146 #define VA_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
154 SNDRV_PCM_RATE_32000 | 147 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
155 SNDRV_PCM_RATE_96000 | 148 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
156 #define VA_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16 149 #define VA_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
157 SNDRV_PCM_FMTBIT_S24_LE |\ 150 SNDRV_PCM_FMTBIT_S24_LE |\
158 SNDRV_PCM_FMTBIT_S24_3LE) 151 SNDRV_PCM_FMTBIT_S24_3LE)
159 152
160 #define VA_MACRO_MCLK_FREQ 9600000 153 #define VA_MACRO_MCLK_FREQ 9600000
161 #define VA_MACRO_TX_PATH_OFFSET 0x80 154 #define VA_MACRO_TX_PATH_OFFSET 0x80
162 #define VA_MACRO_SWR_MIC_MUX_SEL_MASK 0xF 155 #define VA_MACRO_SWR_MIC_MUX_SEL_MASK 0xF
163 #define VA_MACRO_ADC_MUX_CFG_OFFSET 0x8 156 #define VA_MACRO_ADC_MUX_CFG_OFFSET 0x8
164 157
165 static const DECLARE_TLV_DB_SCALE(digital_gain 158 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
166 159
167 enum { 160 enum {
168 VA_MACRO_AIF_INVALID = 0, 161 VA_MACRO_AIF_INVALID = 0,
169 VA_MACRO_AIF1_CAP, 162 VA_MACRO_AIF1_CAP,
170 VA_MACRO_AIF2_CAP, 163 VA_MACRO_AIF2_CAP,
171 VA_MACRO_AIF3_CAP, 164 VA_MACRO_AIF3_CAP,
172 VA_MACRO_MAX_DAIS, 165 VA_MACRO_MAX_DAIS,
173 }; 166 };
174 167
175 enum { 168 enum {
176 VA_MACRO_DEC0, 169 VA_MACRO_DEC0,
177 VA_MACRO_DEC1, 170 VA_MACRO_DEC1,
178 VA_MACRO_DEC2, 171 VA_MACRO_DEC2,
179 VA_MACRO_DEC3, 172 VA_MACRO_DEC3,
180 VA_MACRO_DEC4, 173 VA_MACRO_DEC4,
181 VA_MACRO_DEC5, 174 VA_MACRO_DEC5,
182 VA_MACRO_DEC6, 175 VA_MACRO_DEC6,
183 VA_MACRO_DEC7, 176 VA_MACRO_DEC7,
184 VA_MACRO_DEC_MAX, 177 VA_MACRO_DEC_MAX,
185 }; 178 };
186 179
187 enum { 180 enum {
188 VA_MACRO_CLK_DIV_2, 181 VA_MACRO_CLK_DIV_2,
189 VA_MACRO_CLK_DIV_3, 182 VA_MACRO_CLK_DIV_3,
190 VA_MACRO_CLK_DIV_4, 183 VA_MACRO_CLK_DIV_4,
191 VA_MACRO_CLK_DIV_6, 184 VA_MACRO_CLK_DIV_6,
192 VA_MACRO_CLK_DIV_8, 185 VA_MACRO_CLK_DIV_8,
193 VA_MACRO_CLK_DIV_16, 186 VA_MACRO_CLK_DIV_16,
194 }; 187 };
195 188
196 #define VA_NUM_CLKS_MAX 3 189 #define VA_NUM_CLKS_MAX 3
197 190
198 struct va_macro { 191 struct va_macro {
199 struct device *dev; 192 struct device *dev;
200 unsigned long active_ch_mask[VA_MACRO_ 193 unsigned long active_ch_mask[VA_MACRO_MAX_DAIS];
201 unsigned long active_ch_cnt[VA_MACRO_M 194 unsigned long active_ch_cnt[VA_MACRO_MAX_DAIS];
202 u16 dmic_clk_div; 195 u16 dmic_clk_div;
203 bool has_swr_master; <<
204 bool has_npl_clk; <<
205 196
206 int dec_mode[VA_MACRO_NUM_DECIMATORS]; 197 int dec_mode[VA_MACRO_NUM_DECIMATORS];
207 struct regmap *regmap; 198 struct regmap *regmap;
208 struct clk *mclk; 199 struct clk *mclk;
209 struct clk *npl; <<
210 struct clk *macro; 200 struct clk *macro;
211 struct clk *dcodec; 201 struct clk *dcodec;
212 struct clk *fsgen; <<
213 struct clk_hw hw; 202 struct clk_hw hw;
214 struct lpass_macro *pds; 203 struct lpass_macro *pds;
215 204
216 s32 dmic_0_1_clk_cnt; 205 s32 dmic_0_1_clk_cnt;
217 s32 dmic_2_3_clk_cnt; 206 s32 dmic_2_3_clk_cnt;
218 s32 dmic_4_5_clk_cnt; 207 s32 dmic_4_5_clk_cnt;
219 s32 dmic_6_7_clk_cnt; 208 s32 dmic_6_7_clk_cnt;
220 u8 dmic_0_1_clk_div; 209 u8 dmic_0_1_clk_div;
221 u8 dmic_2_3_clk_div; 210 u8 dmic_2_3_clk_div;
222 u8 dmic_4_5_clk_div; 211 u8 dmic_4_5_clk_div;
223 u8 dmic_6_7_clk_div; 212 u8 dmic_6_7_clk_div;
224 }; 213 };
225 214
226 #define to_va_macro(_hw) container_of(_hw, str 215 #define to_va_macro(_hw) container_of(_hw, struct va_macro, hw)
227 216
228 struct va_macro_data { <<
229 bool has_swr_master; <<
230 bool has_npl_clk; <<
231 int version; <<
232 }; <<
233 <<
234 static const struct va_macro_data sm8250_va_da <<
235 .has_swr_master = false, <<
236 .has_npl_clk = false, <<
237 .version = LPASS_CODEC_VERSION_1_0, <<
238 }; <<
239 <<
240 static const struct va_macro_data sm8450_va_da <<
241 .has_swr_master = true, <<
242 .has_npl_clk = true, <<
243 }; <<
244 <<
245 static const struct va_macro_data sm8550_va_da <<
246 .has_swr_master = true, <<
247 .has_npl_clk = false, <<
248 }; <<
249 <<
250 static bool va_is_volatile_register(struct dev 217 static bool va_is_volatile_register(struct device *dev, unsigned int reg)
251 { 218 {
252 switch (reg) { 219 switch (reg) {
253 case CDC_VA_TOP_CSR_CORE_ID_0: 220 case CDC_VA_TOP_CSR_CORE_ID_0:
254 case CDC_VA_TOP_CSR_CORE_ID_1: 221 case CDC_VA_TOP_CSR_CORE_ID_1:
255 case CDC_VA_TOP_CSR_CORE_ID_2: 222 case CDC_VA_TOP_CSR_CORE_ID_2:
256 case CDC_VA_TOP_CSR_CORE_ID_3: 223 case CDC_VA_TOP_CSR_CORE_ID_3:
257 case CDC_VA_TOP_CSR_DMIC0_CTL: 224 case CDC_VA_TOP_CSR_DMIC0_CTL:
258 case CDC_VA_TOP_CSR_DMIC1_CTL: 225 case CDC_VA_TOP_CSR_DMIC1_CTL:
259 case CDC_VA_TOP_CSR_DMIC2_CTL: 226 case CDC_VA_TOP_CSR_DMIC2_CTL:
260 case CDC_VA_TOP_CSR_DMIC3_CTL: 227 case CDC_VA_TOP_CSR_DMIC3_CTL:
261 return true; 228 return true;
262 } 229 }
263 return false; 230 return false;
264 } 231 }
265 232
266 static const struct reg_default va_defaults[] 233 static const struct reg_default va_defaults[] = {
267 /* VA macro */ 234 /* VA macro */
268 { CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x 235 { CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
269 { CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 236 { CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00},
270 { CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 0x0 237 { CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 0x00},
271 { CDC_VA_TOP_CSR_TOP_CFG0, 0x00}, 238 { CDC_VA_TOP_CSR_TOP_CFG0, 0x00},
272 { CDC_VA_TOP_CSR_DMIC0_CTL, 0x00}, 239 { CDC_VA_TOP_CSR_DMIC0_CTL, 0x00},
273 { CDC_VA_TOP_CSR_DMIC1_CTL, 0x00}, 240 { CDC_VA_TOP_CSR_DMIC1_CTL, 0x00},
274 { CDC_VA_TOP_CSR_DMIC2_CTL, 0x00}, 241 { CDC_VA_TOP_CSR_DMIC2_CTL, 0x00},
275 { CDC_VA_TOP_CSR_DMIC3_CTL, 0x00}, 242 { CDC_VA_TOP_CSR_DMIC3_CTL, 0x00},
276 { CDC_VA_TOP_CSR_DMIC_CFG, 0x80}, 243 { CDC_VA_TOP_CSR_DMIC_CFG, 0x80},
277 { CDC_VA_TOP_CSR_DEBUG_BUS, 0x00}, 244 { CDC_VA_TOP_CSR_DEBUG_BUS, 0x00},
278 { CDC_VA_TOP_CSR_DEBUG_EN, 0x00}, 245 { CDC_VA_TOP_CSR_DEBUG_EN, 0x00},
279 { CDC_VA_TOP_CSR_TX_I2S_CTL, 0x0C}, 246 { CDC_VA_TOP_CSR_TX_I2S_CTL, 0x0C},
280 { CDC_VA_TOP_CSR_I2S_CLK, 0x00}, 247 { CDC_VA_TOP_CSR_I2S_CLK, 0x00},
281 { CDC_VA_TOP_CSR_I2S_RESET, 0x00}, 248 { CDC_VA_TOP_CSR_I2S_RESET, 0x00},
282 { CDC_VA_TOP_CSR_CORE_ID_0, 0x00}, 249 { CDC_VA_TOP_CSR_CORE_ID_0, 0x00},
283 { CDC_VA_TOP_CSR_CORE_ID_1, 0x00}, 250 { CDC_VA_TOP_CSR_CORE_ID_1, 0x00},
284 { CDC_VA_TOP_CSR_CORE_ID_2, 0x00}, 251 { CDC_VA_TOP_CSR_CORE_ID_2, 0x00},
285 { CDC_VA_TOP_CSR_CORE_ID_3, 0x00}, 252 { CDC_VA_TOP_CSR_CORE_ID_3, 0x00},
286 { CDC_VA_TOP_CSR_SWR_MIC_CTL0, 0xEE}, 253 { CDC_VA_TOP_CSR_SWR_MIC_CTL0, 0xEE},
287 { CDC_VA_TOP_CSR_SWR_MIC_CTL1, 0xEE}, 254 { CDC_VA_TOP_CSR_SWR_MIC_CTL1, 0xEE},
288 { CDC_VA_TOP_CSR_SWR_MIC_CTL2, 0xEE}, 255 { CDC_VA_TOP_CSR_SWR_MIC_CTL2, 0xEE},
289 { CDC_VA_TOP_CSR_SWR_CTRL, 0x06}, 256 { CDC_VA_TOP_CSR_SWR_CTRL, 0x06},
290 257
291 /* VA core */ 258 /* VA core */
292 { CDC_VA_INP_MUX_ADC_MUX0_CFG0, 0x00}, 259 { CDC_VA_INP_MUX_ADC_MUX0_CFG0, 0x00},
293 { CDC_VA_INP_MUX_ADC_MUX0_CFG1, 0x00}, 260 { CDC_VA_INP_MUX_ADC_MUX0_CFG1, 0x00},
294 { CDC_VA_INP_MUX_ADC_MUX1_CFG0, 0x00}, 261 { CDC_VA_INP_MUX_ADC_MUX1_CFG0, 0x00},
295 { CDC_VA_INP_MUX_ADC_MUX1_CFG1, 0x00}, 262 { CDC_VA_INP_MUX_ADC_MUX1_CFG1, 0x00},
296 { CDC_VA_INP_MUX_ADC_MUX2_CFG0, 0x00}, 263 { CDC_VA_INP_MUX_ADC_MUX2_CFG0, 0x00},
297 { CDC_VA_INP_MUX_ADC_MUX2_CFG1, 0x00}, 264 { CDC_VA_INP_MUX_ADC_MUX2_CFG1, 0x00},
298 { CDC_VA_INP_MUX_ADC_MUX3_CFG0, 0x00}, 265 { CDC_VA_INP_MUX_ADC_MUX3_CFG0, 0x00},
299 { CDC_VA_INP_MUX_ADC_MUX3_CFG1, 0x00}, 266 { CDC_VA_INP_MUX_ADC_MUX3_CFG1, 0x00},
300 { CDC_VA_TX0_TX_PATH_CTL, 0x04}, 267 { CDC_VA_TX0_TX_PATH_CTL, 0x04},
301 { CDC_VA_TX0_TX_PATH_CFG0, 0x10}, 268 { CDC_VA_TX0_TX_PATH_CFG0, 0x10},
302 { CDC_VA_TX0_TX_PATH_CFG1, 0x0B}, 269 { CDC_VA_TX0_TX_PATH_CFG1, 0x0B},
303 { CDC_VA_TX0_TX_VOL_CTL, 0x00}, 270 { CDC_VA_TX0_TX_VOL_CTL, 0x00},
304 { CDC_VA_TX0_TX_PATH_SEC0, 0x00}, 271 { CDC_VA_TX0_TX_PATH_SEC0, 0x00},
305 { CDC_VA_TX0_TX_PATH_SEC1, 0x00}, 272 { CDC_VA_TX0_TX_PATH_SEC1, 0x00},
306 { CDC_VA_TX0_TX_PATH_SEC2, 0x01}, 273 { CDC_VA_TX0_TX_PATH_SEC2, 0x01},
307 { CDC_VA_TX0_TX_PATH_SEC3, 0x3C}, 274 { CDC_VA_TX0_TX_PATH_SEC3, 0x3C},
308 { CDC_VA_TX0_TX_PATH_SEC4, 0x20}, 275 { CDC_VA_TX0_TX_PATH_SEC4, 0x20},
309 { CDC_VA_TX0_TX_PATH_SEC5, 0x00}, 276 { CDC_VA_TX0_TX_PATH_SEC5, 0x00},
310 { CDC_VA_TX0_TX_PATH_SEC6, 0x00}, 277 { CDC_VA_TX0_TX_PATH_SEC6, 0x00},
311 { CDC_VA_TX0_TX_PATH_SEC7, 0x25}, 278 { CDC_VA_TX0_TX_PATH_SEC7, 0x25},
312 { CDC_VA_TX1_TX_PATH_CTL, 0x04}, 279 { CDC_VA_TX1_TX_PATH_CTL, 0x04},
313 { CDC_VA_TX1_TX_PATH_CFG0, 0x10}, 280 { CDC_VA_TX1_TX_PATH_CFG0, 0x10},
314 { CDC_VA_TX1_TX_PATH_CFG1, 0x0B}, 281 { CDC_VA_TX1_TX_PATH_CFG1, 0x0B},
315 { CDC_VA_TX1_TX_VOL_CTL, 0x00}, 282 { CDC_VA_TX1_TX_VOL_CTL, 0x00},
316 { CDC_VA_TX1_TX_PATH_SEC0, 0x00}, 283 { CDC_VA_TX1_TX_PATH_SEC0, 0x00},
317 { CDC_VA_TX1_TX_PATH_SEC1, 0x00}, 284 { CDC_VA_TX1_TX_PATH_SEC1, 0x00},
318 { CDC_VA_TX1_TX_PATH_SEC2, 0x01}, 285 { CDC_VA_TX1_TX_PATH_SEC2, 0x01},
319 { CDC_VA_TX1_TX_PATH_SEC3, 0x3C}, 286 { CDC_VA_TX1_TX_PATH_SEC3, 0x3C},
320 { CDC_VA_TX1_TX_PATH_SEC4, 0x20}, 287 { CDC_VA_TX1_TX_PATH_SEC4, 0x20},
321 { CDC_VA_TX1_TX_PATH_SEC5, 0x00}, 288 { CDC_VA_TX1_TX_PATH_SEC5, 0x00},
322 { CDC_VA_TX1_TX_PATH_SEC6, 0x00}, 289 { CDC_VA_TX1_TX_PATH_SEC6, 0x00},
323 { CDC_VA_TX2_TX_PATH_CTL, 0x04}, 290 { CDC_VA_TX2_TX_PATH_CTL, 0x04},
324 { CDC_VA_TX2_TX_PATH_CFG0, 0x10}, 291 { CDC_VA_TX2_TX_PATH_CFG0, 0x10},
325 { CDC_VA_TX2_TX_PATH_CFG1, 0x0B}, 292 { CDC_VA_TX2_TX_PATH_CFG1, 0x0B},
326 { CDC_VA_TX2_TX_VOL_CTL, 0x00}, 293 { CDC_VA_TX2_TX_VOL_CTL, 0x00},
327 { CDC_VA_TX2_TX_PATH_SEC0, 0x00}, 294 { CDC_VA_TX2_TX_PATH_SEC0, 0x00},
328 { CDC_VA_TX2_TX_PATH_SEC1, 0x00}, 295 { CDC_VA_TX2_TX_PATH_SEC1, 0x00},
329 { CDC_VA_TX2_TX_PATH_SEC2, 0x01}, 296 { CDC_VA_TX2_TX_PATH_SEC2, 0x01},
330 { CDC_VA_TX2_TX_PATH_SEC3, 0x3C}, 297 { CDC_VA_TX2_TX_PATH_SEC3, 0x3C},
331 { CDC_VA_TX2_TX_PATH_SEC4, 0x20}, 298 { CDC_VA_TX2_TX_PATH_SEC4, 0x20},
332 { CDC_VA_TX2_TX_PATH_SEC5, 0x00}, 299 { CDC_VA_TX2_TX_PATH_SEC5, 0x00},
333 { CDC_VA_TX2_TX_PATH_SEC6, 0x00}, 300 { CDC_VA_TX2_TX_PATH_SEC6, 0x00},
334 { CDC_VA_TX3_TX_PATH_CTL, 0x04}, 301 { CDC_VA_TX3_TX_PATH_CTL, 0x04},
335 { CDC_VA_TX3_TX_PATH_CFG0, 0x10}, 302 { CDC_VA_TX3_TX_PATH_CFG0, 0x10},
336 { CDC_VA_TX3_TX_PATH_CFG1, 0x0B}, 303 { CDC_VA_TX3_TX_PATH_CFG1, 0x0B},
337 { CDC_VA_TX3_TX_VOL_CTL, 0x00}, 304 { CDC_VA_TX3_TX_VOL_CTL, 0x00},
338 { CDC_VA_TX3_TX_PATH_SEC0, 0x00}, 305 { CDC_VA_TX3_TX_PATH_SEC0, 0x00},
339 { CDC_VA_TX3_TX_PATH_SEC1, 0x00}, 306 { CDC_VA_TX3_TX_PATH_SEC1, 0x00},
340 { CDC_VA_TX3_TX_PATH_SEC2, 0x01}, 307 { CDC_VA_TX3_TX_PATH_SEC2, 0x01},
341 { CDC_VA_TX3_TX_PATH_SEC3, 0x3C}, 308 { CDC_VA_TX3_TX_PATH_SEC3, 0x3C},
342 { CDC_VA_TX3_TX_PATH_SEC4, 0x20}, 309 { CDC_VA_TX3_TX_PATH_SEC4, 0x20},
343 { CDC_VA_TX3_TX_PATH_SEC5, 0x00}, 310 { CDC_VA_TX3_TX_PATH_SEC5, 0x00},
344 { CDC_VA_TX3_TX_PATH_SEC6, 0x00}, 311 { CDC_VA_TX3_TX_PATH_SEC6, 0x00},
345 }; 312 };
346 313
347 static bool va_is_rw_register(struct device *d 314 static bool va_is_rw_register(struct device *dev, unsigned int reg)
348 { 315 {
349 switch (reg) { 316 switch (reg) {
350 case CDC_VA_CLK_RST_CTRL_MCLK_CONTROL: 317 case CDC_VA_CLK_RST_CTRL_MCLK_CONTROL:
351 case CDC_VA_CLK_RST_CTRL_FS_CNT_CONTRO 318 case CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL:
352 case CDC_VA_CLK_RST_CTRL_SWR_CONTROL: 319 case CDC_VA_CLK_RST_CTRL_SWR_CONTROL:
353 case CDC_VA_TOP_CSR_TOP_CFG0: 320 case CDC_VA_TOP_CSR_TOP_CFG0:
354 case CDC_VA_TOP_CSR_DMIC0_CTL: 321 case CDC_VA_TOP_CSR_DMIC0_CTL:
355 case CDC_VA_TOP_CSR_DMIC1_CTL: 322 case CDC_VA_TOP_CSR_DMIC1_CTL:
356 case CDC_VA_TOP_CSR_DMIC2_CTL: 323 case CDC_VA_TOP_CSR_DMIC2_CTL:
357 case CDC_VA_TOP_CSR_DMIC3_CTL: 324 case CDC_VA_TOP_CSR_DMIC3_CTL:
358 case CDC_VA_TOP_CSR_DMIC_CFG: 325 case CDC_VA_TOP_CSR_DMIC_CFG:
359 case CDC_VA_TOP_CSR_SWR_MIC_CTL0: <<
360 case CDC_VA_TOP_CSR_SWR_MIC_CTL1: <<
361 case CDC_VA_TOP_CSR_SWR_MIC_CTL2: <<
362 case CDC_VA_TOP_CSR_DEBUG_BUS: 326 case CDC_VA_TOP_CSR_DEBUG_BUS:
363 case CDC_VA_TOP_CSR_DEBUG_EN: 327 case CDC_VA_TOP_CSR_DEBUG_EN:
364 case CDC_VA_TOP_CSR_TX_I2S_CTL: 328 case CDC_VA_TOP_CSR_TX_I2S_CTL:
365 case CDC_VA_TOP_CSR_I2S_CLK: 329 case CDC_VA_TOP_CSR_I2S_CLK:
366 case CDC_VA_TOP_CSR_I2S_RESET: 330 case CDC_VA_TOP_CSR_I2S_RESET:
367 case CDC_VA_INP_MUX_ADC_MUX0_CFG0: 331 case CDC_VA_INP_MUX_ADC_MUX0_CFG0:
368 case CDC_VA_INP_MUX_ADC_MUX0_CFG1: 332 case CDC_VA_INP_MUX_ADC_MUX0_CFG1:
369 case CDC_VA_INP_MUX_ADC_MUX1_CFG0: 333 case CDC_VA_INP_MUX_ADC_MUX1_CFG0:
370 case CDC_VA_INP_MUX_ADC_MUX1_CFG1: 334 case CDC_VA_INP_MUX_ADC_MUX1_CFG1:
371 case CDC_VA_INP_MUX_ADC_MUX2_CFG0: 335 case CDC_VA_INP_MUX_ADC_MUX2_CFG0:
372 case CDC_VA_INP_MUX_ADC_MUX2_CFG1: 336 case CDC_VA_INP_MUX_ADC_MUX2_CFG1:
373 case CDC_VA_INP_MUX_ADC_MUX3_CFG0: 337 case CDC_VA_INP_MUX_ADC_MUX3_CFG0:
374 case CDC_VA_INP_MUX_ADC_MUX3_CFG1: 338 case CDC_VA_INP_MUX_ADC_MUX3_CFG1:
375 case CDC_VA_TX0_TX_PATH_CTL: 339 case CDC_VA_TX0_TX_PATH_CTL:
376 case CDC_VA_TX0_TX_PATH_CFG0: 340 case CDC_VA_TX0_TX_PATH_CFG0:
377 case CDC_VA_TX0_TX_PATH_CFG1: 341 case CDC_VA_TX0_TX_PATH_CFG1:
378 case CDC_VA_TX0_TX_VOL_CTL: 342 case CDC_VA_TX0_TX_VOL_CTL:
379 case CDC_VA_TX0_TX_PATH_SEC0: 343 case CDC_VA_TX0_TX_PATH_SEC0:
380 case CDC_VA_TX0_TX_PATH_SEC1: 344 case CDC_VA_TX0_TX_PATH_SEC1:
381 case CDC_VA_TX0_TX_PATH_SEC2: 345 case CDC_VA_TX0_TX_PATH_SEC2:
382 case CDC_VA_TX0_TX_PATH_SEC3: 346 case CDC_VA_TX0_TX_PATH_SEC3:
383 case CDC_VA_TX0_TX_PATH_SEC4: 347 case CDC_VA_TX0_TX_PATH_SEC4:
384 case CDC_VA_TX0_TX_PATH_SEC5: 348 case CDC_VA_TX0_TX_PATH_SEC5:
385 case CDC_VA_TX0_TX_PATH_SEC6: 349 case CDC_VA_TX0_TX_PATH_SEC6:
386 case CDC_VA_TX0_TX_PATH_SEC7: 350 case CDC_VA_TX0_TX_PATH_SEC7:
387 case CDC_VA_TX1_TX_PATH_CTL: 351 case CDC_VA_TX1_TX_PATH_CTL:
388 case CDC_VA_TX1_TX_PATH_CFG0: 352 case CDC_VA_TX1_TX_PATH_CFG0:
389 case CDC_VA_TX1_TX_PATH_CFG1: 353 case CDC_VA_TX1_TX_PATH_CFG1:
390 case CDC_VA_TX1_TX_VOL_CTL: 354 case CDC_VA_TX1_TX_VOL_CTL:
391 case CDC_VA_TX1_TX_PATH_SEC0: 355 case CDC_VA_TX1_TX_PATH_SEC0:
392 case CDC_VA_TX1_TX_PATH_SEC1: 356 case CDC_VA_TX1_TX_PATH_SEC1:
393 case CDC_VA_TX1_TX_PATH_SEC2: 357 case CDC_VA_TX1_TX_PATH_SEC2:
394 case CDC_VA_TX1_TX_PATH_SEC3: 358 case CDC_VA_TX1_TX_PATH_SEC3:
395 case CDC_VA_TX1_TX_PATH_SEC4: 359 case CDC_VA_TX1_TX_PATH_SEC4:
396 case CDC_VA_TX1_TX_PATH_SEC5: 360 case CDC_VA_TX1_TX_PATH_SEC5:
397 case CDC_VA_TX1_TX_PATH_SEC6: 361 case CDC_VA_TX1_TX_PATH_SEC6:
398 case CDC_VA_TX2_TX_PATH_CTL: 362 case CDC_VA_TX2_TX_PATH_CTL:
399 case CDC_VA_TX2_TX_PATH_CFG0: 363 case CDC_VA_TX2_TX_PATH_CFG0:
400 case CDC_VA_TX2_TX_PATH_CFG1: 364 case CDC_VA_TX2_TX_PATH_CFG1:
401 case CDC_VA_TX2_TX_VOL_CTL: 365 case CDC_VA_TX2_TX_VOL_CTL:
402 case CDC_VA_TX2_TX_PATH_SEC0: 366 case CDC_VA_TX2_TX_PATH_SEC0:
403 case CDC_VA_TX2_TX_PATH_SEC1: 367 case CDC_VA_TX2_TX_PATH_SEC1:
404 case CDC_VA_TX2_TX_PATH_SEC2: 368 case CDC_VA_TX2_TX_PATH_SEC2:
405 case CDC_VA_TX2_TX_PATH_SEC3: 369 case CDC_VA_TX2_TX_PATH_SEC3:
406 case CDC_VA_TX2_TX_PATH_SEC4: 370 case CDC_VA_TX2_TX_PATH_SEC4:
407 case CDC_VA_TX2_TX_PATH_SEC5: 371 case CDC_VA_TX2_TX_PATH_SEC5:
408 case CDC_VA_TX2_TX_PATH_SEC6: 372 case CDC_VA_TX2_TX_PATH_SEC6:
409 case CDC_VA_TX3_TX_PATH_CTL: 373 case CDC_VA_TX3_TX_PATH_CTL:
410 case CDC_VA_TX3_TX_PATH_CFG0: 374 case CDC_VA_TX3_TX_PATH_CFG0:
411 case CDC_VA_TX3_TX_PATH_CFG1: 375 case CDC_VA_TX3_TX_PATH_CFG1:
412 case CDC_VA_TX3_TX_VOL_CTL: 376 case CDC_VA_TX3_TX_VOL_CTL:
413 case CDC_VA_TX3_TX_PATH_SEC0: 377 case CDC_VA_TX3_TX_PATH_SEC0:
414 case CDC_VA_TX3_TX_PATH_SEC1: 378 case CDC_VA_TX3_TX_PATH_SEC1:
415 case CDC_VA_TX3_TX_PATH_SEC2: 379 case CDC_VA_TX3_TX_PATH_SEC2:
416 case CDC_VA_TX3_TX_PATH_SEC3: 380 case CDC_VA_TX3_TX_PATH_SEC3:
417 case CDC_VA_TX3_TX_PATH_SEC4: 381 case CDC_VA_TX3_TX_PATH_SEC4:
418 case CDC_VA_TX3_TX_PATH_SEC5: 382 case CDC_VA_TX3_TX_PATH_SEC5:
419 case CDC_VA_TX3_TX_PATH_SEC6: 383 case CDC_VA_TX3_TX_PATH_SEC6:
420 return true; 384 return true;
421 } 385 }
422 386
423 return false; 387 return false;
424 } 388 }
425 389
426 static bool va_is_readable_register(struct dev 390 static bool va_is_readable_register(struct device *dev, unsigned int reg)
427 { 391 {
428 switch (reg) { 392 switch (reg) {
429 case CDC_VA_TOP_CSR_CORE_ID_0: 393 case CDC_VA_TOP_CSR_CORE_ID_0:
430 case CDC_VA_TOP_CSR_CORE_ID_1: 394 case CDC_VA_TOP_CSR_CORE_ID_1:
431 case CDC_VA_TOP_CSR_CORE_ID_2: 395 case CDC_VA_TOP_CSR_CORE_ID_2:
432 case CDC_VA_TOP_CSR_CORE_ID_3: 396 case CDC_VA_TOP_CSR_CORE_ID_3:
433 return true; 397 return true;
434 } 398 }
435 399
436 return va_is_rw_register(dev, reg); 400 return va_is_rw_register(dev, reg);
437 } 401 }
438 402
439 static const struct regmap_config va_regmap_co 403 static const struct regmap_config va_regmap_config = {
440 .name = "va_macro", 404 .name = "va_macro",
441 .reg_bits = 32, 405 .reg_bits = 32,
442 .val_bits = 32, 406 .val_bits = 32,
443 .reg_stride = 4, 407 .reg_stride = 4,
444 .cache_type = REGCACHE_FLAT, 408 .cache_type = REGCACHE_FLAT,
445 .reg_defaults = va_defaults, 409 .reg_defaults = va_defaults,
446 .num_reg_defaults = ARRAY_SIZE(va_defa 410 .num_reg_defaults = ARRAY_SIZE(va_defaults),
447 .max_register = VA_MAX_OFFSET, 411 .max_register = VA_MAX_OFFSET,
448 .volatile_reg = va_is_volatile_registe 412 .volatile_reg = va_is_volatile_register,
449 .readable_reg = va_is_readable_registe 413 .readable_reg = va_is_readable_register,
450 .writeable_reg = va_is_rw_register, 414 .writeable_reg = va_is_rw_register,
451 }; 415 };
452 416
453 static int va_clk_rsc_fs_gen_request(struct va 417 static int va_clk_rsc_fs_gen_request(struct va_macro *va, bool enable)
454 { 418 {
455 struct regmap *regmap = va->regmap; 419 struct regmap *regmap = va->regmap;
456 420
457 if (enable) { 421 if (enable) {
458 regmap_update_bits(regmap, CDC 422 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_MCLK_CONTROL,
459 CDC_VA_MCLK 423 CDC_VA_MCLK_CONTROL_EN,
460 CDC_VA_MCLK 424 CDC_VA_MCLK_CONTROL_EN);
461 /* clear the fs counter */ !! 425
462 regmap_update_bits(regmap, CDC <<
463 CDC_VA_FS_C <<
464 CDC_VA_FS_C <<
465 regmap_update_bits(regmap, CDC 426 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL,
466 CDC_VA_FS_C !! 427 CDC_VA_FS_CONTROL_EN,
467 CDC_VA_FS_C 428 CDC_VA_FS_CONTROL_EN);
468 429
469 regmap_update_bits(regmap, CDC 430 regmap_update_bits(regmap, CDC_VA_TOP_CSR_TOP_CFG0,
470 CDC_VA_FS_B 431 CDC_VA_FS_BROADCAST_EN,
471 CDC_VA_FS_B 432 CDC_VA_FS_BROADCAST_EN);
472 } else { 433 } else {
473 regmap_update_bits(regmap, CDC 434 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_MCLK_CONTROL,
474 CDC_VA_MCLK 435 CDC_VA_MCLK_CONTROL_EN, 0x0);
475 436
476 regmap_update_bits(regmap, CDC 437 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL,
477 CDC_VA_FS_C 438 CDC_VA_FS_CONTROL_EN, 0x0);
478 439
479 regmap_update_bits(regmap, CDC 440 regmap_update_bits(regmap, CDC_VA_TOP_CSR_TOP_CFG0,
480 CDC_VA_FS_B 441 CDC_VA_FS_BROADCAST_EN, 0x0);
481 } 442 }
482 443
483 return 0; 444 return 0;
484 } 445 }
485 446
486 static int va_macro_mclk_enable(struct va_macr 447 static int va_macro_mclk_enable(struct va_macro *va, bool mclk_enable)
487 { 448 {
488 struct regmap *regmap = va->regmap; 449 struct regmap *regmap = va->regmap;
489 450
490 if (mclk_enable) { 451 if (mclk_enable) {
491 va_clk_rsc_fs_gen_request(va, 452 va_clk_rsc_fs_gen_request(va, true);
492 regcache_mark_dirty(regmap); 453 regcache_mark_dirty(regmap);
493 regcache_sync_region(regmap, 0 454 regcache_sync_region(regmap, 0x0, VA_MAX_OFFSET);
494 } else { 455 } else {
495 va_clk_rsc_fs_gen_request(va, 456 va_clk_rsc_fs_gen_request(va, false);
496 } 457 }
497 458
498 return 0; 459 return 0;
499 } 460 }
500 461
501 static int va_macro_mclk_event(struct snd_soc_ 462 static int va_macro_mclk_event(struct snd_soc_dapm_widget *w,
502 struct snd_kcon 463 struct snd_kcontrol *kcontrol, int event)
503 { 464 {
504 struct snd_soc_component *comp = snd_s 465 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
505 struct va_macro *va = snd_soc_componen 466 struct va_macro *va = snd_soc_component_get_drvdata(comp);
506 467
507 switch (event) { 468 switch (event) {
508 case SND_SOC_DAPM_PRE_PMU: 469 case SND_SOC_DAPM_PRE_PMU:
509 return clk_prepare_enable(va-> !! 470 return va_macro_mclk_enable(va, true);
510 case SND_SOC_DAPM_POST_PMD: 471 case SND_SOC_DAPM_POST_PMD:
511 clk_disable_unprepare(va->fsge !! 472 return va_macro_mclk_enable(va, false);
512 } 473 }
513 474
514 return 0; 475 return 0;
515 } 476 }
516 477
517 static int va_macro_put_dec_enum(struct snd_kc 478 static int va_macro_put_dec_enum(struct snd_kcontrol *kcontrol,
518 struct snd_ct 479 struct snd_ctl_elem_value *ucontrol)
519 { 480 {
520 struct snd_soc_dapm_widget *widget = 481 struct snd_soc_dapm_widget *widget =
521 snd_soc_dapm_kcontrol_widget(k 482 snd_soc_dapm_kcontrol_widget(kcontrol);
522 struct snd_soc_component *component = 483 struct snd_soc_component *component =
523 snd_soc_dapm_to_component(widg 484 snd_soc_dapm_to_component(widget->dapm);
524 struct soc_enum *e = (struct soc_enum 485 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
525 unsigned int val; 486 unsigned int val;
526 u16 mic_sel_reg; 487 u16 mic_sel_reg;
527 488
528 val = ucontrol->value.enumerated.item[ 489 val = ucontrol->value.enumerated.item[0];
529 490
530 switch (e->reg) { 491 switch (e->reg) {
531 case CDC_VA_INP_MUX_ADC_MUX0_CFG0: 492 case CDC_VA_INP_MUX_ADC_MUX0_CFG0:
532 mic_sel_reg = CDC_VA_TX0_TX_PA 493 mic_sel_reg = CDC_VA_TX0_TX_PATH_CFG0;
533 break; 494 break;
534 case CDC_VA_INP_MUX_ADC_MUX1_CFG0: 495 case CDC_VA_INP_MUX_ADC_MUX1_CFG0:
535 mic_sel_reg = CDC_VA_TX1_TX_PA 496 mic_sel_reg = CDC_VA_TX1_TX_PATH_CFG0;
536 break; 497 break;
537 case CDC_VA_INP_MUX_ADC_MUX2_CFG0: 498 case CDC_VA_INP_MUX_ADC_MUX2_CFG0:
538 mic_sel_reg = CDC_VA_TX2_TX_PA 499 mic_sel_reg = CDC_VA_TX2_TX_PATH_CFG0;
539 break; 500 break;
540 case CDC_VA_INP_MUX_ADC_MUX3_CFG0: 501 case CDC_VA_INP_MUX_ADC_MUX3_CFG0:
541 mic_sel_reg = CDC_VA_TX3_TX_PA 502 mic_sel_reg = CDC_VA_TX3_TX_PATH_CFG0;
542 break; 503 break;
543 default: 504 default:
544 dev_err(component->dev, "%s: e 505 dev_err(component->dev, "%s: e->reg: 0x%x not expected\n",
545 __func__, e->reg); 506 __func__, e->reg);
546 return -EINVAL; 507 return -EINVAL;
547 } 508 }
548 509
549 if (val != 0) 510 if (val != 0)
550 snd_soc_component_update_bits( 511 snd_soc_component_update_bits(component, mic_sel_reg,
551 512 CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK,
552 513 CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC);
553 514
554 return snd_soc_dapm_put_enum_double(kc 515 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
555 } 516 }
556 517
557 static int va_macro_tx_mixer_get(struct snd_kc 518 static int va_macro_tx_mixer_get(struct snd_kcontrol *kcontrol,
558 struct snd_ct 519 struct snd_ctl_elem_value *ucontrol)
559 { 520 {
560 struct snd_soc_dapm_widget *widget = 521 struct snd_soc_dapm_widget *widget =
561 snd_soc_dapm_kcontrol_widget(k 522 snd_soc_dapm_kcontrol_widget(kcontrol);
562 struct snd_soc_component *component = 523 struct snd_soc_component *component =
563 snd_soc_dapm_t 524 snd_soc_dapm_to_component(widget->dapm);
564 struct soc_mixer_control *mc = 525 struct soc_mixer_control *mc =
565 (struct soc_mixer_control *)kc 526 (struct soc_mixer_control *)kcontrol->private_value;
566 u32 dai_id = widget->shift; 527 u32 dai_id = widget->shift;
567 u32 dec_id = mc->shift; 528 u32 dec_id = mc->shift;
568 struct va_macro *va = snd_soc_componen 529 struct va_macro *va = snd_soc_component_get_drvdata(component);
569 530
570 if (test_bit(dec_id, &va->active_ch_ma 531 if (test_bit(dec_id, &va->active_ch_mask[dai_id]))
571 ucontrol->value.integer.value[ 532 ucontrol->value.integer.value[0] = 1;
572 else 533 else
573 ucontrol->value.integer.value[ 534 ucontrol->value.integer.value[0] = 0;
574 535
575 return 0; 536 return 0;
576 } 537 }
577 538
578 static int va_macro_tx_mixer_put(struct snd_kc 539 static int va_macro_tx_mixer_put(struct snd_kcontrol *kcontrol,
579 struct snd_ct 540 struct snd_ctl_elem_value *ucontrol)
580 { 541 {
581 struct snd_soc_dapm_widget *widget = 542 struct snd_soc_dapm_widget *widget =
582 snd_so 543 snd_soc_dapm_kcontrol_widget(kcontrol);
583 struct snd_soc_component *component = 544 struct snd_soc_component *component =
584 snd_soc_dapm_t 545 snd_soc_dapm_to_component(widget->dapm);
585 struct snd_soc_dapm_update *update = N 546 struct snd_soc_dapm_update *update = NULL;
586 struct soc_mixer_control *mc = 547 struct soc_mixer_control *mc =
587 (struct soc_mixer_control *)kc 548 (struct soc_mixer_control *)kcontrol->private_value;
588 u32 dai_id = widget->shift; 549 u32 dai_id = widget->shift;
589 u32 dec_id = mc->shift; 550 u32 dec_id = mc->shift;
590 u32 enable = ucontrol->value.integer.v 551 u32 enable = ucontrol->value.integer.value[0];
591 struct va_macro *va = snd_soc_componen 552 struct va_macro *va = snd_soc_component_get_drvdata(component);
592 553
593 if (enable) { 554 if (enable) {
594 set_bit(dec_id, &va->active_ch 555 set_bit(dec_id, &va->active_ch_mask[dai_id]);
595 va->active_ch_cnt[dai_id]++; 556 va->active_ch_cnt[dai_id]++;
596 } else { 557 } else {
597 clear_bit(dec_id, &va->active_ 558 clear_bit(dec_id, &va->active_ch_mask[dai_id]);
598 va->active_ch_cnt[dai_id]--; 559 va->active_ch_cnt[dai_id]--;
599 } 560 }
600 561
601 snd_soc_dapm_mixer_update_power(widget 562 snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update);
602 563
603 return 0; 564 return 0;
604 } 565 }
605 566
606 static int va_dmic_clk_enable(struct snd_soc_c 567 static int va_dmic_clk_enable(struct snd_soc_component *component,
607 u32 dmic, bool e 568 u32 dmic, bool enable)
608 { 569 {
609 struct va_macro *va = snd_soc_componen 570 struct va_macro *va = snd_soc_component_get_drvdata(component);
610 u16 dmic_clk_reg; 571 u16 dmic_clk_reg;
611 s32 *dmic_clk_cnt; 572 s32 *dmic_clk_cnt;
612 u8 *dmic_clk_div; 573 u8 *dmic_clk_div;
613 u8 freq_change_mask; 574 u8 freq_change_mask;
614 u8 clk_div; 575 u8 clk_div;
615 576
616 switch (dmic) { 577 switch (dmic) {
617 case 0: 578 case 0:
618 case 1: 579 case 1:
619 dmic_clk_cnt = &(va->dmic_0_1_ 580 dmic_clk_cnt = &(va->dmic_0_1_clk_cnt);
620 dmic_clk_div = &(va->dmic_0_1_ 581 dmic_clk_div = &(va->dmic_0_1_clk_div);
621 dmic_clk_reg = CDC_VA_TOP_CSR_ 582 dmic_clk_reg = CDC_VA_TOP_CSR_DMIC0_CTL;
622 freq_change_mask = CDC_VA_DMIC 583 freq_change_mask = CDC_VA_DMIC0_FREQ_CHANGE_MASK;
623 break; 584 break;
624 case 2: 585 case 2:
625 case 3: 586 case 3:
626 dmic_clk_cnt = &(va->dmic_2_3_ 587 dmic_clk_cnt = &(va->dmic_2_3_clk_cnt);
627 dmic_clk_div = &(va->dmic_2_3_ 588 dmic_clk_div = &(va->dmic_2_3_clk_div);
628 dmic_clk_reg = CDC_VA_TOP_CSR_ 589 dmic_clk_reg = CDC_VA_TOP_CSR_DMIC1_CTL;
629 freq_change_mask = CDC_VA_DMIC 590 freq_change_mask = CDC_VA_DMIC1_FREQ_CHANGE_MASK;
630 break; 591 break;
631 case 4: 592 case 4:
632 case 5: 593 case 5:
633 dmic_clk_cnt = &(va->dmic_4_5_ 594 dmic_clk_cnt = &(va->dmic_4_5_clk_cnt);
634 dmic_clk_div = &(va->dmic_4_5_ 595 dmic_clk_div = &(va->dmic_4_5_clk_div);
635 dmic_clk_reg = CDC_VA_TOP_CSR_ 596 dmic_clk_reg = CDC_VA_TOP_CSR_DMIC2_CTL;
636 freq_change_mask = CDC_VA_DMIC 597 freq_change_mask = CDC_VA_DMIC2_FREQ_CHANGE_MASK;
637 break; 598 break;
638 case 6: 599 case 6:
639 case 7: 600 case 7:
640 dmic_clk_cnt = &(va->dmic_6_7_ 601 dmic_clk_cnt = &(va->dmic_6_7_clk_cnt);
641 dmic_clk_div = &(va->dmic_6_7_ 602 dmic_clk_div = &(va->dmic_6_7_clk_div);
642 dmic_clk_reg = CDC_VA_TOP_CSR_ 603 dmic_clk_reg = CDC_VA_TOP_CSR_DMIC3_CTL;
643 freq_change_mask = CDC_VA_DMIC 604 freq_change_mask = CDC_VA_DMIC3_FREQ_CHANGE_MASK;
644 break; 605 break;
645 default: 606 default:
646 dev_err(component->dev, "%s: I 607 dev_err(component->dev, "%s: Invalid DMIC Selection\n",
647 __func__); 608 __func__);
648 return -EINVAL; 609 return -EINVAL;
649 } 610 }
650 611
651 if (enable) { 612 if (enable) {
652 clk_div = va->dmic_clk_div; 613 clk_div = va->dmic_clk_div;
653 (*dmic_clk_cnt)++; 614 (*dmic_clk_cnt)++;
654 if (*dmic_clk_cnt == 1) { 615 if (*dmic_clk_cnt == 1) {
655 snd_soc_component_upda 616 snd_soc_component_update_bits(component,
656 617 CDC_VA_TOP_CSR_DMIC_CFG,
657 618 CDC_VA_RESET_ALL_DMICS_MASK,
658 619 CDC_VA_RESET_ALL_DMICS_DISABLE);
659 snd_soc_component_upda 620 snd_soc_component_update_bits(component, dmic_clk_reg,
660 CDC_VA 621 CDC_VA_DMIC_CLK_SEL_MASK,
661 clk_di 622 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT);
662 snd_soc_component_upda 623 snd_soc_component_update_bits(component, dmic_clk_reg,
663 624 CDC_VA_DMIC_EN_MASK,
664 625 CDC_VA_DMIC_ENABLE);
665 } else { 626 } else {
666 if (*dmic_clk_div > cl 627 if (*dmic_clk_div > clk_div) {
667 snd_soc_compon 628 snd_soc_component_update_bits(component,
668 629 CDC_VA_TOP_CSR_DMIC_CFG,
669 630 freq_change_mask,
670 631 freq_change_mask);
671 snd_soc_compon 632 snd_soc_component_update_bits(component, dmic_clk_reg,
672 633 CDC_VA_DMIC_CLK_SEL_MASK,
673 634 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT);
674 snd_soc_compon 635 snd_soc_component_update_bits(component,
675 636 CDC_VA_TOP_CSR_DMIC_CFG,
676 637 freq_change_mask,
677 638 CDC_VA_DMIC_FREQ_CHANGE_DISABLE);
678 } else { 639 } else {
679 clk_div = *dmi 640 clk_div = *dmic_clk_div;
680 } 641 }
681 } 642 }
682 *dmic_clk_div = clk_div; 643 *dmic_clk_div = clk_div;
683 } else { 644 } else {
684 (*dmic_clk_cnt)--; 645 (*dmic_clk_cnt)--;
685 if (*dmic_clk_cnt == 0) { 646 if (*dmic_clk_cnt == 0) {
686 snd_soc_component_upda 647 snd_soc_component_update_bits(component, dmic_clk_reg,
687 648 CDC_VA_DMIC_EN_MASK, 0);
688 clk_div = 0; 649 clk_div = 0;
689 snd_soc_component_upda 650 snd_soc_component_update_bits(component, dmic_clk_reg,
690 651 CDC_VA_DMIC_CLK_SEL_MASK,
691 652 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT);
692 } else { 653 } else {
693 clk_div = va->dmic_clk 654 clk_div = va->dmic_clk_div;
694 if (*dmic_clk_div > cl 655 if (*dmic_clk_div > clk_div) {
695 clk_div = va-> 656 clk_div = va->dmic_clk_div;
696 snd_soc_compon 657 snd_soc_component_update_bits(component,
697 658 CDC_VA_TOP_CSR_DMIC_CFG,
698 659 freq_change_mask,
699 660 freq_change_mask);
700 snd_soc_compon 661 snd_soc_component_update_bits(component, dmic_clk_reg,
701 662 CDC_VA_DMIC_CLK_SEL_MASK,
702 663 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT);
703 snd_soc_compon 664 snd_soc_component_update_bits(component,
704 665 CDC_VA_TOP_CSR_DMIC_CFG,
705 666 freq_change_mask,
706 667 CDC_VA_DMIC_FREQ_CHANGE_DISABLE);
707 } else { 668 } else {
708 clk_div = *dmi 669 clk_div = *dmic_clk_div;
709 } 670 }
710 } 671 }
711 *dmic_clk_div = clk_div; 672 *dmic_clk_div = clk_div;
712 } 673 }
713 674
714 return 0; 675 return 0;
715 } 676 }
716 677
717 static int va_macro_enable_dmic(struct snd_soc 678 static int va_macro_enable_dmic(struct snd_soc_dapm_widget *w,
718 struct snd_kco 679 struct snd_kcontrol *kcontrol, int event)
719 { 680 {
720 struct snd_soc_component *comp = snd_s 681 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
721 unsigned int dmic = w->shift; 682 unsigned int dmic = w->shift;
722 683
723 switch (event) { 684 switch (event) {
724 case SND_SOC_DAPM_PRE_PMU: 685 case SND_SOC_DAPM_PRE_PMU:
725 va_dmic_clk_enable(comp, dmic, 686 va_dmic_clk_enable(comp, dmic, true);
726 break; 687 break;
727 case SND_SOC_DAPM_POST_PMD: 688 case SND_SOC_DAPM_POST_PMD:
728 va_dmic_clk_enable(comp, dmic, 689 va_dmic_clk_enable(comp, dmic, false);
729 break; 690 break;
730 } 691 }
731 692
732 return 0; 693 return 0;
733 } 694 }
734 695
735 static int va_macro_enable_dec(struct snd_soc_ 696 static int va_macro_enable_dec(struct snd_soc_dapm_widget *w,
736 struct snd_kcon 697 struct snd_kcontrol *kcontrol, int event)
737 { 698 {
738 struct snd_soc_component *comp = snd_s 699 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
739 unsigned int decimator; 700 unsigned int decimator;
740 u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_g 701 u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg;
741 u16 tx_gain_ctl_reg; 702 u16 tx_gain_ctl_reg;
742 u8 hpf_cut_off_freq; 703 u8 hpf_cut_off_freq;
743 704
744 struct va_macro *va = snd_soc_componen 705 struct va_macro *va = snd_soc_component_get_drvdata(comp);
745 706
746 decimator = w->shift; 707 decimator = w->shift;
747 708
748 tx_vol_ctl_reg = CDC_VA_TX0_TX_PATH_CT 709 tx_vol_ctl_reg = CDC_VA_TX0_TX_PATH_CTL +
749 VA_MACRO_TX_PA 710 VA_MACRO_TX_PATH_OFFSET * decimator;
750 hpf_gate_reg = CDC_VA_TX0_TX_PATH_SEC2 711 hpf_gate_reg = CDC_VA_TX0_TX_PATH_SEC2 +
751 VA_MACRO_TX_PA 712 VA_MACRO_TX_PATH_OFFSET * decimator;
752 dec_cfg_reg = CDC_VA_TX0_TX_PATH_CFG0 713 dec_cfg_reg = CDC_VA_TX0_TX_PATH_CFG0 +
753 VA_MACRO_TX_PA 714 VA_MACRO_TX_PATH_OFFSET * decimator;
754 tx_gain_ctl_reg = CDC_VA_TX0_TX_VOL_CT 715 tx_gain_ctl_reg = CDC_VA_TX0_TX_VOL_CTL +
755 VA_MACRO_TX_PA 716 VA_MACRO_TX_PATH_OFFSET * decimator;
756 717
757 switch (event) { 718 switch (event) {
758 case SND_SOC_DAPM_PRE_PMU: 719 case SND_SOC_DAPM_PRE_PMU:
759 snd_soc_component_update_bits( 720 snd_soc_component_update_bits(comp,
760 dec_cfg_reg, CDC_VA_AD 721 dec_cfg_reg, CDC_VA_ADC_MODE_MASK,
761 va->dec_mode[decimator 722 va->dec_mode[decimator] << CDC_VA_ADC_MODE_SHIFT);
762 /* Enable TX PGA Mute */ 723 /* Enable TX PGA Mute */
763 break; 724 break;
764 case SND_SOC_DAPM_POST_PMU: 725 case SND_SOC_DAPM_POST_PMU:
765 /* Enable TX CLK */ 726 /* Enable TX CLK */
766 snd_soc_component_update_bits( 727 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
767 728 CDC_VA_TX_PATH_CLK_EN_MASK,
768 729 CDC_VA_TX_PATH_CLK_EN);
769 snd_soc_component_update_bits( 730 snd_soc_component_update_bits(comp, hpf_gate_reg,
770 731 CDC_VA_TX_HPF_ZERO_GATE_MASK,
771 732 CDC_VA_TX_HPF_ZERO_GATE);
772 733
773 usleep_range(1000, 1010); 734 usleep_range(1000, 1010);
774 hpf_cut_off_freq = (snd_soc_co 735 hpf_cut_off_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
775 TX_HPF_CUT 736 TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
776 737
777 if (hpf_cut_off_freq != CF_MIN 738 if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) {
778 snd_soc_component_upda 739 snd_soc_component_update_bits(comp, dec_cfg_reg,
779 740 TX_HPF_CUT_OFF_FREQ_MASK,
780 741 CF_MIN_3DB_150HZ << 5);
781 742
782 snd_soc_component_upda 743 snd_soc_component_update_bits(comp, hpf_gate_reg,
783 CDC_VA_T 744 CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK,
784 CDC_VA_T 745 CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_REQ);
785 746
786 /* 747 /*
787 * Minimum 1 clk cycle 748 * Minimum 1 clk cycle delay is required as per HW spec
788 */ 749 */
789 usleep_range(1000, 101 750 usleep_range(1000, 1010);
790 751
791 snd_soc_component_upda 752 snd_soc_component_update_bits(comp,
792 hpf_gate_reg, 753 hpf_gate_reg,
793 CDC_VA_TX_HPF_ 754 CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK,
794 0x0); 755 0x0);
795 } 756 }
796 757
797 758
798 usleep_range(1000, 1010); 759 usleep_range(1000, 1010);
799 snd_soc_component_update_bits( 760 snd_soc_component_update_bits(comp, hpf_gate_reg,
800 761 CDC_VA_TX_HPF_ZERO_GATE_MASK,
801 762 CDC_VA_TX_HPF_ZERO_NO_GATE);
802 /* 763 /*
803 * 6ms delay is required as pe 764 * 6ms delay is required as per HW spec
804 */ 765 */
805 usleep_range(6000, 6010); 766 usleep_range(6000, 6010);
806 /* apply gain after decimator 767 /* apply gain after decimator is enabled */
807 snd_soc_component_write(comp, 768 snd_soc_component_write(comp, tx_gain_ctl_reg,
808 snd_soc_component_read 769 snd_soc_component_read(comp, tx_gain_ctl_reg));
809 break; 770 break;
810 case SND_SOC_DAPM_POST_PMD: 771 case SND_SOC_DAPM_POST_PMD:
811 /* Disable TX CLK */ 772 /* Disable TX CLK */
812 snd_soc_component_update_bits( 773 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
813 774 CDC_VA_TX_PATH_CLK_EN_MASK,
814 775 CDC_VA_TX_PATH_CLK_DISABLE);
815 break; 776 break;
816 } 777 }
817 return 0; 778 return 0;
818 } 779 }
819 780
820 static int va_macro_dec_mode_get(struct snd_kc 781 static int va_macro_dec_mode_get(struct snd_kcontrol *kcontrol,
821 struct snd_ct 782 struct snd_ctl_elem_value *ucontrol)
822 { 783 {
823 struct snd_soc_component *comp = snd_s 784 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
824 struct va_macro *va = snd_soc_componen 785 struct va_macro *va = snd_soc_component_get_drvdata(comp);
825 struct soc_enum *e = (struct soc_enum 786 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
826 int path = e->shift_l; 787 int path = e->shift_l;
827 788
828 ucontrol->value.enumerated.item[0] = v 789 ucontrol->value.enumerated.item[0] = va->dec_mode[path];
829 790
830 return 0; 791 return 0;
831 } 792 }
832 793
833 static int va_macro_dec_mode_put(struct snd_kc 794 static int va_macro_dec_mode_put(struct snd_kcontrol *kcontrol,
834 struct snd_ct 795 struct snd_ctl_elem_value *ucontrol)
835 { 796 {
836 struct snd_soc_component *comp = snd_s 797 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
837 int value = ucontrol->value.enumerated 798 int value = ucontrol->value.enumerated.item[0];
838 struct soc_enum *e = (struct soc_enum 799 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
839 int path = e->shift_l; 800 int path = e->shift_l;
840 struct va_macro *va = snd_soc_componen 801 struct va_macro *va = snd_soc_component_get_drvdata(comp);
841 802
842 va->dec_mode[path] = value; 803 va->dec_mode[path] = value;
843 804
844 return 0; 805 return 0;
845 } 806 }
846 807
847 static int va_macro_hw_params(struct snd_pcm_s 808 static int va_macro_hw_params(struct snd_pcm_substream *substream,
848 struct snd_pcm_h 809 struct snd_pcm_hw_params *params,
849 struct snd_soc_d 810 struct snd_soc_dai *dai)
850 { 811 {
851 int tx_fs_rate; 812 int tx_fs_rate;
852 struct snd_soc_component *component = 813 struct snd_soc_component *component = dai->component;
853 u32 decimator, sample_rate; 814 u32 decimator, sample_rate;
854 u16 tx_fs_reg; 815 u16 tx_fs_reg;
855 struct device *va_dev = component->dev 816 struct device *va_dev = component->dev;
856 struct va_macro *va = snd_soc_componen 817 struct va_macro *va = snd_soc_component_get_drvdata(component);
857 818
858 sample_rate = params_rate(params); 819 sample_rate = params_rate(params);
859 switch (sample_rate) { 820 switch (sample_rate) {
860 case 8000: 821 case 8000:
861 tx_fs_rate = 0; 822 tx_fs_rate = 0;
862 break; 823 break;
863 case 16000: 824 case 16000:
864 tx_fs_rate = 1; 825 tx_fs_rate = 1;
865 break; 826 break;
866 case 32000: 827 case 32000:
867 tx_fs_rate = 3; 828 tx_fs_rate = 3;
868 break; 829 break;
869 case 48000: 830 case 48000:
870 tx_fs_rate = 4; 831 tx_fs_rate = 4;
871 break; 832 break;
872 case 96000: 833 case 96000:
873 tx_fs_rate = 5; 834 tx_fs_rate = 5;
874 break; 835 break;
875 case 192000: 836 case 192000:
876 tx_fs_rate = 6; 837 tx_fs_rate = 6;
877 break; 838 break;
878 case 384000: 839 case 384000:
879 tx_fs_rate = 7; 840 tx_fs_rate = 7;
880 break; 841 break;
881 default: 842 default:
882 dev_err(va_dev, "%s: Invalid T 843 dev_err(va_dev, "%s: Invalid TX sample rate: %d\n",
883 __func__, params_rate( 844 __func__, params_rate(params));
884 return -EINVAL; 845 return -EINVAL;
885 } 846 }
886 847
887 for_each_set_bit(decimator, &va->activ 848 for_each_set_bit(decimator, &va->active_ch_mask[dai->id],
888 VA_MACRO_DEC_MAX) { 849 VA_MACRO_DEC_MAX) {
889 tx_fs_reg = CDC_VA_TX0_TX_PATH 850 tx_fs_reg = CDC_VA_TX0_TX_PATH_CTL +
890 VA_MACRO_TX_PATH_O 851 VA_MACRO_TX_PATH_OFFSET * decimator;
891 snd_soc_component_update_bits( 852 snd_soc_component_update_bits(component, tx_fs_reg, 0x0F,
892 853 tx_fs_rate);
893 } 854 }
894 return 0; 855 return 0;
895 } 856 }
896 857
897 static int va_macro_get_channel_map(const stru !! 858 static int va_macro_get_channel_map(struct snd_soc_dai *dai,
898 unsigned i 859 unsigned int *tx_num, unsigned int *tx_slot,
899 unsigned i 860 unsigned int *rx_num, unsigned int *rx_slot)
900 { 861 {
901 struct snd_soc_component *component = 862 struct snd_soc_component *component = dai->component;
902 struct device *va_dev = component->dev 863 struct device *va_dev = component->dev;
903 struct va_macro *va = snd_soc_componen 864 struct va_macro *va = snd_soc_component_get_drvdata(component);
904 865
905 switch (dai->id) { 866 switch (dai->id) {
906 case VA_MACRO_AIF1_CAP: 867 case VA_MACRO_AIF1_CAP:
907 case VA_MACRO_AIF2_CAP: 868 case VA_MACRO_AIF2_CAP:
908 case VA_MACRO_AIF3_CAP: 869 case VA_MACRO_AIF3_CAP:
909 *tx_slot = va->active_ch_mask[ 870 *tx_slot = va->active_ch_mask[dai->id];
910 *tx_num = va->active_ch_cnt[da 871 *tx_num = va->active_ch_cnt[dai->id];
911 break; 872 break;
912 default: 873 default:
913 dev_err(va_dev, "%s: Invalid A 874 dev_err(va_dev, "%s: Invalid AIF\n", __func__);
914 break; 875 break;
915 } 876 }
916 return 0; 877 return 0;
917 } 878 }
918 879
919 static int va_macro_digital_mute(struct snd_so 880 static int va_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
920 { 881 {
921 struct snd_soc_component *component = 882 struct snd_soc_component *component = dai->component;
922 struct va_macro *va = snd_soc_componen 883 struct va_macro *va = snd_soc_component_get_drvdata(component);
923 u16 tx_vol_ctl_reg, decimator; 884 u16 tx_vol_ctl_reg, decimator;
924 885
925 for_each_set_bit(decimator, &va->activ 886 for_each_set_bit(decimator, &va->active_ch_mask[dai->id],
926 VA_MACRO_DEC_MAX) { 887 VA_MACRO_DEC_MAX) {
927 tx_vol_ctl_reg = CDC_VA_TX0_TX 888 tx_vol_ctl_reg = CDC_VA_TX0_TX_PATH_CTL +
928 VA_MAC 889 VA_MACRO_TX_PATH_OFFSET * decimator;
929 if (mute) 890 if (mute)
930 snd_soc_component_upda 891 snd_soc_component_update_bits(component, tx_vol_ctl_reg,
931 CDC_VA 892 CDC_VA_TX_PATH_PGA_MUTE_EN_MASK,
932 CDC_VA 893 CDC_VA_TX_PATH_PGA_MUTE_EN);
933 else 894 else
934 snd_soc_component_upda 895 snd_soc_component_update_bits(component, tx_vol_ctl_reg,
935 CDC_VA 896 CDC_VA_TX_PATH_PGA_MUTE_EN_MASK,
936 CDC_VA 897 CDC_VA_TX_PATH_PGA_MUTE_DISABLE);
937 } 898 }
938 899
939 return 0; 900 return 0;
940 } 901 }
941 902
942 static const struct snd_soc_dai_ops va_macro_d 903 static const struct snd_soc_dai_ops va_macro_dai_ops = {
943 .hw_params = va_macro_hw_params, 904 .hw_params = va_macro_hw_params,
944 .get_channel_map = va_macro_get_channe 905 .get_channel_map = va_macro_get_channel_map,
945 .mute_stream = va_macro_digital_mute, 906 .mute_stream = va_macro_digital_mute,
946 }; 907 };
947 908
948 static struct snd_soc_dai_driver va_macro_dais 909 static struct snd_soc_dai_driver va_macro_dais[] = {
949 { 910 {
950 .name = "va_macro_tx1", 911 .name = "va_macro_tx1",
951 .id = VA_MACRO_AIF1_CAP, 912 .id = VA_MACRO_AIF1_CAP,
952 .capture = { 913 .capture = {
953 .stream_name = "VA_AIF 914 .stream_name = "VA_AIF1 Capture",
954 .rates = VA_MACRO_RATE 915 .rates = VA_MACRO_RATES,
955 .formats = VA_MACRO_FO 916 .formats = VA_MACRO_FORMATS,
956 .rate_max = 192000, 917 .rate_max = 192000,
957 .rate_min = 8000, 918 .rate_min = 8000,
958 .channels_min = 1, 919 .channels_min = 1,
959 .channels_max = 8, 920 .channels_max = 8,
960 }, 921 },
961 .ops = &va_macro_dai_ops, 922 .ops = &va_macro_dai_ops,
962 }, 923 },
963 { 924 {
964 .name = "va_macro_tx2", 925 .name = "va_macro_tx2",
965 .id = VA_MACRO_AIF2_CAP, 926 .id = VA_MACRO_AIF2_CAP,
966 .capture = { 927 .capture = {
967 .stream_name = "VA_AIF 928 .stream_name = "VA_AIF2 Capture",
968 .rates = VA_MACRO_RATE 929 .rates = VA_MACRO_RATES,
969 .formats = VA_MACRO_FO 930 .formats = VA_MACRO_FORMATS,
970 .rate_max = 192000, 931 .rate_max = 192000,
971 .rate_min = 8000, 932 .rate_min = 8000,
972 .channels_min = 1, 933 .channels_min = 1,
973 .channels_max = 8, 934 .channels_max = 8,
974 }, 935 },
975 .ops = &va_macro_dai_ops, 936 .ops = &va_macro_dai_ops,
976 }, 937 },
977 { 938 {
978 .name = "va_macro_tx3", 939 .name = "va_macro_tx3",
979 .id = VA_MACRO_AIF3_CAP, 940 .id = VA_MACRO_AIF3_CAP,
980 .capture = { 941 .capture = {
981 .stream_name = "VA_AIF 942 .stream_name = "VA_AIF3 Capture",
982 .rates = VA_MACRO_RATE 943 .rates = VA_MACRO_RATES,
983 .formats = VA_MACRO_FO 944 .formats = VA_MACRO_FORMATS,
984 .rate_max = 192000, 945 .rate_max = 192000,
985 .rate_min = 8000, 946 .rate_min = 8000,
986 .channels_min = 1, 947 .channels_min = 1,
987 .channels_max = 8, 948 .channels_max = 8,
988 }, 949 },
989 .ops = &va_macro_dai_ops, 950 .ops = &va_macro_dai_ops,
990 }, 951 },
991 }; 952 };
992 953
993 static const char * const adc_mux_text[] = { 954 static const char * const adc_mux_text[] = {
994 "VA_DMIC", "SWR_MIC" 955 "VA_DMIC", "SWR_MIC"
995 }; 956 };
996 957
997 static SOC_ENUM_SINGLE_DECL(va_dec0_enum, CDC_ 958 static SOC_ENUM_SINGLE_DECL(va_dec0_enum, CDC_VA_INP_MUX_ADC_MUX0_CFG1,
998 0, adc_mux_text); 959 0, adc_mux_text);
999 static SOC_ENUM_SINGLE_DECL(va_dec1_enum, CDC_ 960 static SOC_ENUM_SINGLE_DECL(va_dec1_enum, CDC_VA_INP_MUX_ADC_MUX1_CFG1,
1000 0, adc_mux_text); 961 0, adc_mux_text);
1001 static SOC_ENUM_SINGLE_DECL(va_dec2_enum, CDC 962 static SOC_ENUM_SINGLE_DECL(va_dec2_enum, CDC_VA_INP_MUX_ADC_MUX2_CFG1,
1002 0, adc_mux_text); 963 0, adc_mux_text);
1003 static SOC_ENUM_SINGLE_DECL(va_dec3_enum, CDC 964 static SOC_ENUM_SINGLE_DECL(va_dec3_enum, CDC_VA_INP_MUX_ADC_MUX3_CFG1,
1004 0, adc_mux_text); 965 0, adc_mux_text);
1005 966
1006 static const struct snd_kcontrol_new va_dec0_ 967 static const struct snd_kcontrol_new va_dec0_mux = SOC_DAPM_ENUM("va_dec0",
1007 968 va_dec0_enum);
1008 static const struct snd_kcontrol_new va_dec1_ 969 static const struct snd_kcontrol_new va_dec1_mux = SOC_DAPM_ENUM("va_dec1",
1009 970 va_dec1_enum);
1010 static const struct snd_kcontrol_new va_dec2_ 971 static const struct snd_kcontrol_new va_dec2_mux = SOC_DAPM_ENUM("va_dec2",
1011 972 va_dec2_enum);
1012 static const struct snd_kcontrol_new va_dec3_ 973 static const struct snd_kcontrol_new va_dec3_mux = SOC_DAPM_ENUM("va_dec3",
1013 974 va_dec3_enum);
1014 975
1015 static const char * const dmic_mux_text[] = { 976 static const char * const dmic_mux_text[] = {
1016 "ZERO", "DMIC0", "DMIC1", "DMIC2", "D 977 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3",
1017 "DMIC4", "DMIC5", "DMIC6", "DMIC7" 978 "DMIC4", "DMIC5", "DMIC6", "DMIC7"
1018 }; 979 };
1019 980
1020 static SOC_ENUM_SINGLE_DECL(va_dmic0_enum, CD 981 static SOC_ENUM_SINGLE_DECL(va_dmic0_enum, CDC_VA_INP_MUX_ADC_MUX0_CFG0,
1021 4, dmic_mux_text); 982 4, dmic_mux_text);
1022 983
1023 static SOC_ENUM_SINGLE_DECL(va_dmic1_enum, CD 984 static SOC_ENUM_SINGLE_DECL(va_dmic1_enum, CDC_VA_INP_MUX_ADC_MUX1_CFG0,
1024 4, dmic_mux_text); 985 4, dmic_mux_text);
1025 986
1026 static SOC_ENUM_SINGLE_DECL(va_dmic2_enum, CD 987 static SOC_ENUM_SINGLE_DECL(va_dmic2_enum, CDC_VA_INP_MUX_ADC_MUX2_CFG0,
1027 4, dmic_mux_text); 988 4, dmic_mux_text);
1028 989
1029 static SOC_ENUM_SINGLE_DECL(va_dmic3_enum, CD 990 static SOC_ENUM_SINGLE_DECL(va_dmic3_enum, CDC_VA_INP_MUX_ADC_MUX3_CFG0,
1030 4, dmic_mux_text); 991 4, dmic_mux_text);
1031 992
1032 static const struct snd_kcontrol_new va_dmic0 993 static const struct snd_kcontrol_new va_dmic0_mux = SOC_DAPM_ENUM_EXT("va_dmic0",
1033 va_dmic0_enum, snd_s 994 va_dmic0_enum, snd_soc_dapm_get_enum_double,
1034 va_macro_put_dec_enu 995 va_macro_put_dec_enum);
1035 996
1036 static const struct snd_kcontrol_new va_dmic1 997 static const struct snd_kcontrol_new va_dmic1_mux = SOC_DAPM_ENUM_EXT("va_dmic1",
1037 va_dmic1_enum, snd_s 998 va_dmic1_enum, snd_soc_dapm_get_enum_double,
1038 va_macro_put_dec_enu 999 va_macro_put_dec_enum);
1039 1000
1040 static const struct snd_kcontrol_new va_dmic2 1001 static const struct snd_kcontrol_new va_dmic2_mux = SOC_DAPM_ENUM_EXT("va_dmic2",
1041 va_dmic2_enum, snd_s 1002 va_dmic2_enum, snd_soc_dapm_get_enum_double,
1042 va_macro_put_dec_enu 1003 va_macro_put_dec_enum);
1043 1004
1044 static const struct snd_kcontrol_new va_dmic3 1005 static const struct snd_kcontrol_new va_dmic3_mux = SOC_DAPM_ENUM_EXT("va_dmic3",
1045 va_dmic3_enum, snd_s 1006 va_dmic3_enum, snd_soc_dapm_get_enum_double,
1046 va_macro_put_dec_enu 1007 va_macro_put_dec_enum);
1047 1008
1048 static const struct snd_kcontrol_new va_aif1_ 1009 static const struct snd_kcontrol_new va_aif1_cap_mixer[] = {
1049 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, 1010 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0,
1050 va_macro_tx_mixer_get 1011 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1051 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, 1012 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0,
1052 va_macro_tx_mixer_get 1013 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1053 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, 1014 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0,
1054 va_macro_tx_mixer_get 1015 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1055 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, 1016 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0,
1056 va_macro_tx_mixer_get 1017 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1057 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, 1018 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0,
1058 va_macro_tx_mixer_get 1019 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1059 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, 1020 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0,
1060 va_macro_tx_mixer_get 1021 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1061 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, 1022 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0,
1062 va_macro_tx_mixer_get 1023 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1063 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, 1024 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0,
1064 va_macro_tx_mixer_get 1025 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1065 }; 1026 };
1066 1027
1067 static const struct snd_kcontrol_new va_aif2_ 1028 static const struct snd_kcontrol_new va_aif2_cap_mixer[] = {
1068 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, 1029 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0,
1069 va_macro_tx_mixer_get 1030 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1070 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, 1031 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0,
1071 va_macro_tx_mixer_get 1032 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1072 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, 1033 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0,
1073 va_macro_tx_mixer_get 1034 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1074 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, 1035 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0,
1075 va_macro_tx_mixer_get 1036 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1076 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, 1037 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0,
1077 va_macro_tx_mixer_get 1038 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1078 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, 1039 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0,
1079 va_macro_tx_mixer_get 1040 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1080 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, 1041 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0,
1081 va_macro_tx_mixer_get 1042 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1082 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, 1043 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0,
1083 va_macro_tx_mixer_get 1044 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1084 }; 1045 };
1085 1046
1086 static const struct snd_kcontrol_new va_aif3_ 1047 static const struct snd_kcontrol_new va_aif3_cap_mixer[] = {
1087 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, 1048 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0,
1088 va_macro_tx_mixer_get 1049 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1089 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, 1050 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0,
1090 va_macro_tx_mixer_get 1051 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1091 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, 1052 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0,
1092 va_macro_tx_mixer_get 1053 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1093 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, 1054 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0,
1094 va_macro_tx_mixer_get 1055 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1095 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, 1056 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0,
1096 va_macro_tx_mixer_get 1057 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1097 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, 1058 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0,
1098 va_macro_tx_mixer_get 1059 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1099 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, 1060 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0,
1100 va_macro_tx_mixer_get 1061 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1101 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, 1062 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0,
1102 va_macro_tx_mixer_get 1063 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1103 }; 1064 };
1104 1065
1105 static const struct snd_soc_dapm_widget va_ma 1066 static const struct snd_soc_dapm_widget va_macro_dapm_widgets[] = {
1106 SND_SOC_DAPM_AIF_OUT("VA_AIF1 CAP", " 1067 SND_SOC_DAPM_AIF_OUT("VA_AIF1 CAP", "VA_AIF1 Capture", 0,
1107 SND_SOC_NOPM, VA_MACRO_AIF1_C 1068 SND_SOC_NOPM, VA_MACRO_AIF1_CAP, 0),
1108 1069
1109 SND_SOC_DAPM_AIF_OUT("VA_AIF2 CAP", " 1070 SND_SOC_DAPM_AIF_OUT("VA_AIF2 CAP", "VA_AIF2 Capture", 0,
1110 SND_SOC_NOPM, VA_MACRO_AIF2_C 1071 SND_SOC_NOPM, VA_MACRO_AIF2_CAP, 0),
1111 1072
1112 SND_SOC_DAPM_AIF_OUT("VA_AIF3 CAP", " 1073 SND_SOC_DAPM_AIF_OUT("VA_AIF3 CAP", "VA_AIF3 Capture", 0,
1113 SND_SOC_NOPM, VA_MACRO_AIF3_C 1074 SND_SOC_NOPM, VA_MACRO_AIF3_CAP, 0),
1114 1075
1115 SND_SOC_DAPM_MIXER("VA_AIF1_CAP Mixer 1076 SND_SOC_DAPM_MIXER("VA_AIF1_CAP Mixer", SND_SOC_NOPM,
1116 VA_MACRO_AIF1_CAP, 0, 1077 VA_MACRO_AIF1_CAP, 0,
1117 va_aif1_cap_mixer, ARRAY_SIZE 1078 va_aif1_cap_mixer, ARRAY_SIZE(va_aif1_cap_mixer)),
1118 1079
1119 SND_SOC_DAPM_MIXER("VA_AIF2_CAP Mixer 1080 SND_SOC_DAPM_MIXER("VA_AIF2_CAP Mixer", SND_SOC_NOPM,
1120 VA_MACRO_AIF2_CAP, 0, 1081 VA_MACRO_AIF2_CAP, 0,
1121 va_aif2_cap_mixer, ARRAY_SIZE 1082 va_aif2_cap_mixer, ARRAY_SIZE(va_aif2_cap_mixer)),
1122 1083
1123 SND_SOC_DAPM_MIXER("VA_AIF3_CAP Mixer 1084 SND_SOC_DAPM_MIXER("VA_AIF3_CAP Mixer", SND_SOC_NOPM,
1124 VA_MACRO_AIF3_CAP, 0, 1085 VA_MACRO_AIF3_CAP, 0,
1125 va_aif3_cap_mixer, ARRAY_SIZE 1086 va_aif3_cap_mixer, ARRAY_SIZE(va_aif3_cap_mixer)),
1126 1087
1127 SND_SOC_DAPM_MUX("VA DMIC MUX0", SND_ 1088 SND_SOC_DAPM_MUX("VA DMIC MUX0", SND_SOC_NOPM, 0, 0, &va_dmic0_mux),
1128 SND_SOC_DAPM_MUX("VA DMIC MUX1", SND_ 1089 SND_SOC_DAPM_MUX("VA DMIC MUX1", SND_SOC_NOPM, 0, 0, &va_dmic1_mux),
1129 SND_SOC_DAPM_MUX("VA DMIC MUX2", SND_ 1090 SND_SOC_DAPM_MUX("VA DMIC MUX2", SND_SOC_NOPM, 0, 0, &va_dmic2_mux),
1130 SND_SOC_DAPM_MUX("VA DMIC MUX3", SND_ 1091 SND_SOC_DAPM_MUX("VA DMIC MUX3", SND_SOC_NOPM, 0, 0, &va_dmic3_mux),
1131 1092
1132 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-mi 1093 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micb", 0, 0),
1133 SND_SOC_DAPM_INPUT("DMIC0 Pin"), 1094 SND_SOC_DAPM_INPUT("DMIC0 Pin"),
1134 SND_SOC_DAPM_INPUT("DMIC1 Pin"), 1095 SND_SOC_DAPM_INPUT("DMIC1 Pin"),
1135 SND_SOC_DAPM_INPUT("DMIC2 Pin"), 1096 SND_SOC_DAPM_INPUT("DMIC2 Pin"),
1136 SND_SOC_DAPM_INPUT("DMIC3 Pin"), 1097 SND_SOC_DAPM_INPUT("DMIC3 Pin"),
1137 SND_SOC_DAPM_INPUT("DMIC4 Pin"), 1098 SND_SOC_DAPM_INPUT("DMIC4 Pin"),
1138 SND_SOC_DAPM_INPUT("DMIC5 Pin"), 1099 SND_SOC_DAPM_INPUT("DMIC5 Pin"),
1139 SND_SOC_DAPM_INPUT("DMIC6 Pin"), 1100 SND_SOC_DAPM_INPUT("DMIC6 Pin"),
1140 SND_SOC_DAPM_INPUT("DMIC7 Pin"), 1101 SND_SOC_DAPM_INPUT("DMIC7 Pin"),
1141 1102
1142 SND_SOC_DAPM_ADC_E("VA DMIC0", NULL, 1103 SND_SOC_DAPM_ADC_E("VA DMIC0", NULL, SND_SOC_NOPM, 0, 0,
1143 va_macro_enable_dmic, SND_SOC 1104 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1144 SND_SOC_DAPM_POST_PMD), 1105 SND_SOC_DAPM_POST_PMD),
1145 1106
1146 SND_SOC_DAPM_ADC_E("VA DMIC1", NULL, 1107 SND_SOC_DAPM_ADC_E("VA DMIC1", NULL, SND_SOC_NOPM, 1, 0,
1147 va_macro_enable_dmic, SND_SOC 1108 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1148 SND_SOC_DAPM_POST_PMD), 1109 SND_SOC_DAPM_POST_PMD),
1149 1110
1150 SND_SOC_DAPM_ADC_E("VA DMIC2", NULL, 1111 SND_SOC_DAPM_ADC_E("VA DMIC2", NULL, SND_SOC_NOPM, 2, 0,
1151 va_macro_enable_dmic, SND_SOC 1112 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1152 SND_SOC_DAPM_POST_PMD), 1113 SND_SOC_DAPM_POST_PMD),
1153 1114
1154 SND_SOC_DAPM_ADC_E("VA DMIC3", NULL, 1115 SND_SOC_DAPM_ADC_E("VA DMIC3", NULL, SND_SOC_NOPM, 3, 0,
1155 va_macro_enable_dmic, SND_SOC 1116 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1156 SND_SOC_DAPM_POST_PMD), 1117 SND_SOC_DAPM_POST_PMD),
1157 1118
1158 SND_SOC_DAPM_ADC_E("VA DMIC4", NULL, 1119 SND_SOC_DAPM_ADC_E("VA DMIC4", NULL, SND_SOC_NOPM, 4, 0,
1159 va_macro_enable_dmic, SND_SOC 1120 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1160 SND_SOC_DAPM_POST_PMD), 1121 SND_SOC_DAPM_POST_PMD),
1161 1122
1162 SND_SOC_DAPM_ADC_E("VA DMIC5", NULL, 1123 SND_SOC_DAPM_ADC_E("VA DMIC5", NULL, SND_SOC_NOPM, 5, 0,
1163 va_macro_enable_dmic, SND_SOC 1124 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1164 SND_SOC_DAPM_POST_PMD), 1125 SND_SOC_DAPM_POST_PMD),
1165 1126
1166 SND_SOC_DAPM_ADC_E("VA DMIC6", NULL, 1127 SND_SOC_DAPM_ADC_E("VA DMIC6", NULL, SND_SOC_NOPM, 6, 0,
1167 va_macro_enable_dmic, SND_SOC 1128 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1168 SND_SOC_DAPM_POST_PMD), 1129 SND_SOC_DAPM_POST_PMD),
1169 1130
1170 SND_SOC_DAPM_ADC_E("VA DMIC7", NULL, 1131 SND_SOC_DAPM_ADC_E("VA DMIC7", NULL, SND_SOC_NOPM, 7, 0,
1171 va_macro_enable_dmic, SND_SOC 1132 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1172 SND_SOC_DAPM_POST_PMD), 1133 SND_SOC_DAPM_POST_PMD),
1173 1134
1174 SND_SOC_DAPM_INPUT("VA SWR_ADC0"), 1135 SND_SOC_DAPM_INPUT("VA SWR_ADC0"),
1175 SND_SOC_DAPM_INPUT("VA SWR_ADC1"), 1136 SND_SOC_DAPM_INPUT("VA SWR_ADC1"),
1176 SND_SOC_DAPM_INPUT("VA SWR_ADC2"), 1137 SND_SOC_DAPM_INPUT("VA SWR_ADC2"),
1177 SND_SOC_DAPM_INPUT("VA SWR_ADC3"), 1138 SND_SOC_DAPM_INPUT("VA SWR_ADC3"),
1178 SND_SOC_DAPM_INPUT("VA SWR_MIC0"), 1139 SND_SOC_DAPM_INPUT("VA SWR_MIC0"),
1179 SND_SOC_DAPM_INPUT("VA SWR_MIC1"), 1140 SND_SOC_DAPM_INPUT("VA SWR_MIC1"),
1180 SND_SOC_DAPM_INPUT("VA SWR_MIC2"), 1141 SND_SOC_DAPM_INPUT("VA SWR_MIC2"),
1181 SND_SOC_DAPM_INPUT("VA SWR_MIC3"), 1142 SND_SOC_DAPM_INPUT("VA SWR_MIC3"),
1182 SND_SOC_DAPM_INPUT("VA SWR_MIC4"), 1143 SND_SOC_DAPM_INPUT("VA SWR_MIC4"),
1183 SND_SOC_DAPM_INPUT("VA SWR_MIC5"), 1144 SND_SOC_DAPM_INPUT("VA SWR_MIC5"),
1184 SND_SOC_DAPM_INPUT("VA SWR_MIC6"), 1145 SND_SOC_DAPM_INPUT("VA SWR_MIC6"),
1185 SND_SOC_DAPM_INPUT("VA SWR_MIC7"), 1146 SND_SOC_DAPM_INPUT("VA SWR_MIC7"),
1186 1147
1187 SND_SOC_DAPM_MUX_E("VA DEC0 MUX", SND 1148 SND_SOC_DAPM_MUX_E("VA DEC0 MUX", SND_SOC_NOPM, VA_MACRO_DEC0, 0,
1188 &va_dec0_mux, va_m 1149 &va_dec0_mux, va_macro_enable_dec,
1189 SND_SOC_DAPM_PRE_P 1150 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1190 SND_SOC_DAPM_PRE_P 1151 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1191 1152
1192 SND_SOC_DAPM_MUX_E("VA DEC1 MUX", SND 1153 SND_SOC_DAPM_MUX_E("VA DEC1 MUX", SND_SOC_NOPM, VA_MACRO_DEC1, 0,
1193 &va_dec1_mux, va_m 1154 &va_dec1_mux, va_macro_enable_dec,
1194 SND_SOC_DAPM_PRE_P 1155 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1195 SND_SOC_DAPM_PRE_P 1156 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1196 1157
1197 SND_SOC_DAPM_MUX_E("VA DEC2 MUX", SND 1158 SND_SOC_DAPM_MUX_E("VA DEC2 MUX", SND_SOC_NOPM, VA_MACRO_DEC2, 0,
1198 &va_dec2_mux, va_m 1159 &va_dec2_mux, va_macro_enable_dec,
1199 SND_SOC_DAPM_PRE_P 1160 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1200 SND_SOC_DAPM_PRE_P 1161 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1201 1162
1202 SND_SOC_DAPM_MUX_E("VA DEC3 MUX", SND 1163 SND_SOC_DAPM_MUX_E("VA DEC3 MUX", SND_SOC_NOPM, VA_MACRO_DEC3, 0,
1203 &va_dec3_mux, va_m 1164 &va_dec3_mux, va_macro_enable_dec,
1204 SND_SOC_DAPM_PRE_P 1165 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1205 SND_SOC_DAPM_PRE_P 1166 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1206 1167
1207 SND_SOC_DAPM_SUPPLY_S("VA_MCLK", -1, 1168 SND_SOC_DAPM_SUPPLY_S("VA_MCLK", -1, SND_SOC_NOPM, 0, 0,
1208 va_macro_mclk_e 1169 va_macro_mclk_event,
1209 SND_SOC_DAPM_PR 1170 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1210 }; 1171 };
1211 1172
1212 static const struct snd_soc_dapm_route va_aud 1173 static const struct snd_soc_dapm_route va_audio_map[] = {
1213 {"VA_AIF1 CAP", NULL, "VA_MCLK"}, 1174 {"VA_AIF1 CAP", NULL, "VA_MCLK"},
1214 {"VA_AIF2 CAP", NULL, "VA_MCLK"}, 1175 {"VA_AIF2 CAP", NULL, "VA_MCLK"},
1215 {"VA_AIF3 CAP", NULL, "VA_MCLK"}, 1176 {"VA_AIF3 CAP", NULL, "VA_MCLK"},
1216 1177
1217 {"VA_AIF1 CAP", NULL, "VA_AIF1_CAP Mi 1178 {"VA_AIF1 CAP", NULL, "VA_AIF1_CAP Mixer"},
1218 {"VA_AIF2 CAP", NULL, "VA_AIF2_CAP Mi 1179 {"VA_AIF2 CAP", NULL, "VA_AIF2_CAP Mixer"},
1219 {"VA_AIF3 CAP", NULL, "VA_AIF3_CAP Mi 1180 {"VA_AIF3 CAP", NULL, "VA_AIF3_CAP Mixer"},
1220 1181
1221 {"VA_AIF1_CAP Mixer", "DEC0", "VA DEC 1182 {"VA_AIF1_CAP Mixer", "DEC0", "VA DEC0 MUX"},
1222 {"VA_AIF1_CAP Mixer", "DEC1", "VA DEC 1183 {"VA_AIF1_CAP Mixer", "DEC1", "VA DEC1 MUX"},
1223 {"VA_AIF1_CAP Mixer", "DEC2", "VA DEC 1184 {"VA_AIF1_CAP Mixer", "DEC2", "VA DEC2 MUX"},
1224 {"VA_AIF1_CAP Mixer", "DEC3", "VA DEC 1185 {"VA_AIF1_CAP Mixer", "DEC3", "VA DEC3 MUX"},
1225 1186
1226 {"VA_AIF2_CAP Mixer", "DEC0", "VA DEC 1187 {"VA_AIF2_CAP Mixer", "DEC0", "VA DEC0 MUX"},
1227 {"VA_AIF2_CAP Mixer", "DEC1", "VA DEC 1188 {"VA_AIF2_CAP Mixer", "DEC1", "VA DEC1 MUX"},
1228 {"VA_AIF2_CAP Mixer", "DEC2", "VA DEC 1189 {"VA_AIF2_CAP Mixer", "DEC2", "VA DEC2 MUX"},
1229 {"VA_AIF2_CAP Mixer", "DEC3", "VA DEC 1190 {"VA_AIF2_CAP Mixer", "DEC3", "VA DEC3 MUX"},
1230 1191
1231 {"VA_AIF3_CAP Mixer", "DEC0", "VA DEC 1192 {"VA_AIF3_CAP Mixer", "DEC0", "VA DEC0 MUX"},
1232 {"VA_AIF3_CAP Mixer", "DEC1", "VA DEC 1193 {"VA_AIF3_CAP Mixer", "DEC1", "VA DEC1 MUX"},
1233 {"VA_AIF3_CAP Mixer", "DEC2", "VA DEC 1194 {"VA_AIF3_CAP Mixer", "DEC2", "VA DEC2 MUX"},
1234 {"VA_AIF3_CAP Mixer", "DEC3", "VA DEC 1195 {"VA_AIF3_CAP Mixer", "DEC3", "VA DEC3 MUX"},
1235 1196
1236 {"VA DEC0 MUX", "VA_DMIC", "VA DMIC M 1197 {"VA DEC0 MUX", "VA_DMIC", "VA DMIC MUX0"},
1237 {"VA DMIC MUX0", "DMIC0", "VA DMIC0"} 1198 {"VA DMIC MUX0", "DMIC0", "VA DMIC0"},
1238 {"VA DMIC MUX0", "DMIC1", "VA DMIC1"} 1199 {"VA DMIC MUX0", "DMIC1", "VA DMIC1"},
1239 {"VA DMIC MUX0", "DMIC2", "VA DMIC2"} 1200 {"VA DMIC MUX0", "DMIC2", "VA DMIC2"},
1240 {"VA DMIC MUX0", "DMIC3", "VA DMIC3"} 1201 {"VA DMIC MUX0", "DMIC3", "VA DMIC3"},
1241 {"VA DMIC MUX0", "DMIC4", "VA DMIC4"} 1202 {"VA DMIC MUX0", "DMIC4", "VA DMIC4"},
1242 {"VA DMIC MUX0", "DMIC5", "VA DMIC5"} 1203 {"VA DMIC MUX0", "DMIC5", "VA DMIC5"},
1243 {"VA DMIC MUX0", "DMIC6", "VA DMIC6"} 1204 {"VA DMIC MUX0", "DMIC6", "VA DMIC6"},
1244 {"VA DMIC MUX0", "DMIC7", "VA DMIC7"} 1205 {"VA DMIC MUX0", "DMIC7", "VA DMIC7"},
1245 1206
1246 {"VA DEC1 MUX", "VA_DMIC", "VA DMIC M 1207 {"VA DEC1 MUX", "VA_DMIC", "VA DMIC MUX1"},
1247 {"VA DMIC MUX1", "DMIC0", "VA DMIC0"} 1208 {"VA DMIC MUX1", "DMIC0", "VA DMIC0"},
1248 {"VA DMIC MUX1", "DMIC1", "VA DMIC1"} 1209 {"VA DMIC MUX1", "DMIC1", "VA DMIC1"},
1249 {"VA DMIC MUX1", "DMIC2", "VA DMIC2"} 1210 {"VA DMIC MUX1", "DMIC2", "VA DMIC2"},
1250 {"VA DMIC MUX1", "DMIC3", "VA DMIC3"} 1211 {"VA DMIC MUX1", "DMIC3", "VA DMIC3"},
1251 {"VA DMIC MUX1", "DMIC4", "VA DMIC4"} 1212 {"VA DMIC MUX1", "DMIC4", "VA DMIC4"},
1252 {"VA DMIC MUX1", "DMIC5", "VA DMIC5"} 1213 {"VA DMIC MUX1", "DMIC5", "VA DMIC5"},
1253 {"VA DMIC MUX1", "DMIC6", "VA DMIC6"} 1214 {"VA DMIC MUX1", "DMIC6", "VA DMIC6"},
1254 {"VA DMIC MUX1", "DMIC7", "VA DMIC7"} 1215 {"VA DMIC MUX1", "DMIC7", "VA DMIC7"},
1255 1216
1256 {"VA DEC2 MUX", "VA_DMIC", "VA DMIC M 1217 {"VA DEC2 MUX", "VA_DMIC", "VA DMIC MUX2"},
1257 {"VA DMIC MUX2", "DMIC0", "VA DMIC0"} 1218 {"VA DMIC MUX2", "DMIC0", "VA DMIC0"},
1258 {"VA DMIC MUX2", "DMIC1", "VA DMIC1"} 1219 {"VA DMIC MUX2", "DMIC1", "VA DMIC1"},
1259 {"VA DMIC MUX2", "DMIC2", "VA DMIC2"} 1220 {"VA DMIC MUX2", "DMIC2", "VA DMIC2"},
1260 {"VA DMIC MUX2", "DMIC3", "VA DMIC3"} 1221 {"VA DMIC MUX2", "DMIC3", "VA DMIC3"},
1261 {"VA DMIC MUX2", "DMIC4", "VA DMIC4"} 1222 {"VA DMIC MUX2", "DMIC4", "VA DMIC4"},
1262 {"VA DMIC MUX2", "DMIC5", "VA DMIC5"} 1223 {"VA DMIC MUX2", "DMIC5", "VA DMIC5"},
1263 {"VA DMIC MUX2", "DMIC6", "VA DMIC6"} 1224 {"VA DMIC MUX2", "DMIC6", "VA DMIC6"},
1264 {"VA DMIC MUX2", "DMIC7", "VA DMIC7"} 1225 {"VA DMIC MUX2", "DMIC7", "VA DMIC7"},
1265 1226
1266 {"VA DEC3 MUX", "VA_DMIC", "VA DMIC M 1227 {"VA DEC3 MUX", "VA_DMIC", "VA DMIC MUX3"},
1267 {"VA DMIC MUX3", "DMIC0", "VA DMIC0"} 1228 {"VA DMIC MUX3", "DMIC0", "VA DMIC0"},
1268 {"VA DMIC MUX3", "DMIC1", "VA DMIC1"} 1229 {"VA DMIC MUX3", "DMIC1", "VA DMIC1"},
1269 {"VA DMIC MUX3", "DMIC2", "VA DMIC2"} 1230 {"VA DMIC MUX3", "DMIC2", "VA DMIC2"},
1270 {"VA DMIC MUX3", "DMIC3", "VA DMIC3"} 1231 {"VA DMIC MUX3", "DMIC3", "VA DMIC3"},
1271 {"VA DMIC MUX3", "DMIC4", "VA DMIC4"} 1232 {"VA DMIC MUX3", "DMIC4", "VA DMIC4"},
1272 {"VA DMIC MUX3", "DMIC5", "VA DMIC5"} 1233 {"VA DMIC MUX3", "DMIC5", "VA DMIC5"},
1273 {"VA DMIC MUX3", "DMIC6", "VA DMIC6"} 1234 {"VA DMIC MUX3", "DMIC6", "VA DMIC6"},
1274 {"VA DMIC MUX3", "DMIC7", "VA DMIC7"} 1235 {"VA DMIC MUX3", "DMIC7", "VA DMIC7"},
1275 1236
1276 { "VA DMIC0", NULL, "DMIC0 Pin" }, 1237 { "VA DMIC0", NULL, "DMIC0 Pin" },
1277 { "VA DMIC1", NULL, "DMIC1 Pin" }, 1238 { "VA DMIC1", NULL, "DMIC1 Pin" },
1278 { "VA DMIC2", NULL, "DMIC2 Pin" }, 1239 { "VA DMIC2", NULL, "DMIC2 Pin" },
1279 { "VA DMIC3", NULL, "DMIC3 Pin" }, 1240 { "VA DMIC3", NULL, "DMIC3 Pin" },
1280 { "VA DMIC4", NULL, "DMIC4 Pin" }, 1241 { "VA DMIC4", NULL, "DMIC4 Pin" },
1281 { "VA DMIC5", NULL, "DMIC5 Pin" }, 1242 { "VA DMIC5", NULL, "DMIC5 Pin" },
1282 { "VA DMIC6", NULL, "DMIC6 Pin" }, 1243 { "VA DMIC6", NULL, "DMIC6 Pin" },
1283 { "VA DMIC7", NULL, "DMIC7 Pin" }, 1244 { "VA DMIC7", NULL, "DMIC7 Pin" },
1284 }; 1245 };
1285 1246
1286 static const char * const dec_mode_mux_text[] 1247 static const char * const dec_mode_mux_text[] = {
1287 "ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HI 1248 "ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HIGH_PERF",
1288 }; 1249 };
1289 1250
1290 static const struct soc_enum dec_mode_mux_enu 1251 static const struct soc_enum dec_mode_mux_enum[] = {
1291 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRA 1252 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(dec_mode_mux_text),
1292 dec_mode_mux_text), 1253 dec_mode_mux_text),
1293 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRA 1254 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(dec_mode_mux_text),
1294 dec_mode_mux_text), 1255 dec_mode_mux_text),
1295 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARR 1256 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(dec_mode_mux_text),
1296 dec_mode_mux_text), 1257 dec_mode_mux_text),
1297 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRA 1258 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(dec_mode_mux_text),
1298 dec_mode_mux_text), 1259 dec_mode_mux_text),
1299 }; 1260 };
1300 1261
1301 static const struct snd_kcontrol_new va_macro 1262 static const struct snd_kcontrol_new va_macro_snd_controls[] = {
1302 SOC_SINGLE_S8_TLV("VA_DEC0 Volume", C 1263 SOC_SINGLE_S8_TLV("VA_DEC0 Volume", CDC_VA_TX0_TX_VOL_CTL,
1303 -84, 40, digital_ga 1264 -84, 40, digital_gain),
1304 SOC_SINGLE_S8_TLV("VA_DEC1 Volume", C 1265 SOC_SINGLE_S8_TLV("VA_DEC1 Volume", CDC_VA_TX1_TX_VOL_CTL,
1305 -84, 40, digital_ga 1266 -84, 40, digital_gain),
1306 SOC_SINGLE_S8_TLV("VA_DEC2 Volume", C 1267 SOC_SINGLE_S8_TLV("VA_DEC2 Volume", CDC_VA_TX2_TX_VOL_CTL,
1307 -84, 40, digital_ga 1268 -84, 40, digital_gain),
1308 SOC_SINGLE_S8_TLV("VA_DEC3 Volume", C 1269 SOC_SINGLE_S8_TLV("VA_DEC3 Volume", CDC_VA_TX3_TX_VOL_CTL,
1309 -84, 40, digital_ga 1270 -84, 40, digital_gain),
1310 1271
1311 SOC_ENUM_EXT("VA_DEC0 MODE", dec_mode 1272 SOC_ENUM_EXT("VA_DEC0 MODE", dec_mode_mux_enum[0],
1312 va_macro_dec_mode_get, v 1273 va_macro_dec_mode_get, va_macro_dec_mode_put),
1313 SOC_ENUM_EXT("VA_DEC1 MODE", dec_mode 1274 SOC_ENUM_EXT("VA_DEC1 MODE", dec_mode_mux_enum[1],
1314 va_macro_dec_mode_get, v 1275 va_macro_dec_mode_get, va_macro_dec_mode_put),
1315 SOC_ENUM_EXT("VA_DEC2 MODE", dec_mode 1276 SOC_ENUM_EXT("VA_DEC2 MODE", dec_mode_mux_enum[2],
1316 va_macro_dec_mode_get, v 1277 va_macro_dec_mode_get, va_macro_dec_mode_put),
1317 SOC_ENUM_EXT("VA_DEC3 MODE", dec_mode 1278 SOC_ENUM_EXT("VA_DEC3 MODE", dec_mode_mux_enum[3],
1318 va_macro_dec_mode_get, v 1279 va_macro_dec_mode_get, va_macro_dec_mode_put),
1319 }; 1280 };
1320 1281
1321 static int va_macro_component_probe(struct sn 1282 static int va_macro_component_probe(struct snd_soc_component *component)
1322 { 1283 {
1323 struct va_macro *va = snd_soc_compone 1284 struct va_macro *va = snd_soc_component_get_drvdata(component);
1324 1285
1325 snd_soc_component_init_regmap(compone 1286 snd_soc_component_init_regmap(component, va->regmap);
1326 1287
1327 return 0; 1288 return 0;
1328 } 1289 }
1329 1290
1330 static const struct snd_soc_component_driver 1291 static const struct snd_soc_component_driver va_macro_component_drv = {
1331 .name = "VA MACRO", 1292 .name = "VA MACRO",
1332 .probe = va_macro_component_probe, 1293 .probe = va_macro_component_probe,
1333 .controls = va_macro_snd_controls, 1294 .controls = va_macro_snd_controls,
1334 .num_controls = ARRAY_SIZE(va_macro_s 1295 .num_controls = ARRAY_SIZE(va_macro_snd_controls),
1335 .dapm_widgets = va_macro_dapm_widgets 1296 .dapm_widgets = va_macro_dapm_widgets,
1336 .num_dapm_widgets = ARRAY_SIZE(va_mac 1297 .num_dapm_widgets = ARRAY_SIZE(va_macro_dapm_widgets),
1337 .dapm_routes = va_audio_map, 1298 .dapm_routes = va_audio_map,
1338 .num_dapm_routes = ARRAY_SIZE(va_audi 1299 .num_dapm_routes = ARRAY_SIZE(va_audio_map),
1339 }; 1300 };
1340 1301
1341 static int fsgen_gate_enable(struct clk_hw *h 1302 static int fsgen_gate_enable(struct clk_hw *hw)
1342 { 1303 {
1343 struct va_macro *va = to_va_macro(hw) !! 1304 return va_macro_mclk_enable(to_va_macro(hw), true);
1344 struct regmap *regmap = va->regmap; <<
1345 int ret; <<
1346 <<
1347 if (va->has_swr_master) { <<
1348 ret = clk_prepare_enable(va-> <<
1349 if (ret) <<
1350 return ret; <<
1351 } <<
1352 <<
1353 ret = va_macro_mclk_enable(va, true); <<
1354 if (va->has_swr_master) <<
1355 regmap_update_bits(regmap, CD <<
1356 CDC_VA_SWR <<
1357 <<
1358 return ret; <<
1359 } 1305 }
1360 1306
1361 static void fsgen_gate_disable(struct clk_hw 1307 static void fsgen_gate_disable(struct clk_hw *hw)
1362 { 1308 {
1363 struct va_macro *va = to_va_macro(hw) !! 1309 va_macro_mclk_enable(to_va_macro(hw), false);
1364 struct regmap *regmap = va->regmap; <<
1365 <<
1366 if (va->has_swr_master) <<
1367 regmap_update_bits(regmap, CD <<
1368 CDC_VA_SWR_CLK_EN_ <<
1369 <<
1370 va_macro_mclk_enable(va, false); <<
1371 if (va->has_swr_master) <<
1372 clk_disable_unprepare(va->mcl <<
1373 } 1310 }
1374 1311
1375 static int fsgen_gate_is_enabled(struct clk_h 1312 static int fsgen_gate_is_enabled(struct clk_hw *hw)
1376 { 1313 {
1377 struct va_macro *va = to_va_macro(hw) 1314 struct va_macro *va = to_va_macro(hw);
1378 int val; 1315 int val;
1379 1316
1380 regmap_read(va->regmap, CDC_VA_TOP_CS 1317 regmap_read(va->regmap, CDC_VA_TOP_CSR_TOP_CFG0, &val);
1381 1318
1382 return !!(val & CDC_VA_FS_BROADCAST_ 1319 return !!(val & CDC_VA_FS_BROADCAST_EN);
1383 } 1320 }
1384 1321
1385 static const struct clk_ops fsgen_gate_ops = 1322 static const struct clk_ops fsgen_gate_ops = {
1386 .prepare = fsgen_gate_enable, 1323 .prepare = fsgen_gate_enable,
1387 .unprepare = fsgen_gate_disable, 1324 .unprepare = fsgen_gate_disable,
1388 .is_enabled = fsgen_gate_is_enabled, 1325 .is_enabled = fsgen_gate_is_enabled,
1389 }; 1326 };
1390 1327
1391 static int va_macro_register_fsgen_output(str 1328 static int va_macro_register_fsgen_output(struct va_macro *va)
1392 { 1329 {
1393 struct clk *parent = va->mclk; 1330 struct clk *parent = va->mclk;
1394 struct device *dev = va->dev; 1331 struct device *dev = va->dev;
1395 struct device_node *np = dev->of_node 1332 struct device_node *np = dev->of_node;
1396 const char *parent_clk_name; 1333 const char *parent_clk_name;
1397 const char *clk_name = "fsgen"; 1334 const char *clk_name = "fsgen";
1398 struct clk_init_data init; 1335 struct clk_init_data init;
1399 int ret; 1336 int ret;
1400 1337
1401 if (va->has_npl_clk) <<
1402 parent = va->npl; <<
1403 <<
1404 parent_clk_name = __clk_get_name(pare 1338 parent_clk_name = __clk_get_name(parent);
1405 1339
1406 of_property_read_string(np, "clock-ou 1340 of_property_read_string(np, "clock-output-names", &clk_name);
1407 1341
1408 init.name = clk_name; 1342 init.name = clk_name;
1409 init.ops = &fsgen_gate_ops; 1343 init.ops = &fsgen_gate_ops;
1410 init.flags = 0; 1344 init.flags = 0;
1411 init.parent_names = &parent_clk_name; 1345 init.parent_names = &parent_clk_name;
1412 init.num_parents = 1; 1346 init.num_parents = 1;
1413 va->hw.init = &init; 1347 va->hw.init = &init;
1414 ret = devm_clk_hw_register(va->dev, & 1348 ret = devm_clk_hw_register(va->dev, &va->hw);
1415 if (ret) 1349 if (ret)
1416 return ret; 1350 return ret;
1417 1351
1418 return devm_of_clk_add_hw_provider(de 1352 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &va->hw);
1419 } 1353 }
1420 1354
1421 static int va_macro_validate_dmic_sample_rate 1355 static int va_macro_validate_dmic_sample_rate(u32 dmic_sample_rate,
1422 1356 struct va_macro *va)
1423 { 1357 {
1424 u32 div_factor; 1358 u32 div_factor;
1425 u32 mclk_rate = VA_MACRO_MCLK_FREQ; 1359 u32 mclk_rate = VA_MACRO_MCLK_FREQ;
1426 1360
1427 if (!dmic_sample_rate || mclk_rate % 1361 if (!dmic_sample_rate || mclk_rate % dmic_sample_rate != 0)
1428 goto undefined_rate; 1362 goto undefined_rate;
1429 1363
1430 div_factor = mclk_rate / dmic_sample_ 1364 div_factor = mclk_rate / dmic_sample_rate;
1431 1365
1432 switch (div_factor) { 1366 switch (div_factor) {
1433 case 2: 1367 case 2:
1434 va->dmic_clk_div = VA_MACRO_C 1368 va->dmic_clk_div = VA_MACRO_CLK_DIV_2;
1435 break; 1369 break;
1436 case 3: 1370 case 3:
1437 va->dmic_clk_div = VA_MACRO_C 1371 va->dmic_clk_div = VA_MACRO_CLK_DIV_3;
1438 break; 1372 break;
1439 case 4: 1373 case 4:
1440 va->dmic_clk_div = VA_MACRO_C 1374 va->dmic_clk_div = VA_MACRO_CLK_DIV_4;
1441 break; 1375 break;
1442 case 6: 1376 case 6:
1443 va->dmic_clk_div = VA_MACRO_C 1377 va->dmic_clk_div = VA_MACRO_CLK_DIV_6;
1444 break; 1378 break;
1445 case 8: 1379 case 8:
1446 va->dmic_clk_div = VA_MACRO_C 1380 va->dmic_clk_div = VA_MACRO_CLK_DIV_8;
1447 break; 1381 break;
1448 case 16: 1382 case 16:
1449 va->dmic_clk_div = VA_MACRO_C 1383 va->dmic_clk_div = VA_MACRO_CLK_DIV_16;
1450 break; 1384 break;
1451 default: 1385 default:
1452 /* Any other DIV factor is in 1386 /* Any other DIV factor is invalid */
1453 goto undefined_rate; 1387 goto undefined_rate;
1454 } 1388 }
1455 1389
1456 return dmic_sample_rate; 1390 return dmic_sample_rate;
1457 1391
1458 undefined_rate: 1392 undefined_rate:
1459 dev_err(va->dev, "%s: Invalid rate %d 1393 dev_err(va->dev, "%s: Invalid rate %d, for mclk %d\n",
1460 __func__, dmic_sample_rate, m 1394 __func__, dmic_sample_rate, mclk_rate);
1461 dmic_sample_rate = 0; 1395 dmic_sample_rate = 0;
1462 1396
1463 return dmic_sample_rate; 1397 return dmic_sample_rate;
1464 } 1398 }
1465 1399
1466 static void va_macro_set_lpass_codec_version( <<
1467 { <<
1468 int core_id_0 = 0, core_id_1 = 0, cor <<
1469 int version = LPASS_CODEC_VERSION_UNK <<
1470 <<
1471 regmap_read(va->regmap, CDC_VA_TOP_CS <<
1472 regmap_read(va->regmap, CDC_VA_TOP_CS <<
1473 regmap_read(va->regmap, CDC_VA_TOP_CS <<
1474 <<
1475 if ((core_id_0 == 0x01) && (core_id_1 <<
1476 version = LPASS_CODEC_VERSION <<
1477 if ((core_id_0 == 0x02) && (core_id_1 <<
1478 version = LPASS_CODEC_VERSION <<
1479 if ((core_id_0 == 0x02) && (core_id_1 <<
1480 version = LPASS_CODEC_VERSION <<
1481 if ((core_id_0 == 0x02) && (core_id_1 <<
1482 version = LPASS_CODEC_VERSION <<
1483 if ((core_id_0 == 0x02) && (core_id_1 <<
1484 version = LPASS_CODEC_VERSION <<
1485 if ((core_id_0 == 0x02) && (core_id_1 <<
1486 version = LPASS_CODEC_VERSION <<
1487 if ((core_id_0 == 0x02) && (core_id_1 <<
1488 version = LPASS_CODEC_VERSION <<
1489 <<
1490 if (version == LPASS_CODEC_VERSION_UN <<
1491 dev_warn(va->dev, "Unknown Co <<
1492 core_id_0, core_id_1 <<
1493 <<
1494 lpass_macro_set_codec_version(version <<
1495 <<
1496 dev_dbg(va->dev, "LPASS Codec Version <<
1497 } <<
1498 <<
1499 static int va_macro_probe(struct platform_dev 1400 static int va_macro_probe(struct platform_device *pdev)
1500 { 1401 {
1501 struct device *dev = &pdev->dev; 1402 struct device *dev = &pdev->dev;
1502 const struct va_macro_data *data; <<
1503 struct va_macro *va; 1403 struct va_macro *va;
1504 void __iomem *base; 1404 void __iomem *base;
1505 u32 sample_rate = 0; 1405 u32 sample_rate = 0;
1506 int ret; 1406 int ret;
1507 1407
1508 va = devm_kzalloc(dev, sizeof(*va), G 1408 va = devm_kzalloc(dev, sizeof(*va), GFP_KERNEL);
1509 if (!va) 1409 if (!va)
1510 return -ENOMEM; 1410 return -ENOMEM;
1511 1411
1512 va->dev = dev; 1412 va->dev = dev;
1513 1413
1514 va->macro = devm_clk_get_optional(dev 1414 va->macro = devm_clk_get_optional(dev, "macro");
1515 if (IS_ERR(va->macro)) 1415 if (IS_ERR(va->macro))
1516 return dev_err_probe(dev, PTR !! 1416 return PTR_ERR(va->macro);
1517 1417
1518 va->dcodec = devm_clk_get_optional(de 1418 va->dcodec = devm_clk_get_optional(dev, "dcodec");
1519 if (IS_ERR(va->dcodec)) 1419 if (IS_ERR(va->dcodec))
1520 return dev_err_probe(dev, PTR !! 1420 return PTR_ERR(va->dcodec);
1521 1421
1522 va->mclk = devm_clk_get(dev, "mclk"); 1422 va->mclk = devm_clk_get(dev, "mclk");
1523 if (IS_ERR(va->mclk)) 1423 if (IS_ERR(va->mclk))
1524 return dev_err_probe(dev, PTR !! 1424 return PTR_ERR(va->mclk);
1525 1425
1526 va->pds = lpass_macro_pds_init(dev); 1426 va->pds = lpass_macro_pds_init(dev);
1527 if (IS_ERR(va->pds)) 1427 if (IS_ERR(va->pds))
1528 return PTR_ERR(va->pds); 1428 return PTR_ERR(va->pds);
1529 1429
1530 ret = of_property_read_u32(dev->of_no 1430 ret = of_property_read_u32(dev->of_node, "qcom,dmic-sample-rate",
1531 &sample_ra 1431 &sample_rate);
1532 if (ret) { 1432 if (ret) {
1533 dev_err(dev, "qcom,dmic-sampl 1433 dev_err(dev, "qcom,dmic-sample-rate dt entry missing\n");
1534 va->dmic_clk_div = VA_MACRO_C 1434 va->dmic_clk_div = VA_MACRO_CLK_DIV_2;
1535 } else { 1435 } else {
1536 ret = va_macro_validate_dmic_ 1436 ret = va_macro_validate_dmic_sample_rate(sample_rate, va);
1537 if (!ret) { 1437 if (!ret) {
1538 ret = -EINVAL; 1438 ret = -EINVAL;
1539 goto err; 1439 goto err;
1540 } 1440 }
1541 } 1441 }
1542 1442
1543 base = devm_platform_ioremap_resource 1443 base = devm_platform_ioremap_resource(pdev, 0);
1544 if (IS_ERR(base)) { 1444 if (IS_ERR(base)) {
1545 ret = PTR_ERR(base); 1445 ret = PTR_ERR(base);
1546 goto err; 1446 goto err;
1547 } 1447 }
1548 1448
1549 va->regmap = devm_regmap_init_mmio(de 1449 va->regmap = devm_regmap_init_mmio(dev, base, &va_regmap_config);
1550 if (IS_ERR(va->regmap)) { 1450 if (IS_ERR(va->regmap)) {
1551 ret = -EINVAL; 1451 ret = -EINVAL;
1552 goto err; 1452 goto err;
1553 } 1453 }
1554 1454
1555 dev_set_drvdata(dev, va); 1455 dev_set_drvdata(dev, va);
1556 1456
1557 data = of_device_get_match_data(dev); <<
1558 va->has_swr_master = data->has_swr_ma <<
1559 va->has_npl_clk = data->has_npl_clk; <<
1560 <<
1561 /* mclk rate */ 1457 /* mclk rate */
1562 clk_set_rate(va->mclk, 2 * VA_MACRO_M 1458 clk_set_rate(va->mclk, 2 * VA_MACRO_MCLK_FREQ);
1563 1459
1564 if (va->has_npl_clk) { <<
1565 va->npl = devm_clk_get(dev, " <<
1566 if (IS_ERR(va->npl)) { <<
1567 ret = PTR_ERR(va->npl <<
1568 goto err; <<
1569 } <<
1570 <<
1571 clk_set_rate(va->npl, 2 * VA_ <<
1572 } <<
1573 <<
1574 ret = clk_prepare_enable(va->macro); 1460 ret = clk_prepare_enable(va->macro);
1575 if (ret) 1461 if (ret)
1576 goto err; 1462 goto err;
1577 1463
1578 ret = clk_prepare_enable(va->dcodec); 1464 ret = clk_prepare_enable(va->dcodec);
1579 if (ret) 1465 if (ret)
1580 goto err_dcodec; 1466 goto err_dcodec;
1581 1467
1582 ret = clk_prepare_enable(va->mclk); 1468 ret = clk_prepare_enable(va->mclk);
1583 if (ret) 1469 if (ret)
1584 goto err_mclk; 1470 goto err_mclk;
1585 1471
1586 if (va->has_npl_clk) { !! 1472 ret = va_macro_register_fsgen_output(va);
1587 ret = clk_prepare_enable(va-> !! 1473 if (ret)
1588 if (ret) !! 1474 goto err_clkout;
1589 goto err_npl; <<
1590 } <<
1591 <<
1592 /** <<
1593 * old version of codecs do not have <<
1594 * version from registers, get them f <<
1595 */ <<
1596 if (data->version) <<
1597 lpass_macro_set_codec_version <<
1598 else /* read version from register */ <<
1599 va_macro_set_lpass_codec_vers <<
1600 <<
1601 if (va->has_swr_master) { <<
1602 /* Set default CLK div to 1 * <<
1603 regmap_update_bits(va->regmap <<
1604 CDC_VA_SWR_ <<
1605 CDC_VA_SWR_ <<
1606 regmap_update_bits(va->regmap <<
1607 CDC_VA_SWR_ <<
1608 CDC_VA_SWR_ <<
1609 regmap_update_bits(va->regmap <<
1610 CDC_VA_SWR_ <<
1611 CDC_VA_SWR_ <<
1612 <<
1613 } <<
1614 <<
1615 if (va->has_swr_master) { <<
1616 regmap_update_bits(va->regmap <<
1617 CDC_VA_SWR <<
1618 regmap_update_bits(va->regmap <<
1619 CDC_VA_SWR <<
1620 regmap_update_bits(va->regmap <<
1621 CDC_VA_SWR <<
1622 } <<
1623 1475
1624 ret = devm_snd_soc_register_component 1476 ret = devm_snd_soc_register_component(dev, &va_macro_component_drv,
1625 1477 va_macro_dais,
1626 1478 ARRAY_SIZE(va_macro_dais));
1627 if (ret) 1479 if (ret)
1628 goto err_clkout; 1480 goto err_clkout;
1629 1481
1630 pm_runtime_set_autosuspend_delay(dev, 1482 pm_runtime_set_autosuspend_delay(dev, 3000);
1631 pm_runtime_use_autosuspend(dev); 1483 pm_runtime_use_autosuspend(dev);
1632 pm_runtime_mark_last_busy(dev); 1484 pm_runtime_mark_last_busy(dev);
1633 pm_runtime_set_active(dev); 1485 pm_runtime_set_active(dev);
1634 pm_runtime_enable(dev); 1486 pm_runtime_enable(dev);
1635 1487
1636 ret = va_macro_register_fsgen_output( <<
1637 if (ret) <<
1638 goto err_clkout; <<
1639 <<
1640 va->fsgen = clk_hw_get_clk(&va->hw, " <<
1641 if (IS_ERR(va->fsgen)) { <<
1642 ret = PTR_ERR(va->fsgen); <<
1643 goto err_clkout; <<
1644 } <<
1645 <<
1646 return 0; 1488 return 0;
1647 1489
1648 err_clkout: 1490 err_clkout:
1649 if (va->has_npl_clk) <<
1650 clk_disable_unprepare(va->npl <<
1651 err_npl: <<
1652 clk_disable_unprepare(va->mclk); 1491 clk_disable_unprepare(va->mclk);
1653 err_mclk: 1492 err_mclk:
1654 clk_disable_unprepare(va->dcodec); 1493 clk_disable_unprepare(va->dcodec);
1655 err_dcodec: 1494 err_dcodec:
1656 clk_disable_unprepare(va->macro); 1495 clk_disable_unprepare(va->macro);
1657 err: 1496 err:
1658 lpass_macro_pds_exit(va->pds); 1497 lpass_macro_pds_exit(va->pds);
1659 1498
1660 return ret; 1499 return ret;
1661 } 1500 }
1662 1501
1663 static void va_macro_remove(struct platform_d !! 1502 static int va_macro_remove(struct platform_device *pdev)
1664 { 1503 {
1665 struct va_macro *va = dev_get_drvdata 1504 struct va_macro *va = dev_get_drvdata(&pdev->dev);
1666 1505
1667 if (va->has_npl_clk) <<
1668 clk_disable_unprepare(va->npl <<
1669 <<
1670 clk_disable_unprepare(va->mclk); 1506 clk_disable_unprepare(va->mclk);
1671 clk_disable_unprepare(va->dcodec); 1507 clk_disable_unprepare(va->dcodec);
1672 clk_disable_unprepare(va->macro); 1508 clk_disable_unprepare(va->macro);
1673 1509
1674 lpass_macro_pds_exit(va->pds); 1510 lpass_macro_pds_exit(va->pds);
>> 1511
>> 1512 return 0;
1675 } 1513 }
1676 1514
1677 static int __maybe_unused va_macro_runtime_su 1515 static int __maybe_unused va_macro_runtime_suspend(struct device *dev)
1678 { 1516 {
1679 struct va_macro *va = dev_get_drvdata 1517 struct va_macro *va = dev_get_drvdata(dev);
1680 1518
1681 regcache_cache_only(va->regmap, true) 1519 regcache_cache_only(va->regmap, true);
1682 regcache_mark_dirty(va->regmap); 1520 regcache_mark_dirty(va->regmap);
1683 1521
1684 if (va->has_npl_clk) <<
1685 clk_disable_unprepare(va->npl <<
1686 <<
1687 clk_disable_unprepare(va->mclk); 1522 clk_disable_unprepare(va->mclk);
1688 1523
1689 return 0; 1524 return 0;
1690 } 1525 }
1691 1526
1692 static int __maybe_unused va_macro_runtime_re 1527 static int __maybe_unused va_macro_runtime_resume(struct device *dev)
1693 { 1528 {
1694 struct va_macro *va = dev_get_drvdata 1529 struct va_macro *va = dev_get_drvdata(dev);
1695 int ret; 1530 int ret;
1696 1531
1697 ret = clk_prepare_enable(va->mclk); 1532 ret = clk_prepare_enable(va->mclk);
1698 if (ret) { 1533 if (ret) {
1699 dev_err(va->dev, "unable to p 1534 dev_err(va->dev, "unable to prepare mclk\n");
1700 return ret; 1535 return ret;
1701 } 1536 }
1702 1537
1703 if (va->has_npl_clk) { <<
1704 ret = clk_prepare_enable(va-> <<
1705 if (ret) { <<
1706 clk_disable_unprepare <<
1707 dev_err(va->dev, "una <<
1708 return ret; <<
1709 } <<
1710 } <<
1711 <<
1712 regcache_cache_only(va->regmap, false 1538 regcache_cache_only(va->regmap, false);
1713 regcache_sync(va->regmap); 1539 regcache_sync(va->regmap);
1714 1540
1715 return 0; 1541 return 0;
1716 } 1542 }
1717 1543
1718 1544
1719 static const struct dev_pm_ops va_macro_pm_op 1545 static const struct dev_pm_ops va_macro_pm_ops = {
1720 SET_RUNTIME_PM_OPS(va_macro_runtime_s 1546 SET_RUNTIME_PM_OPS(va_macro_runtime_suspend, va_macro_runtime_resume, NULL)
1721 }; 1547 };
1722 1548
1723 static const struct of_device_id va_macro_dt_ 1549 static const struct of_device_id va_macro_dt_match[] = {
1724 { .compatible = "qcom,sc7280-lpass-va !! 1550 { .compatible = "qcom,sc7280-lpass-va-macro" },
1725 { .compatible = "qcom,sm8250-lpass-va !! 1551 { .compatible = "qcom,sm8250-lpass-va-macro" },
1726 { .compatible = "qcom,sm8450-lpass-va <<
1727 { .compatible = "qcom,sm8550-lpass-va <<
1728 { .compatible = "qcom,sc8280xp-lpass- <<
1729 {} 1552 {}
1730 }; 1553 };
1731 MODULE_DEVICE_TABLE(of, va_macro_dt_match); 1554 MODULE_DEVICE_TABLE(of, va_macro_dt_match);
1732 1555
1733 static struct platform_driver va_macro_driver 1556 static struct platform_driver va_macro_driver = {
1734 .driver = { 1557 .driver = {
1735 .name = "va_macro", 1558 .name = "va_macro",
1736 .of_match_table = va_macro_dt 1559 .of_match_table = va_macro_dt_match,
1737 .suppress_bind_attrs = true, 1560 .suppress_bind_attrs = true,
1738 .pm = &va_macro_pm_ops, 1561 .pm = &va_macro_pm_ops,
1739 }, 1562 },
1740 .probe = va_macro_probe, 1563 .probe = va_macro_probe,
1741 .remove = va_macro_remove, 1564 .remove = va_macro_remove,
1742 }; 1565 };
1743 1566
1744 module_platform_driver(va_macro_driver); 1567 module_platform_driver(va_macro_driver);
1745 MODULE_DESCRIPTION("VA macro driver"); 1568 MODULE_DESCRIPTION("VA macro driver");
1746 MODULE_LICENSE("GPL"); 1569 MODULE_LICENSE("GPL");
1747 1570
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