1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* 2 /*
3 * max98388.h -- MAX98388 ALSA SoC audio drive 3 * max98388.h -- MAX98388 ALSA SoC audio driver header
4 * 4 *
5 * Copyright(c) 2022, Analog Devices Inc. 5 * Copyright(c) 2022, Analog Devices Inc.
6 */ 6 */
7 7
8 #ifndef _MAX98388_H 8 #ifndef _MAX98388_H
9 #define _MAX98388_H 9 #define _MAX98388_H
10 10
11 /* Device Status Registers */ 11 /* Device Status Registers */
12 #define MAX98388_R2000_SW_RESET 12 #define MAX98388_R2000_SW_RESET 0x2000
13 #define MAX98388_R2001_INT_RAW1 13 #define MAX98388_R2001_INT_RAW1 0x2001
14 #define MAX98388_R2002_INT_RAW2 14 #define MAX98388_R2002_INT_RAW2 0x2002
15 #define MAX98388_R2004_INT_STATE1 15 #define MAX98388_R2004_INT_STATE1 0x2004
16 #define MAX98388_R2005_INT_STATE2 16 #define MAX98388_R2005_INT_STATE2 0x2005
17 /* Thermal Protection Registers */ 17 /* Thermal Protection Registers */
18 #define MAX98388_R2020_THERM_WARN_THRESH 18 #define MAX98388_R2020_THERM_WARN_THRESH 0x2020
19 /* Error Monitor */ 19 /* Error Monitor */
20 #define MAX98388_R2031_SPK_MON_THRESH 20 #define MAX98388_R2031_SPK_MON_THRESH 0x2031
21 #define MAX98388_R2032_SPK_MON_LD_SEL 21 #define MAX98388_R2032_SPK_MON_LD_SEL 0x2032
22 #define MAX98388_R2033_SPK_MON_DURATION 22 #define MAX98388_R2033_SPK_MON_DURATION 0x2033
23 #define MAX98388_R2037_ERR_MON_CTRL 23 #define MAX98388_R2037_ERR_MON_CTRL 0x2037
24 /* PCM Registers */ 24 /* PCM Registers */
25 #define MAX98388_R2040_PCM_MODE_CFG 25 #define MAX98388_R2040_PCM_MODE_CFG 0x2040
26 #define MAX98388_R2041_PCM_CLK_SETUP 26 #define MAX98388_R2041_PCM_CLK_SETUP 0x2041
27 #define MAX98388_R2042_PCM_SR_SETUP 27 #define MAX98388_R2042_PCM_SR_SETUP 0x2042
28 #define MAX98388_R2044_PCM_TX_CTRL1 28 #define MAX98388_R2044_PCM_TX_CTRL1 0x2044
29 #define MAX98388_R2045_PCM_TX_CTRL2 29 #define MAX98388_R2045_PCM_TX_CTRL2 0x2045
30 #define MAX98388_R2050_PCM_TX_HIZ_CTRL1 30 #define MAX98388_R2050_PCM_TX_HIZ_CTRL1 0x2050
31 #define MAX98388_R2051_PCM_TX_HIZ_CTRL2 31 #define MAX98388_R2051_PCM_TX_HIZ_CTRL2 0x2051
32 #define MAX98388_R2052_PCM_TX_HIZ_CTRL3 32 #define MAX98388_R2052_PCM_TX_HIZ_CTRL3 0x2052
33 #define MAX98388_R2053_PCM_TX_HIZ_CTRL4 33 #define MAX98388_R2053_PCM_TX_HIZ_CTRL4 0x2053
34 #define MAX98388_R2054_PCM_TX_HIZ_CTRL5 34 #define MAX98388_R2054_PCM_TX_HIZ_CTRL5 0x2054
35 #define MAX98388_R2055_PCM_TX_HIZ_CTRL6 35 #define MAX98388_R2055_PCM_TX_HIZ_CTRL6 0x2055
36 #define MAX98388_R2056_PCM_TX_HIZ_CTRL7 36 #define MAX98388_R2056_PCM_TX_HIZ_CTRL7 0x2056
37 #define MAX98388_R2057_PCM_TX_HIZ_CTRL8 37 #define MAX98388_R2057_PCM_TX_HIZ_CTRL8 0x2057
38 #define MAX98388_R2058_PCM_RX_SRC1 38 #define MAX98388_R2058_PCM_RX_SRC1 0x2058
39 #define MAX98388_R2059_PCM_RX_SRC2 39 #define MAX98388_R2059_PCM_RX_SRC2 0x2059
40 #define MAX98388_R205C_PCM_TX_DRIVE_STRENGTH 40 #define MAX98388_R205C_PCM_TX_DRIVE_STRENGTH 0x205C
41 #define MAX98388_R205D_PCM_TX_SRC_EN 41 #define MAX98388_R205D_PCM_TX_SRC_EN 0x205D
42 #define MAX98388_R205E_PCM_RX_EN 42 #define MAX98388_R205E_PCM_RX_EN 0x205E
43 #define MAX98388_R205F_PCM_TX_EN 43 #define MAX98388_R205F_PCM_TX_EN 0x205F
44 /* Speaker Channel Control */ 44 /* Speaker Channel Control */
45 #define MAX98388_R2090_SPK_CH_VOL_CTRL 45 #define MAX98388_R2090_SPK_CH_VOL_CTRL 0x2090
46 #define MAX98388_R2091_SPK_CH_CFG 46 #define MAX98388_R2091_SPK_CH_CFG 0x2091
47 #define MAX98388_R2092_SPK_AMP_OUT_CFG 47 #define MAX98388_R2092_SPK_AMP_OUT_CFG 0x2092
48 #define MAX98388_R2093_SPK_AMP_SSM_CFG 48 #define MAX98388_R2093_SPK_AMP_SSM_CFG 0x2093
49 #define MAX98388_R2094_SPK_AMP_ER_CTRL 49 #define MAX98388_R2094_SPK_AMP_ER_CTRL 0x2094
50 #define MAX98388_R209E_SPK_CH_PINK_NOISE_EN 50 #define MAX98388_R209E_SPK_CH_PINK_NOISE_EN 0x209E
51 #define MAX98388_R209F_SPK_CH_AMP_EN 51 #define MAX98388_R209F_SPK_CH_AMP_EN 0x209F
52 #define MAX98388_R20A0_IV_DATA_DSP_CTRL 52 #define MAX98388_R20A0_IV_DATA_DSP_CTRL 0x20A0
53 #define MAX98388_R20A7_IV_DATA_EN 53 #define MAX98388_R20A7_IV_DATA_EN 0x20A7
54 #define MAX98388_R20E0_BP_ALC_THRESH 54 #define MAX98388_R20E0_BP_ALC_THRESH 0x20E0
55 #define MAX98388_R20E1_BP_ALC_RATES 55 #define MAX98388_R20E1_BP_ALC_RATES 0x20E1
56 #define MAX98388_R20E2_BP_ALC_ATTEN 56 #define MAX98388_R20E2_BP_ALC_ATTEN 0x20E2
57 #define MAX98388_R20E3_BP_ALC_REL 57 #define MAX98388_R20E3_BP_ALC_REL 0x20E3
58 #define MAX98388_R20E4_BP_ALC_MUTE 58 #define MAX98388_R20E4_BP_ALC_MUTE 0x20E4
59 #define MAX98388_R20EE_BP_INF_HOLD_REL 59 #define MAX98388_R20EE_BP_INF_HOLD_REL 0x20EE
60 #define MAX98388_R20EF_BP_ALC_EN 60 #define MAX98388_R20EF_BP_ALC_EN 0x20EF
61 #define MAX98388_R210E_AUTO_RESTART 61 #define MAX98388_R210E_AUTO_RESTART 0x210E
62 #define MAX98388_R210F_GLOBAL_EN 62 #define MAX98388_R210F_GLOBAL_EN 0x210F
63 #define MAX98388_R22FF_REV_ID 63 #define MAX98388_R22FF_REV_ID 0x22FF
64 64
65 /* MAX98388_R2000_SW_RESET */ 65 /* MAX98388_R2000_SW_RESET */
66 #define MAX98388_SOFT_RESET 66 #define MAX98388_SOFT_RESET (0x1 << 0)
67 67
68 /* MAX98388_R2020_THERM_WARN_THRESH */ 68 /* MAX98388_R2020_THERM_WARN_THRESH */
69 #define MAX98388_THERM_SHDN_THRESH_SHIFT 69 #define MAX98388_THERM_SHDN_THRESH_SHIFT (0)
70 #define MAX98388_THERM_WARN_THRESH_SHIFT 70 #define MAX98388_THERM_WARN_THRESH_SHIFT (2)
71 71
72 /* MAX98388_R2022_PCM_TX_SRC_1 */ 72 /* MAX98388_R2022_PCM_TX_SRC_1 */
73 #define MAX98388_PCM_TX_CH_SRC_A_V_SHIFT 73 #define MAX98388_PCM_TX_CH_SRC_A_V_SHIFT (0)
74 #define MAX98388_PCM_TX_CH_SRC_A_I_SHIFT 74 #define MAX98388_PCM_TX_CH_SRC_A_I_SHIFT (4)
75 75
76 /* MAX98388_R2024_PCM_DATA_FMT_CFG */ 76 /* MAX98388_R2024_PCM_DATA_FMT_CFG */
77 #define MAX98388_PCM_MODE_CFG_FORMAT_MASK 77 #define MAX98388_PCM_MODE_CFG_FORMAT_MASK (0x7 << 3)
78 #define MAX98388_PCM_MODE_CFG_FORMAT_SHIFT 78 #define MAX98388_PCM_MODE_CFG_FORMAT_SHIFT (3)
79 #define MAX98388_PCM_TX_CH_INTERLEAVE_MASK 79 #define MAX98388_PCM_TX_CH_INTERLEAVE_MASK (0x1 << 2)
80 #define MAX98388_PCM_FORMAT_I2S 80 #define MAX98388_PCM_FORMAT_I2S (0x0 << 0)
81 #define MAX98388_PCM_FORMAT_LJ 81 #define MAX98388_PCM_FORMAT_LJ (0x1 << 0)
82 #define MAX98388_PCM_FORMAT_TDM_MODE0 82 #define MAX98388_PCM_FORMAT_TDM_MODE0 (0x3 << 0)
83 #define MAX98388_PCM_FORMAT_TDM_MODE1 83 #define MAX98388_PCM_FORMAT_TDM_MODE1 (0x4 << 0)
84 #define MAX98388_PCM_FORMAT_TDM_MODE2 84 #define MAX98388_PCM_FORMAT_TDM_MODE2 (0x5 << 0)
85 #define MAX98388_PCM_MODE_CFG_CHANSZ_MASK 85 #define MAX98388_PCM_MODE_CFG_CHANSZ_MASK (0x3 << 6)
86 #define MAX98388_PCM_MODE_CFG_CHANSZ_16 86 #define MAX98388_PCM_MODE_CFG_CHANSZ_16 (0x1 << 6)
87 #define MAX98388_PCM_MODE_CFG_CHANSZ_24 87 #define MAX98388_PCM_MODE_CFG_CHANSZ_24 (0x2 << 6)
88 #define MAX98388_PCM_MODE_CFG_CHANSZ_32 88 #define MAX98388_PCM_MODE_CFG_CHANSZ_32 (0x3 << 6)
89 89
90 /* MAX98388_R2031_SPK_MON_THRESH */ 90 /* MAX98388_R2031_SPK_MON_THRESH */
91 #define MAX98388_SPKMON_THRESH_SHIFT 91 #define MAX98388_SPKMON_THRESH_SHIFT (0)
92 92
93 /* MAX98388_R2032_SPK_MON_LD_SEL */ 93 /* MAX98388_R2032_SPK_MON_LD_SEL */
94 #define MAX98388_SPKMON_LOAD_SHIFT 94 #define MAX98388_SPKMON_LOAD_SHIFT (0)
95 95
96 /* MAX98388_R2033_SPK_MON_DURATION */ 96 /* MAX98388_R2033_SPK_MON_DURATION */
97 #define MAX98388_SPKMON_DURATION_SHIFT 97 #define MAX98388_SPKMON_DURATION_SHIFT (0)
98 98
99 /* MAX98388_R2037_ERR_MON_CTRL */ 99 /* MAX98388_R2037_ERR_MON_CTRL */
100 #define MAX98388_CLOCK_MON_SHIFT 100 #define MAX98388_CLOCK_MON_SHIFT (0)
101 #define MAX98388_SPK_MON_SHIFT 101 #define MAX98388_SPK_MON_SHIFT (1)
102 102
103 /* MAX98388_R203E_AMP_PATH_GAIN */ 103 /* MAX98388_R203E_AMP_PATH_GAIN */
104 #define MAX98388_SPK_DIGI_GAIN_MASK 104 #define MAX98388_SPK_DIGI_GAIN_MASK (0xF << 4)
105 #define MAX98388_SPK_DIGI_GAIN_SHIFT 105 #define MAX98388_SPK_DIGI_GAIN_SHIFT (4)
106 #define MAX98388_FS_GAIN_MAX_MASK 106 #define MAX98388_FS_GAIN_MAX_MASK (0xF << 0)
107 #define MAX98388_FS_GAIN_MAX_SHIFT 107 #define MAX98388_FS_GAIN_MAX_SHIFT (0)
108 108
109 /* MAX98388_R2041_PCM_CLK_SETUP */ 109 /* MAX98388_R2041_PCM_CLK_SETUP */
110 #define MAX98388_PCM_MODE_CFG_PCM_BCLKEDGE 110 #define MAX98388_PCM_MODE_CFG_PCM_BCLKEDGE (0x1 << 4)
111 #define MAX98388_PCM_CLK_SETUP_BSEL_MASK 111 #define MAX98388_PCM_CLK_SETUP_BSEL_MASK (0xF << 0)
112 112
113 /* MAX98388_R2042_PCM_SR_SETUP */ 113 /* MAX98388_R2042_PCM_SR_SETUP */
114 #define MAX98388_PCM_SR_MASK 114 #define MAX98388_PCM_SR_MASK (0xF << 0)
115 #define MAX98388_PCM_SR_IV_MASK 115 #define MAX98388_PCM_SR_IV_MASK (0xF << 4)
116 #define MAX98388_PCM_SR_IV_SHIFT 116 #define MAX98388_PCM_SR_IV_SHIFT (4)
117 #define MAX98388_PCM_SR_8000 117 #define MAX98388_PCM_SR_8000 (0x0 << 0)
118 #define MAX98388_PCM_SR_11025 118 #define MAX98388_PCM_SR_11025 (0x1 << 0)
119 #define MAX98388_PCM_SR_12000 119 #define MAX98388_PCM_SR_12000 (0x2 << 0)
120 #define MAX98388_PCM_SR_16000 120 #define MAX98388_PCM_SR_16000 (0x3 << 0)
121 #define MAX98388_PCM_SR_22050 121 #define MAX98388_PCM_SR_22050 (0x4 << 0)
122 #define MAX98388_PCM_SR_24000 122 #define MAX98388_PCM_SR_24000 (0x5 << 0)
123 #define MAX98388_PCM_SR_32000 123 #define MAX98388_PCM_SR_32000 (0x6 << 0)
124 #define MAX98388_PCM_SR_44100 124 #define MAX98388_PCM_SR_44100 (0x7 << 0)
125 #define MAX98388_PCM_SR_48000 125 #define MAX98388_PCM_SR_48000 (0x8 << 0)
126 #define MAX98388_PCM_SR_88200 126 #define MAX98388_PCM_SR_88200 (0x9 << 0)
127 #define MAX98388_PCM_SR_96000 127 #define MAX98388_PCM_SR_96000 (0xA << 0)
128 128
129 /* MAX98388_R2043_AMP_EN */ 129 /* MAX98388_R2043_AMP_EN */
130 #define MAX98388_SPK_EN_MASK 130 #define MAX98388_SPK_EN_MASK (0x1 << 0)
131 #define MAX98388_SPKFB_EN_MASK 131 #define MAX98388_SPKFB_EN_MASK (0x1 << 1)
132 #define MAX98388_SPKFB_EN_SHIFT 132 #define MAX98388_SPKFB_EN_SHIFT (1)
133 133
134 /* MAX98388_R2052_MEAS_ADC_PVDD_FLT_CFG */ 134 /* MAX98388_R2052_MEAS_ADC_PVDD_FLT_CFG */
135 #define MAX98388_FLT_EN_SHIFT 135 #define MAX98388_FLT_EN_SHIFT (4)
136 136
137 /* MAX98388_R2058_PCM_RX_SRC1 */ 137 /* MAX98388_R2058_PCM_RX_SRC1 */
138 #define MAX98388_PCM_TO_SPK_MONOMIX_CFG_SHIFT 138 #define MAX98388_PCM_TO_SPK_MONOMIX_CFG_SHIFT (0)
139 139
140 /* MAX98388_R2059_PCM_RX_SRC2 */ 140 /* MAX98388_R2059_PCM_RX_SRC2 */
141 #define MAX98388_RX_SRC_CH0_SHIFT 141 #define MAX98388_RX_SRC_CH0_SHIFT (0)
142 #define MAX98388_RX_SRC_CH1_SHIFT 142 #define MAX98388_RX_SRC_CH1_SHIFT (4)
143 143
144 /* MAX98388_R2091_SPK_CH_CFG */ 144 /* MAX98388_R2091_SPK_CH_CFG */
145 #define MAX98388_SPK_CFG_DCBLK_SHIFT 145 #define MAX98388_SPK_CFG_DCBLK_SHIFT (0)
146 #define MAX98388_SPK_CFG_DITH_EN_SHIFT 146 #define MAX98388_SPK_CFG_DITH_EN_SHIFT (1)
147 #define MAX98388_SPK_CFG_INV_SHIFT 147 #define MAX98388_SPK_CFG_INV_SHIFT (2)
148 #define MAX98388_SPK_CFG_VOL_RMPUP_SHIFT 148 #define MAX98388_SPK_CFG_VOL_RMPUP_SHIFT (3)
149 #define MAX98388_SPK_CFG_VOL_RMPDN_SHIFT 149 #define MAX98388_SPK_CFG_VOL_RMPDN_SHIFT (4)
150 150
151 /* MAX98388_R2092_SPK_AMP_OUT_CFG */ 151 /* MAX98388_R2092_SPK_AMP_OUT_CFG */
152 #define MAX98388_SPK_AMP_OUT_GAIN_SHIFT 152 #define MAX98388_SPK_AMP_OUT_GAIN_SHIFT (0)
153 #define MAX98388_SPK_AMP_OUT_MODE_SHIFT 153 #define MAX98388_SPK_AMP_OUT_MODE_SHIFT (3)
154 154
155 /* MAX98388_R2093_SPK_AMP_SSM_CFG */ 155 /* MAX98388_R2093_SPK_AMP_SSM_CFG */
156 #define MAX98388_SPK_AMP_SSM_EN_SHIFT 156 #define MAX98388_SPK_AMP_SSM_EN_SHIFT (0)
157 #define MAX98388_SPK_AMP_SSM_MOD_SHIFT 157 #define MAX98388_SPK_AMP_SSM_MOD_SHIFT (1)
158 158
159 /* MAX98388_R2094_SPK_AMP_ER_CTRL */ 159 /* MAX98388_R2094_SPK_AMP_ER_CTRL */
160 #define MAX98388_EDGE_RATE_RISE_SHIFT 160 #define MAX98388_EDGE_RATE_RISE_SHIFT (0)
161 #define MAX98388_EDGE_RATE_FALL_SHIFT 161 #define MAX98388_EDGE_RATE_FALL_SHIFT (2)
162 162
163 /* MAX98388_R209E_SPK_CH_PINK_NOISE_EN */ 163 /* MAX98388_R209E_SPK_CH_PINK_NOISE_EN */
164 #define MAX98388_PINK_NOISE_GEN_SHIFT 164 #define MAX98388_PINK_NOISE_GEN_SHIFT (0)
165 165
166 /* MAX98388_R20A0_IV_DATA_DSP_CTRL */ 166 /* MAX98388_R20A0_IV_DATA_DSP_CTRL */
167 #define MAX98388_AMP_DSP_CTRL_VOL_DCBLK_SHIFT 167 #define MAX98388_AMP_DSP_CTRL_VOL_DCBLK_SHIFT (0)
168 #define MAX98388_AMP_DSP_CTRL_CUR_DCBLK_SHIFT 168 #define MAX98388_AMP_DSP_CTRL_CUR_DCBLK_SHIFT (1)
169 #define MAX98388_AMP_DSP_CTRL_VOL_INV_SHIFT 169 #define MAX98388_AMP_DSP_CTRL_VOL_INV_SHIFT (2)
170 #define MAX98388_AMP_DSP_CTRL_CUR_INV_SHIFT 170 #define MAX98388_AMP_DSP_CTRL_CUR_INV_SHIFT (3)
171 #define MAX98388_AMP_DSP_CTRL_DITH_SHIFT 171 #define MAX98388_AMP_DSP_CTRL_DITH_SHIFT (4)
172 172
173 /* MAX98388_R20B2_BDE_L4_CFG_2 */ 173 /* MAX98388_R20B2_BDE_L4_CFG_2 */
174 #define MAX98388_LVL4_HOLD_EN_SHIFT 174 #define MAX98388_LVL4_HOLD_EN_SHIFT (6)
175 #define MAX98388_LVL4_MUTE_EN_SHIFT 175 #define MAX98388_LVL4_MUTE_EN_SHIFT (7)
176 176
177 /* MAX98388_R20B5_BDE_EN */ 177 /* MAX98388_R20B5_BDE_EN */
178 #define MAX98388_BDE_EN_SHIFT 178 #define MAX98388_BDE_EN_SHIFT (0)
179 179
180 /* MAX98388_R20D1_DHT_CFG */ 180 /* MAX98388_R20D1_DHT_CFG */
181 #define MAX98388_DHT_ROT_PNT_SHIFT 181 #define MAX98388_DHT_ROT_PNT_SHIFT (0)
182 #define MAX98388_DHT_SPK_GAIN_MIN_SHIFT 182 #define MAX98388_DHT_SPK_GAIN_MIN_SHIFT (4)
183 183
184 /* MAX98388_R20D2_DHT_ATTACK_CFG */ 184 /* MAX98388_R20D2_DHT_ATTACK_CFG */
185 #define MAX98388_DHT_ATTACK_RATE_SHIFT 185 #define MAX98388_DHT_ATTACK_RATE_SHIFT (0)
186 #define MAX98388_DHT_ATTACK_STEP_SHIFT 186 #define MAX98388_DHT_ATTACK_STEP_SHIFT (3)
187 187
188 /* MAX98388_R20D3_DHT_RELEASE_CFG */ 188 /* MAX98388_R20D3_DHT_RELEASE_CFG */
189 #define MAX98388_DHT_RELEASE_RATE_SHIFT 189 #define MAX98388_DHT_RELEASE_RATE_SHIFT (0)
190 #define MAX98388_DHT_RELEASE_STEP_SHIFT 190 #define MAX98388_DHT_RELEASE_STEP_SHIFT (3)
191 191
192 /* MAX98388_R20D4_DHT_EN */ 192 /* MAX98388_R20D4_DHT_EN */
193 #define MAX98388_DHT_EN_SHIFT 193 #define MAX98388_DHT_EN_SHIFT (0)
194 194
195 /* MAX98388_R20E0_BP_ALC_THRESH */ 195 /* MAX98388_R20E0_BP_ALC_THRESH */
196 #define MAX98388_ALC_THRESH_SHIFT 196 #define MAX98388_ALC_THRESH_SHIFT (0)
197 197
198 /* MAX98388_R20E1_BP_ALC_RATES */ 198 /* MAX98388_R20E1_BP_ALC_RATES */
199 #define MAX98388_ALC_RELEASE_RATE_SHIFT 199 #define MAX98388_ALC_RELEASE_RATE_SHIFT (0)
200 #define MAX98388_ALC_ATTACK_RATE_SHIFT 200 #define MAX98388_ALC_ATTACK_RATE_SHIFT (4)
201 201
202 /* MAX98388_R20E2_BP_ALC_ATTEN */ 202 /* MAX98388_R20E2_BP_ALC_ATTEN */
203 #define MAX98388_ALC_MAX_ATTEN_SHIFT 203 #define MAX98388_ALC_MAX_ATTEN_SHIFT (0)
204 204
205 /* MAX98388_R20E3_BP_ALC_REL */ 205 /* MAX98388_R20E3_BP_ALC_REL */
206 #define MAX98388_ALC_DEBOUNCE_TIME_SHIFT 206 #define MAX98388_ALC_DEBOUNCE_TIME_SHIFT (0)
207 207
208 /* MAX98388_R20E4_BP_ALC_MUTE */ 208 /* MAX98388_R20E4_BP_ALC_MUTE */
209 #define MAX98388_ALC_MUTE_EN_SHIFT 209 #define MAX98388_ALC_MUTE_EN_SHIFT (0)
210 #define MAX98388_ALC_MUTE_DELAY_SHIFT 210 #define MAX98388_ALC_MUTE_DELAY_SHIFT (1)
211 #define MAX98388_ALC_MUTE_RAMP_EN_SHIFT 211 #define MAX98388_ALC_MUTE_RAMP_EN_SHIFT (4)
212 #define MAX98388_ALC_UNMUTE_RAMP_EN_SHIFT 212 #define MAX98388_ALC_UNMUTE_RAMP_EN_SHIFT (5)
213 213
214 /* MAX98388_R210E_AUTO_RESTART */ 214 /* MAX98388_R210E_AUTO_RESTART */
215 #define MAX98388_PVDD_UVLO_AUTORESTART_SHIFT 215 #define MAX98388_PVDD_UVLO_AUTORESTART_SHIFT (0)
216 #define MAX98388_THERM_AUTORESTART_SHIFT 216 #define MAX98388_THERM_AUTORESTART_SHIFT (1)
217 #define MAX98388_OVC_AUTORESTART_SHIFT 217 #define MAX98388_OVC_AUTORESTART_SHIFT (2)
218 #define MAX98388_CMON_AUTORESTART_SHIFT 218 #define MAX98388_CMON_AUTORESTART_SHIFT (3)
219 219
220 /* MAX98388_R210F_GLOBAL_EN */ 220 /* MAX98388_R210F_GLOBAL_EN */
221 #define MAX98388_GLOBAL_EN_MASK 221 #define MAX98388_GLOBAL_EN_MASK (0x1 << 0)
222 222
223 struct max98388_priv { 223 struct max98388_priv {
224 struct regmap *regmap; 224 struct regmap *regmap;
225 struct gpio_desc *reset_gpio; 225 struct gpio_desc *reset_gpio;
226 unsigned int v_slot; 226 unsigned int v_slot;
227 unsigned int i_slot; 227 unsigned int i_slot;
228 unsigned int spkfb_slot; 228 unsigned int spkfb_slot;
229 bool interleave_mode; 229 bool interleave_mode;
230 unsigned int ch_size; 230 unsigned int ch_size;
231 bool tdm_mode; 231 bool tdm_mode;
232 }; 232 };
233 233
234 #endif 234 #endif
235 235
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