1 /* SPDX-License-Identifier: GPL-2.0 */ 1
2 /*
3 * max98396.h -- MAX98396 ALSA SoC audio drive
4 *
5 * Copyright(c) 2022, Analog Devices Inc.
6 */
7
8 #ifndef _MAX98396_H
9 #define _MAX98396_H
10
11 #define MAX98396_R2000_SW_RESET
12 #define MAX98396_R2001_INT_RAW1
13 #define MAX98396_R2002_INT_RAW2
14 #define MAX98396_R2003_INT_RAW3
15 #define MAX98396_R2004_INT_RAW4
16 #define MAX98396_R2006_INT_STATE1
17 #define MAX98396_R2007_INT_STATE2
18 #define MAX98396_R2008_INT_STATE3
19 #define MAX98396_R2009_INT_STATE4
20 #define MAX98396_R200B_INT_FLAG1
21 #define MAX98396_R200C_INT_FLAG2
22 #define MAX98396_R200D_INT_FLAG3
23 #define MAX98396_R200E_INT_FLAG4
24 #define MAX98396_R2010_INT_EN1
25 #define MAX98396_R2011_INT_EN2
26 #define MAX98396_R2012_INT_EN3
27 #define MAX98396_R2013_INT_EN4
28 #define MAX98396_R2015_INT_FLAG_CLR1
29 #define MAX98396_R2016_INT_FLAG_CLR2
30 #define MAX98396_R2017_INT_FLAG_CLR3
31 #define MAX98396_R2018_INT_FLAG_CLR4
32 #define MAX98396_R201F_IRQ_CTRL
33 #define MAX98396_R2020_THERM_WARN_THRESH
34 #define MAX98396_R2021_THERM_WARN_THRESH2
35 #define MAX98396_R2022_THERM_SHDN_THRESH
36 #define MAX98396_R2023_THERM_HYSTERESIS
37 #define MAX98396_R2024_THERM_FOLDBACK_SET
38 #define MAX98396_R2027_THERM_FOLDBACK_EN
39 #define MAX98396_R2030_NOISEGATE_MODE_CTRL
40 #define MAX98396_R2033_NOISEGATE_MODE_EN
41 #define MAX98396_R2038_CLK_MON_CTRL
42 #define MAX98396_R2039_DATA_MON_CTRL
43 #define MAX98396_R203F_ENABLE_CTRLS
44 #define MAX98396_R2040_PIN_CFG
45 #define MAX98396_R2041_PCM_MODE_CFG
46 #define MAX98396_R2042_PCM_CLK_SETUP
47 #define MAX98396_R2043_PCM_SR_SETUP
48 #define MAX98396_R2044_PCM_TX_CTRL_1
49 #define MAX98396_R2045_PCM_TX_CTRL_2
50 #define MAX98396_R2046_PCM_TX_CTRL_3
51 #define MAX98396_R2047_PCM_TX_CTRL_4
52 #define MAX98396_R2048_PCM_TX_CTRL_5
53 #define MAX98396_R2049_PCM_TX_CTRL_6
54 #define MAX98396_R204A_PCM_TX_CTRL_7
55 #define MAX98396_R204B_PCM_TX_CTRL_8
56 #define MAX98396_R204C_PCM_TX_HIZ_CTRL_1
57 #define MAX98396_R204D_PCM_TX_HIZ_CTRL_2
58 #define MAX98396_R204E_PCM_TX_HIZ_CTRL_3
59 #define MAX98396_R204F_PCM_TX_HIZ_CTRL_4
60 #define MAX98396_R2050_PCM_TX_HIZ_CTRL_5
61 #define MAX98396_R2051_PCM_TX_HIZ_CTRL_6
62 #define MAX98396_R2052_PCM_TX_HIZ_CTRL_7
63 #define MAX98396_R2053_PCM_TX_HIZ_CTRL_8
64 #define MAX98396_R2055_PCM_RX_SRC1
65 #define MAX98396_R2056_PCM_RX_SRC2
66 #define MAX98396_R2058_PCM_BYPASS_SRC
67 #define MAX98396_R205D_PCM_TX_SRC_EN
68 #define MAX98396_R205E_PCM_RX_EN
69 #define MAX98396_R205F_PCM_TX_EN
70 #define MAX98396_R2070_ICC_RX_EN_A
71 #define MAX98396_R2071_ICC_RX_EN_B
72 #define MAX98396_R2072_ICC_TX_CTRL
73 #define MAX98396_R207F_ICC_EN
74 #define MAX98396_R2083_TONE_GEN_DC_CFG
75 #define MAX98396_R2084_TONE_GEN_DC_LVL1
76 #define MAX98396_R2085_TONE_GEN_DC_LVL2
77 #define MAX98396_R2086_TONE_GEN_DC_LVL3
78 #define MAX98396_R208F_TONE_GEN_EN
79 #define MAX98396_R2090_AMP_VOL_CTRL
80 #define MAX98396_R2091_AMP_PATH_GAIN
81 #define MAX98396_R2092_AMP_DSP_CFG
82 #define MAX98396_R2093_SSM_CFG
83 #define MAX98396_R2094_SPK_CLS_DG_THRESH
84 #define MAX98396_R2095_SPK_CLS_DG_HDR
85 #define MAX98396_R2096_SPK_CLS_DG_HOLD_TIME
86 #define MAX98396_R2097_SPK_CLS_DG_DELAY
87 #define MAX98396_R2098_SPK_CLS_DG_MODE
88 #define MAX98396_R2099_SPK_CLS_DG_VBAT_LVL
89 #define MAX98396_R209A_SPK_EDGE_CTRL
90 #define MAX98396_R209C_SPK_EDGE_CTRL1
91 #define MAX98396_R209D_SPK_EDGE_CTRL2
92 #define MAX98396_R209E_AMP_CLIP_GAIN
93 #define MAX98396_R209F_BYPASS_PATH_CFG
94 #define MAX98396_R20A0_AMP_SUPPLY_CTL
95 #define MAX98396_R20AF_AMP_EN
96 #define MAX98396_R20B0_ADC_SR
97 #define MAX98396_R20B1_ADC_PVDD_CFG
98 #define MAX98396_R20B2_ADC_VBAT_CFG
99 #define MAX98396_R20B3_ADC_THERMAL_CFG
100 #define MAX98396_R20B4_ADC_READBACK_CTRL1
101 #define MAX98396_R20B5_ADC_READBACK_CTRL2
102 #define MAX98396_R20B6_ADC_PVDD_READBACK_MSB
103 #define MAX98396_R20B7_ADC_PVDD_READBACK_LSB
104 #define MAX98396_R20B8_ADC_VBAT_READBACK_MSB
105 #define MAX98396_R20B9_ADC_VBAT_READBACK_LSB
106 #define MAX98396_R20BA_ADC_TEMP_READBACK_MSB
107 #define MAX98396_R20BB_ADC_TEMP_READBACK_LSB
108 #define MAX98396_R20BC_ADC_LO_PVDD_READBACK_MS
109 #define MAX98396_R20BD_ADC_LO_PVDD_READBACK_LS
110 #define MAX98396_R20BE_ADC_LO_VBAT_READBACK_MS
111 #define MAX98396_R20BF_ADC_LO_VBAT_READBACK_LS
112 #define MAX98396_R20C7_ADC_CFG
113 #define MAX98396_R20D0_DHT_CFG1
114 #define MAX98396_R20D1_LIMITER_CFG1
115 #define MAX98396_R20D2_LIMITER_CFG2
116 #define MAX98396_R20D3_DHT_CFG2
117 #define MAX98396_R20D4_DHT_CFG3
118 #define MAX98396_R20D5_DHT_CFG4
119 #define MAX98396_R20D6_DHT_HYSTERESIS_CFG
120 #define MAX98396_R20DF_DHT_EN
121 #define MAX98396_R20E0_IV_SENSE_PATH_CFG
122 #define MAX98396_R20E4_IV_SENSE_PATH_EN
123 #define MAX98396_R20E5_BPE_STATE
124 #define MAX98396_R20E6_BPE_L3_THRESH_MSB
125 #define MAX98396_R20E7_BPE_L3_THRESH_LSB
126 #define MAX98396_R20E8_BPE_L2_THRESH_MSB
127 #define MAX98396_R20E9_BPE_L2_THRESH_LSB
128 #define MAX98396_R20EA_BPE_L1_THRESH_MSB
129 #define MAX98396_R20EB_BPE_L1_THRESH_LSB
130 #define MAX98396_R20EC_BPE_L0_THRESH_MSB
131 #define MAX98396_R20ED_BPE_L0_THRESH_LSB
132 #define MAX98396_R20EE_BPE_L3_DWELL_HOLD_TIME
133 #define MAX98396_R20EF_BPE_L2_DWELL_HOLD_TIME
134 #define MAX98396_R20F0_BPE_L1_DWELL_HOLD_TIME
135 #define MAX98396_R20F1_BPE_L0_HOLD_TIME
136 #define MAX98396_R20F2_BPE_L3_ATTACK_REL_STEP
137 #define MAX98396_R20F3_BPE_L2_ATTACK_REL_STEP
138 #define MAX98396_R20F4_BPE_L1_ATTACK_REL_STEP
139 #define MAX98396_R20F5_BPE_L0_ATTACK_REL_STEP
140 #define MAX98396_R20F6_BPE_L3_MAX_GAIN_ATTN
141 #define MAX98396_R20F7_BPE_L2_MAX_GAIN_ATTN
142 #define MAX98396_R20F8_BPE_L1_MAX_GAIN_ATTN
143 #define MAX98396_R20F9_BPE_L0_MAX_GAIN_ATTN
144 #define MAX98396_R20FA_BPE_L3_ATT_REL_RATE
145 #define MAX98396_R20FB_BPE_L2_ATT_REL_RATE
146 #define MAX98396_R20FC_BPE_L1_ATT_REL_RATE
147 #define MAX98396_R20FD_BPE_L0_ATT_REL_RATE
148 #define MAX98396_R20FE_BPE_L3_LIMITER_CFG
149 #define MAX98396_R20FF_BPE_L2_LIMITER_CFG
150 #define MAX98396_R2100_BPE_L1_LIMITER_CFG
151 #define MAX98396_R2101_BPE_L0_LIMITER_CFG
152 #define MAX98396_R2102_BPE_L3_LIM_ATT_REL_RATE
153 #define MAX98396_R2103_BPE_L2_LIM_ATT_REL_RATE
154 #define MAX98396_R2104_BPE_L1_LIM_ATT_REL_RATE
155 #define MAX98396_R2105_BPE_L0_LIM_ATT_REL_RATE
156 #define MAX98396_R2106_BPE_THRESH_HYSTERESIS
157 #define MAX98396_R2107_BPE_INFINITE_HOLD_CLR
158 #define MAX98396_R2108_BPE_SUPPLY_SRC
159 #define MAX98396_R2109_BPE_LOW_STATE
160 #define MAX98396_R210A_BPE_LOW_GAIN
161 #define MAX98396_R210B_BPE_LOW_LIMITER
162 #define MAX98396_R210D_BPE_EN
163 #define MAX98396_R210E_AUTO_RESTART
164 #define MAX98396_R210F_GLOBAL_EN
165 #define MAX98396_R21FF_REVISION_ID
166
167 /* MAX98927 Registers */
168 #define MAX98397_R203A_SPK_MON_THRESH
169 #define MAX98397_R204C_PCM_TX_CTRL_9
170 #define MAX98397_R204D_PCM_TX_HIZ_CTRL_1
171 #define MAX98397_R204E_PCM_TX_HIZ_CTRL_2
172 #define MAX98397_R204F_PCM_TX_HIZ_CTRL_3
173 #define MAX98397_R2050_PCM_TX_HIZ_CTRL_4
174 #define MAX98397_R2051_PCM_TX_HIZ_CTRL_5
175 #define MAX98397_R2052_PCM_TX_HIZ_CTRL_6
176 #define MAX98397_R2053_PCM_TX_HIZ_CTRL_7
177 #define MAX98397_R2054_PCM_TX_HIZ_CTRL_8
178 #define MAX98397_R2056_PCM_RX_SRC1
179 #define MAX98397_R2057_PCM_RX_SRC2
180 #define MAX98397_R2060_PCM_TX_SUPPLY_SEL
181 #define MAX98397_R209B_SPK_PATH_WB_ONLY
182 #define MAX98397_R20B4_ADC_VDDH_CFG
183 #define MAX98397_R20B5_ADC_READBACK_CTRL1
184 #define MAX98397_R20B6_ADC_READBACK_CTRL2
185 #define MAX98397_R20B7_ADC_PVDD_READBACK_MSB
186 #define MAX98397_R20B8_ADC_PVDD_READBACK_LSB
187 #define MAX98397_R20B9_ADC_VBAT_READBACK_MSB
188 #define MAX98397_R20BA_ADC_VBAT_READBACK_LSB
189 #define MAX98397_R20BB_ADC_TEMP_READBACK_MSB
190 #define MAX98397_R20BC_ADC_TEMP_READBACK_LSB
191 #define MAX98397_R20BD_ADC_VDDH__READBACK_MSB
192 #define MAX98397_R20BE_ADC_VDDH_READBACK_LSB
193 #define MAX98397_R20BF_ADC_LO_PVDD_READBACK_MS
194 #define MAX98397_R20C0_ADC_LO_PVDD_READBACK_LS
195 #define MAX98397_R20C1_ADC_LO_VBAT_READBACK_MS
196 #define MAX98397_R20C2_ADC_LO_VBAT_READBACK_LS
197 #define MAX98397_R20C3_ADC_LO_VDDH_READBACK_MS
198 #define MAX98397_R20C4_ADC_LO_VDDH_READBACK_LS
199 #define MAX98397_R20C5_MEAS_ADC_OPTIMAL_MODE
200 #define MAX98397_R22FF_REVISION_ID
201
202 #define GET_REG_ADDR_REV_ID(x)\
203 ((x) > 0 ? MAX98397_R22FF_REVISION_ID
204
205 /* MAX98396_R2024_THERM_FOLDBACK_SET */
206 #define MAX98396_THERM_FB_SLOPE1_SHIFT
207 #define MAX98396_THERM_FB_SLOPE2_SHIFT
208 #define MAX98396_THERM_FB_REL_SHIFT
209 #define MAX98396_THERM_FB_HOLD_SHIFT
210
211 /* MAX98396_R2038_CLK_MON_CTRL */
212 #define MAX98396_CLK_MON_AUTO_RESTART_MASK
213 #define MAX98396_CLK_MON_AUTO_RESTART_SHIFT
214
215 /* MAX98396_R2039_DATA_MON_CTRL */
216 #define MAX98396_DMON_MAG_THRESH_SHIFT
217 #define MAX98396_DMON_MAG_THRESH_MASK
218 #define MAX98396_DMON_STUCK_THRESH_SHIFT
219 #define MAX98396_DMON_STUCK_THRESH_MASK
220 #define MAX98396_DMON_DURATION_MASK
221
222 /* MAX98396_R203F_ENABLE_CTRLS */
223 #define MAX98396_CTRL_CMON_EN_SHIFT
224 #define MAX98396_CTRL_DMON_STUCK_EN_MASK
225 #define MAX98396_CTRL_DMON_MAG_EN_MASK
226
227 /* MAX98396_R2041_PCM_MODE_CFG */
228 #define MAX98396_PCM_MODE_CFG_FORMAT_MASK
229 #define MAX98396_PCM_TX_CH_INTERLEAVE_MASK
230 #define MAX98396_PCM_FORMAT_I2S
231 #define MAX98396_PCM_FORMAT_LJ
232 #define MAX98396_PCM_FORMAT_TDM_MODE0
233 #define MAX98396_PCM_FORMAT_TDM_MODE1
234 #define MAX98396_PCM_FORMAT_TDM_MODE2
235 #define MAX98396_PCM_MODE_CFG_CHANSZ_MASK
236 #define MAX98396_PCM_MODE_CFG_CHANSZ_16
237 #define MAX98396_PCM_MODE_CFG_CHANSZ_24
238 #define MAX98396_PCM_MODE_CFG_CHANSZ_32
239 #define MAX98396_PCM_MODE_CFG_LRCLKEDGE
240
241 /* MAX98396_R2042_PCM_CLK_SETUP */
242 #define MAX98396_PCM_MODE_CFG_BCLKEDGE
243 #define MAX98396_PCM_CLK_SETUP_BSEL_MASK
244 #define MAX98396_PCM_BCLKEDGE_BSEL_MASK
245
246 /* MAX98396_R2043_PCM_SR_SETUP */
247 #define MAX98396_PCM_SR_SHIFT
248 #define MAX98396_IVADC_SR_SHIFT
249 #define MAX98396_PCM_SR_MASK
250 #define MAX98396_IVADC_SR_MASK
251 #define MAX98396_PCM_SR_8000
252 #define MAX98396_PCM_SR_11025
253 #define MAX98396_PCM_SR_12000
254 #define MAX98396_PCM_SR_16000
255 #define MAX98396_PCM_SR_22050
256 #define MAX98396_PCM_SR_24000
257 #define MAX98396_PCM_SR_32000
258 #define MAX98396_PCM_SR_44100
259 #define MAX98396_PCM_SR_48000
260 #define MAX98396_PCM_SR_88200
261 #define MAX98396_PCM_SR_96000
262 #define MAX98396_PCM_SR_176400
263 #define MAX98396_PCM_SR_192000
264
265 /* MAX98396_R2055_PCM_RX_SRC1 */
266 #define MAX98396_PCM_RX_MASK
267
268 /* MAX98396_R2056_PCM_RX_SRC2 */
269 #define MAX98396_PCM_DMIX_CH1_SHIFT
270 #define MAX98396_PCM_DMIX_CH0_SRC_MASK
271 #define MAX98396_PCM_DMIX_CH1_SRC_MASK
272
273 /* MAX98396_R205E_PCM_RX_EN */
274 #define MAX98396_PCM_RX_EN_MASK
275 #define MAX98396_PCM_RX_BYP_EN_MASK
276
277 /* MAX98396_R2092_AMP_DSP_CFG */
278 #define MAX98396_DSP_SPK_DCBLK_EN_SHIFT
279 #define MAX98396_DSP_SPK_DITH_EN_SHIFT
280 #define MAX98396_DSP_SPK_INVERT_SHIFT
281 #define MAX98396_DSP_SPK_VOL_RMPUP_SHIFT
282 #define MAX98396_DSP_SPK_VOL_RMPDN_SHIFT
283 #define MAX98396_DSP_SPK_SAFE_EN_SHIFT
284 #define MAX98396_DSP_SPK_WB_FLT_EN_SHIFT
285
286 /* MAX98396_R20A0_AMP_SUPPLY_CTL */
287 #define MAX98396_AMP_SUPPLY_NOVBAT
288
289 /* MAX98396_R20E0_IV_SENSE_PATH_CFG */
290 #define MAX98396_IV_SENSE_DCBLK_EN_MASK
291 #define MAX98396_IV_SENSE_DCBLK_EN_SHIFT
292 #define MAX98396_IV_SENSE_DITH_EN_SHIFT
293 #define MAX98396_IV_SENSE_WB_FLT_EN_SHIFT
294
295 /* MAX98396_R210E_AUTO_RESTART_BEHAVIOR */
296 #define MAX98396_PVDD_UVLO_RESTART_SHFT
297 #define MAX98396_VBAT_UVLO_RESTART_SHFT
298 #define MAX98396_THEM_SHDN_RESTART_SHFT
299 #define MAX98396_OVC_RESTART_SHFT
300
301 enum {
302 CODEC_TYPE_MAX98396,
303 CODEC_TYPE_MAX98397,
304 };
305
306 #define MAX98396_NUM_CORE_SUPPLIES 3
307
308 struct max98396_priv {
309 struct regmap *regmap;
310 struct gpio_desc *reset_gpio;
311 struct regulator_bulk_data core_suppli
312 struct regulator *pvdd, *vbat;
313 unsigned int v_slot;
314 unsigned int i_slot;
315 unsigned int spkfb_slot;
316 unsigned int bypass_slot;
317 bool dmon_stuck_enable;
318 unsigned int dmon_stuck_threshold;
319 bool dmon_mag_enable;
320 unsigned int dmon_mag_threshold;
321 unsigned int dmon_duration;
322 bool interleave_mode;
323 bool tdm_mode;
324 int tdm_max_samplerate;
325 int device_id;
326 };
327 #endif
328
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