1 /* SPDX-License-Identifier: GPL-2.0-only */ 1
2 /*
3 * max98925.h -- MAX98925 ALSA SoC Audio drive
4 *
5 * Copyright 2013-2015 Maxim Integrated Produc
6 */
7
8 #ifndef _MAX98925_H
9 #define _MAX98925_H
10
11 #define MAX98925_VERSION 0x51
12 #define MAX98925_VERSION1 0x80
13 #define MAX98925_VBAT_DATA 0x00
14 #define MAX98925_VBST_DATA 0x01
15 #define MAX98925_LIVE_STATUS0 0x02
16 #define MAX98925_LIVE_STATUS1 0x03
17 #define MAX98925_LIVE_STATUS2 0x04
18 #define MAX98925_STATE0 0x05
19 #define MAX98925_STATE1 0x06
20 #define MAX98925_STATE2 0x07
21 #define MAX98925_FLAG0 0x08
22 #define MAX98925_FLAG1 0x09
23 #define MAX98925_FLAG2 0x0A
24 #define MAX98925_IRQ_ENABLE0 0x0B
25 #define MAX98925_IRQ_ENABLE1 0x0C
26 #define MAX98925_IRQ_ENABLE2 0x0D
27 #define MAX98925_IRQ_CLEAR0 0x0E
28 #define MAX98925_IRQ_CLEAR1 0x0F
29 #define MAX98925_IRQ_CLEAR2 0x10
30 #define MAX98925_MAP0 0x11
31 #define MAX98925_MAP1 0x12
32 #define MAX98925_MAP2 0x13
33 #define MAX98925_MAP3 0x14
34 #define MAX98925_MAP4 0x15
35 #define MAX98925_MAP5 0x16
36 #define MAX98925_MAP6 0x17
37 #define MAX98925_MAP7 0x18
38 #define MAX98925_MAP8 0x19
39 #define MAX98925_DAI_CLK_MODE1 0x1A
40 #define MAX98925_DAI_CLK_MODE2 0x1B
41 #define MAX98925_DAI_CLK_DIV_M_MSBS 0x1C
42 #define MAX98925_DAI_CLK_DIV_M_LSBS 0x1D
43 #define MAX98925_DAI_CLK_DIV_N_MSBS 0x1E
44 #define MAX98925_DAI_CLK_DIV_N_LSBS 0x1F
45 #define MAX98925_FORMAT 0x20
46 #define MAX98925_TDM_SLOT_SELECT 0x21
47 #define MAX98925_DOUT_CFG_VMON 0x22
48 #define MAX98925_DOUT_CFG_IMON 0x23
49 #define MAX98925_DOUT_CFG_VBAT 0x24
50 #define MAX98925_DOUT_CFG_VBST 0x25
51 #define MAX98925_DOUT_CFG_FLAG 0x26
52 #define MAX98925_DOUT_HIZ_CFG1 0x27
53 #define MAX98925_DOUT_HIZ_CFG2 0x28
54 #define MAX98925_DOUT_HIZ_CFG3 0x29
55 #define MAX98925_DOUT_HIZ_CFG4 0x2A
56 #define MAX98925_DOUT_DRV_STRENGTH 0x2B
57 #define MAX98925_FILTERS 0x2C
58 #define MAX98925_GAIN 0x2D
59 #define MAX98925_GAIN_RAMPING 0x2E
60 #define MAX98925_SPK_AMP 0x2F
61 #define MAX98925_THRESHOLD 0x30
62 #define MAX98925_ALC_ATTACK 0x31
63 #define MAX98925_ALC_ATTEN_RLS 0x32
64 #define MAX98925_ALC_HOLD_RLS 0x33
65 #define MAX98925_ALC_CONFIGURATION 0x34
66 #define MAX98925_BOOST_CONVERTER 0x35
67 #define MAX98925_BLOCK_ENABLE 0x36
68 #define MAX98925_CONFIGURATION 0x37
69 #define MAX98925_GLOBAL_ENABLE 0x38
70 #define MAX98925_BOOST_LIMITER 0x3A
71 #define MAX98925_REV_VERSION 0xFF
72
73 #define MAX98925_REG_CNT (MAX989
74
75 /* MAX98925 Register Bit Fields */
76
77 /* MAX98925_R002_LIVE_STATUS0 */
78 #define M98925_THERMWARN_STATUS_MASK
79 #define M98925_THERMWARN_STATUS_SHIFT
80 #define M98925_THERMWARN_STATUS_WIDTH
81 #define M98925_THERMSHDN_STATUS_MASK
82 #define M98925_THERMSHDN_STATUS_SHIFT
83 #define M98925_THERMSHDN_STATUS_WIDTH
84
85 /* MAX98925_R003_LIVE_STATUS1 */
86 #define M98925_SPKCURNT_STATUS_MASK
87 #define M98925_SPKCURNT_STATUS_SHIFT
88 #define M98925_SPKCURNT_STATUS_WIDTH
89 #define M98925_WATCHFAIL_STATUS_MASK
90 #define M98925_WATCHFAIL_STATUS_SHIFT
91 #define M98925_WATCHFAIL_STATUS_WIDTH
92 #define M98925_ALCINFH_STATUS_MASK
93 #define M98925_ALCINFH_STATUS_SHIFT
94 #define M98925_ALCINFH_STATUS_WIDTH
95 #define M98925_ALCACT_STATUS_MASK
96 #define M98925_ALCACT_STATUS_SHIFT
97 #define M98925_ALCACT_STATUS_WIDTH
98 #define M98925_ALCMUT_STATUS_MASK
99 #define M98925_ALCMUT_STATUS_SHIFT
100 #define M98925_ALCMUT_STATUS_WIDTH
101 #define M98925_ACLP_STATUS_MASK
102 #define M98925_ACLP_STATUS_SHIFT
103 #define M98925_ACLP_STATUS_WIDTH
104
105 /* MAX98925_R004_LIVE_STATUS2 */
106 #define M98925_SLOTOVRN_STATUS_MASK
107 #define M98925_SLOTOVRN_STATUS_SHIFT
108 #define M98925_SLOTOVRN_STATUS_WIDTH
109 #define M98925_INVALSLOT_STATUS_MASK
110 #define M98925_INVALSLOT_STATUS_SHIFT
111 #define M98925_INVALSLOT_STATUS_WIDTH
112 #define M98925_SLOTCNFLT_STATUS_MASK
113 #define M98925_SLOTCNFLT_STATUS_SHIFT
114 #define M98925_SLOTCNFLT_STATUS_WIDTH
115 #define M98925_VBSTOVFL_STATUS_MASK
116 #define M98925_VBSTOVFL_STATUS_SHIFT
117 #define M98925_VBSTOVFL_STATUS_WIDTH
118 #define M98925_VBATOVFL_STATUS_MASK
119 #define M98925_VBATOVFL_STATUS_SHIFT
120 #define M98925_VBATOVFL_STATUS_WIDTH
121 #define M98925_IMONOVFL_STATUS_MASK
122 #define M98925_IMONOVFL_STATUS_SHIFT
123 #define M98925_IMONOVFL_STATUS_WIDTH
124 #define M98925_VMONOVFL_STATUS_MASK
125 #define M98925_VMONOVFL_STATUS_SHIFT
126 #define M98925_VMONOVFL_STATUS_WIDTH
127
128 /* MAX98925_R005_STATE0 */
129 #define M98925_THERMWARN_END_STATE_MASK
130 #define M98925_THERMWARN_END_STATE_SHIFT
131 #define M98925_THERMWARN_END_STATE_WIDTH
132 #define M98925_THERMWARN_BGN_STATE_MASK
133 #define M98925_THERMWARN_BGN_STATE_SHIFT
134 #define M98925_THERMWARN_BGN_STATE_WIDTH
135 #define M98925_THERMSHDN_END_STATE_MASK
136 #define M98925_THERMSHDN_END_STATE_SHIFT
137 #define M98925_THERMSHDN_END_STATE_WIDTH
138 #define M98925_THERMSHDN_BGN_STATE_MASK
139 #define M98925_THERMSHDN_BGN_STATE_SHIFT
140 #define M98925_THERMSHDN_BGN_STATE_WIDTH
141
142 /* MAX98925_R006_STATE1 */
143 #define M98925_SPRCURNT_STATE_MASK
144 #define M98925_SPRCURNT_STATE_SHIFT
145 #define M98925_SPRCURNT_STATE_WIDTH
146 #define M98925_WATCHFAIL_STATE_MASK
147 #define M98925_WATCHFAIL_STATE_SHIFT
148 #define M98925_WATCHFAIL_STATE_WIDTH
149 #define M98925_ALCINFH_STATE_MASK
150 #define M98925_ALCINFH_STATE_SHIFT
151 #define M98925_ALCINFH_STATE_WIDTH
152 #define M98925_ALCACT_STATE_MASK
153 #define M98925_ALCACT_STATE_SHIFT
154 #define M98925_ALCACT_STATE_WIDTH
155 #define M98925_ALCMUT_STATE_MASK
156 #define M98925_ALCMUT_STATE_SHIFT
157 #define M98925_ALCMUT_STATE_WIDTH
158 #define M98925_ALCP_STATE_MASK
159 #define M98925_ALCP_STATE_SHIFT
160 #define M98925_ALCP_STATE_WIDTH
161
162 /* MAX98925_R007_STATE2 */
163 #define M98925_SLOTOVRN_STATE_MASK
164 #define M98925_SLOTOVRN_STATE_SHIFT
165 #define M98925_SLOTOVRN_STATE_WIDTH
166 #define M98925_INVALSLOT_STATE_MASK
167 #define M98925_INVALSLOT_STATE_SHIFT
168 #define M98925_INVALSLOT_STATE_WIDTH
169 #define M98925_SLOTCNFLT_STATE_MASK
170 #define M98925_SLOTCNFLT_STATE_SHIFT
171 #define M98925_SLOTCNFLT_STATE_WIDTH
172 #define M98925_VBSTOVFL_STATE_MASK
173 #define M98925_VBSTOVFL_STATE_SHIFT
174 #define M98925_VBSTOVFL_STATE_WIDTH
175 #define M98925_VBATOVFL_STATE_MASK
176 #define M98925_VBATOVFL_STATE_SHIFT
177 #define M98925_VBATOVFL_STATE_WIDTH
178 #define M98925_IMONOVFL_STATE_MASK
179 #define M98925_IMONOVFL_STATE_SHIFT
180 #define M98925_IMONOVFL_STATE_WIDTH
181 #define M98925_VMONOVFL_STATE_MASK
182 #define M98925_VMONOVFL_STATE_SHIFT
183 #define M98925_VMONOVFL_STATE_WIDTH
184
185 /* MAX98925_R008_FLAG0 */
186 #define M98925_THERMWARN_END_FLAG_MASK
187 #define M98925_THERMWARN_END_FLAG_SHIFT
188 #define M98925_THERMWARN_END_FLAG_WIDTH
189 #define M98925_THERMWARN_BGN_FLAG_MASK
190 #define M98925_THERMWARN_BGN_FLAG_SHIFT
191 #define M98925_THERMWARN_BGN_FLAG_WIDTH
192 #define M98925_THERMSHDN_END_FLAG_MASK
193 #define M98925_THERMSHDN_END_FLAG_SHIFT
194 #define M98925_THERMSHDN_END_FLAG_WIDTH
195 #define M98925_THERMSHDN_BGN_FLAG_MASK
196 #define M98925_THERMSHDN_BGN_FLAG_SHIFT
197 #define M98925_THERMSHDN_BGN_FLAG_WIDTH
198
199 /* MAX98925_R009_FLAG1 */
200 #define M98925_SPKCURNT_FLAG_MASK
201 #define M98925_SPKCURNT_FLAG_SHIFT
202 #define M98925_SPKCURNT_FLAG_WIDTH
203 #define M98925_WATCHFAIL_FLAG_MASK
204 #define M98925_WATCHFAIL_FLAG_SHIFT
205 #define M98925_WATCHFAIL_FLAG_WIDTH
206 #define M98925_ALCINFH_FLAG_MASK
207 #define M98925_ALCINFH_FLAG_SHIFT
208 #define M98925_ALCINFH_FLAG_WIDTH
209 #define M98925_ALCACT_FLAG_MASK
210 #define M98925_ALCACT_FLAG_SHIFT
211 #define M98925_ALCACT_FLAG_WIDTH
212 #define M98925_ALCMUT_FLAG_MASK
213 #define M98925_ALCMUT_FLAG_SHIFT
214 #define M98925_ALCMUT_FLAG_WIDTH
215 #define M98925_ALCP_FLAG_MASK
216 #define M98925_ALCP_FLAG_SHIFT
217 #define M98925_ALCP_FLAG_WIDTH
218
219 /* MAX98925_R00A_FLAG2 */
220 #define M98925_SLOTOVRN_FLAG_MASK
221 #define M98925_SLOTOVRN_FLAG_SHIFT
222 #define M98925_SLOTOVRN_FLAG_WIDTH
223 #define M98925_INVALSLOT_FLAG_MASK
224 #define M98925_INVALSLOT_FLAG_SHIFT
225 #define M98925_INVALSLOT_FLAG_WIDTH
226 #define M98925_SLOTCNFLT_FLAG_MASK
227 #define M98925_SLOTCNFLT_FLAG_SHIFT
228 #define M98925_SLOTCNFLT_FLAG_WIDTH
229 #define M98925_VBSTOVFL_FLAG_MASK
230 #define M98925_VBSTOVFL_FLAG_SHIFT
231 #define M98925_VBSTOVFL_FLAG_WIDTH
232 #define M98925_VBATOVFL_FLAG_MASK
233 #define M98925_VBATOVFL_FLAG_SHIFT
234 #define M98925_VBATOVFL_FLAG_WIDTH
235 #define M98925_IMONOVFL_FLAG_MASK
236 #define M98925_IMONOVFL_FLAG_SHIFT
237 #define M98925_IMONOVFL_FLAG_WIDTH
238 #define M98925_VMONOVFL_FLAG_MASK
239 #define M98925_VMONOVFL_FLAG_SHIFT
240 #define M98925_VMONOVFL_FLAG_WIDTH
241
242 /* MAX98925_R00B_IRQ_ENABLE0 */
243 #define M98925_THERMWARN_END_EN_MASK
244 #define M98925_THERMWARN_END_EN_SHIFT
245 #define M98925_THERMWARN_END_EN_WIDTH
246 #define M98925_THERMWARN_BGN_EN_MASK
247 #define M98925_THERMWARN_BGN_EN_SHIFT
248 #define M98925_THERMWARN_BGN_EN_WIDTH
249 #define M98925_THERMSHDN_END_EN_MASK
250 #define M98925_THERMSHDN_END_EN_SHIFT
251 #define M98925_THERMSHDN_END_EN_WIDTH
252 #define M98925_THERMSHDN_BGN_EN_MASK
253 #define M98925_THERMSHDN_BGN_EN_SHIFT
254 #define M98925_THERMSHDN_BGN_EN_WIDTH
255
256 /* MAX98925_R00C_IRQ_ENABLE1 */
257 #define M98925_SPKCURNT_EN_MASK
258 #define M98925_SPKCURNT_EN_SHIFT
259 #define M98925_SPKCURNT_EN_WIDTH
260 #define M98925_WATCHFAIL_EN_MASK
261 #define M98925_WATCHFAIL_EN_SHIFT
262 #define M98925_WATCHFAIL_EN_WIDTH
263 #define M98925_ALCINFH_EN_MASK
264 #define M98925_ALCINFH_EN_SHIFT
265 #define M98925_ALCINFH_EN_WIDTH
266 #define M98925_ALCACT_EN_MASK
267 #define M98925_ALCACT_EN_SHIFT
268 #define M98925_ALCACT_EN_WIDTH
269 #define M98925_ALCMUT_EN_MASK
270 #define M98925_ALCMUT_EN_SHIFT
271 #define M98925_ALCMUT_EN_WIDTH
272 #define M98925_ALCP_EN_MASK
273 #define M98925_ALCP_EN_SHIFT
274 #define M98925_ALCP_EN_WIDTH
275
276 /* MAX98925_R00D_IRQ_ENABLE2 */
277 #define M98925_SLOTOVRN_EN_MASK
278 #define M98925_SLOTOVRN_EN_SHIFT
279 #define M98925_SLOTOVRN_EN_WIDTH
280 #define M98925_INVALSLOT_EN_MASK
281 #define M98925_INVALSLOT_EN_SHIFT
282 #define M98925_INVALSLOT_EN_WIDTH
283 #define M98925_SLOTCNFLT_EN_MASK
284 #define M98925_SLOTCNFLT_EN_SHIFT
285 #define M98925_SLOTCNFLT_EN_WIDTH
286 #define M98925_VBSTOVFL_EN_MASK
287 #define M98925_VBSTOVFL_EN_SHIFT
288 #define M98925_VBSTOVFL_EN_WIDTH
289 #define M98925_VBATOVFL_EN_MASK
290 #define M98925_VBATOVFL_EN_SHIFT
291 #define M98925_VBATOVFL_EN_WIDTH
292 #define M98925_IMONOVFL_EN_MASK
293 #define M98925_IMONOVFL_EN_SHIFT
294 #define M98925_IMONOVFL_EN_WIDTH
295 #define M98925_VMONOVFL_EN_MASK
296 #define M98925_VMONOVFL_EN_SHIFT
297 #define M98925_VMONOVFL_EN_WIDTH
298
299 /* MAX98925_R00E_IRQ_CLEAR0 */
300 #define M98925_THERMWARN_END_CLR_MASK
301 #define M98925_THERMWARN_END_CLR_SHIFT
302 #define M98925_THERMWARN_END_CLR_WIDTH
303 #define M98925_THERMWARN_BGN_CLR_MASK
304 #define M98925_THERMWARN_BGN_CLR_SHIFT
305 #define M98925_THERMWARN_BGN_CLR_WIDTH
306 #define M98925_THERMSHDN_END_CLR_MASK
307 #define M98925_THERMSHDN_END_CLR_SHIFT
308 #define M98925_THERMSHDN_END_CLR_WIDTH
309 #define M98925_THERMSHDN_BGN_CLR_MASK
310 #define M98925_THERMSHDN_BGN_CLR_SHIFT
311 #define M98925_THERMSHDN_BGN_CLR_WIDTH
312
313 /* MAX98925_R00F_IRQ_CLEAR1 */
314 #define M98925_SPKCURNT_CLR_MASK
315 #define M98925_SPKCURNT_CLR_SHIFT
316 #define M98925_SPKCURNT_CLR_WIDTH
317 #define M98925_WATCHFAIL_CLR_MASK
318 #define M98925_WATCHFAIL_CLR_SHIFT
319 #define M98925_WATCHFAIL_CLR_WIDTH
320 #define M98925_ALCINFH_CLR_MASK
321 #define M98925_ALCINFH_CLR_SHIFT
322 #define M98925_ALCINFH_CLR_WIDTH
323 #define M98925_ALCACT_CLR_MASK
324 #define M98925_ALCACT_CLR_SHIFT
325 #define M98925_ALCACT_CLR_WIDTH
326 #define M98925_ALCMUT_CLR_MASK
327 #define M98925_ALCMUT_CLR_SHIFT
328 #define M98925_ALCMUT_CLR_WIDTH
329 #define M98925_ALCP_CLR_MASK
330 #define M98925_ALCP_CLR_SHIFT
331 #define M98925_ALCP_CLR_WIDTH
332
333 /* MAX98925_R010_IRQ_CLEAR2 */
334 #define M98925_SLOTOVRN_CLR_MASK
335 #define M98925_SLOTOVRN_CLR_SHIFT
336 #define M98925_SLOTOVRN_CLR_WIDTH
337 #define M98925_INVALSLOT_CLR_MASK
338 #define M98925_INVALSLOT_CLR_SHIFT
339 #define M98925_INVALSLOT_CLR_WIDTH
340 #define M98925_SLOTCNFLT_CLR_MASK
341 #define M98925_SLOTCNFLT_CLR_SHIFT
342 #define M98925_SLOTCNFLT_CLR_WIDTH
343 #define M98925_VBSTOVFL_CLR_MASK
344 #define M98925_VBSTOVFL_CLR_SHIFT
345 #define M98925_VBSTOVFL_CLR_WIDTH
346 #define M98925_VBATOVFL_CLR_MASK
347 #define M98925_VBATOVFL_CLR_SHIFT
348 #define M98925_VBATOVFL_CLR_WIDTH
349 #define M98925_IMONOVFL_CLR_MASK
350 #define M98925_IMONOVFL_CLR_SHIFT
351 #define M98925_IMONOVFL_CLR_WIDTH
352 #define M98925_VMONOVFL_CLR_MASK
353 #define M98925_VMONOVFL_CLR_SHIFT
354 #define M98925_VMONOVFL_CLR_WIDTH
355
356 /* MAX98925_R011_MAP0 */
357 #define M98925_ER_THERMWARN_EN_MASK
358 #define M98925_ER_THERMWARN_EN_SHIFT
359 #define M98925_ER_THERMWARN_EN_WIDTH
360 #define M98925_ER_THERMWARN_MAP_MASK
361 #define M98925_ER_THERMWARN_MAP_SHIFT
362 #define M98925_ER_THERMWARN_MAP_WIDTH
363
364 /* MAX98925_R012_MAP1 */
365 #define M98925_ER_ALCMUT_EN_MASK
366 #define M98925_ER_ALCMUT_EN_SHIFT
367 #define M98925_ER_ALCMUT_EN_WIDTH
368 #define M98925_ER_ALCMUT_MAP_MASK
369 #define M98925_ER_ALCMUT_MAP_SHIFT
370 #define M98925_ER_ALCMUT_MAP_WIDTH
371 #define M98925_ER_ALCP_EN_MASK
372 #define M98925_ER_ALCP_EN_SHIFT
373 #define M98925_ER_ALCP_EN_WIDTH
374 #define M98925_ER_ALCP_MAP_MASK
375 #define M98925_ER_ALCP_MAP_SHIFT
376 #define M98925_ER_ALCP_MAP_WIDTH
377
378 /* MAX98925_R013_MAP2 */
379 #define M98925_ER_ALCINFH_EN_MASK
380 #define M98925_ER_ALCINFH_EN_SHIFT
381 #define M98925_ER_ALCINFH_EN_WIDTH
382 #define M98925_ER_ALCINFH_MAP_MASK
383 #define M98925_ER_ALCINFH_MAP_SHIFT
384 #define M98925_ER_ALCINFH_MAP_WIDTH
385 #define M98925_ER_ALCACT_EN_MASK
386 #define M98925_ER_ALCACT_EN_SHIFT
387 #define M98925_ER_ALCACT_EN_WIDTH
388 #define M98925_ER_ALCACT_MAP_MASK
389 #define M98925_ER_ALCACT_MAP_SHIFT
390 #define M98925_ER_ALCACT_MAP_WIDTH
391
392 /* MAX98925_R014_MAP3 */
393 #define M98925_ER_SPKCURNT_EN_MASK
394 #define M98925_ER_SPKCURNT_EN_SHIFT
395 #define M98925_ER_SPKCURNT_EN_WIDTH
396 #define M98925_ER_SPKCURNT_MAP_MASK
397 #define M98925_ER_SPKCURNT_MAP_SHIFT
398 #define M98925_ER_SPKCURNT_MAP_WIDTH
399
400 /* MAX98925_R015_MAP4 */
401 /* RESERVED */
402
403 /* MAX98925_R016_MAP5 */
404 #define M98925_ER_IMONOVFL_EN_MASK
405 #define M98925_ER_IMONOVFL_EN_SHIFT
406 #define M98925_ER_IMONOVFL_EN_WIDTH
407 #define M98925_ER_IMONOVFL_MAP_MASK
408 #define M98925_ER_IMONOVFL_MAP_SHIFT
409 #define M98925_ER_IMONOVFL_MAP_WIDTH
410 #define M98925_ER_VMONOVFL_EN_MASK
411 #define M98925_ER_VMONOVFL_EN_SHIFT
412 #define M98925_ER_VMONOVFL_EN_WIDTH
413 #define M98925_ER_VMONOVFL_MAP_MASK
414 #define M98925_ER_VMONOVFL_MAP_SHIFT
415 #define M98925_ER_VMONOVFL_MAP_WIDTH
416
417 /* MAX98925_R017_MAP6 */
418 #define M98925_ER_VBSTOVFL_EN_MASK
419 #define M98925_ER_VBSTOVFL_EN_SHIFT
420 #define M98925_ER_VBSTOVFL_EN_WIDTH
421 #define M98925_ER_VBSTOVFL_MAP_MASK
422 #define M98925_ER_VBSTOVFL_MAP_SHIFT
423 #define M98925_ER_VBSTOVFL_MAP_WIDTH
424 #define M98925_ER_VBATOVFL_EN_MASK
425 #define M98925_ER_VBATOVFL_EN_SHIFT
426 #define M98925_ER_VBATOVFL_EN_WIDTH
427 #define M98925_ER_VBATOVFL_MAP_MASK
428 #define M98925_ER_VBATOVFL_MAP_SHIFT
429 #define M98925_ER_VBATOVFL_MAP_WIDTH
430
431 /* MAX98925_R018_MAP7 */
432 #define M98925_ER_INVALSLOT_EN_MASK
433 #define M98925_ER_INVALSLOT_EN_SHIFT
434 #define M98925_ER_INVALSLOT_EN_WIDTH
435 #define M98925_ER_INVALSLOT_MAP_MASK
436 #define M98925_ER_INVALSLOT_MAP_SHIFT
437 #define M98925_ER_INVALSLOT_MAP_WIDTH
438 #define M98925_ER_SLOTCNFLT_EN_MASK
439 #define M98925_ER_SLOTCNFLT_EN_SHIFT
440 #define M98925_ER_SLOTCNFLT_EN_WIDTH
441 #define M98925_ER_SLOTCNFLT_MAP_MASK
442 #define M98925_ER_SLOTCNFLT_MAP_SHIFT
443 #define M98925_ER_SLOTCNFLT_MAP_WIDTH
444
445 /* MAX98925_R019_MAP8 */
446 #define M98925_ER_SLOTOVRN_EN_MASK (1<<3)
447 #define M98925_ER_SLOTOVRN_EN_SHIFT 3
448 #define M98925_ER_SLOTOVRN_EN_WIDTH 1
449 #define M98925_ER_SLOTOVRN_MAP_MASK (0x07<
450 #define M98925_ER_SLOTOVRN_MAP_SHIFT 0
451 #define M98925_ER_SLOTOVRN_MAP_WIDTH 3
452
453 /* MAX98925_R01A_DAI_CLK_MODE1 */
454 #define M98925_DAI_CLK_SOURCE_MASK (1<<6)
455 #define M98925_DAI_CLK_SOURCE_SHIFT 6
456 #define M98925_DAI_CLK_SOURCE_WIDTH 1
457 #define M98925_MDLL_MULT_MASK (0x0F<
458 #define M98925_MDLL_MULT_SHIFT 0
459 #define M98925_MDLL_MULT_WIDTH 4
460
461 #define M98925_MDLL_MULT_MCLKx8 6
462 #define M98925_MDLL_MULT_MCLKx16 8
463
464 /* MAX98925_R01B_DAI_CLK_MODE2 */
465 #define M98925_DAI_SR_MASK
466 #define M98925_DAI_SR_SHIFT
467 #define M98925_DAI_SR_WIDTH
468 #define M98925_DAI_MAS_MASK
469 #define M98925_DAI_MAS_SHIFT
470 #define M98925_DAI_MAS_WIDTH
471 #define M98925_DAI_BSEL_MASK
472 #define M98925_DAI_BSEL_SHIFT
473 #define M98925_DAI_BSEL_WIDTH
474
475 #define M98925_DAI_BSEL_32 (0 << M98925_DAI_BS
476 #define M98925_DAI_BSEL_48 (1 << M98925_DAI_BS
477 #define M98925_DAI_BSEL_64 (2 << M98925_DAI_BS
478 #define M98925_DAI_BSEL_256 (6 << M98925_DAI_B
479
480 /* MAX98925_R01C_DAI_CLK_DIV_M_MSBS */
481 #define M98925_DAI_M_MSBS_MASK
482 #define M98925_DAI_M_MSBS_SHIFT
483 #define M98925_DAI_M_MSBS_WIDTH
484
485 /* MAX98925_R01D_DAI_CLK_DIV_M_LSBS */
486 #define M98925_DAI_M_LSBS_MASK
487 #define M98925_DAI_M_LSBS_SHIFT
488 #define M98925_DAI_M_LSBS_WIDTH
489
490 /* MAX98925_R01E_DAI_CLK_DIV_N_MSBS */
491 #define M98925_DAI_N_MSBS_MASK
492 #define M98925_DAI_N_MSBS_SHIFT
493 #define M98925_DAI_N_MSBS_WIDTH
494
495 /* MAX98925_R01F_DAI_CLK_DIV_N_LSBS */
496 #define M98925_DAI_N_LSBS_MASK
497 #define M98925_DAI_N_LSBS_SHIFT
498 #define M98925_DAI_N_LSBS_WIDTH
499
500 /* MAX98925_R020_FORMAT */
501 #define M98925_DAI_CHANSZ_MASK
502 #define M98925_DAI_CHANSZ_SHIFT
503 #define M98925_DAI_CHANSZ_WIDTH
504 #define M98925_DAI_EXTBCLK_HIZ_MASK
505 #define M98925_DAI_EXTBCLK_HIZ_SHIFT
506 #define M98925_DAI_EXTBCLK_HIZ_WIDTH
507 #define M98925_DAI_WCI_MASK
508 #define M98925_DAI_WCI_SHIFT
509 #define M98925_DAI_WCI_WIDTH
510 #define M98925_DAI_BCI_MASK
511 #define M98925_DAI_BCI_SHIFT
512 #define M98925_DAI_BCI_WIDTH
513 #define M98925_DAI_DLY_MASK
514 #define M98925_DAI_DLY_SHIFT
515 #define M98925_DAI_DLY_WIDTH
516 #define M98925_DAI_TDM_MASK
517 #define M98925_DAI_TDM_SHIFT
518 #define M98925_DAI_TDM_WIDTH
519
520 #define M98925_DAI_CHANSZ_16 (1 << M98925_DAI_
521 #define M98925_DAI_CHANSZ_24 (2 << M98925_DAI_
522 #define M98925_DAI_CHANSZ_32 (3 << M98925_DAI_
523
524 /* MAX98925_R021_TDM_SLOT_SELECT */
525 #define M98925_DAI_DO_EN_MASK
526 #define M98925_DAI_DO_EN_SHIFT
527 #define M98925_DAI_DO_EN_WIDTH
528 #define M98925_DAI_DIN_EN_MASK
529 #define M98925_DAI_DIN_EN_SHIFT
530 #define M98925_DAI_DIN_EN_WIDTH
531 #define M98925_DAI_INR_SOURCE_MASK
532 #define M98925_DAI_INR_SOURCE_SHIFT
533 #define M98925_DAI_INR_SOURCE_WIDTH
534 #define M98925_DAI_INL_SOURCE_MASK
535 #define M98925_DAI_INL_SOURCE_SHIFT
536 #define M98925_DAI_INL_SOURCE_WIDTH
537
538 /* MAX98925_R022_DOUT_CFG_VMON */
539 #define M98925_DAI_VMON_EN_MASK
540 #define M98925_DAI_VMON_EN_SHIFT
541 #define M98925_DAI_VMON_EN_WIDTH
542 #define M98925_DAI_VMON_SLOT_MASK
543 #define M98925_DAI_VMON_SLOT_SHIFT
544 #define M98925_DAI_VMON_SLOT_WIDTH
545
546 #define M98925_DAI_VMON_SLOT_00_01 (0 << M9892
547 #define M98925_DAI_VMON_SLOT_01_02 (1 << M9892
548 #define M98925_DAI_VMON_SLOT_02_03 (2 << M9892
549 #define M98925_DAI_VMON_SLOT_03_04 (3 << M9892
550 #define M98925_DAI_VMON_SLOT_04_05 (4 << M9892
551 #define M98925_DAI_VMON_SLOT_05_06 (5 << M9892
552 #define M98925_DAI_VMON_SLOT_06_07 (6 << M9892
553 #define M98925_DAI_VMON_SLOT_07_08 (7 << M9892
554 #define M98925_DAI_VMON_SLOT_08_09 (8 << M9892
555 #define M98925_DAI_VMON_SLOT_09_0A (9 << M9892
556 #define M98925_DAI_VMON_SLOT_0A_0B (10 << M989
557 #define M98925_DAI_VMON_SLOT_0B_0C (11 << M989
558 #define M98925_DAI_VMON_SLOT_0C_0D (12 << M989
559 #define M98925_DAI_VMON_SLOT_0D_0E (13 << M989
560 #define M98925_DAI_VMON_SLOT_0E_0F (14 << M989
561 #define M98925_DAI_VMON_SLOT_0F_10 (15 << M989
562 #define M98925_DAI_VMON_SLOT_10_11 (16 << M989
563 #define M98925_DAI_VMON_SLOT_11_12 (17 << M989
564 #define M98925_DAI_VMON_SLOT_12_13 (18 << M989
565 #define M98925_DAI_VMON_SLOT_13_14 (19 << M989
566 #define M98925_DAI_VMON_SLOT_14_15 (20 << M989
567 #define M98925_DAI_VMON_SLOT_15_16 (21 << M989
568 #define M98925_DAI_VMON_SLOT_16_17 (22 << M989
569 #define M98925_DAI_VMON_SLOT_17_18 (23 << M989
570 #define M98925_DAI_VMON_SLOT_18_19 (24 << M989
571 #define M98925_DAI_VMON_SLOT_19_1A (25 << M989
572 #define M98925_DAI_VMON_SLOT_1A_1B (26 << M989
573 #define M98925_DAI_VMON_SLOT_1B_1C (27 << M989
574 #define M98925_DAI_VMON_SLOT_1C_1D (28 << M989
575 #define M98925_DAI_VMON_SLOT_1D_1E (29 << M989
576 #define M98925_DAI_VMON_SLOT_1E_1F (30 << M989
577
578 /* MAX98925_R023_DOUT_CFG_IMON */
579 #define M98925_DAI_IMON_EN_MASK
580 #define M98925_DAI_IMON_EN_SHIFT
581 #define M98925_DAI_IMON_EN_WIDTH
582 #define M98925_DAI_IMON_SLOT_MASK
583 #define M98925_DAI_IMON_SLOT_SHIFT
584 #define M98925_DAI_IMON_SLOT_WIDTH
585
586 #define M98925_DAI_IMON_SLOT_00_01 (0 << M9892
587 #define M98925_DAI_IMON_SLOT_01_02 (1 << M9892
588 #define M98925_DAI_IMON_SLOT_02_03 (2 << M9892
589 #define M98925_DAI_IMON_SLOT_03_04 (3 << M9892
590 #define M98925_DAI_IMON_SLOT_04_05 (4 << M9892
591 #define M98925_DAI_IMON_SLOT_05_06 (5 << M9892
592 #define M98925_DAI_IMON_SLOT_06_07 (6 << M9892
593 #define M98925_DAI_IMON_SLOT_07_08 (7 << M9892
594 #define M98925_DAI_IMON_SLOT_08_09 (8 << M9892
595 #define M98925_DAI_IMON_SLOT_09_0A (9 << M9892
596 #define M98925_DAI_IMON_SLOT_0A_0B (10 << M989
597 #define M98925_DAI_IMON_SLOT_0B_0C (11 << M989
598 #define M98925_DAI_IMON_SLOT_0C_0D (12 << M989
599 #define M98925_DAI_IMON_SLOT_0D_0E (13 << M989
600 #define M98925_DAI_IMON_SLOT_0E_0F (14 << M989
601 #define M98925_DAI_IMON_SLOT_0F_10 (15 << M989
602 #define M98925_DAI_IMON_SLOT_10_11 (16 << M989
603 #define M98925_DAI_IMON_SLOT_11_12 (17 << M989
604 #define M98925_DAI_IMON_SLOT_12_13 (18 << M989
605 #define M98925_DAI_IMON_SLOT_13_14 (19 << M989
606 #define M98925_DAI_IMON_SLOT_14_15 (20 << M989
607 #define M98925_DAI_IMON_SLOT_15_16 (21 << M989
608 #define M98925_DAI_IMON_SLOT_16_17 (22 << M989
609 #define M98925_DAI_IMON_SLOT_17_18 (23 << M989
610 #define M98925_DAI_IMON_SLOT_18_19 (24 << M989
611 #define M98925_DAI_IMON_SLOT_19_1A (25 << M989
612 #define M98925_DAI_IMON_SLOT_1A_1B (26 << M989
613 #define M98925_DAI_IMON_SLOT_1B_1C (27 << M989
614 #define M98925_DAI_IMON_SLOT_1C_1D (28 << M989
615 #define M98925_DAI_IMON_SLOT_1D_1E (29 << M989
616 #define M98925_DAI_IMON_SLOT_1E_1F (30 << M989
617
618 /* MAX98925_R024_DOUT_CFG_VBAT */
619 #define M98925_DAI_VBAT_EN_MASK
620 #define M98925_DAI_VBAT_EN_SHIFT
621 #define M98925_DAI_VBAT_EN_WIDTH
622 #define M98925_DAI_VBAT_SLOT_MASK
623 #define M98925_DAI_VBAT_SLOT_SHIFT
624 #define M98925_DAI_VBAT_SLOT_WIDTH
625
626 /* MAX98925_R025_DOUT_CFG_VBST */
627 #define M98925_DAI_VBST_EN_MASK
628 #define M98925_DAI_VBST_EN_SHIFT
629 #define M98925_DAI_VBST_EN_WIDTH
630 #define M98925_DAI_VBST_SLOT_MASK
631 #define M98925_DAI_VBST_SLOT_SHIFT
632 #define M98925_DAI_VBST_SLOT_WIDTH
633
634 /* MAX98925_R026_DOUT_CFG_FLAG */
635 #define M98925_DAI_FLAG_EN_MASK
636 #define M98925_DAI_FLAG_EN_SHIFT
637 #define M98925_DAI_FLAG_EN_WIDTH
638 #define M98925_DAI_FLAG_SLOT_MASK
639 #define M98925_DAI_FLAG_SLOT_SHIFT
640 #define M98925_DAI_FLAG_SLOT_WIDTH
641
642 /* MAX98925_R027_DOUT_HIZ_CFG1 */
643 #define M98925_DAI_SLOT_HIZ_CFG1_MASK
644 #define M98925_DAI_SLOT_HIZ_CFG1_SHIFT
645 #define M98925_DAI_SLOT_HIZ_CFG1_WIDTH
646
647 /* MAX98925_R028_DOUT_HIZ_CFG2 */
648 #define M98925_DAI_SLOT_HIZ_CFG2_MASK
649 #define M98925_DAI_SLOT_HIZ_CFG2_SHIFT
650 #define M98925_DAI_SLOT_HIZ_CFG2_WIDTH
651
652 /* MAX98925_R029_DOUT_HIZ_CFG3 */
653 #define M98925_DAI_SLOT_HIZ_CFG3_MASK
654 #define M98925_DAI_SLOT_HIZ_CFG3_SHIFT
655 #define M98925_DAI_SLOT_HIZ_CFG3_WIDTH
656
657 /* MAX98925_R02A_DOUT_HIZ_CFG4 */
658 #define M98925_DAI_SLOT_HIZ_CFG4_MASK
659 #define M98925_DAI_SLOT_HIZ_CFG4_SHIFT
660 #define M98925_DAI_SLOT_HIZ_CFG4_WIDTH
661
662 /* MAX98925_R02B_DOUT_DRV_STRENGTH */
663 #define M98925_DAI_OUT_DRIVE_MASK
664 #define M98925_DAI_OUT_DRIVE_SHIFT
665 #define M98925_DAI_OUT_DRIVE_WIDTH
666
667 /* MAX98925_R02C_FILTERS */
668 #define M98925_ADC_DITHER_EN_MASK
669 #define M98925_ADC_DITHER_EN_SHIFT
670 #define M98925_ADC_DITHER_EN_WIDTH
671 #define M98925_IV_DCB_EN_MASK
672 #define M98925_IV_DCB_EN_SHIFT
673 #define M98925_IV_DCB_EN_WIDTH
674 #define M98925_DAC_DITHER_EN_MASK
675 #define M98925_DAC_DITHER_EN_SHIFT
676 #define M98925_DAC_DITHER_EN_WIDTH
677 #define M98925_DAC_FILTER_MODE_MASK
678 #define M98925_DAC_FILTER_MODE_SHIFT
679 #define M98925_DAC_FILTER_MODE_WIDTH
680 #define M98925_DAC_HPF_MASK
681 #define M98925_DAC_HPF_SHIFT
682 #define M98925_DAC_HPF_WIDTH
683 #define M98925_DAC_HPF_DISABLE (0 <<
684 #define M98925_DAC_HPF_DC_BLOCK (1 <<
685 #define M98925_DAC_HPF_EN_100 (2 <<
686 #define M98925_DAC_HPF_EN_200 (3 <<
687 #define M98925_DAC_HPF_EN_400 (4 <<
688 #define M98925_DAC_HPF_EN_800 (5 <<
689
690 /* MAX98925_R02D_GAIN */
691 #define M98925_DAC_IN_SEL_MASK
692 #define M98925_DAC_IN_SEL_SHIFT
693 #define M98925_DAC_IN_SEL_WIDTH
694 #define M98925_SPK_GAIN_MASK
695 #define M98925_SPK_GAIN_SHIFT
696 #define M98925_SPK_GAIN_WIDTH
697
698 #define M98925_DAC_IN_SEL_LEFT_DAI (0 << M9892
699 #define M98925_DAC_IN_SEL_RIGHT_DAI (1 << M989
700 #define M98925_DAC_IN_SEL_SUMMED_DAI (2 << M98
701 #define M98925_DAC_IN_SEL_DIV2_SUMMED_DAI (3 <
702
703 /* MAX98925_R02E_GAIN_RAMPING */
704 #define M98925_SPK_RMP_EN_MASK (1<<1)
705 #define M98925_SPK_RMP_EN_SHIFT 1
706 #define M98925_SPK_RMP_EN_WIDTH 1
707 #define M98925_SPK_ZCD_EN_MASK (1<<0)
708 #define M98925_SPK_ZCD_EN_SHIFT 0
709 #define M98925_SPK_ZCD_EN_WIDTH 1
710
711 /* MAX98925_R02F_SPK_AMP */
712 #define M98925_SPK_MODE_MASK (1<<0)
713 #define M98925_SPK_MODE_SHIFT 0
714 #define M98925_SPK_MODE_WIDTH 1
715
716 /* MAX98925_R030_THRESHOLD */
717 #define M98925_ALC_EN_MASK
718 #define M98925_ALC_EN_SHIFT
719 #define M98925_ALC_EN_WIDTH
720 #define M98925_ALC_TH_MASK
721 #define M98925_ALC_TH_SHIFT
722 #define M98925_ALC_TH_WIDTH
723
724 /* MAX98925_R031_ALC_ATTACK */
725 #define M98925_ALC_ATK_STEP_MASK (0x0F<
726 #define M98925_ALC_ATK_STEP_SHIFT 4
727 #define M98925_ALC_ATK_STEP_WIDTH 4
728 #define M98925_ALC_ATK_RATE_MASK (0x7<<
729 #define M98925_ALC_ATK_RATE_SHIFT 0
730 #define M98925_ALC_ATK_RATE_WIDTH 3
731
732 /* MAX98925_R032_ALC_ATTEN_RLS */
733 #define M98925_ALC_MAX_ATTEN_MASK (0x0F<
734 #define M98925_ALC_MAX_ATTEN_SHIFT 4
735 #define M98925_ALC_MAX_ATTEN_WIDTH 4
736 #define M98925_ALC_RLS_RATE_MASK (0x7<<
737 #define M98925_ALC_RLS_RATE_SHIFT 0
738 #define M98925_ALC_RLS_RATE_WIDTH 3
739
740 /* MAX98925_R033_ALC_HOLD_RLS */
741 #define M98925_ALC_RLS_TGR_MASK (1<<0)
742 #define M98925_ALC_RLS_TGR_SHIFT 0
743 #define M98925_ALC_RLS_TGR_WIDTH 1
744
745 /* MAX98925_R034_ALC_CONFIGURATION */
746 #define M98925_ALC_MUTE_EN_MASK (1<<7)
747 #define M98925_ALC_MUTE_EN_SHIFT 7
748 #define M98925_ALC_MUTE_EN_WIDTH 1
749 #define M98925_ALC_MUTE_DLY_MASK (0x07<
750 #define M98925_ALC_MUTE_DLY_SHIFT 4
751 #define M98925_ALC_MUTE_DLY_WIDTH 3
752 #define M98925_ALC_RLS_DBT_MASK (0x07<
753 #define M98925_ALC_RLS_DBT_SHIFT 0
754 #define M98925_ALC_RLS_DBT_WIDTH 3
755
756 /* MAX98925_R035_BOOST_CONVERTER */
757 #define M98925_BST_SYNC_MASK (1<<7)
758 #define M98925_BST_SYNC_SHIFT 7
759 #define M98925_BST_SYNC_WIDTH 1
760 #define M98925_BST_PHASE_MASK (0x03<
761 #define M98925_BST_PHASE_SHIFT 4
762 #define M98925_BST_PHASE_WIDTH 2
763 #define M98925_BST_SKIP_MODE_MASK (0x03<
764 #define M98925_BST_SKIP_MODE_SHIFT 0
765 #define M98925_BST_SKIP_MODE_WIDTH 2
766
767 /* MAX98925_R036_BLOCK_ENABLE */
768 #define M98925_BST_EN_MASK
769 #define M98925_BST_EN_SHIFT
770 #define M98925_BST_EN_WIDTH
771 #define M98925_WATCH_EN_MASK (1<<6)
772 #define M98925_WATCH_EN_SHIFT 6
773 #define M98925_WATCH_EN_WIDTH 1
774 #define M98925_CLKMON_EN_MASK (1<<5)
775 #define M98925_CLKMON_EN_SHIFT 5
776 #define M98925_CLKMON_EN_WIDTH 1
777 #define M98925_SPK_EN_MASK
778 #define M98925_SPK_EN_SHIFT
779 #define M98925_SPK_EN_WIDTH
780 #define M98925_ADC_VBST_EN_MASK (1<<3)
781 #define M98925_ADC_VBST_EN_SHIFT 3
782 #define M98925_ADC_VBST_EN_WIDTH 1
783 #define M98925_ADC_VBAT_EN_MASK (1<<2)
784 #define M98925_ADC_VBAT_EN_SHIFT 2
785 #define M98925_ADC_VBAT_EN_WIDTH 1
786 #define M98925_ADC_IMON_EN_MASK (1<<1)
787 #define M98925_ADC_IMON_EN_SHIFT 1
788 #define M98925_ADC_IMON_EN_WIDTH 1
789 #define M98925_ADC_VMON_EN_MASK (1<<0)
790 #define M98925_ADC_VMON_EN_SHIFT 0
791 #define M98925_ADC_VMON_EN_WIDTH 1
792
793 /* MAX98925_R037_CONFIGURATION */
794 #define M98925_BST_VOUT_MASK (0x0F<
795 #define M98925_BST_VOUT_SHIFT 4
796 #define M98925_BST_VOUT_WIDTH 4
797 #define M98925_THERMWARN_LEVEL_MASK (0x03<
798 #define M98925_THERMWARN_LEVEL_SHIFT
799 #define M98925_THERMWARN_LEVEL_WIDTH
800 #define M98925_WATCH_TIME_MASK
801 #define M98925_WATCH_TIME_SHIFT
802 #define M98925_WATCH_TIME_WIDTH
803
804 /* MAX98925_R038_GLOBAL_ENABLE */
805 #define M98925_EN_MASK (1<<7)
806 #define M98925_EN_SHIFT 7
807 #define M98925_EN_WIDTH 1
808
809 /* MAX98925_R03A_BOOST_LIMITER */
810 #define M98925_BST_ILIM_MASK (0x1F<<3)
811 #define M98925_BST_ILIM_SHIFT 3
812 #define M98925_BST_ILIM_WIDTH 5
813
814 /* MAX98925_R0FF_VERSION */
815 #define M98925_REV_ID_MASK (0xFF<<0)
816 #define M98925_REV_ID_SHIFT 0
817 #define M98925_REV_ID_WIDTH 8
818
819 struct max98925_priv {
820 struct regmap *regmap;
821 struct snd_soc_component *component;
822 struct max98925_pdata *pdata;
823 unsigned int sysclk;
824 unsigned int v_slot;
825 unsigned int i_slot;
826 unsigned int spk_gain;
827 unsigned int ch_size;
828 };
829 #endif
830
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