1 // SPDX-License-Identifier: GPL-2.0 1
2 /*
3 * MT6357 ALSA SoC audio codec driver
4 *
5 * Copyright (c) 2024 Baylibre
6 * Author: Nicolas Belin <nbelin@baylibre.com>
7 */
8
9 #include <linux/dma-mapping.h>
10 #include <sound/soc.h>
11 #include <sound/tlv.h>
12 #include <linux/mfd/mt6397/core.h>
13 #include <linux/regulator/consumer.h>
14
15 #include "mt6357.h"
16
17 static void set_playback_gpio(struct mt6357_pr
18 {
19 regmap_write(priv->regmap, MT6357_GPIO
20 if (enable) {
21 /* set gpio mosi mode */
22 regmap_write(priv->regmap, MT6
23 MT6357_GPIO8_MODE
24 MT6357_GPIO9_MODE
25 MT6357_GPIO10_MOD
26 MT6357_GPIO11_MOD
27 } else {
28 /* pad_aud_*_mosi are GPIO mod
29 * reason:
30 * pad_aud_dat_mosi*, because
31 */
32 regmap_update_bits(priv->regma
33 MT6357_GPIO
34 MT6357_GPIO
35 MT6357_GPIO
36 MT6357_GPIO
37 MT6357_GPIO
38 MT6357_GPIO
39 MT6357_GPIO
40 MT6357_GPIO
41 }
42 }
43
44 static void set_capture_gpio(struct mt6357_pri
45 {
46 regmap_write(priv->regmap, MT6357_GPIO
47 if (enable) {
48 /* set gpio miso mode */
49 regmap_write(priv->regmap, MT6
50 MT6357_GPIO12_MOD
51 MT6357_GPIO13_MOD
52 MT6357_GPIO14_MOD
53 MT6357_GPIO15_MOD
54 } else {
55 /* pad_aud_*_mosi are GPIO mod
56 * reason:
57 * pad_aud_clk_miso, because w
58 * will also have 26m, so will
59 * pad_aud_dat_miso*, because
60 */
61 regmap_update_bits(priv->regma
62 MT6357_GPIO
63 MT6357_GPIO
64 MT6357_GPIO
65 MT6357_GPIO
66 MT6357_GPIO
67 MT6357_GPIO
68 MT6357_GPIO
69 MT6357_GPIO
70 }
71 }
72
73 static void hp_main_output_ramp(struct mt6357_
74 {
75 int i, stage;
76
77 /* Enable/Reduce HPL/R main output sta
78 for (i = 0; i <= MT6357_HPLOUT_STG_CTR
79 stage = up ? i : MT6357_HPLOUT
80 regmap_update_bits(priv->regma
81 MT6357_HPLO
82 stage << MT
83 regmap_update_bits(priv->regma
84 MT6357_HPRO
85 stage << MT
86 usleep_range(600, 700);
87 }
88 }
89
90 static void hp_aux_feedback_loop_gain_ramp(str
91 {
92 int i, stage;
93
94 /* Reduce HP aux feedback loop gain st
95 for (i = 0; i <= MT6357_HP_AUX_LOOP_GA
96 stage = up ? i : MT6357_HP_AUX
97 regmap_update_bits(priv->regma
98 MT6357_HP_A
99 stage << MT
100 usleep_range(600, 700);
101 }
102 }
103
104 static void hp_pull_down(struct mt6357_priv *p
105 {
106 if (enable)
107 regmap_update_bits(priv->regma
108 MT6357_HPP_
109 MT6357_HPP_
110 else
111 regmap_update_bits(priv->regma
112 MT6357_HPP_
113 MT6357_HPP_
114 }
115
116 static bool is_valid_hp_pga_idx(int reg_idx)
117 {
118 return (reg_idx >= DL_GAIN_8DB && reg_
119 }
120
121 static void volume_ramp(struct mt6357_priv *pr
122 int rfrom, int rto, un
123 {
124 int lcount, rcount, sleep = 0;
125
126 if (!is_valid_hp_pga_idx(lfrom) || !is
127 pr_debug("%s(), invalid left v
128 __func__, lfrom, lto)
129
130 if (!is_valid_hp_pga_idx(rfrom) || !is
131 pr_debug("%s(), invalid right
132 __func__, rfrom, rto)
133
134 if (lto > lfrom)
135 lcount = 1;
136 else
137 lcount = -1;
138
139 if (rto > rfrom)
140 rcount = 1;
141 else
142 rcount = -1;
143
144 while ((lto != lfrom) || (rto != rfrom
145 if (lto != lfrom) {
146 lfrom += lcount;
147 if (is_valid_hp_pga_id
148 regmap_update_
149
150
151 sleep = 1;
152 }
153 }
154 if (rto != rfrom) {
155 rfrom += rcount;
156 if (is_valid_hp_pga_id
157 regmap_update_
158
159
160 sleep = 1;
161 }
162 }
163 if (sleep)
164 usleep_range(200, 300)
165 }
166 }
167
168 static void lo_volume_ramp(struct mt6357_priv
169 {
170 volume_ramp(priv, lfrom, lto, rfrom, r
171 }
172
173 static void hp_volume_ramp(struct mt6357_priv
174 {
175 volume_ramp(priv, lfrom, lto, rfrom, r
176 }
177
178 static void hs_volume_ramp(struct mt6357_priv
179 {
180 volume_ramp(priv, from, to, 0, 0, MT63
181 }
182
183 /* Volume and channel swap controls */
184 static const DECLARE_TLV_DB_SCALE(playback_tlv
185 static const DECLARE_TLV_DB_SCALE(capture_tlv,
186 static const DECLARE_TLV_DB_SCALE(hp_degain_tl
187
188 static const struct snd_kcontrol_new mt6357_co
189 /* dl pga gain */
190 SOC_DOUBLE_TLV("Headphone Volume",
191 MT6357_ZCD_CON2, MT6357
192 MT6357_AUD_HPR_GAIN_SFT
193 1, playback_tlv),
194 SOC_SINGLE_TLV("Headphone Vin Volume",
195 MT6357_AUDDEC_ANA_CON7,
196 MT6357_HP_IVBUF_DEGAIN_
197 SOC_DOUBLE_TLV("Lineout Volume",
198 MT6357_ZCD_CON1, MT6357
199 MT6357_AUD_LOR_GAIN_SFT
200 1, playback_tlv),
201 SOC_SINGLE_TLV("Handset Volume",
202 MT6357_ZCD_CON3, MT6357
203 MT6357_AUD_HS_GAIN_MAX,
204 /* ul pga gain */
205 SOC_DOUBLE_R_TLV("Mic Volume",
206 MT6357_AUDENC_ANA_CON
207 MT6357_AUDPREAMPLGAIN
208 0, capture_tlv),
209 };
210
211 /* Uplink controls */
212
213 enum {
214 MIC_TYPE_MUX_IDLE,
215 MIC_TYPE_MUX_ACC,
216 MIC_TYPE_MUX_DMIC,
217 MIC_TYPE_MUX_DCC,
218 MIC_TYPE_MUX_DCC_ECM_DIFF,
219 MIC_TYPE_MUX_DCC_ECM_SINGLE,
220 MIC_TYPE_MUX_LPBK,
221 MIC_TYPE_MUX_SGEN,
222 };
223
224 #define IS_DCC_BASE(type) ((type) == MIC_TYPE_
225 (type) == MIC_TYPE_MUX
226 (type) == MIC_TYPE_MUX
227
228 static const char * const mic_type_mux_map[] =
229 "Idle",
230 "ACC",
231 "DMIC",
232 "DCC",
233 "DCC_ECM_DIFF",
234 "DCC_ECM_SINGLE",
235 "Loopback",
236 "Sine Generator",
237 };
238
239 static SOC_ENUM_SINGLE_DECL(mic_type_mux_map_e
240 0, mic_type_mux_ma
241
242 static const struct snd_kcontrol_new mic_type_
243 SOC_DAPM_ENUM("Mic Type Select", mic_t
244
245 static const char * const pga_mux_map[] = {
246 "None", "AIN0", "AIN1", "AIN2"
247 };
248
249 static SOC_ENUM_SINGLE_DECL(pga_left_mux_map_e
250 MT6357_AUDENC_ANA_
251 MT6357_AUDPREAMPLI
252 pga_mux_map);
253
254 static const struct snd_kcontrol_new pga_left_
255 SOC_DAPM_ENUM("PGA L Select", pga_left
256
257 static SOC_ENUM_SINGLE_DECL(pga_right_mux_map_
258 MT6357_AUDENC_ANA_
259 MT6357_AUDPREAMPRI
260 pga_mux_map);
261
262 static const struct snd_kcontrol_new pga_right
263 SOC_DAPM_ENUM("PGA R Select", pga_righ
264
265 /* Downlink controls */
266 static const char * const hslo_mux_map[] = {
267 "Open", "DACR", "Playback", "Test mode
268 };
269
270 static SOC_ENUM_SINGLE_DECL(lo_mux_map_enum,
271 MT6357_AUDDEC_ANA_
272 MT6357_AUD_LOL_MUX
273 hslo_mux_map);
274
275 static const struct snd_kcontrol_new lo_mux_co
276 SOC_DAPM_ENUM("Line out source", lo_mu
277
278 static SOC_ENUM_SINGLE_DECL(hs_mux_map_enum,
279 MT6357_AUDDEC_ANA_
280 MT6357_AUD_HS_MUX_
281 hslo_mux_map);
282
283 static const struct snd_kcontrol_new hs_mux_co
284 SOC_DAPM_ENUM("Handset source", hs_mux
285
286 static const char * const hplr_mux_map[] = {
287 "Open", "Line Out", "DAC", "Handset"
288 };
289
290 static SOC_ENUM_SINGLE_DECL(hpr_mux_map_enum,
291 MT6357_AUDDEC_ANA_
292 MT6357_AUD_HPR_MUX
293 hplr_mux_map);
294
295 static const struct snd_kcontrol_new hpr_mux_c
296 SOC_DAPM_ENUM("Headphone Right source"
297
298 static SOC_ENUM_SINGLE_DECL(hpl_mux_map_enum,
299 MT6357_AUDDEC_ANA_
300 MT6357_AUD_HPL_MUX
301 hplr_mux_map);
302
303 static const struct snd_kcontrol_new hpl_mux_c
304 SOC_DAPM_ENUM("Headphone Left source",
305
306 static const char * const dac_mux_map[] = {
307 "Normal Path", "Sine Generator"
308 };
309
310 static SOC_ENUM_SINGLE_DECL(dac_mux_map_enum,
311 MT6357_AFE_TOP_CON
312 MT6357_DL_SINE_ON_
313 dac_mux_map);
314
315 static const struct snd_kcontrol_new dac_mux_c
316 SOC_DAPM_ENUM("DAC Select", dac_mux_ma
317
318 static int mt6357_set_dmic(struct mt6357_priv
319 {
320 if (enable) {
321 /* DMIC enable */
322 regmap_update_bits(priv->regma
323 MT6357_AUDD
324 MT6357_AUDD
325 /* enable aud_pad TX fifos */
326 regmap_update_bits(priv->regma
327 MT6357_AUD_
328 MT6357_AUD_
329 /* UL dmic setting: dual mode
330 regmap_update_bits(priv->regma
331 MT6357_C_TW
332 MT6357_C_TW
333 /* UL turn on SDM 3 level mode
334 regmap_update_bits(priv->regma
335 MT6357_UL_S
336 MT6357_UL_S
337 /* UL turn on */
338 regmap_update_bits(priv->regma
339 MT6357_UL_S
340 MT6357_UL_S
341 /* Wait to avoid any pop noise
342 msleep(100);
343 } else {
344 /* UL turn off */
345 regmap_update_bits(priv->regma
346 MT6357_UL_S
347 MT6357_UL_S
348 /* UL turn on SDM 3 level mode
349 regmap_update_bits(priv->regma
350 MT6357_UL_S
351 MT6357_UL_S
352 /* disable aud_pad TX fifos */
353 regmap_update_bits(priv->regma
354 MT6357_AUD_
355 MT6357_AUD_
356 /* UL dmic setting: dual mode
357 regmap_update_bits(priv->regma
358 MT6357_C_TW
359 MT6357_C_TW
360 /* DMIC disable */
361 regmap_update_bits(priv->regma
362 MT6357_AUDD
363 MT6357_AUDD
364 }
365 return 0;
366 }
367
368 static int mt6357_set_amic(struct mt6357_priv
369 {
370 if (enable) {
371 if (IS_DCC_BASE(mic_type)) {
372 regmap_update_bits(pri
373 MT6
374 regmap_update_bits(pri
375 MT6
376 regmap_update_bits(pri
377 MT6
378 regmap_update_bits(pri
379 MT6
380 MT6
381
382 /* mic bias 0: set the
383 switch (mic_type) {
384 case MIC_TYPE_MUX_DCC_
385 regmap_update_
386
387
388 break;
389 case MIC_TYPE_MUX_DCC_
390 regmap_update_
391
392
393 break;
394 default:
395 regmap_update_
396
397
398 break;
399 }
400
401 /* mic bias 1: set the
402 if (mic_type == MIC_TY
403 regmap_update_
404
405
406
407 /* Audio L/R preamplif
408 regmap_update_bits(pri
409 MT6
410 MT6
411 regmap_update_bits(pri
412 MT6
413 MT6
414 /* L preamplifier DCCE
415 regmap_update_bits(pri
416 MT6
417 MT6
418 /* R preamplifier DCCE
419 regmap_update_bits(pri
420 MT6
421 MT6
422 } else {
423 /* Audio L preamplifie
424 regmap_update_bits(pri
425 MT6
426 MT6
427 /* L preamplifier ACC
428 regmap_update_bits(pri
429 MT6
430 MT6
431 /* Audio R preamplifie
432 regmap_update_bits(pri
433 MT6
434 MT6
435 /* R preamplifier ACC
436 regmap_update_bits(pri
437 MT6
438 MT6
439 }
440 } else {
441 /* disable any Mic Bias 0 DC c
442 regmap_update_bits(priv->regma
443 MT6357_AUD_
444 MT6357_AUD_
445 /* disable any Mic Bias 1 DC c
446 regmap_update_bits(priv->regma
447 MT6357_AUD_
448 MT6357_AUD_
449 if (IS_DCC_BASE(mic_type)) {
450 regmap_update_bits(pri
451 MT6
452 regmap_update_bits(pri
453 MT6
454 regmap_update_bits(pri
455 MT6
456 }
457 }
458
459 return 0;
460 }
461
462 static int mt6357_set_loopback(struct mt6357_p
463 {
464 if (enable) {
465 /* enable aud_pad TX fifos */
466 regmap_update_bits(priv->regma
467 MT6357_AUD_
468 MT6357_AUD_
469 /* enable aud_pad lpk TX fifos
470 regmap_update_bits(priv->regma
471 MT6357_AUD_
472 MT6357_AUD_
473 /* Set UL Part: enable new lpb
474 regmap_update_bits(priv->regma
475 MT6357_ADDA
476 MT6357_ADDA
477 /* UL turn on */
478 regmap_update_bits(priv->regma
479 MT6357_UL_S
480 MT6357_UL_S
481 } else {
482 /* UL turn off */
483 regmap_update_bits(priv->regma
484 MT6357_UL_S
485 MT6357_UL_S
486 /* disable new lpbk 2 */
487 regmap_update_bits(priv->regma
488 MT6357_ADDA
489 MT6357_ADDA
490 /* disable aud_pad lpbk TX fif
491 regmap_update_bits(priv->regma
492 MT6357_AUD_
493 MT6357_AUD_
494 /* disable aud_pad TX fifos */
495 regmap_update_bits(priv->regma
496 MT6357_AUD_
497 MT6357_AUD_
498 }
499
500 return 0;
501 }
502
503 static int mt6357_set_ul_sine_gen(struct mt635
504 {
505 if (enable) {
506 /* enable aud_pad TX fifos */
507 regmap_update_bits(priv->regma
508 MT6357_AUD_
509 MT6357_AUD_
510 /* UL turn on */
511 regmap_update_bits(priv->regma
512 MT6357_UL_S
513 MT6357_UL_S
514 } else {
515 /* UL turn off */
516 regmap_update_bits(priv->regma
517 MT6357_UL_S
518 MT6357_UL_S
519 /* disable aud_pad TX fifos */
520 regmap_update_bits(priv->regma
521 MT6357_AUD_
522 MT6357_AUD_
523 }
524
525 return 0;
526 }
527
528 static int mt_aif_out_event(struct snd_soc_dap
529 struct snd_kcontro
530 int event)
531 {
532 struct snd_soc_component *cmpnt = snd_
533 struct mt6357_priv *priv = snd_soc_com
534
535 switch (event) {
536 case SND_SOC_DAPM_PRE_PMU:
537 set_capture_gpio(priv, true);
538 break;
539 case SND_SOC_DAPM_POST_PMD:
540 set_capture_gpio(priv, false);
541 break;
542 default:
543 break;
544 }
545
546 return 0;
547 }
548
549 static int mt_adc_supply_event(struct snd_soc_
550 struct snd_kcon
551 int event)
552 {
553 struct snd_soc_component *cmpnt = snd_
554 struct mt6357_priv *priv = snd_soc_com
555
556 switch (event) {
557 case SND_SOC_DAPM_PRE_PMU:
558 /* Enable audio ADC CLKGEN */
559 regmap_update_bits(priv->regma
560 MT6357_RSTB
561 /* Enable LCLDO_ENC 2P8V */
562 regmap_update_bits(priv->regma
563 MT6357_LCLD
564 /* LCLDO_ENC remote sense */
565 regmap_update_bits(priv->regma
566 MT6357_VA28
567 MT6357_LCLD
568 MT6357_VA28
569 MT6357_LCLD
570 break;
571 case SND_SOC_DAPM_POST_PMD:
572 /* LCLDO_ENC remote sense off
573 regmap_update_bits(priv->regma
574 MT6357_VA28
575 MT6357_LCLD
576 MT6357_VA28
577 MT6357_LCLD
578 /* disable LCLDO_ENC 2P8V */
579 regmap_update_bits(priv->regma
580 MT6357_LCLD
581 MT6357_LCLD
582 /* disable audio ADC CLKGEN *
583 regmap_update_bits(priv->regma
584 MT6357_RSTB
585 MT6357_RSTB
586 break;
587 default:
588 break;
589 }
590
591 return 0;
592 }
593
594 static int mt_mic_type_event(struct snd_soc_da
595 struct snd_kcontr
596 int event)
597 {
598 struct snd_soc_component *cmpnt = snd_
599 struct mt6357_priv *priv = snd_soc_com
600 unsigned int mic_type = dapm_kcontrol_
601
602 switch (event) {
603 case SND_SOC_DAPM_PRE_PMU:
604 switch (mic_type) {
605 case MIC_TYPE_MUX_DMIC:
606 mt6357_set_dmic(priv,
607 break;
608 case MIC_TYPE_MUX_LPBK:
609 mt6357_set_loopback(pr
610 break;
611 case MIC_TYPE_MUX_SGEN:
612 mt6357_set_ul_sine_gen
613 break;
614 default:
615 mt6357_set_amic(priv,
616 break;
617 }
618 break;
619 case SND_SOC_DAPM_POST_PMD:
620 switch (mic_type) {
621 case MIC_TYPE_MUX_DMIC:
622 mt6357_set_dmic(priv,
623 break;
624 case MIC_TYPE_MUX_LPBK:
625 mt6357_set_loopback(pr
626 break;
627 case MIC_TYPE_MUX_SGEN:
628 mt6357_set_ul_sine_gen
629 break;
630 default:
631 mt6357_set_amic(priv,
632 break;
633 }
634 break;
635 default:
636 break;
637 }
638
639 return 0;
640 }
641
642 static int mt_pga_left_event(struct snd_soc_da
643 struct snd_kcontr
644 int event)
645 {
646 struct snd_soc_component *cmpnt = snd_
647 struct mt6357_priv *priv = snd_soc_com
648
649 switch (event) {
650 case SND_SOC_DAPM_POST_PMU:
651 /* L preamplifier enable */
652 regmap_update_bits(priv->regma
653 MT6357_AUDP
654 MT6357_AUDP
655 /* L ADC input sel : L PGA. En
656 regmap_update_bits(priv->regma
657 MT6357_AUDA
658 MT6357_AUDA
659 regmap_update_bits(priv->regma
660 MT6357_AUDA
661 MT6357_AUDA
662 /* Audio L preamplifier DCC pr
663 regmap_update_bits(priv->regma
664 MT6357_AUDP
665 MT6357_AUDP
666 break;
667 case SND_SOC_DAPM_PRE_PMD:
668 /* Audio L ADC input sel : off
669 regmap_update_bits(priv->regma
670 MT6357_AUDA
671 MT6357_AUDA
672 regmap_update_bits(priv->regma
673 MT6357_AUDA
674 MT6357_AUDA
675 /* L preamplifier ACC */
676 regmap_update_bits(priv->regma
677 MT6357_AUDP
678 MT6357_AUDP
679 /* L preamplifier disable */
680 regmap_update_bits(priv->regma
681 MT6357_AUDP
682 MT6357_AUDP
683 /* disable Audio L preamplifie
684 regmap_update_bits(priv->regma
685 MT6357_AUDP
686 MT6357_AUDP
687 break;
688 default:
689 break;
690 }
691
692 return 0;
693 }
694
695 static int mt_pga_right_event(struct snd_soc_d
696 struct snd_kcont
697 int event)
698 {
699 struct snd_soc_component *cmpnt = snd_
700 struct mt6357_priv *priv = snd_soc_com
701
702 switch (event) {
703 case SND_SOC_DAPM_POST_PMU:
704 /* R preamplifier enable */
705 regmap_update_bits(priv->regma
706 MT6357_AUDP
707 /* R ADC input sel : R PGA. En
708 regmap_update_bits(priv->regma
709 MT6357_AUDA
710 MT6357_AUDA
711 regmap_update_bits(priv->regma
712 MT6357_AUDA
713 /* Audio R preamplifier DCC pr
714 regmap_update_bits(priv->regma
715 MT6357_AUDP
716 MT6357_AUDP
717 break;
718 case SND_SOC_DAPM_PRE_PMD:
719 /* Audio R ADC input sel : off
720 regmap_update_bits(priv->regma
721 MT6357_AUDA
722 regmap_update_bits(priv->regma
723 MT6357_AUDA
724 /* R preamplifier ACC */
725 regmap_update_bits(priv->regma
726 MT6357_AUDP
727 /* R preamplifier disable */
728 regmap_update_bits(priv->regma
729 MT6357_AUDP
730 /* disable Audio R preamplifie
731 regmap_update_bits(priv->regma
732 MT6357_AUDP
733 MT6357_AUDP
734 break;
735 default:
736 break;
737 }
738
739 return 0;
740 }
741
742 static int adc_enable_event(struct snd_soc_dap
743 struct snd_kcontro
744 int event)
745 {
746 struct snd_soc_component *cmpnt = snd_
747 struct mt6357_priv *priv = snd_soc_com
748 int lgain, rgain;
749
750 switch (event) {
751 case SND_SOC_DAPM_PRE_PMU:
752 regmap_read(priv->regmap, MT63
753 regmap_read(priv->regmap, MT63
754 /* L PGA 0 dB gain */
755 regmap_update_bits(priv->regma
756 MT6357_AUDP
757 UL_GAIN_0DB
758 /* R PGA 0 dB gain */
759 regmap_update_bits(priv->regma
760 MT6357_AUDP
761 UL_GAIN_0DB
762 /* enable aud_pad TX fifos */
763 regmap_update_bits(priv->regma
764 MT6357_AUD_
765 MT6357_AUD_
766 /* UL turn on */
767 regmap_update_bits(priv->regma
768 MT6357_UL_S
769 /* Wait to avoid any pop noise
770 msleep(100);
771 /* set the mic gains to the st
772 regmap_update_bits(priv->regma
773 MT6357_AUDP
774 regmap_update_bits(priv->regma
775 MT6357_AUDP
776 break;
777 case SND_SOC_DAPM_POST_PMD:
778 /* UL turn off */
779 regmap_update_bits(priv->regma
780 MT6357_UL_S
781 /* disable aud_pad TX fifos */
782 regmap_update_bits(priv->regma
783 MT6357_AUD_
784 MT6357_AUD_
785 break;
786 default:
787 break;
788 }
789
790 return 0;
791 }
792
793 static void configure_downlinks(struct mt6357_
794 {
795 if (enable) {
796 regmap_update_bits(priv->regma
797 MT6357_AUD_
798 MT6357_AUD_
799 /* Disable headphone short-cir
800 regmap_update_bits(priv->regma
801 MT6357_AUD_
802 MT6357_AUD_
803 MT6357_AUD_
804 /* Disable handset short-circu
805 regmap_update_bits(priv->regma
806 MT6357_AUD_
807 MT6357_AUD_
808 /* Disable lineout short-circu
809 regmap_update_bits(priv->regma
810 MT6357_AUD_
811 MT6357_AUD_
812 /* Reduce ESD resistance of AU
813 regmap_update_bits(priv->regma
814 MT6357_AUD_
815 MT6357_AUD_
816 /* Turn on DA_600K_NCP_VA18 */
817 regmap_write(priv->regmap, MT6
818 /* Set NCP clock as 604kHz //
819 regmap_write(priv->regmap, MT6
820 /* Toggle DIVCKS_CHG */
821 regmap_write(priv->regmap, MT6
822 /* Set NCP soft start mode as
823 regmap_write(priv->regmap, MT6
824 MT6357_DIVCKS_PWD
825 /* Enable NCP */
826 regmap_write(priv->regmap, MT6
827 MT6357_DIVCKS_PWD
828 usleep_range(250, 270);
829 /* Enable cap-less LDOs (1.5V)
830 regmap_update_bits(priv->regma
831 MT6357_VA33
832 MT6357_LCLD
833 MT6357_LCLD
834 MT6357_HCLD
835 MT6357_HCLD
836 MT6357_VA33
837 MT6357_LCLD
838 MT6357_LCLD
839 MT6357_HCLD
840 MT6357_HCLD
841 /* Enable NV regulator (-1.2V)
842 regmap_update_bits(priv->regma
843 MT6357_NVRE
844 usleep_range(100, 120);
845 /* Enable IBIST */
846 regmap_update_bits(priv->regma
847 MT6357_AUD_
848 MT6357_AUD_
849 /* Enable AUD_CLK */
850 regmap_update_bits(priv->regma
851 MT6357_RSTB
852 MT6357_RSTB
853 /* Enable low-noise mode of DA
854 regmap_update_bits(priv->regma
855 MT6357_DAC_
856 MT6357_DAC_
857 usleep_range(100, 120);
858 } else {
859 /* Disable low-noise mode of D
860 regmap_update_bits(priv->regma
861 MT6357_DAC_
862 MT6357_DAC_
863 /* Disable AUD_CLK */
864 regmap_update_bits(priv->regma
865 MT6357_RSTB
866 MT6357_RSTB
867 /* Enable linout short-circuit
868 regmap_update_bits(priv->regma
869 MT6357_AUD_
870 MT6357_AUD_
871 /* Enable handset short-circui
872 regmap_update_bits(priv->regma
873 MT6357_AUD_
874 MT6357_AUD_
875 /* Enable headphone short-circ
876 regmap_update_bits(priv->regma
877 MT6357_AUD_
878 MT6357_AUD_
879 MT6357_AUD_
880 MT6357_AUD_
881 /* Disable IBIST */
882 regmap_update_bits(priv->regma
883 MT6357_AUD_
884 MT6357_AUD_
885 /* Disable NV regulator (-1.2V
886 regmap_update_bits(priv->regma
887 MT6357_NVRE
888 MT6357_NVRE
889 /* Disable cap-less LDOs (1.5V
890 regmap_update_bits(priv->regma
891 MT6357_VA33
892 MT6357_LCLD
893 MT6357_LCLD
894 MT6357_HCLD
895 MT6357_HCLD
896 MT6357_VA33
897 MT6357_LCLD
898 MT6357_LCLD
899 MT6357_HCLD
900 MT6357_HCLD
901 /* Disable NCP */
902 regmap_update_bits(priv->regma
903 MT6357_DIVC
904 }
905 }
906
907 static int mt_audio_in_event(struct snd_soc_da
908 struct snd_kcontr
909 int event)
910 {
911 struct snd_soc_component *cmpnt = snd_
912 struct mt6357_priv *priv = snd_soc_com
913
914 switch (event) {
915 case SND_SOC_DAPM_PRE_PMU:
916 set_playback_gpio(priv, true);
917
918 /* Pull-down HPL/R to AVSS28_A
919 if (priv->pull_down_needed)
920 hp_pull_down(priv, tru
921
922 /* Disable HP main CMFB Switch
923 regmap_update_bits(priv->regma
924 MT6357_HPRL
925 MT6357_HPRL
926 /* Audio system digital clock
927 regmap_write(priv->regmap, MT6
928 MT6357_CCI_AUDIO_
929 MT6357_CCI_ACD_MO
930 MT6357_CCI_AFIFO_
931 MT6357_CCI_ACD_FU
932 /* sdm audio fifo clock power
933 regmap_write(priv->regmap, MT6
934 MT6357_CCI_AUD_AN
935 (4 << MT6357_CCI_
936 MT6357_CCI_SCRAMB
937 MT6357_CCI_RAND_E
938 MT6357_CCI_SPLT_S
939 MT6357_CCI_SPLT_S
940 MT6357_CCI_ZERO_P
941 MT6357_CCI_SCRAMB
942 /* scrambler clock on enable *
943 regmap_write(priv->regmap, MT6
944 MT6357_CCI_AUDIO_
945 MT6357_CCI_ACD_MO
946 MT6357_CCI_AFIFO_
947 MT6357_CCI_ACD_FU
948 /* sdm power on */
949 regmap_write(priv->regmap, MT6
950 MT6357_CCI_AUDIO_
951 MT6357_CCI_ACD_MO
952 MT6357_CCI_AFIFO_
953 MT6357_CCI_ACD_FU
954
955 configure_downlinks(priv, true
956 break;
957 case SND_SOC_DAPM_POST_PMD:
958 configure_downlinks(priv, fals
959 /* DL scrambler disabling sequ
960 regmap_write(priv->regmap, MT6
961 MT6357_CCI_AUDIO_
962 MT6357_CCI_ACD_MO
963 MT6357_CCI_AFIFO_
964 MT6357_CCI_ACD_FU
965 regmap_write(priv->regmap, MT6
966 MT6357_CCI_AUD_AN
967 (4 << MT6357_CCI_
968 MT6357_CCI_SCRAMB
969 MT6357_CCI_RAND_E
970 MT6357_CCI_SPLT_S
971 MT6357_CCI_SPLT_S
972 MT6357_CCI_ZERO_P
973 MT6357_CCI_SCRAMB
974
975 set_playback_gpio(priv, false)
976
977 /* disable Pull-down HPL/R to
978 if (priv->pull_down_needed)
979 hp_pull_down(priv, fal
980 break;
981 default:
982 break;
983 }
984
985 return 0;
986 }
987
988 static int mt_delay_250_event(struct snd_soc_d
989 struct snd_kcont
990 int event)
991 {
992 switch (event) {
993 case SND_SOC_DAPM_POST_PMU:
994 usleep_range(250, 270);
995 break;
996 case SND_SOC_DAPM_PRE_PMD:
997 usleep_range(250, 270);
998 break;
999 default:
1000 break;
1001 }
1002
1003 return 0;
1004 }
1005
1006 static int lo_mux_event(struct snd_soc_dapm_w
1007 struct snd_kcontrol *
1008 int event)
1009 {
1010 struct snd_soc_component *cmpnt = snd
1011 struct mt6357_priv *priv = snd_soc_co
1012 int lgain, rgain;
1013
1014 /* Get current gain value */
1015 regmap_read(priv->regmap, MT6357_ZCD_
1016 rgain = (lgain & MT6357_AUD_LOR_GAIN_
1017 lgain = lgain & MT6357_AUD_LOL_GAIN_M
1018 switch (event) {
1019 case SND_SOC_DAPM_POST_PMU:
1020 /* Set -40dB before enable HS
1021 regmap_update_bits(priv->regm
1022 MT6357_AUD
1023 MT6357_AUD
1024 MT6357_DL_
1025 /* Set LO STB enhance circuit
1026 regmap_update_bits(priv->regm
1027 MT6357_AUD
1028 MT6357_AUD
1029 /* Enable LO driver bias circ
1030 regmap_update_bits(priv->regm
1031 MT6357_AUD
1032 MT6357_AUD
1033 /* Enable LO driver core circ
1034 regmap_update_bits(priv->regm
1035 MT6357_AUD
1036 MT6357_AUD
1037 /* Set LOL gain to normal gai
1038 lo_volume_ramp(priv, DL_GAIN_
1039 DL_GAIN_N_40DB
1040 break;
1041 case SND_SOC_DAPM_PRE_PMD:
1042 /* decrease LOL gain to minim
1043
1044 lo_volume_ramp(priv, lgain, D
1045 rgain, DL_GAIN
1046 /* Disable LO driver core cir
1047 regmap_update_bits(priv->regm
1048 MT6357_AUD
1049 MT6357_AUD
1050 /* Disable LO driver bias cir
1051 regmap_update_bits(priv->regm
1052 MT6357_AUD
1053 MT6357_AUD
1054 /* Clear LO STB enhance circu
1055 regmap_update_bits(priv->regm
1056 MT6357_AUD
1057 MT6357_AUD
1058 /* Save the gain value into t
1059 regmap_update_bits(priv->regm
1060 MT6357_AUD
1061 MT6357_AUD
1062 lgain << M
1063 rgain << M
1064
1065 break;
1066 default:
1067 break;
1068 }
1069
1070 return 0;
1071 }
1072
1073 static int hs_mux_event(struct snd_soc_dapm_w
1074 struct snd_kcontrol *
1075 int event)
1076 {
1077 struct snd_soc_component *cmpnt = snd
1078 struct mt6357_priv *priv = snd_soc_co
1079 int gain; /* HS register has only one
1080
1081 /* Get current gain value */
1082 regmap_read(priv->regmap, MT6357_ZCD_
1083 switch (event) {
1084 case SND_SOC_DAPM_POST_PMU:
1085 /* Set -40dB before enable HS
1086 regmap_update_bits(priv->regm
1087 MT6357_AUD
1088 DL_GAIN_N_
1089
1090 /* Set HS STB enhance circuit
1091 regmap_update_bits(priv->regm
1092 MT6357_AUD
1093 MT6357_AUD
1094 /* Enable HS driver bias circ
1095 regmap_update_bits(priv->regm
1096 MT6357_AUD
1097 MT6357_AUD
1098 /* Enable HS driver core circ
1099 regmap_update_bits(priv->regm
1100 MT6357_AUD
1101 MT6357_AUD
1102 /* Set HS gain to normal gain
1103 hs_volume_ramp(priv, DL_GAIN_
1104 break;
1105 case SND_SOC_DAPM_PRE_PMD:
1106 /* decrease HS gain to minimu
1107 hs_volume_ramp(priv, gain, D
1108 /* Disable HS driver core cir
1109 regmap_update_bits(priv->regm
1110 MT6357_AUD
1111 MT6357_AUD
1112 /* Disable HS driver bias cir
1113 regmap_update_bits(priv->regm
1114 MT6357_AUD
1115 MT6357_AUD
1116 /* Clear HS STB enhance circu
1117 regmap_update_bits(priv->regm
1118 MT6357_AUD
1119 MT6357_AUD
1120 /* Save the gain value into t
1121 regmap_update_bits(priv->regm
1122 MT6357_AUD
1123 break;
1124 default:
1125 break;
1126 }
1127
1128 return 0;
1129 }
1130
1131 static int hp_main_mux_event(struct snd_soc_d
1132 struct snd_kcont
1133 int event)
1134 {
1135 struct snd_soc_component *cmpnt = snd
1136 struct mt6357_priv *priv = snd_soc_co
1137 int lgain, rgain;
1138
1139 /* Get current gain value */
1140 regmap_read(priv->regmap, MT6357_ZCD_
1141 rgain = (lgain & MT6357_AUD_HPR_GAIN_
1142 lgain = lgain & MT6357_AUD_HPL_GAIN_M
1143 switch (event) {
1144 case SND_SOC_DAPM_POST_PMU:
1145 priv->hp_channel_number++;
1146 if (priv->hp_channel_number >
1147 break;
1148 /* Set -40dB before enable HS
1149 regmap_update_bits(priv->regm
1150 MT6357_AUD
1151 MT6357_AUD
1152 MT6357_DL_
1153 /* Set HPP/N STB enhance circ
1154 regmap_update_bits(priv->regm
1155 MT6357_HPR
1156 MT6357_HPL
1157 MT6357_HPR
1158 MT6357_HPL
1159 /* Enable HP aux output stage
1160 regmap_update_bits(priv->regm
1161 MT6357_HPR
1162 MT6357_HPL
1163 MT6357_HPR
1164 MT6357_HPL
1165 /* Enable HP aux feedback loo
1166 regmap_update_bits(priv->regm
1167 MT6357_HPR
1168 MT6357_HPL
1169 MT6357_HPR
1170 MT6357_HPL
1171 /* Enable HP aux CMFB loop */
1172 regmap_update_bits(priv->regm
1173 MT6357_HP_
1174 MT6357_HPL
1175 MT6357_HPR
1176 MT6357_HP_
1177 MT6357_HPL
1178 MT6357_HPR
1179 /* Enable HP driver bias circ
1180 regmap_update_bits(priv->regm
1181 MT6357_AUD
1182 MT6357_AUD
1183 MT6357_AUD
1184 MT6357_AUD
1185 /* Enable HP driver core circ
1186 regmap_update_bits(priv->regm
1187 MT6357_AUD
1188 MT6357_AUD
1189 MT6357_AUD
1190 MT6357_AUD
1191 /* Short HP main output to HP
1192 regmap_update_bits(priv->regm
1193 MT6357_HPR
1194 MT6357_HPL
1195 MT6357_HPR
1196 MT6357_HPL
1197 /* Enable HP main CMFB loop *
1198 regmap_update_bits(priv->regm
1199 MT6357_HPR
1200 MT6357_HPR
1201 /* Disable HP aux CMFB loop *
1202 regmap_update_bits(priv->regm
1203 MT6357_HPR
1204 MT6357_HPL
1205 MT6357_HPR
1206 MT6357_HPL
1207 /* Enable HP main output stag
1208 regmap_update_bits(priv->regm
1209 MT6357_HPR
1210 MT6357_HPL
1211 MT6357_HPR
1212 MT6357_HPL
1213 /* Enable HPR/L main output s
1214 hp_main_output_ramp(priv, tru
1215 usleep_range(1000, 1200);
1216 /* Reduce HP aux feedback loo
1217 hp_aux_feedback_loop_gain_ram
1218 /* Disable HP aux feedback lo
1219 regmap_update_bits(priv->regm
1220 MT6357_HPR
1221 MT6357_HPL
1222 MT6357_HPR
1223 MT6357_HPL
1224 /* apply volume setting */
1225 hp_volume_ramp(priv, DL_GAIN_
1226 DL_GAIN_N_40DB
1227 /* Disable HP aux output stag
1228 regmap_update_bits(priv->regm
1229 MT6357_HPR
1230 MT6357_HPL
1231 MT6357_HPR
1232 MT6357_HPL
1233 /* Unshort HP main output to
1234 regmap_update_bits(priv->regm
1235 MT6357_HPR
1236 MT6357_HPL
1237 MT6357_HPR
1238 MT6357_HPL
1239 usleep_range(100, 120);
1240 break;
1241 case SND_SOC_DAPM_PRE_PMD:
1242 priv->hp_channel_number--;
1243 if (priv->hp_channel_number >
1244 break;
1245 /* Short HP main output to HP
1246 regmap_update_bits(priv->regm
1247 MT6357_HPR
1248 MT6357_HPL
1249 MT6357_HPR
1250 MT6357_HPL
1251 /* Enable HP aux output stage
1252 regmap_update_bits(priv->regm
1253 MT6357_HPR
1254 MT6357_HPL
1255 MT6357_HPR
1256 MT6357_HPL
1257 /* decrease HPL/R gain to nor
1258 hp_volume_ramp(priv, lgain, D
1259 rgain, DL_GAIN
1260 /* Enable HP aux feedback loo
1261 regmap_update_bits(priv->regm
1262 MT6357_HPR
1263 MT6357_HPL
1264 MT6357_HPR
1265 MT6357_HPL
1266 /* Reduce HP aux feedback loo
1267 hp_aux_feedback_loop_gain_ram
1268 /* decrease HPR/L main output
1269 hp_main_output_ramp(priv, fal
1270 /* Disable HP main output sta
1271 regmap_update_bits(priv->regm
1272 MT6357_HPR
1273 MT6357_HPL
1274 MT6357_HPR
1275 MT6357_HPL
1276 /* Enable HP aux CMFB loop */
1277 regmap_update_bits(priv->regm
1278 MT6357_HP_
1279 MT6357_HPL
1280 MT6357_HPR
1281 MT6357_HP_
1282 MT6357_HPL
1283 MT6357_HPR
1284 /* Disable HP main CMFB loop
1285 regmap_update_bits(priv->regm
1286 MT6357_HPR
1287 MT6357_HPR
1288 /* Unshort HP main output to
1289 regmap_update_bits(priv->regm
1290 MT6357_HPR
1291 MT6357_HPL
1292 MT6357_HPR
1293 MT6357_HPL
1294 /* Disable HP driver core cir
1295 regmap_update_bits(priv->regm
1296 MT6357_AUD
1297 MT6357_AUD
1298 MT6357_AUD
1299 MT6357_AUD
1300 /* Disable HP driver bias cir
1301 regmap_update_bits(priv->regm
1302 MT6357_AUD
1303 MT6357_AUD
1304 MT6357_AUD
1305 MT6357_AUD
1306 /* Disable HP aux CMFB loop,
1307 * Enable HP main CMFB for HP
1308 */
1309 regmap_update_bits(priv->regm
1310 MT6357_HPR
1311 MT6357_HPR
1312 MT6357_HPL
1313 MT6357_HPR
1314 MT6357_HPR
1315 MT6357_HPL
1316 /* Disable HP aux feedback lo
1317 regmap_update_bits(priv->regm
1318 MT6357_HPR
1319 MT6357_HPL
1320 MT6357_HPR
1321 MT6357_HPL
1322 /* Disable HP aux output stag
1323 regmap_update_bits(priv->regm
1324 MT6357_HPR
1325 MT6357_HPL
1326 MT6357_HPR
1327 MT6357_HPL
1328 /* Save the gain value into t
1329 regmap_update_bits(priv->regm
1330 MT6357_AUD
1331 MT6357_AUD
1332 lgain << M
1333 rgain << M
1334 break;
1335 default:
1336 break;
1337 }
1338
1339 return 0;
1340 }
1341
1342 static int right_dac_event(struct snd_soc_dap
1343 struct snd_kcontro
1344 int event)
1345 {
1346 struct snd_soc_component *cmpnt = snd
1347 struct mt6357_priv *priv = snd_soc_co
1348
1349 switch (event) {
1350 case SND_SOC_DAPM_PRE_PMU:
1351 /* Enable Audio DAC and contr
1352 regmap_update_bits(priv->regm
1353 MT6357_AUD
1354 MT6357_AUD
1355 MT6357_AUD
1356 MT6357_AUD
1357 break;
1358 case SND_SOC_DAPM_POST_PMU:
1359 /* disable Pull-down HPL/R to
1360 if (priv->pull_down_needed)
1361 hp_pull_down(priv, fa
1362 break;
1363 case SND_SOC_DAPM_PRE_PMD:
1364 /* Pull-down HPL/R to AVSS28_
1365 if (priv->pull_down_needed)
1366 hp_pull_down(priv, tr
1367 /* Disable Audio DAC and cont
1368 regmap_update_bits(priv->regm
1369 MT6357_AUD
1370 MT6357_AUD
1371 MT6357_AUD
1372 MT6357_AUD
1373 break;
1374 default:
1375 break;
1376 }
1377
1378 return 0;
1379 }
1380
1381 static int left_dac_event(struct snd_soc_dapm
1382 struct snd_kcontrol
1383 int event)
1384 {
1385 struct snd_soc_component *cmpnt = snd
1386 struct mt6357_priv *priv = snd_soc_co
1387
1388 switch (event) {
1389 case SND_SOC_DAPM_PRE_PMU:
1390 /* Enable Audio DAC and contr
1391 regmap_update_bits(priv->regm
1392 MT6357_AUD
1393 MT6357_AUD
1394 MT6357_AUD
1395 MT6357_AUD
1396 break;
1397 case SND_SOC_DAPM_POST_PMU:
1398 /* disable Pull-down HPL/R to
1399 if (priv->pull_down_needed)
1400 hp_pull_down(priv, fa
1401 break;
1402 case SND_SOC_DAPM_PRE_PMD:
1403 /* Pull-down HPL/R to AVSS28_
1404 if (priv->pull_down_needed)
1405 hp_pull_down(priv, tr
1406 /* Disable Audio DAC and cont
1407 regmap_update_bits(priv->regm
1408 MT6357_AUD
1409 MT6357_AUD
1410 MT6357_AUD
1411 MT6357_AUD
1412 break;
1413 default:
1414 break;
1415 }
1416
1417 return 0;
1418 }
1419
1420 /* Supply widgets subsequence */
1421 enum {
1422 /* common */
1423 SUPPLY_SEQ_CLK_BUF,
1424 SUPPLY_SEQ_AUD_GLB,
1425 SUPPLY_SEQ_CLKSQ,
1426 SUPPLY_SEQ_VOW_AUD_LPW,
1427 SUPPLY_SEQ_AUD_VOW,
1428 SUPPLY_SEQ_VOW_CLK,
1429 SUPPLY_SEQ_VOW_LDO,
1430 SUPPLY_SEQ_TOP_CK,
1431 SUPPLY_SEQ_TOP_CK_LAST,
1432 SUPPLY_SEQ_AUD_TOP,
1433 SUPPLY_SEQ_AUD_TOP_LAST,
1434 SUPPLY_SEQ_AFE,
1435 /* capture */
1436 SUPPLY_SEQ_ADC_SUPPLY,
1437 };
1438
1439 /* DAPM Widgets */
1440 static const struct snd_soc_dapm_widget mt635
1441 /* Analog Clocks */
1442 SND_SOC_DAPM_SUPPLY_S("CLK_BUF", SUPP
1443 MT6357_DCXO_CW1
1444 MT6357_XO_AUDIO
1445 SND_SOC_DAPM_SUPPLY_S("AUDGLB", SUPPL
1446 MT6357_AUDDEC_A
1447 MT6357_AUDGLB_P
1448 SND_SOC_DAPM_SUPPLY_S("CLKSQ Audio",
1449 MT6357_AUDENC_A
1450 MT6357_CLKSQ_EN
1451 SND_SOC_DAPM_SUPPLY_S("AUDNCP_CK", SU
1452 MT6357_AUD_TOP_
1453 MT6357_AUDNCP_C
1454 SND_SOC_DAPM_SUPPLY_S("ZCD13M_CK", SU
1455 MT6357_AUD_TOP_
1456 MT6357_ZCD13M_C
1457 SND_SOC_DAPM_SUPPLY_S("AUD_CK", SUPPL
1458 MT6357_AUD_TOP_
1459 MT6357_AUD_CK_P
1460 mt_delay_250_ev
1461 SND_SOC_DAPM_PO
1462 SND_SOC_DAPM_SUPPLY_S("AUDIF_CK", SUP
1463 MT6357_AUD_TOP_
1464 MT6357_AUDIF_CK
1465
1466 /* Digital Clocks */
1467 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_AFE_
1468 MT6357_AUDIO_TO
1469 MT6357_PDN_AFE_
1470 mt_delay_250_ev
1471 SND_SOC_DAPM_PO
1472 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_DAC_
1473 MT6357_AUDIO_TO
1474 MT6357_PDN_DAC_
1475 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADC_
1476 MT6357_AUDIO_TO
1477 MT6357_PDN_ADC_
1478 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_I2S_
1479 MT6357_AUDIO_TO
1480 MT6357_PDN_I2S_
1481 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PWR_
1482 MT6357_AUDIO_TO
1483 MT6357_PWR_CLK_
1484 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_
1485 MT6357_AUDIO_TO
1486 MT6357_PDN_AFE_
1487 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_
1488 MT6357_AUDIO_TO
1489 MT6357_PDN_RESE
1490 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_LPBK
1491 MT6357_AUDIO_TO
1492 MT6357_PDN_LPBK
1493
1494 /* General */
1495 SND_SOC_DAPM_SUPPLY_S("AFE_ON", SUPPL
1496 MT6357_AFE_UL_D
1497 MT6357_AFE_ON_S
1498
1499 /* Uplinks */
1500 SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "MT6
1501 SND_SOC_NOPM,
1502 mt_aif_out_eve
1503 SND_SOC_DAPM_P
1504 SND_SOC_DAPM_SUPPLY_S("ADC Supply", S
1505 SND_SOC_NOPM, 0
1506 mt_adc_supply_e
1507 SND_SOC_DAPM_PR
1508 SND_SOC_DAPM_ADC_E("ADC", NULL, SND_S
1509 SND_SOC_DAPM_PRE_P
1510 SND_SOC_DAPM_MUX_E("PGA L Mux", SND_S
1511 &pga_left_mux_cont
1512 mt_pga_left_event,
1513 SND_SOC_DAPM_POST_
1514 SND_SOC_DAPM_MUX_E("PGA R Mux", SND_S
1515 &pga_right_mux_con
1516 mt_pga_right_event
1517 SND_SOC_DAPM_POST_
1518 SND_SOC_DAPM_PGA("PGA L", SND_SOC_NOP
1519 SND_SOC_DAPM_PGA("PGA R", SND_SOC_NOP
1520 SND_SOC_DAPM_MUX_E("Mic Type Mux", SN
1521 &mic_type_mux_cont
1522 mt_mic_type_event,
1523 SND_SOC_DAPM_PRE_P
1524 SND_SOC_DAPM_SUPPLY("MICBIAS0", MT635
1525 MT6357_AUD_MICBIA
1526 SND_SOC_DAPM_SUPPLY("MICBIAS1", MT635
1527 MT6357_AUD_MICBIA
1528
1529 /* UL inputs */
1530 SND_SOC_DAPM_INPUT("AIN0"),
1531 SND_SOC_DAPM_INPUT("AIN1"),
1532 SND_SOC_DAPM_INPUT("AIN2"),
1533 SND_SOC_DAPM_INPUT("LPBK"),
1534 SND_SOC_DAPM_INPUT("SGEN UL"),
1535
1536 /* Downlinks */
1537 SND_SOC_DAPM_AIF_IN_E("AIF_RX", "MT63
1538 SND_SOC_NOPM, 0
1539 mt_audio_in_eve
1540 SND_SOC_DAPM_PR
1541 SND_SOC_DAPM_INPUT("SGEN DL"),
1542 SND_SOC_DAPM_MUX("DAC Mux", SND_SOC_N
1543
1544 SND_SOC_DAPM_DAC_E("DACR", NULL, SND_
1545 SND_SOC_DAPM_PRE_P
1546 SND_SOC_DAPM_DAC_E("DACL", NULL, SND_
1547 SND_SOC_DAPM_PRE_P
1548
1549 SND_SOC_DAPM_SUPPLY("DL Digital Suppl
1550 SND_SOC_DAPM_SUPPLY("DL Analog Supply
1551 SND_SOC_DAPM_SUPPLY("DL SRC", MT6357_
1552 MT6357_DL_2_SRC_O
1553
1554 SND_SOC_DAPM_MUX_E("Line Out Source",
1555 lo_mux_event,
1556 SND_SOC_DAPM_POST_
1557
1558 SND_SOC_DAPM_MUX_E("Handset Source",
1559 hs_mux_event,
1560 SND_SOC_DAPM_POST_
1561
1562 SND_SOC_DAPM_MUX_E("Headphone Right S
1563 hp_main_mux_event,
1564 SND_SOC_DAPM_POST_
1565
1566 SND_SOC_DAPM_MUX_E("Headphone Left So
1567 hp_main_mux_event,
1568 SND_SOC_DAPM_POST_
1569 /* DL outputs */
1570 SND_SOC_DAPM_OUTPUT("Headphones"),
1571 SND_SOC_DAPM_OUTPUT("Hansdet"),
1572 SND_SOC_DAPM_OUTPUT("Line out"),
1573
1574 /* Sine generator */
1575 SND_SOC_DAPM_SUPPLY("SGEN UL Enable",
1576 MT6357_AFE_TOP_CO
1577 SND_SOC_DAPM_SUPPLY("SGEN Enable",
1578 MT6357_AFE_SGEN_C
1579 MT6357_SGEN_DAC_E
1580 SND_SOC_DAPM_PRE_
1581 SND_SOC_DAPM_SUPPLY("SGEN MUTE",
1582 MT6357_AFE_SGEN_C
1583 MT6357_SGEN_MUTE_
1584 };
1585
1586 static const struct snd_soc_dapm_route mt6357
1587 /* Capture */
1588 {"AIF1TX", NULL, "Mic Type Mux"},
1589 {"AIF1TX", NULL, "CLK_BUF"},
1590 {"AIF1TX", NULL, "AUDGLB"},
1591 {"AIF1TX", NULL, "CLKSQ Audio"},
1592 {"AIF1TX", NULL, "AUD_CK"},
1593 {"AIF1TX", NULL, "AUDIF_CK"},
1594
1595 {"AIF1TX", NULL, "AUDIO_TOP_AFE_CTL"}
1596 {"AIF1TX", NULL, "AUDIO_TOP_ADC_CTL"}
1597 {"AIF1TX", NULL, "AUDIO_TOP_PWR_CLK"}
1598 {"AIF1TX", NULL, "AUDIO_TOP_PDN_RESER
1599 {"AIF1TX", NULL, "AUDIO_TOP_I2S_DL"},
1600 {"AIF1TX", NULL, "AFE_ON"},
1601
1602 {"Mic Type Mux", "ACC", "ADC"},
1603 {"Mic Type Mux", "DCC", "ADC"},
1604 {"Mic Type Mux", "DCC_ECM_DIFF", "ADC
1605 {"Mic Type Mux", "DCC_ECM_SINGLE", "A
1606 {"Mic Type Mux", "DMIC", "AIN0"},
1607 {"Mic Type Mux", "DMIC", "AIN2"},
1608 {"Mic Type Mux", "Loopback", "LPBK"},
1609 {"Mic Type Mux", "Sine Generator", "S
1610
1611 {"SGEN UL", NULL, "AUDIO_TOP_PDN_AFE_
1612 {"SGEN UL", NULL, "SGEN UL Enable"},
1613 {"SGEN UL", NULL, "SGEN MUTE"},
1614 {"SGEN UL", NULL, "SGEN Enable"},
1615
1616 {"ADC", NULL, "PGA L Mux"},
1617 {"ADC", NULL, "PGA R Mux"},
1618 {"ADC", NULL, "ADC Supply"},
1619
1620 {"PGA L Mux", "AIN0", "AIN0"},
1621 {"PGA L Mux", "AIN1", "AIN1"},
1622 {"PGA L Mux", "AIN2", "AIN2"},
1623
1624 {"PGA R Mux", "AIN0", "AIN0"},
1625 {"PGA R Mux", "AIN1", "AIN1"},
1626 {"PGA R Mux", "AIN2", "AIN2"},
1627
1628 {"AIN0", NULL, "MICBIAS0"},
1629 {"AIN1", NULL, "MICBIAS1"},
1630 {"AIN2", NULL, "MICBIAS0"},
1631 {"LPBK", NULL, "AUDIO_TOP_LPBK"},
1632
1633 /* Playback */
1634 {"DAC Mux", "Normal Path", "AIF_RX"},
1635 {"DAC Mux", "Sine Generator", "SGEN D
1636
1637 {"AIF_RX", NULL, "DL SRC"},
1638
1639 {"SGEN DL", NULL, "DL SRC"},
1640 {"SGEN DL", NULL, "SGEN MUTE"},
1641 {"SGEN DL", NULL, "SGEN Enable"},
1642 {"SGEN DL", NULL, "DL Digital Supply"
1643 {"SGEN DL", NULL, "AUDIO_TOP_PDN_AFE_
1644
1645 {"DACL", NULL, "DAC Mux"},
1646 {"DACR", NULL, "DAC Mux"},
1647
1648 {"DL Analog Supply", NULL, "CLK_BUF"}
1649 {"DL Analog Supply", NULL, "AUDGLB"},
1650 {"DL Analog Supply", NULL, "CLKSQ Aud
1651 {"DL Analog Supply", NULL, "AUDNCP_CK
1652 {"DL Analog Supply", NULL, "ZCD13M_CK
1653 {"DL Analog Supply", NULL, "AUD_CK"},
1654 {"DL Analog Supply", NULL, "AUDIF_CK"
1655
1656 {"DL Digital Supply", NULL, "AUDIO_TO
1657 {"DL Digital Supply", NULL, "AUDIO_TO
1658 {"DL Digital Supply", NULL, "AUDIO_TO
1659 {"DL Digital Supply", NULL, "AFE_ON"}
1660
1661 {"DACR", NULL, "DL Digital Supply"},
1662 {"DACR", NULL, "DL Analog Supply"},
1663 {"DACL", NULL, "DL Digital Supply"},
1664 {"DACL", NULL, "DL Analog Supply"},
1665
1666 {"Line Out Source", "DACR", "DACR"},
1667 {"Line Out Source", "Playback", "DACL
1668 {"Line Out Source", "Test mode", "DAC
1669
1670 {"Handset Source", "DACR", "DACR"},
1671 {"Handset Source", "Playback", "DACL"
1672 {"Handset Source", "Test mode", "DACL
1673
1674 {"Headphone Right Source", "DAC", "DA
1675 {"Headphone Right Source", "Line Out"
1676 {"Headphone Right Source", "Handset",
1677
1678 {"Headphone Left Source", "DAC", "DAC
1679 {"Headphone Left Source", "Line Out",
1680 {"Headphone Left Source", "Handset",
1681
1682 {"Line out", NULL, "Line Out Source"}
1683 {"Hansdet", NULL, "Handset Source"},
1684
1685 {"Headphones", NULL, "Headphone Right
1686 {"Headphones", NULL, "Headphone Left
1687 };
1688
1689 static struct snd_soc_dai_driver mtk_6357_dai
1690 {
1691 .name = "mt6357-snd-codec-aif
1692 .playback = {
1693 .stream_name = "MT635
1694 .channels_min = 1,
1695 .channels_max = 2,
1696 .rates = SNDRV_PCM_RA
1697 .formats = MT6357_SND
1698 },
1699 .capture = {
1700 .stream_name = "MT635
1701 .channels_min = 1,
1702 .channels_max = 2,
1703 .rates = MT6357_SOC_H
1704 .formats = MT6357_SND
1705 },
1706 },
1707 };
1708
1709 static int mt6357_codec_probe(struct snd_soc_
1710 {
1711 struct mt6357_priv *priv = snd_soc_co
1712
1713 snd_soc_component_init_regmap(codec,
1714
1715 /* Enable audio part */
1716 regmap_update_bits(priv->regmap, MT63
1717 MT6357_XO_AUDIO_EN
1718 /* Disable HeadphoneL/HeadphoneR shor
1719 regmap_update_bits(priv->regmap, MT63
1720 MT6357_AUD_HPR_SC_
1721 MT6357_AUD_HPL_SC_
1722 MT6357_AUD_HPR_SC_
1723 MT6357_AUD_HPL_SC_
1724 /* Disable voice short circuit protec
1725 regmap_update_bits(priv->regmap, MT63
1726 MT6357_AUD_HS_SC_V
1727 MT6357_AUD_HS_SC_V
1728 /* disable LO buffer left short circu
1729 regmap_update_bits(priv->regmap, MT63
1730 MT6357_AUD_LOL_SC_
1731 MT6357_AUD_LOL_SC_
1732 /* set gpio */
1733 set_playback_gpio(priv, false);
1734 set_capture_gpio(priv, false);
1735 /* Disable audio part */
1736 regmap_update_bits(priv->regmap, MT63
1737 MT6357_XO_AUDIO_EN
1738 MT6357_XO_AUDIO_EN
1739
1740 return 0;
1741 }
1742
1743 static const struct snd_soc_component_driver
1744 .probe = mt6357_codec_probe,
1745 .read = snd_soc_component_read,
1746 .write = snd_soc_component_write,
1747 .controls = mt6357_controls,
1748 .num_controls = ARRAY_SIZE(mt6357_con
1749 .dapm_widgets = mt6357_dapm_widgets,
1750 .num_dapm_widgets = ARRAY_SIZE(mt6357
1751 .dapm_routes = mt6357_dapm_routes,
1752 .num_dapm_routes = ARRAY_SIZE(mt6357_
1753 };
1754
1755 static const u32 micbias_values[] = {
1756 1700000, 1800000, 1900000, 2000000,
1757 2100000, 2500000, 2600000, 2700000
1758 };
1759
1760 static u32 mt6357_get_micbias_idx(struct devi
1761 {
1762 int err;
1763 u32 idx, val;
1764
1765 err = of_property_read_u32(np, micbia
1766 if (err)
1767 return 0;
1768
1769 for (idx = 0; idx < ARRAY_SIZE(micbia
1770 if (val == micbias_values[idx
1771 return idx;
1772 }
1773 return 0;
1774 }
1775
1776 static int mt6357_parse_dt(struct mt6357_priv
1777 {
1778 u32 micbias_voltage_index = 0;
1779 struct device_node *np = priv->dev->p
1780
1781 if (!np)
1782 return -EINVAL;
1783
1784 priv->pull_down_needed = false;
1785 if (of_property_read_bool(np, "mediat
1786 priv->pull_down_needed = true
1787
1788 micbias_voltage_index = mt6357_get_mi
1789 regmap_update_bits(priv->regmap, MT63
1790 MT6357_AUD_MICBIAS
1791 micbias_voltage_in
1792
1793 micbias_voltage_index = mt6357_get_mi
1794 regmap_update_bits(priv->regmap, MT63
1795 MT6357_AUD_MICBIAS
1796 micbias_voltage_in
1797
1798 return 0;
1799 }
1800
1801 static int mt6357_platform_driver_probe(struc
1802 {
1803 struct mt6397_chip *mt6397 = dev_get_
1804 struct mt6357_priv *priv;
1805 int ret;
1806
1807 ret = devm_regulator_get_enable(&pdev
1808 if (ret)
1809 return dev_err_probe(&pdev->d
1810
1811 priv = devm_kzalloc(&pdev->dev, sizeo
1812 if (!priv)
1813 return -ENOMEM;
1814
1815 dev_set_drvdata(&pdev->dev, priv);
1816 priv->dev = &pdev->dev;
1817
1818 priv->regmap = mt6397->regmap;
1819 if (IS_ERR(priv->regmap))
1820 return PTR_ERR(priv->regmap);
1821
1822 ret = mt6357_parse_dt(priv);
1823 if (ret)
1824 return dev_err_probe(&pdev->d
1825
1826 pdev->dev.coherent_dma_mask = DMA_BIT
1827 if (!pdev->dev.dma_mask)
1828 pdev->dev.dma_mask = &pdev->d
1829
1830 return devm_snd_soc_register_componen
1831
1832
1833
1834 }
1835
1836 static const struct platform_device_id mt6357
1837 {"mt6357-sound", 0},
1838 { /* sentinel */ },
1839 };
1840 MODULE_DEVICE_TABLE(platform, mt6357_platform
1841
1842 static struct platform_driver mt6357_platform
1843 .driver = {
1844 .name = "mt6357-sound",
1845 .probe_type = PROBE_PREFER_AS
1846 },
1847 .probe = mt6357_platform_driver_probe
1848 .id_table = mt6357_platform_ids,
1849 };
1850
1851 module_platform_driver(mt6357_platform_driver
1852
1853 MODULE_DESCRIPTION("MT6357 ALSA SoC codec dri
1854 MODULE_AUTHOR("Nicolas Belin <nbelin@baylibre
1855 MODULE_LICENSE("GPL");
1856
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