1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 // 2 //
3 // mt6359-accdet.c -- ALSA SoC mt6359 accdet 3 // mt6359-accdet.c -- ALSA SoC mt6359 accdet driver
4 // 4 //
5 // Copyright (C) 2021 MediaTek Inc. 5 // Copyright (C) 2021 MediaTek Inc.
6 // Author: Argus Lin <argus.lin@mediatek.com> 6 // Author: Argus Lin <argus.lin@mediatek.com>
7 // 7 //
8 8
>> 9 #include <linux/of_gpio.h>
9 #include <linux/of.h> 10 #include <linux/of.h>
>> 11 #include <linux/of_irq.h>
>> 12 #include <linux/of_device.h>
>> 13 #include <linux/of_address.h>
10 #include <linux/input.h> 14 #include <linux/input.h>
11 #include <linux/kthread.h> 15 #include <linux/kthread.h>
12 #include <linux/io.h> 16 #include <linux/io.h>
13 #include <linux/sched/clock.h> 17 #include <linux/sched/clock.h>
14 #include <linux/workqueue.h> 18 #include <linux/workqueue.h>
15 #include <linux/timer.h> 19 #include <linux/timer.h>
16 #include <linux/delay.h> 20 #include <linux/delay.h>
17 #include <linux/module.h> 21 #include <linux/module.h>
18 #include <linux/platform_device.h> 22 #include <linux/platform_device.h>
19 #include <linux/init.h> 23 #include <linux/init.h>
20 #include <linux/irqdomain.h> 24 #include <linux/irqdomain.h>
21 #include <linux/irq.h> 25 #include <linux/irq.h>
22 #include <linux/regmap.h> 26 #include <linux/regmap.h>
23 #include <sound/soc.h> 27 #include <sound/soc.h>
24 #include <sound/jack.h> 28 #include <sound/jack.h>
25 #include <linux/mfd/mt6397/core.h> 29 #include <linux/mfd/mt6397/core.h>
26 30
27 #include "mt6359-accdet.h" 31 #include "mt6359-accdet.h"
28 #include "mt6359.h" 32 #include "mt6359.h"
29 33
30 /* global variable definitions */ 34 /* global variable definitions */
31 #define REGISTER_VAL(x) ((x) - 1) 35 #define REGISTER_VAL(x) ((x) - 1)
32 36
33 /* mt6359 accdet capability */ 37 /* mt6359 accdet capability */
34 #define ACCDET_PMIC_EINT_IRQ BIT(0) 38 #define ACCDET_PMIC_EINT_IRQ BIT(0)
35 #define ACCDET_AP_GPIO_EINT BIT(1) 39 #define ACCDET_AP_GPIO_EINT BIT(1)
36 40
37 #define ACCDET_PMIC_EINT0 BIT(2) 41 #define ACCDET_PMIC_EINT0 BIT(2)
38 #define ACCDET_PMIC_EINT1 BIT(3) 42 #define ACCDET_PMIC_EINT1 BIT(3)
39 #define ACCDET_PMIC_BI_EINT BIT(4) 43 #define ACCDET_PMIC_BI_EINT BIT(4)
40 44
41 #define ACCDET_PMIC_GPIO_TRIG_EINT BIT(5) 45 #define ACCDET_PMIC_GPIO_TRIG_EINT BIT(5)
42 #define ACCDET_PMIC_INVERTER_TRIG_EINT BIT(6) 46 #define ACCDET_PMIC_INVERTER_TRIG_EINT BIT(6)
43 #define ACCDET_PMIC_RSV_EINT BIT(7) 47 #define ACCDET_PMIC_RSV_EINT BIT(7)
44 48
45 #define ACCDET_THREE_KEY BIT(8) 49 #define ACCDET_THREE_KEY BIT(8)
46 #define ACCDET_FOUR_KEY BIT(9) 50 #define ACCDET_FOUR_KEY BIT(9)
47 #define ACCDET_TRI_KEY_CDD BIT(10 51 #define ACCDET_TRI_KEY_CDD BIT(10)
48 #define ACCDET_RSV_KEY BIT(11 52 #define ACCDET_RSV_KEY BIT(11)
49 53
50 #define ACCDET_ANALOG_FASTDISCHARGE BIT(12 54 #define ACCDET_ANALOG_FASTDISCHARGE BIT(12)
51 #define ACCDET_DIGITAL_FASTDISCHARGE BIT(13 55 #define ACCDET_DIGITAL_FASTDISCHARGE BIT(13)
52 #define ACCDET_AD_FASTDISCHRAGE BIT(14 56 #define ACCDET_AD_FASTDISCHRAGE BIT(14)
53 57
54 static struct platform_driver mt6359_accdet_dr 58 static struct platform_driver mt6359_accdet_driver;
55 static const struct snd_soc_component_driver m 59 static const struct snd_soc_component_driver mt6359_accdet_soc_driver;
56 60
57 /* local function declaration */ 61 /* local function declaration */
58 static void accdet_set_debounce(struct mt6359_ 62 static void accdet_set_debounce(struct mt6359_accdet *priv, int state,
59 unsigned int d 63 unsigned int debounce);
60 static unsigned int adjust_eint_analog_setting 64 static unsigned int adjust_eint_analog_setting(struct mt6359_accdet *priv);
61 static void config_digital_init_by_mode(struct 65 static void config_digital_init_by_mode(struct mt6359_accdet *priv);
62 static void config_eint_init_by_mode(struct mt 66 static void config_eint_init_by_mode(struct mt6359_accdet *priv);
63 static inline void mt6359_accdet_init(struct m 67 static inline void mt6359_accdet_init(struct mt6359_accdet *priv);
64 static unsigned int mt6359_accdet_jd_setting(s 68 static unsigned int mt6359_accdet_jd_setting(struct mt6359_accdet *priv);
65 static void mt6359_accdet_recover_jd_setting(s 69 static void mt6359_accdet_recover_jd_setting(struct mt6359_accdet *priv);
66 static void mt6359_accdet_jack_report(struct m 70 static void mt6359_accdet_jack_report(struct mt6359_accdet *priv);
67 static void recover_eint_analog_setting(struct 71 static void recover_eint_analog_setting(struct mt6359_accdet *priv);
68 static void recover_eint_digital_setting(struc 72 static void recover_eint_digital_setting(struct mt6359_accdet *priv);
69 static void recover_eint_setting(struct mt6359 73 static void recover_eint_setting(struct mt6359_accdet *priv);
70 74
71 static unsigned int adjust_eint_analog_setting 75 static unsigned int adjust_eint_analog_setting(struct mt6359_accdet *priv)
72 { 76 {
73 if (priv->data->eint_detect_mode == 0x 77 if (priv->data->eint_detect_mode == 0x3 ||
74 priv->data->eint_detect_mode == 0x 78 priv->data->eint_detect_mode == 0x4) {
75 /* ESD switches off */ 79 /* ESD switches off */
76 regmap_update_bits(priv->regma 80 regmap_update_bits(priv->regmap,
77 RG_ACCDETSP 81 RG_ACCDETSPARE_ADDR, 1 << 8, 0);
78 } 82 }
79 if (priv->data->eint_detect_mode == 0x 83 if (priv->data->eint_detect_mode == 0x4) {
80 if (priv->caps & ACCDET_PMIC_E 84 if (priv->caps & ACCDET_PMIC_EINT0) {
81 /* enable RG_EINT0CONF 85 /* enable RG_EINT0CONFIGACCDET */
82 regmap_update_bits(pri 86 regmap_update_bits(priv->regmap,
83 RG_ 87 RG_EINT0CONFIGACCDET_ADDR,
84 RG_ 88 RG_EINT0CONFIGACCDET_MASK_SFT,
85 BIT 89 BIT(RG_EINT0CONFIGACCDET_SFT));
86 } else if (priv->caps & ACCDET 90 } else if (priv->caps & ACCDET_PMIC_EINT1) {
87 /* enable RG_EINT1CONF 91 /* enable RG_EINT1CONFIGACCDET */
88 regmap_update_bits(pri 92 regmap_update_bits(priv->regmap,
89 RG_ 93 RG_EINT1CONFIGACCDET_ADDR,
90 RG_ 94 RG_EINT1CONFIGACCDET_MASK_SFT,
91 BIT 95 BIT(RG_EINT1CONFIGACCDET_SFT));
92 } 96 }
93 if (priv->data->eint_use_ext_r 97 if (priv->data->eint_use_ext_res == 0x3 ||
94 priv->data->eint_use_ext_r 98 priv->data->eint_use_ext_res == 0x4) {
95 /*select 500k, use int 99 /*select 500k, use internal resistor */
96 regmap_update_bits(pri 100 regmap_update_bits(priv->regmap,
97 RG_ 101 RG_EINT0HIRENB_ADDR,
98 RG_ 102 RG_EINT0HIRENB_MASK_SFT,
99 BIT 103 BIT(RG_EINT0HIRENB_SFT));
100 } 104 }
101 } 105 }
102 return 0; 106 return 0;
103 } 107 }
104 108
105 static unsigned int adjust_eint_digital_settin 109 static unsigned int adjust_eint_digital_setting(struct mt6359_accdet *priv)
106 { 110 {
107 if (priv->caps & ACCDET_PMIC_EINT0) { 111 if (priv->caps & ACCDET_PMIC_EINT0) {
108 /* disable inverter */ 112 /* disable inverter */
109 regmap_update_bits(priv->regma 113 regmap_update_bits(priv->regmap,
110 ACCDET_EINT 114 ACCDET_EINT0_INVERTER_SW_EN_ADDR,
111 ACCDET_EINT 115 ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT, 0);
112 } else if (priv->caps & ACCDET_PMIC_EI 116 } else if (priv->caps & ACCDET_PMIC_EINT1) {
113 /* disable inverter */ 117 /* disable inverter */
114 regmap_update_bits(priv->regma 118 regmap_update_bits(priv->regmap,
115 ACCDET_EINT 119 ACCDET_EINT1_INVERTER_SW_EN_ADDR,
116 ACCDET_EINT 120 ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT, 0);
117 } 121 }
118 122
119 if (priv->data->eint_detect_mode == 0x 123 if (priv->data->eint_detect_mode == 0x4) {
120 if (priv->caps & ACCDET_PMIC_E 124 if (priv->caps & ACCDET_PMIC_EINT0) {
121 /* set DA stable signa 125 /* set DA stable signal */
122 regmap_update_bits(pri 126 regmap_update_bits(priv->regmap,
123 ACC 127 ACCDET_DA_STABLE_ADDR,
124 ACC 128 ACCDET_EINT0_CEN_STABLE_MASK_SFT, 0);
125 } else if (priv->caps & ACCDET 129 } else if (priv->caps & ACCDET_PMIC_EINT1) {
126 /* set DA stable signa 130 /* set DA stable signal */
127 regmap_update_bits(pri 131 regmap_update_bits(priv->regmap,
128 ACC 132 ACCDET_DA_STABLE_ADDR,
129 ACC 133 ACCDET_EINT1_CEN_STABLE_MASK_SFT, 0);
130 } 134 }
131 } 135 }
132 return 0; 136 return 0;
133 } 137 }
134 138
135 static unsigned int mt6359_accdet_jd_setting(s 139 static unsigned int mt6359_accdet_jd_setting(struct mt6359_accdet *priv)
136 { 140 {
137 if (priv->jd_sts == M_PLUG_IN) { 141 if (priv->jd_sts == M_PLUG_IN) {
138 /* adjust digital setting */ 142 /* adjust digital setting */
139 adjust_eint_digital_setting(pr 143 adjust_eint_digital_setting(priv);
140 /* adjust analog setting */ 144 /* adjust analog setting */
141 adjust_eint_analog_setting(pri 145 adjust_eint_analog_setting(priv);
142 } else if (priv->jd_sts == M_PLUG_OUT) 146 } else if (priv->jd_sts == M_PLUG_OUT) {
143 /* set debounce to 1ms */ 147 /* set debounce to 1ms */
144 accdet_set_debounce(priv, eint 148 accdet_set_debounce(priv, eint_state000,
145 priv->data 149 priv->data->pwm_deb->eint_debounce0);
146 } else { 150 } else {
147 dev_dbg(priv->dev, "should not 151 dev_dbg(priv->dev, "should not be here %s()\n", __func__);
148 } 152 }
149 153
150 return 0; 154 return 0;
151 } 155 }
152 156
153 static void recover_eint_analog_setting(struct 157 static void recover_eint_analog_setting(struct mt6359_accdet *priv)
154 { 158 {
155 if (priv->data->eint_detect_mode == 0x 159 if (priv->data->eint_detect_mode == 0x3 ||
156 priv->data->eint_detect_mode == 0x 160 priv->data->eint_detect_mode == 0x4) {
157 /* ESD switches on */ 161 /* ESD switches on */
158 regmap_update_bits(priv->regma 162 regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR,
159 1 << 8, 1 < 163 1 << 8, 1 << 8);
160 } 164 }
161 if (priv->data->eint_detect_mode == 0x 165 if (priv->data->eint_detect_mode == 0x4) {
162 if (priv->caps & ACCDET_PMIC_E 166 if (priv->caps & ACCDET_PMIC_EINT0) {
163 /* disable RG_EINT0CON 167 /* disable RG_EINT0CONFIGACCDET */
164 regmap_update_bits(pri 168 regmap_update_bits(priv->regmap,
165 RG_ 169 RG_EINT0CONFIGACCDET_ADDR,
166 RG_ 170 RG_EINT0CONFIGACCDET_MASK_SFT, 0);
167 } else if (priv->caps & ACCDET 171 } else if (priv->caps & ACCDET_PMIC_EINT1) {
168 /* disable RG_EINT1CON 172 /* disable RG_EINT1CONFIGACCDET */
169 regmap_update_bits(pri 173 regmap_update_bits(priv->regmap,
170 RG_ 174 RG_EINT1CONFIGACCDET_ADDR,
171 RG_ 175 RG_EINT1CONFIGACCDET_MASK_SFT, 0);
172 } 176 }
173 regmap_update_bits(priv->regma 177 regmap_update_bits(priv->regmap, RG_EINT0HIRENB_ADDR,
174 RG_EINT0HIR 178 RG_EINT0HIRENB_MASK_SFT, 0);
175 } 179 }
176 } 180 }
177 181
178 static void recover_eint_digital_setting(struc 182 static void recover_eint_digital_setting(struct mt6359_accdet *priv)
179 { 183 {
180 if (priv->caps & ACCDET_PMIC_EINT0) { 184 if (priv->caps & ACCDET_PMIC_EINT0) {
181 regmap_update_bits(priv->regma 185 regmap_update_bits(priv->regmap,
182 ACCDET_EINT 186 ACCDET_EINT0_M_SW_EN_ADDR,
183 ACCDET_EINT 187 ACCDET_EINT0_M_SW_EN_MASK_SFT, 0);
184 } else if (priv->caps & ACCDET_PMIC_EI 188 } else if (priv->caps & ACCDET_PMIC_EINT1) {
185 regmap_update_bits(priv->regma 189 regmap_update_bits(priv->regmap,
186 ACCDET_EINT 190 ACCDET_EINT1_M_SW_EN_ADDR,
187 ACCDET_EINT 191 ACCDET_EINT1_M_SW_EN_MASK_SFT, 0);
188 } 192 }
189 if (priv->data->eint_detect_mode == 0x 193 if (priv->data->eint_detect_mode == 0x4) {
190 /* enable eint0cen */ 194 /* enable eint0cen */
191 if (priv->caps & ACCDET_PMIC_E 195 if (priv->caps & ACCDET_PMIC_EINT0) {
192 /* enable eint0cen */ 196 /* enable eint0cen */
193 regmap_update_bits(pri 197 regmap_update_bits(priv->regmap,
194 ACC 198 ACCDET_DA_STABLE_ADDR,
195 ACC 199 ACCDET_EINT0_CEN_STABLE_MASK_SFT,
196 BIT 200 BIT(ACCDET_EINT0_CEN_STABLE_SFT));
197 } else if (priv->caps & ACCDET 201 } else if (priv->caps & ACCDET_PMIC_EINT1) {
198 /* enable eint1cen */ 202 /* enable eint1cen */
199 regmap_update_bits(pri 203 regmap_update_bits(priv->regmap,
200 ACC 204 ACCDET_DA_STABLE_ADDR,
201 ACC 205 ACCDET_EINT1_CEN_STABLE_MASK_SFT,
202 BIT 206 BIT(ACCDET_EINT1_CEN_STABLE_SFT));
203 } 207 }
204 } 208 }
205 209
206 if (priv->data->eint_detect_mode != 0x 210 if (priv->data->eint_detect_mode != 0x1) {
207 if (priv->caps & ACCDET_PMIC_E 211 if (priv->caps & ACCDET_PMIC_EINT0) {
208 /* enable inverter */ 212 /* enable inverter */
209 regmap_update_bits(pri 213 regmap_update_bits(priv->regmap,
210 ACC 214 ACCDET_EINT0_INVERTER_SW_EN_ADDR,
211 ACC 215 ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT,
212 BIT 216 BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT));
213 } else if (priv->caps & ACCDET 217 } else if (priv->caps & ACCDET_PMIC_EINT1) {
214 /* enable inverter */ 218 /* enable inverter */
215 regmap_update_bits(pri 219 regmap_update_bits(priv->regmap,
216 ACC 220 ACCDET_EINT1_INVERTER_SW_EN_ADDR,
217 ACC 221 ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT,
218 BIT 222 BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT));
219 } 223 }
220 } 224 }
221 } 225 }
222 226
223 static void recover_eint_setting(struct mt6359 227 static void recover_eint_setting(struct mt6359_accdet *priv)
224 { 228 {
225 if (priv->jd_sts == M_PLUG_OUT) { 229 if (priv->jd_sts == M_PLUG_OUT) {
226 recover_eint_analog_setting(pr 230 recover_eint_analog_setting(priv);
227 recover_eint_digital_setting(p 231 recover_eint_digital_setting(priv);
228 } 232 }
229 } 233 }
230 234
231 static void mt6359_accdet_recover_jd_setting(s 235 static void mt6359_accdet_recover_jd_setting(struct mt6359_accdet *priv)
232 { 236 {
233 int ret; 237 int ret;
234 unsigned int value = 0; 238 unsigned int value = 0;
235 239
236 regmap_update_bits(priv->regmap, ACCDE 240 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
237 ACCDET_IRQ_CLR_MASK 241 ACCDET_IRQ_CLR_MASK_SFT, BIT(ACCDET_IRQ_CLR_SFT));
238 usleep_range(200, 300); 242 usleep_range(200, 300);
239 ret = regmap_read_poll_timeout(priv->r 243 ret = regmap_read_poll_timeout(priv->regmap,
240 ACCDET_ 244 ACCDET_IRQ_ADDR,
241 value, 245 value,
242 (value 246 (value & ACCDET_IRQ_MASK_SFT) == 0,
243 0, 247 0,
244 1000); 248 1000);
245 if (ret) 249 if (ret)
246 dev_warn(priv->dev, "%s(), ret 250 dev_warn(priv->dev, "%s(), ret %d\n", __func__, ret);
247 /* clear accdet int, modify for fix i 251 /* clear accdet int, modify for fix interrupt trigger twice error */
248 regmap_update_bits(priv->regmap, ACCDE 252 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
249 ACCDET_IRQ_CLR_MASK 253 ACCDET_IRQ_CLR_MASK_SFT, 0);
250 regmap_update_bits(priv->regmap, RG_IN 254 regmap_update_bits(priv->regmap, RG_INT_STATUS_ACCDET_ADDR,
251 RG_INT_STATUS_ACCDE 255 RG_INT_STATUS_ACCDET_MASK_SFT,
252 BIT(RG_INT_STATUS_A 256 BIT(RG_INT_STATUS_ACCDET_SFT));
253 257
254 /* recover accdet debounce0,3 */ 258 /* recover accdet debounce0,3 */
255 accdet_set_debounce(priv, accdet_state 259 accdet_set_debounce(priv, accdet_state000,
256 priv->data->pwm_de 260 priv->data->pwm_deb->debounce0);
257 accdet_set_debounce(priv, accdet_state 261 accdet_set_debounce(priv, accdet_state001,
258 priv->data->pwm_de 262 priv->data->pwm_deb->debounce1);
259 accdet_set_debounce(priv, accdet_state 263 accdet_set_debounce(priv, accdet_state011,
260 priv->data->pwm_de 264 priv->data->pwm_deb->debounce3);
261 265
262 priv->jack_type = 0; 266 priv->jack_type = 0;
263 priv->btn_type = 0; 267 priv->btn_type = 0;
264 priv->accdet_status = 0x3; 268 priv->accdet_status = 0x3;
265 mt6359_accdet_jack_report(priv); 269 mt6359_accdet_jack_report(priv);
266 } 270 }
267 271
268 static void accdet_set_debounce(struct mt6359_ 272 static void accdet_set_debounce(struct mt6359_accdet *priv, int state,
269 unsigned int d 273 unsigned int debounce)
270 { 274 {
271 switch (state) { 275 switch (state) {
272 case accdet_state000: 276 case accdet_state000:
273 regmap_write(priv->regmap, ACC 277 regmap_write(priv->regmap, ACCDET_DEBOUNCE0_ADDR, debounce);
274 break; 278 break;
275 case accdet_state001: 279 case accdet_state001:
276 regmap_write(priv->regmap, ACC 280 regmap_write(priv->regmap, ACCDET_DEBOUNCE1_ADDR, debounce);
277 break; 281 break;
278 case accdet_state010: 282 case accdet_state010:
279 regmap_write(priv->regmap, ACC 283 regmap_write(priv->regmap, ACCDET_DEBOUNCE2_ADDR, debounce);
280 break; 284 break;
281 case accdet_state011: 285 case accdet_state011:
282 regmap_write(priv->regmap, ACC 286 regmap_write(priv->regmap, ACCDET_DEBOUNCE3_ADDR, debounce);
283 break; 287 break;
284 case accdet_auxadc: 288 case accdet_auxadc:
285 regmap_write(priv->regmap, 289 regmap_write(priv->regmap,
286 ACCDET_CONNECT_AU 290 ACCDET_CONNECT_AUXADC_TIME_DIG_ADDR, debounce);
287 break; 291 break;
288 case eint_state000: 292 case eint_state000:
289 regmap_update_bits(priv->regma 293 regmap_update_bits(priv->regmap, ACCDET_EINT_DEBOUNCE0_ADDR,
290 0xF << ACCD 294 0xF << ACCDET_EINT_DEBOUNCE0_SFT,
291 debounce << 295 debounce << ACCDET_EINT_DEBOUNCE0_SFT);
292 break; 296 break;
293 case eint_state001: 297 case eint_state001:
294 regmap_update_bits(priv->regma 298 regmap_update_bits(priv->regmap, ACCDET_EINT_DEBOUNCE1_ADDR,
295 0xF << ACCD 299 0xF << ACCDET_EINT_DEBOUNCE1_SFT,
296 debounce << 300 debounce << ACCDET_EINT_DEBOUNCE1_SFT);
297 break; 301 break;
298 case eint_state010: 302 case eint_state010:
299 regmap_update_bits(priv->regma 303 regmap_update_bits(priv->regmap, ACCDET_EINT_DEBOUNCE2_ADDR,
300 0xF << ACCD 304 0xF << ACCDET_EINT_DEBOUNCE2_SFT,
301 debounce << 305 debounce << ACCDET_EINT_DEBOUNCE2_SFT);
302 break; 306 break;
303 case eint_state011: 307 case eint_state011:
304 regmap_update_bits(priv->regma 308 regmap_update_bits(priv->regmap, ACCDET_EINT_DEBOUNCE3_ADDR,
305 0xF << ACCD 309 0xF << ACCDET_EINT_DEBOUNCE3_SFT,
306 debounce << 310 debounce << ACCDET_EINT_DEBOUNCE3_SFT);
307 break; 311 break;
308 case eint_inverter_state000: 312 case eint_inverter_state000:
309 regmap_write(priv->regmap, ACC 313 regmap_write(priv->regmap, ACCDET_EINT_INVERTER_DEBOUNCE_ADDR,
310 debounce); 314 debounce);
311 break; 315 break;
312 default: 316 default:
313 dev_warn(priv->dev, "Error: %s 317 dev_warn(priv->dev, "Error: %s error state (%d)\n", __func__,
314 state); 318 state);
315 break; 319 break;
316 } 320 }
317 } 321 }
318 322
319 static void mt6359_accdet_jack_report(struct m 323 static void mt6359_accdet_jack_report(struct mt6359_accdet *priv)
320 { 324 {
321 int report = 0; 325 int report = 0;
322 326
323 if (!priv->jack) 327 if (!priv->jack)
324 return; 328 return;
325 329
326 report = priv->jack_type | priv->btn_t 330 report = priv->jack_type | priv->btn_type;
327 snd_soc_jack_report(priv->jack, report 331 snd_soc_jack_report(priv->jack, report, MT6359_ACCDET_JACK_MASK);
328 } 332 }
329 333
330 static unsigned int check_button(struct mt6359 334 static unsigned int check_button(struct mt6359_accdet *priv, unsigned int v)
331 { 335 {
332 if (priv->caps & ACCDET_FOUR_KEY) { 336 if (priv->caps & ACCDET_FOUR_KEY) {
333 if (v < priv->data->four_key.d 337 if (v < priv->data->four_key.down &&
334 v >= priv->data->four_key. 338 v >= priv->data->four_key.up)
335 priv->btn_type = SND_J 339 priv->btn_type = SND_JACK_BTN_1;
336 if (v < priv->data->four_key.u 340 if (v < priv->data->four_key.up &&
337 v >= priv->data->four_key. 341 v >= priv->data->four_key.voice)
338 priv->btn_type = SND_J 342 priv->btn_type = SND_JACK_BTN_2;
339 if (v < priv->data->four_key.v 343 if (v < priv->data->four_key.voice &&
340 v >= priv->data->four_key. 344 v >= priv->data->four_key.mid)
341 priv->btn_type = SND_J 345 priv->btn_type = SND_JACK_BTN_3;
342 if (v < priv->data->four_key.m 346 if (v < priv->data->four_key.mid)
343 priv->btn_type = SND_J 347 priv->btn_type = SND_JACK_BTN_0;
344 } else { 348 } else {
345 if (v < priv->data->three_key. 349 if (v < priv->data->three_key.down &&
346 v >= priv->data->three_key 350 v >= priv->data->three_key.up)
347 priv->btn_type = SND_J 351 priv->btn_type = SND_JACK_BTN_1;
348 if (v < priv->data->three_key. 352 if (v < priv->data->three_key.up &&
349 v >= priv->data->three_key 353 v >= priv->data->three_key.mid)
350 priv->btn_type = SND_J 354 priv->btn_type = SND_JACK_BTN_2;
351 if (v < priv->data->three_key. 355 if (v < priv->data->three_key.mid)
352 priv->btn_type = SND_J 356 priv->btn_type = SND_JACK_BTN_0;
353 } 357 }
354 return 0; 358 return 0;
355 } 359 }
356 360
357 static void is_key_pressed(struct mt6359_accde 361 static void is_key_pressed(struct mt6359_accdet *priv, bool pressed)
358 { 362 {
359 priv->btn_type = priv->jack_type & ~MT 363 priv->btn_type = priv->jack_type & ~MT6359_ACCDET_BTN_MASK;
360 364
361 if (pressed) 365 if (pressed)
362 check_button(priv, priv->cali_ 366 check_button(priv, priv->cali_voltage);
363 } 367 }
364 368
365 static inline void check_jack_btn_type(struct 369 static inline void check_jack_btn_type(struct mt6359_accdet *priv)
366 { 370 {
367 unsigned int val = 0; 371 unsigned int val = 0;
368 372
369 regmap_read(priv->regmap, ACCDET_MEM_I 373 regmap_read(priv->regmap, ACCDET_MEM_IN_ADDR, &val);
370 374
371 priv->accdet_status = 375 priv->accdet_status =
372 (val >> ACCDET_STATE_MEM_IN_OF 376 (val >> ACCDET_STATE_MEM_IN_OFFSET) & ACCDET_STATE_AB_MASK;
373 377
374 switch (priv->accdet_status) { 378 switch (priv->accdet_status) {
375 case 0: 379 case 0:
376 if (priv->jack_type == SND_JAC 380 if (priv->jack_type == SND_JACK_HEADSET)
377 is_key_pressed(priv, t 381 is_key_pressed(priv, true);
378 else 382 else
379 priv->jack_type = SND_ 383 priv->jack_type = SND_JACK_HEADPHONE;
380 break; 384 break;
381 case 1: 385 case 1:
382 if (priv->jack_type == SND_JAC 386 if (priv->jack_type == SND_JACK_HEADSET) {
383 is_key_pressed(priv, f 387 is_key_pressed(priv, false);
384 } else { 388 } else {
385 priv->jack_type = SND_ 389 priv->jack_type = SND_JACK_HEADSET;
386 accdet_set_debounce(pr 390 accdet_set_debounce(priv, eint_state011, 0x1);
387 } 391 }
388 break; 392 break;
389 case 3: 393 case 3:
390 default: 394 default:
391 priv->jack_type = 0; 395 priv->jack_type = 0;
392 break; 396 break;
393 } 397 }
394 } 398 }
395 399
396 static void mt6359_accdet_work(struct work_str 400 static void mt6359_accdet_work(struct work_struct *work)
397 { 401 {
398 struct mt6359_accdet *priv = 402 struct mt6359_accdet *priv =
399 container_of(work, struct mt63 403 container_of(work, struct mt6359_accdet, accdet_work);
400 404
401 mutex_lock(&priv->res_lock); 405 mutex_lock(&priv->res_lock);
402 priv->pre_accdet_status = priv->accdet 406 priv->pre_accdet_status = priv->accdet_status;
403 check_jack_btn_type(priv); 407 check_jack_btn_type(priv);
404 408
405 if (priv->jack_plugged && 409 if (priv->jack_plugged &&
406 priv->pre_accdet_status != priv->a 410 priv->pre_accdet_status != priv->accdet_status)
407 mt6359_accdet_jack_report(priv 411 mt6359_accdet_jack_report(priv);
408 mutex_unlock(&priv->res_lock); 412 mutex_unlock(&priv->res_lock);
409 } 413 }
410 414
411 static void mt6359_accdet_jd_work(struct work_ 415 static void mt6359_accdet_jd_work(struct work_struct *work)
412 { 416 {
413 int ret; 417 int ret;
414 unsigned int value = 0; 418 unsigned int value = 0;
415 419
416 struct mt6359_accdet *priv = 420 struct mt6359_accdet *priv =
417 container_of(work, struct mt63 421 container_of(work, struct mt6359_accdet, jd_work);
418 422
419 mutex_lock(&priv->res_lock); 423 mutex_lock(&priv->res_lock);
420 if (priv->jd_sts == M_PLUG_IN) { 424 if (priv->jd_sts == M_PLUG_IN) {
421 priv->jack_plugged = true; 425 priv->jack_plugged = true;
422 426
423 /* set and clear initial bit e 427 /* set and clear initial bit every eint interrupt */
424 regmap_update_bits(priv->regma 428 regmap_update_bits(priv->regmap, ACCDET_SEQ_INIT_ADDR,
425 ACCDET_SEQ_ 429 ACCDET_SEQ_INIT_MASK_SFT,
426 BIT(ACCDET_ 430 BIT(ACCDET_SEQ_INIT_SFT));
427 regmap_update_bits(priv->regma 431 regmap_update_bits(priv->regmap, ACCDET_SEQ_INIT_ADDR,
428 ACCDET_SEQ_ 432 ACCDET_SEQ_INIT_MASK_SFT, 0);
429 ret = regmap_read_poll_timeout 433 ret = regmap_read_poll_timeout(priv->regmap,
430 434 ACCDET_SEQ_INIT_ADDR,
431 435 value,
432 436 (value & ACCDET_SEQ_INIT_MASK_SFT) == 0,
433 437 0,
434 438 1000);
435 if (ret) 439 if (ret)
436 dev_err(priv->dev, "%s 440 dev_err(priv->dev, "%s(), ret %d\n", __func__, ret);
437 441
438 /* enable ACCDET unit */ 442 /* enable ACCDET unit */
439 regmap_update_bits(priv->regma 443 regmap_update_bits(priv->regmap, ACCDET_SW_EN_ADDR,
440 ACCDET_SW_E 444 ACCDET_SW_EN_MASK_SFT, BIT(ACCDET_SW_EN_SFT));
441 } else if (priv->jd_sts == M_PLUG_OUT) 445 } else if (priv->jd_sts == M_PLUG_OUT) {
442 priv->jack_plugged = false; 446 priv->jack_plugged = false;
443 447
444 accdet_set_debounce(priv, accd 448 accdet_set_debounce(priv, accdet_state011,
445 priv->data 449 priv->data->pwm_deb->debounce3);
446 regmap_update_bits(priv->regma 450 regmap_update_bits(priv->regmap, ACCDET_SW_EN_ADDR,
447 ACCDET_SW_E 451 ACCDET_SW_EN_MASK_SFT, 0);
448 mt6359_accdet_recover_jd_setti 452 mt6359_accdet_recover_jd_setting(priv);
449 } 453 }
450 454
451 if (priv->caps & ACCDET_PMIC_EINT_IRQ) 455 if (priv->caps & ACCDET_PMIC_EINT_IRQ)
452 recover_eint_setting(priv); 456 recover_eint_setting(priv);
453 mutex_unlock(&priv->res_lock); 457 mutex_unlock(&priv->res_lock);
454 } 458 }
455 459
456 static irqreturn_t mt6359_accdet_irq(int irq, 460 static irqreturn_t mt6359_accdet_irq(int irq, void *data)
457 { 461 {
458 struct mt6359_accdet *priv = data; 462 struct mt6359_accdet *priv = data;
459 unsigned int irq_val = 0, val = 0, val 463 unsigned int irq_val = 0, val = 0, value = 0;
460 int ret; 464 int ret;
461 465
462 mutex_lock(&priv->res_lock); 466 mutex_lock(&priv->res_lock);
463 regmap_read(priv->regmap, ACCDET_IRQ_A 467 regmap_read(priv->regmap, ACCDET_IRQ_ADDR, &irq_val);
464 468
465 if (irq_val & ACCDET_IRQ_MASK_SFT) { 469 if (irq_val & ACCDET_IRQ_MASK_SFT) {
466 regmap_update_bits(priv->regma 470 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
467 ACCDET_IRQ_ 471 ACCDET_IRQ_CLR_MASK_SFT,
468 BIT(ACCDET_ 472 BIT(ACCDET_IRQ_CLR_SFT));
469 ret = regmap_read_poll_timeout 473 ret = regmap_read_poll_timeout(priv->regmap,
470 474 ACCDET_IRQ_ADDR,
471 475 value,
472 476 (value & ACCDET_IRQ_MASK_SFT) == 0,
473 477 0,
474 478 1000);
475 if (ret) { 479 if (ret) {
476 dev_err(priv->dev, "%s 480 dev_err(priv->dev, "%s(), ret %d\n", __func__, ret);
477 mutex_unlock(&priv->re 481 mutex_unlock(&priv->res_lock);
478 return IRQ_NONE; 482 return IRQ_NONE;
479 } 483 }
480 regmap_update_bits(priv->regma 484 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
481 ACCDET_IRQ_ 485 ACCDET_IRQ_CLR_MASK_SFT, 0);
482 regmap_update_bits(priv->regma 486 regmap_update_bits(priv->regmap, RG_INT_STATUS_ACCDET_ADDR,
483 RG_INT_STAT 487 RG_INT_STATUS_ACCDET_MASK_SFT,
484 BIT(RG_INT_ 488 BIT(RG_INT_STATUS_ACCDET_SFT));
485 489
486 queue_work(priv->accdet_workqu 490 queue_work(priv->accdet_workqueue, &priv->accdet_work);
487 } else { 491 } else {
488 if (irq_val & ACCDET_EINT0_IRQ 492 if (irq_val & ACCDET_EINT0_IRQ_MASK_SFT) {
489 regmap_update_bits(pri 493 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
490 ACC 494 ACCDET_EINT0_IRQ_CLR_MASK_SFT,
491 BIT 495 BIT(ACCDET_EINT0_IRQ_CLR_SFT));
492 ret = regmap_read_poll 496 ret = regmap_read_poll_timeout(priv->regmap,
493 497 ACCDET_IRQ_ADDR,
494 498 value,
495 499 (value & ACCDET_EINT0_IRQ_MASK_SFT) == 0,
496 500 0,
497 501 1000);
498 if (ret) { 502 if (ret) {
499 dev_err(priv-> 503 dev_err(priv->dev, "%s(), ret %d\n", __func__,
500 ret); 504 ret);
501 mutex_unlock(& 505 mutex_unlock(&priv->res_lock);
502 return IRQ_NON 506 return IRQ_NONE;
503 } 507 }
504 regmap_update_bits(pri 508 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
505 ACC 509 ACCDET_EINT0_IRQ_CLR_MASK_SFT, 0);
506 regmap_update_bits(pri 510 regmap_update_bits(priv->regmap,
507 RG_ 511 RG_INT_STATUS_ACCDET_ADDR,
508 RG_ 512 RG_INT_STATUS_ACCDET_EINT0_MASK_SFT,
509 BIT 513 BIT(RG_INT_STATUS_ACCDET_EINT0_SFT));
510 } 514 }
511 if (irq_val & ACCDET_EINT1_IRQ 515 if (irq_val & ACCDET_EINT1_IRQ_MASK_SFT) {
512 regmap_update_bits(pri 516 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
513 ACC 517 ACCDET_EINT1_IRQ_CLR_MASK_SFT,
514 BIT 518 BIT(ACCDET_EINT1_IRQ_CLR_SFT));
515 ret = regmap_read_poll 519 ret = regmap_read_poll_timeout(priv->regmap,
516 520 ACCDET_IRQ_ADDR,
517 521 value,
518 522 (value & ACCDET_EINT1_IRQ_MASK_SFT) == 0,
519 523 0,
520 524 1000);
521 if (ret) { 525 if (ret) {
522 dev_err(priv-> 526 dev_err(priv->dev, "%s(), ret %d\n", __func__,
523 ret); 527 ret);
524 mutex_unlock(& 528 mutex_unlock(&priv->res_lock);
525 return IRQ_NON 529 return IRQ_NONE;
526 } 530 }
527 regmap_update_bits(pri 531 regmap_update_bits(priv->regmap, ACCDET_IRQ_ADDR,
528 ACC 532 ACCDET_EINT1_IRQ_CLR_MASK_SFT, 0);
529 regmap_update_bits(pri 533 regmap_update_bits(priv->regmap,
530 RG_ 534 RG_INT_STATUS_ACCDET_ADDR,
531 RG_ 535 RG_INT_STATUS_ACCDET_EINT1_MASK_SFT,
532 BIT 536 BIT(RG_INT_STATUS_ACCDET_EINT1_SFT));
533 } 537 }
534 /* get jack detection status * 538 /* get jack detection status */
535 regmap_read(priv->regmap, ACCD 539 regmap_read(priv->regmap, ACCDET_EINT0_MEM_IN_ADDR, &val);
536 priv->jd_sts = ((val >> ACCDET 540 priv->jd_sts = ((val >> ACCDET_EINT0_MEM_IN_SFT) &
537 ACCDET_EINT 541 ACCDET_EINT0_MEM_IN_MASK);
538 /* adjust eint digital/analog 542 /* adjust eint digital/analog setting */
539 mt6359_accdet_jd_setting(priv) 543 mt6359_accdet_jd_setting(priv);
540 544
541 queue_work(priv->jd_workqueue, 545 queue_work(priv->jd_workqueue, &priv->jd_work);
542 } 546 }
543 mutex_unlock(&priv->res_lock); 547 mutex_unlock(&priv->res_lock);
544 548
545 return IRQ_HANDLED; 549 return IRQ_HANDLED;
546 } 550 }
547 551
548 static int mt6359_accdet_parse_dt(struct mt635 552 static int mt6359_accdet_parse_dt(struct mt6359_accdet *priv)
549 { 553 {
550 int ret; 554 int ret;
551 struct device *dev = priv->dev; 555 struct device *dev = priv->dev;
552 struct device_node *node = NULL; 556 struct device_node *node = NULL;
553 int pwm_deb[15] = {0}; 557 int pwm_deb[15] = {0};
554 unsigned int tmp = 0; 558 unsigned int tmp = 0;
555 559
556 node = of_get_child_by_name(dev->paren 560 node = of_get_child_by_name(dev->parent->of_node, "accdet");
557 if (!node) 561 if (!node)
558 return -EINVAL; 562 return -EINVAL;
559 563
560 ret = of_property_read_u32(node, "medi 564 ret = of_property_read_u32(node, "mediatek,mic-vol",
561 &priv->data 565 &priv->data->mic_vol);
562 if (ret) 566 if (ret)
563 priv->data->mic_vol = 8; 567 priv->data->mic_vol = 8;
564 568
565 ret = of_property_read_u32(node, "medi 569 ret = of_property_read_u32(node, "mediatek,plugout-debounce",
566 &priv->data 570 &priv->data->plugout_deb);
567 if (ret) 571 if (ret)
568 priv->data->plugout_deb = 1; 572 priv->data->plugout_deb = 1;
569 573
570 ret = of_property_read_u32(node, "medi 574 ret = of_property_read_u32(node, "mediatek,mic-mode",
571 &priv->data 575 &priv->data->mic_mode);
572 if (ret) 576 if (ret)
573 priv->data->mic_mode = 2; 577 priv->data->mic_mode = 2;
574 578
575 ret = of_property_read_u32_array(node, 579 ret = of_property_read_u32_array(node, "mediatek,pwm-deb-setting",
576 pwm_d 580 pwm_deb, ARRAY_SIZE(pwm_deb));
577 /* debounce8(auxadc debounce) is defau 581 /* debounce8(auxadc debounce) is default, needn't get from dts */
578 if (!ret) 582 if (!ret)
579 memcpy(priv->data->pwm_deb, pw 583 memcpy(priv->data->pwm_deb, pwm_deb, sizeof(pwm_deb));
580 584
581 ret = of_property_read_u32(node, "medi 585 ret = of_property_read_u32(node, "mediatek,eint-level-pol",
582 &priv->data 586 &priv->data->eint_pol);
583 if (ret) 587 if (ret)
584 priv->data->eint_pol = 8; 588 priv->data->eint_pol = 8;
585 589
586 ret = of_property_read_u32(node, "medi 590 ret = of_property_read_u32(node, "mediatek,eint-use-ap", &tmp);
587 if (ret) 591 if (ret)
588 tmp = 0; 592 tmp = 0;
589 if (tmp == 0) 593 if (tmp == 0)
590 priv->caps |= ACCDET_PMIC_EINT 594 priv->caps |= ACCDET_PMIC_EINT_IRQ;
591 else if (tmp == 1) 595 else if (tmp == 1)
592 priv->caps |= ACCDET_AP_GPIO_E 596 priv->caps |= ACCDET_AP_GPIO_EINT;
593 597
594 ret = of_property_read_u32(node, "medi 598 ret = of_property_read_u32(node, "mediatek,eint-detect-mode",
595 &priv->data 599 &priv->data->eint_detect_mode);
596 if (ret) { 600 if (ret) {
597 /* eint detection mode equals 601 /* eint detection mode equals to EINT HW Mode */
598 priv->data->eint_detect_mode = 602 priv->data->eint_detect_mode = 0x4;
599 } 603 }
600 604
601 ret = of_property_read_u32(node, "medi 605 ret = of_property_read_u32(node, "mediatek,eint-num", &tmp);
602 if (ret) 606 if (ret)
603 tmp = 0; 607 tmp = 0;
604 if (tmp == 0) 608 if (tmp == 0)
605 priv->caps |= ACCDET_PMIC_EINT 609 priv->caps |= ACCDET_PMIC_EINT0;
606 else if (tmp == 1) 610 else if (tmp == 1)
607 priv->caps |= ACCDET_PMIC_EINT 611 priv->caps |= ACCDET_PMIC_EINT1;
608 else if (tmp == 2) 612 else if (tmp == 2)
609 priv->caps |= ACCDET_PMIC_BI_E 613 priv->caps |= ACCDET_PMIC_BI_EINT;
610 614
611 ret = of_property_read_u32(node, "medi 615 ret = of_property_read_u32(node, "mediatek,eint-trig-mode",
612 &tmp); 616 &tmp);
613 if (ret) 617 if (ret)
614 tmp = 0; 618 tmp = 0;
615 if (tmp == 0) 619 if (tmp == 0)
616 priv->caps |= ACCDET_PMIC_GPIO 620 priv->caps |= ACCDET_PMIC_GPIO_TRIG_EINT;
617 else if (tmp == 1) 621 else if (tmp == 1)
618 priv->caps |= ACCDET_PMIC_INVE 622 priv->caps |= ACCDET_PMIC_INVERTER_TRIG_EINT;
619 623
620 ret = of_property_read_u32(node, "medi 624 ret = of_property_read_u32(node, "mediatek,eint-use-ext-res",
621 &priv->data 625 &priv->data->eint_use_ext_res);
622 if (ret) { 626 if (ret) {
623 /* eint use internal resister 627 /* eint use internal resister */
624 priv->data->eint_use_ext_res = 628 priv->data->eint_use_ext_res = 0x0;
625 } 629 }
626 630
627 ret = of_property_read_u32(node, "medi 631 ret = of_property_read_u32(node, "mediatek,eint-comp-vth",
628 &priv->data 632 &priv->data->eint_comp_vth);
629 if (ret) 633 if (ret)
630 priv->data->eint_comp_vth = 0x 634 priv->data->eint_comp_vth = 0x0;
631 635
632 ret = of_property_read_u32(node, "medi 636 ret = of_property_read_u32(node, "mediatek,key-mode", &tmp);
633 if (ret) 637 if (ret)
634 tmp = 0; 638 tmp = 0;
635 if (tmp == 0) { 639 if (tmp == 0) {
636 int three_key[4]; 640 int three_key[4];
637 641
638 priv->caps |= ACCDET_THREE_KEY 642 priv->caps |= ACCDET_THREE_KEY;
639 ret = of_property_read_u32_arr 643 ret = of_property_read_u32_array(node,
640 644 "mediatek,three-key-thr",
641 645 three_key,
642 646 ARRAY_SIZE(three_key));
643 if (!ret) 647 if (!ret)
644 memcpy(&priv->data->th 648 memcpy(&priv->data->three_key, three_key + 1,
645 sizeof(struct t 649 sizeof(struct three_key_threshold));
646 } else if (tmp == 1) { 650 } else if (tmp == 1) {
647 int four_key[5]; 651 int four_key[5];
648 652
649 priv->caps |= ACCDET_FOUR_KEY; 653 priv->caps |= ACCDET_FOUR_KEY;
650 ret = of_property_read_u32_arr 654 ret = of_property_read_u32_array(node,
651 655 "mediatek,four-key-thr",
652 656 four_key,
653 657 ARRAY_SIZE(four_key));
654 if (!ret) { 658 if (!ret) {
655 memcpy(&priv->data->fo 659 memcpy(&priv->data->four_key, four_key + 1,
656 sizeof(struct f 660 sizeof(struct four_key_threshold));
657 } else { 661 } else {
658 dev_warn(priv->dev, 662 dev_warn(priv->dev,
659 "accdet no 4- 663 "accdet no 4-key-thrsh dts, use efuse\n");
660 } 664 }
661 } else if (tmp == 2) { 665 } else if (tmp == 2) {
662 int three_key[4]; 666 int three_key[4];
663 667
664 priv->caps |= ACCDET_TRI_KEY_C 668 priv->caps |= ACCDET_TRI_KEY_CDD;
665 ret = of_property_read_u32_arr 669 ret = of_property_read_u32_array(node,
666 670 "mediatek,tri-key-cdd-thr",
667 671 three_key,
668 672 ARRAY_SIZE(three_key));
669 if (!ret) 673 if (!ret)
670 memcpy(&priv->data->th 674 memcpy(&priv->data->three_key, three_key + 1,
671 sizeof(struct t 675 sizeof(struct three_key_threshold));
672 } 676 }
673 677
674 of_node_put(node); 678 of_node_put(node);
675 dev_warn(priv->dev, "accdet caps=%x\n" 679 dev_warn(priv->dev, "accdet caps=%x\n", priv->caps);
676 680
677 return 0; 681 return 0;
678 } 682 }
679 683
680 static void config_digital_init_by_mode(struct 684 static void config_digital_init_by_mode(struct mt6359_accdet *priv)
681 { 685 {
682 /* enable eint cmpmem pwm */ 686 /* enable eint cmpmem pwm */
683 regmap_write(priv->regmap, ACCDET_EINT 687 regmap_write(priv->regmap, ACCDET_EINT_CMPMEN_PWM_THRESH_ADDR,
684 (priv->data->pwm_deb->ein 688 (priv->data->pwm_deb->eint_pwm_width << 4 |
685 priv->data->pwm_deb->eint 689 priv->data->pwm_deb->eint_pwm_thresh));
686 /* DA signal stable */ 690 /* DA signal stable */
687 if (priv->caps & ACCDET_PMIC_EINT0) { 691 if (priv->caps & ACCDET_PMIC_EINT0) {
688 regmap_write(priv->regmap, ACC 692 regmap_write(priv->regmap, ACCDET_DA_STABLE_ADDR,
689 ACCDET_EINT0_STAB 693 ACCDET_EINT0_STABLE_VAL);
690 } else if (priv->caps & ACCDET_PMIC_EI 694 } else if (priv->caps & ACCDET_PMIC_EINT1) {
691 regmap_write(priv->regmap, ACC 695 regmap_write(priv->regmap, ACCDET_DA_STABLE_ADDR,
692 ACCDET_EINT1_STAB 696 ACCDET_EINT1_STABLE_VAL);
693 } 697 }
694 /* after receive n+1 number, interrupt 698 /* after receive n+1 number, interrupt issued. */
695 regmap_update_bits(priv->regmap, ACCDE 699 regmap_update_bits(priv->regmap, ACCDET_EINT_M_PLUG_IN_NUM_ADDR,
696 ACCDET_EINT_M_PLUG_ 700 ACCDET_EINT_M_PLUG_IN_NUM_MASK_SFT,
697 BIT(ACCDET_EINT_M_P 701 BIT(ACCDET_EINT_M_PLUG_IN_NUM_SFT));
698 /* setting HW mode, enable digital fas 702 /* setting HW mode, enable digital fast discharge
699 * if use EINT0 & EINT1 detection, ple 703 * if use EINT0 & EINT1 detection, please modify
700 * ACCDET_HWMODE_EN_ADDR[2:1] 704 * ACCDET_HWMODE_EN_ADDR[2:1]
701 */ 705 */
702 regmap_write(priv->regmap, ACCDET_HWMO 706 regmap_write(priv->regmap, ACCDET_HWMODE_EN_ADDR, 0x100);
703 707
704 regmap_update_bits(priv->regmap, ACCDE 708 regmap_update_bits(priv->regmap, ACCDET_EINT_M_DETECT_EN_ADDR,
705 ACCDET_EINT_M_DETEC 709 ACCDET_EINT_M_DETECT_EN_MASK_SFT, 0);
706 710
707 /* enable PWM */ 711 /* enable PWM */
708 regmap_write(priv->regmap, ACCDET_CMP_ 712 regmap_write(priv->regmap, ACCDET_CMP_PWM_EN_ADDR, 0x67);
709 /* enable inverter detection */ 713 /* enable inverter detection */
710 if (priv->data->eint_detect_mode == 0x 714 if (priv->data->eint_detect_mode == 0x1) {
711 /* disable inverter detection 715 /* disable inverter detection */
712 if (priv->caps & ACCDET_PMIC_E 716 if (priv->caps & ACCDET_PMIC_EINT0) {
713 regmap_update_bits(pri 717 regmap_update_bits(priv->regmap,
714 ACC 718 ACCDET_EINT0_INVERTER_SW_EN_ADDR,
715 ACC 719 ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT,
716 0); 720 0);
717 } else if (priv->caps & ACCDET 721 } else if (priv->caps & ACCDET_PMIC_EINT1) {
718 regmap_update_bits(pri 722 regmap_update_bits(priv->regmap,
719 ACC 723 ACCDET_EINT1_INVERTER_SW_EN_ADDR,
720 ACC 724 ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT,
721 0); 725 0);
722 } 726 }
723 } else { 727 } else {
724 if (priv->caps & ACCDET_PMIC_E 728 if (priv->caps & ACCDET_PMIC_EINT0) {
725 regmap_update_bits(pri 729 regmap_update_bits(priv->regmap,
726 ACC 730 ACCDET_EINT0_INVERTER_SW_EN_ADDR,
727 ACC 731 ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT,
728 BIT 732 BIT(ACCDET_EINT0_INVERTER_SW_EN_SFT));
729 } else if (priv->caps & ACCDET 733 } else if (priv->caps & ACCDET_PMIC_EINT1) {
730 regmap_update_bits(pri 734 regmap_update_bits(priv->regmap,
731 ACC 735 ACCDET_EINT1_INVERTER_SW_EN_ADDR,
732 ACC 736 ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT,
733 BIT 737 BIT(ACCDET_EINT1_INVERTER_SW_EN_SFT));
734 } 738 }
735 } 739 }
736 } 740 }
737 741
738 static void config_eint_init_by_mode(struct mt 742 static void config_eint_init_by_mode(struct mt6359_accdet *priv)
739 { 743 {
740 unsigned int val = 0; 744 unsigned int val = 0;
741 745
742 if (priv->caps & ACCDET_PMIC_EINT0) { 746 if (priv->caps & ACCDET_PMIC_EINT0) {
743 regmap_update_bits(priv->regma 747 regmap_update_bits(priv->regmap, RG_EINT0EN_ADDR,
744 RG_EINT0EN_ 748 RG_EINT0EN_MASK_SFT, BIT(RG_EINT0EN_SFT));
745 } else if (priv->caps & ACCDET_PMIC_EI 749 } else if (priv->caps & ACCDET_PMIC_EINT1) {
746 regmap_update_bits(priv->regma 750 regmap_update_bits(priv->regmap, RG_EINT1EN_ADDR,
747 RG_EINT1EN_ 751 RG_EINT1EN_MASK_SFT, BIT(RG_EINT1EN_SFT));
748 } 752 }
749 /* ESD switches on */ 753 /* ESD switches on */
750 regmap_update_bits(priv->regmap, RG_AC 754 regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR,
751 1 << 8, 1 << 8); 755 1 << 8, 1 << 8);
752 /* before playback, set NCP pull low b 756 /* before playback, set NCP pull low before nagative voltage */
753 regmap_update_bits(priv->regmap, RG_NC 757 regmap_update_bits(priv->regmap, RG_NCP_PDDIS_EN_ADDR,
754 RG_NCP_PDDIS_EN_MAS 758 RG_NCP_PDDIS_EN_MASK_SFT, BIT(RG_NCP_PDDIS_EN_SFT));
755 759
756 if (priv->data->eint_detect_mode == 0x 760 if (priv->data->eint_detect_mode == 0x1 ||
757 priv->data->eint_detect_mode == 0x 761 priv->data->eint_detect_mode == 0x2 ||
758 priv->data->eint_detect_mode == 0x 762 priv->data->eint_detect_mode == 0x3) {
759 if (priv->data->eint_use_ext_r 763 if (priv->data->eint_use_ext_res == 0x1) {
760 if (priv->caps & ACCDE 764 if (priv->caps & ACCDET_PMIC_EINT0) {
761 regmap_update_ 765 regmap_update_bits(priv->regmap,
762 766 RG_EINT0CONFIGACCDET_ADDR,
763 767 RG_EINT0CONFIGACCDET_MASK_SFT,
764 768 0);
765 } else if (priv->caps 769 } else if (priv->caps & ACCDET_PMIC_EINT1) {
766 regmap_update_ 770 regmap_update_bits(priv->regmap,
767 771 RG_EINT1CONFIGACCDET_ADDR,
768 772 RG_EINT1CONFIGACCDET_MASK_SFT,
769 773 0);
770 } 774 }
771 } else { 775 } else {
772 if (priv->caps & ACCDE 776 if (priv->caps & ACCDET_PMIC_EINT0) {
773 regmap_update_ 777 regmap_update_bits(priv->regmap,
774 778 RG_EINT0CONFIGACCDET_ADDR,
775 779 RG_EINT0CONFIGACCDET_MASK_SFT,
776 780 BIT(RG_EINT0CONFIGACCDET_SFT));
777 } else if (priv->caps 781 } else if (priv->caps & ACCDET_PMIC_EINT1) {
778 regmap_update_ 782 regmap_update_bits(priv->regmap,
779 783 RG_EINT1CONFIGACCDET_ADDR,
780 784 RG_EINT1CONFIGACCDET_MASK_SFT,
781 785 BIT(RG_EINT1CONFIGACCDET_SFT));
782 } 786 }
783 } 787 }
784 } 788 }
785 789
786 if (priv->data->eint_detect_mode != 0x 790 if (priv->data->eint_detect_mode != 0x1) {
787 /* current detect set 0.25uA * 791 /* current detect set 0.25uA */
788 regmap_update_bits(priv->regma 792 regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR,
789 0x3 << RG_A 793 0x3 << RG_ACCDETSPARE_SFT,
790 0x3 << RG_A 794 0x3 << RG_ACCDETSPARE_SFT);
791 } 795 }
792 regmap_write(priv->regmap, RG_EINTCOMP 796 regmap_write(priv->regmap, RG_EINTCOMPVTH_ADDR,
793 val | priv->data->eint_co 797 val | priv->data->eint_comp_vth << RG_EINTCOMPVTH_SFT);
794 } 798 }
795 799
796 static void mt6359_accdet_init(struct mt6359_a 800 static void mt6359_accdet_init(struct mt6359_accdet *priv)
797 { 801 {
798 unsigned int reg = 0; 802 unsigned int reg = 0;
799 803
800 regmap_update_bits(priv->regmap, ACCDE 804 regmap_update_bits(priv->regmap, ACCDET_SEQ_INIT_ADDR,
801 ACCDET_SEQ_INIT_MAS 805 ACCDET_SEQ_INIT_MASK_SFT, BIT(ACCDET_SEQ_INIT_SFT));
802 mdelay(2); 806 mdelay(2);
803 regmap_update_bits(priv->regmap, ACCDE 807 regmap_update_bits(priv->regmap, ACCDET_SEQ_INIT_ADDR,
804 ACCDET_SEQ_INIT_MAS 808 ACCDET_SEQ_INIT_MASK_SFT, 0);
805 mdelay(1); 809 mdelay(1);
806 /* init the debounce time (debounce/32 810 /* init the debounce time (debounce/32768)sec */
807 accdet_set_debounce(priv, accdet_state 811 accdet_set_debounce(priv, accdet_state000,
808 priv->data->pwm_de 812 priv->data->pwm_deb->debounce0);
809 accdet_set_debounce(priv, accdet_state 813 accdet_set_debounce(priv, accdet_state001,
810 priv->data->pwm_de 814 priv->data->pwm_deb->debounce1);
811 accdet_set_debounce(priv, accdet_state 815 accdet_set_debounce(priv, accdet_state011,
812 priv->data->pwm_de 816 priv->data->pwm_deb->debounce3);
813 accdet_set_debounce(priv, accdet_auxad 817 accdet_set_debounce(priv, accdet_auxadc,
814 priv->data->pwm_de 818 priv->data->pwm_deb->debounce4);
815 819
816 accdet_set_debounce(priv, eint_state00 820 accdet_set_debounce(priv, eint_state000,
817 priv->data->pwm_de 821 priv->data->pwm_deb->eint_debounce0);
818 accdet_set_debounce(priv, eint_state00 822 accdet_set_debounce(priv, eint_state001,
819 priv->data->pwm_de 823 priv->data->pwm_deb->eint_debounce1);
820 accdet_set_debounce(priv, eint_state01 824 accdet_set_debounce(priv, eint_state011,
821 priv->data->pwm_de 825 priv->data->pwm_deb->eint_debounce3);
822 accdet_set_debounce(priv, eint_inverte 826 accdet_set_debounce(priv, eint_inverter_state000,
823 priv->data->pwm_de 827 priv->data->pwm_deb->eint_inverter_debounce);
824 828
825 regmap_update_bits(priv->regmap, RG_AC 829 regmap_update_bits(priv->regmap, RG_ACCDET_RST_ADDR,
826 RG_ACCDET_RST_MASK_ 830 RG_ACCDET_RST_MASK_SFT, BIT(RG_ACCDET_RST_SFT));
827 regmap_update_bits(priv->regmap, RG_AC 831 regmap_update_bits(priv->regmap, RG_ACCDET_RST_ADDR,
828 RG_ACCDET_RST_MASK_ 832 RG_ACCDET_RST_MASK_SFT, 0);
829 833
830 /* clear high micbias1 voltage setting 834 /* clear high micbias1 voltage setting */
831 regmap_update_bits(priv->regmap, RG_AU 835 regmap_update_bits(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR,
832 0x3 << RG_AUDMICBIA 836 0x3 << RG_AUDMICBIAS1HVEN_SFT, 0);
833 regmap_update_bits(priv->regmap, RG_AU 837 regmap_update_bits(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR,
834 0x7 << RG_AUDMICBIA 838 0x7 << RG_AUDMICBIAS1VREF_SFT, 0);
835 839
836 /* init pwm frequency, duty & rise/fal 840 /* init pwm frequency, duty & rise/falling delay */
837 regmap_write(priv->regmap, ACCDET_PWM_ 841 regmap_write(priv->regmap, ACCDET_PWM_WIDTH_ADDR,
838 REGISTER_VAL(priv->data-> 842 REGISTER_VAL(priv->data->pwm_deb->pwm_width));
839 regmap_write(priv->regmap, ACCDET_PWM_ 843 regmap_write(priv->regmap, ACCDET_PWM_THRESH_ADDR,
840 REGISTER_VAL(priv->data-> 844 REGISTER_VAL(priv->data->pwm_deb->pwm_thresh));
841 regmap_write(priv->regmap, ACCDET_RISE 845 regmap_write(priv->regmap, ACCDET_RISE_DELAY_ADDR,
842 (priv->data->pwm_deb->fal 846 (priv->data->pwm_deb->fall_delay << 15 |
843 priv->data->pwm_deb->ris 847 priv->data->pwm_deb->rise_delay));
844 848
845 regmap_read(priv->regmap, RG_AUDPWDBMI 849 regmap_read(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR, ®);
846 if (priv->data->mic_vol <= 7) { 850 if (priv->data->mic_vol <= 7) {
847 /* micbias1 <= 2.7V */ 851 /* micbias1 <= 2.7V */
848 regmap_write(priv->regmap, RG_ 852 regmap_write(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR,
849 reg | (priv->data 853 reg | (priv->data->mic_vol << RG_AUDMICBIAS1VREF_SFT) |
850 RG_AUDMICBIAS1LOW 854 RG_AUDMICBIAS1LOWPEN_MASK_SFT);
851 } else if (priv->data->mic_vol == 8) { 855 } else if (priv->data->mic_vol == 8) {
852 /* micbias1 = 2.8v */ 856 /* micbias1 = 2.8v */
853 regmap_write(priv->regmap, RG_ 857 regmap_write(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR,
854 reg | (3 << RG_AU 858 reg | (3 << RG_AUDMICBIAS1HVEN_SFT) |
855 RG_AUDMICBIAS1LOW 859 RG_AUDMICBIAS1LOWPEN_MASK_SFT);
856 } else if (priv->data->mic_vol == 9) { 860 } else if (priv->data->mic_vol == 9) {
857 /* micbias1 = 2.85v */ 861 /* micbias1 = 2.85v */
858 regmap_write(priv->regmap, RG_ 862 regmap_write(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR,
859 reg | (1 << RG_AU 863 reg | (1 << RG_AUDMICBIAS1HVEN_SFT) |
860 RG_AUDMICBIAS1LOW 864 RG_AUDMICBIAS1LOWPEN_MASK_SFT);
861 } 865 }
862 /* mic mode setting */ 866 /* mic mode setting */
863 regmap_read(priv->regmap, RG_AUDACCDET 867 regmap_read(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR, ®);
864 if (priv->data->mic_mode == HEADSET_MO 868 if (priv->data->mic_mode == HEADSET_MODE_1) {
865 /* ACC mode*/ 869 /* ACC mode*/
866 regmap_write(priv->regmap, RG_ 870 regmap_write(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR,
867 reg | RG_ACCDET_M 871 reg | RG_ACCDET_MODE_ANA11_MODE1);
868 /* enable analog fast discharg 872 /* enable analog fast discharge */
869 regmap_update_bits(priv->regma 873 regmap_update_bits(priv->regmap, RG_ANALOGFDEN_ADDR,
870 RG_ANALOGFD 874 RG_ANALOGFDEN_MASK_SFT,
871 BIT(RG_ANAL 875 BIT(RG_ANALOGFDEN_SFT));
872 regmap_update_bits(priv->regma 876 regmap_update_bits(priv->regmap, RG_ACCDETSPARE_ADDR,
873 0x3 << 11, 877 0x3 << 11, 0x3 << 11);
874 } else if (priv->data->mic_mode == HEA 878 } else if (priv->data->mic_mode == HEADSET_MODE_2) {
875 /* DCC mode Low cost mode with 879 /* DCC mode Low cost mode without internal bias */
876 regmap_write(priv->regmap, RG_ 880 regmap_write(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR,
877 reg | RG_ACCDET_M 881 reg | RG_ACCDET_MODE_ANA11_MODE2);
878 /* enable analog fast discharg 882 /* enable analog fast discharge */
879 regmap_update_bits(priv->regma 883 regmap_update_bits(priv->regmap, RG_ANALOGFDEN_ADDR,
880 0x3 << RG_A 884 0x3 << RG_ANALOGFDEN_SFT,
881 0x3 << RG_A 885 0x3 << RG_ANALOGFDEN_SFT);
882 } else if (priv->data->mic_mode == HEA 886 } else if (priv->data->mic_mode == HEADSET_MODE_6) {
883 /* DCC mode Low cost mode with 887 /* DCC mode Low cost mode with internal bias,
884 * bit8 = 1 to use internal bi 888 * bit8 = 1 to use internal bias
885 */ 889 */
886 regmap_write(priv->regmap, RG_ 890 regmap_write(priv->regmap, RG_AUDACCDETMICBIAS0PULLLOW_ADDR,
887 reg | RG_ACCDET_M 891 reg | RG_ACCDET_MODE_ANA11_MODE6);
888 regmap_update_bits(priv->regma 892 regmap_update_bits(priv->regmap, RG_AUDPWDBMICBIAS1_ADDR,
889 RG_AUDMICBI 893 RG_AUDMICBIAS1DCSW1PEN_MASK_SFT,
890 BIT(RG_AUDM 894 BIT(RG_AUDMICBIAS1DCSW1PEN_SFT));
891 /* enable analog fast discharg 895 /* enable analog fast discharge */
892 regmap_update_bits(priv->regma 896 regmap_update_bits(priv->regmap, RG_ANALOGFDEN_ADDR,
893 0x3 << RG_A 897 0x3 << RG_ANALOGFDEN_SFT,
894 0x3 << RG_A 898 0x3 << RG_ANALOGFDEN_SFT);
895 } 899 }
896 900
897 if (priv->caps & ACCDET_PMIC_EINT_IRQ) 901 if (priv->caps & ACCDET_PMIC_EINT_IRQ) {
898 config_eint_init_by_mode(priv) 902 config_eint_init_by_mode(priv);
899 config_digital_init_by_mode(pr 903 config_digital_init_by_mode(priv);
900 } 904 }
901 } 905 }
902 906
903 int mt6359_accdet_enable_jack_detect(struct sn 907 int mt6359_accdet_enable_jack_detect(struct snd_soc_component *component,
904 struct sn 908 struct snd_soc_jack *jack)
905 { 909 {
906 struct mt6359_accdet *priv = 910 struct mt6359_accdet *priv =
907 snd_soc_component_get_drvdata( 911 snd_soc_component_get_drvdata(component);
908 912
909 snd_jack_set_key(jack->jack, SND_JACK_ 913 snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
910 snd_jack_set_key(jack->jack, SND_JACK_ 914 snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOLUMEDOWN);
911 snd_jack_set_key(jack->jack, SND_JACK_ 915 snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
912 snd_jack_set_key(jack->jack, SND_JACK_ 916 snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOICECOMMAND);
913 917
914 priv->jack = jack; 918 priv->jack = jack;
915 919
916 mt6359_accdet_jack_report(priv); 920 mt6359_accdet_jack_report(priv);
917 921
918 return 0; 922 return 0;
919 } 923 }
920 EXPORT_SYMBOL_GPL(mt6359_accdet_enable_jack_de 924 EXPORT_SYMBOL_GPL(mt6359_accdet_enable_jack_detect);
921 925
922 static int mt6359_accdet_probe(struct platform 926 static int mt6359_accdet_probe(struct platform_device *pdev)
923 { 927 {
924 struct mt6359_accdet *priv; 928 struct mt6359_accdet *priv;
925 struct mt6397_chip *mt6397 = dev_get_d 929 struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
926 int ret; 930 int ret;
927 931
928 dev_dbg(&pdev->dev, "%s(), dev name %s 932 dev_dbg(&pdev->dev, "%s(), dev name %s\n",
929 __func__, dev_name(&pdev->dev) 933 __func__, dev_name(&pdev->dev));
930 934
931 priv = devm_kzalloc(&pdev->dev, sizeof 935 priv = devm_kzalloc(&pdev->dev, sizeof(struct mt6359_accdet),
932 GFP_KERNEL); 936 GFP_KERNEL);
933 if (!priv) 937 if (!priv)
934 return -ENOMEM; 938 return -ENOMEM;
935 939
936 priv->data = devm_kzalloc(&pdev->dev, 940 priv->data = devm_kzalloc(&pdev->dev, sizeof(struct dts_data),
937 GFP_KERNEL); 941 GFP_KERNEL);
938 if (!priv->data) 942 if (!priv->data)
939 return -ENOMEM; 943 return -ENOMEM;
940 944
941 priv->data->pwm_deb = devm_kzalloc(&pd 945 priv->data->pwm_deb = devm_kzalloc(&pdev->dev,
942 siz 946 sizeof(struct pwm_deb_settings),
943 GFP 947 GFP_KERNEL);
944 if (!priv->data->pwm_deb) 948 if (!priv->data->pwm_deb)
945 return -ENOMEM; 949 return -ENOMEM;
946 950
947 priv->regmap = mt6397->regmap; 951 priv->regmap = mt6397->regmap;
948 if (IS_ERR(priv->regmap)) { 952 if (IS_ERR(priv->regmap)) {
949 ret = PTR_ERR(priv->regmap); 953 ret = PTR_ERR(priv->regmap);
950 dev_err(&pdev->dev, "Failed to 954 dev_err(&pdev->dev, "Failed to allocate register map: %d\n",
951 ret); 955 ret);
952 return ret; 956 return ret;
953 } 957 }
954 priv->dev = &pdev->dev; 958 priv->dev = &pdev->dev;
955 959
956 ret = mt6359_accdet_parse_dt(priv); 960 ret = mt6359_accdet_parse_dt(priv);
957 if (ret) { 961 if (ret) {
958 dev_err(&pdev->dev, "Failed to 962 dev_err(&pdev->dev, "Failed to parse dts\n");
959 return ret; 963 return ret;
960 } 964 }
961 mutex_init(&priv->res_lock); 965 mutex_init(&priv->res_lock);
962 966
963 priv->accdet_irq = platform_get_irq(pd 967 priv->accdet_irq = platform_get_irq(pdev, 0);
964 if (priv->accdet_irq >= 0) { 968 if (priv->accdet_irq >= 0) {
965 ret = devm_request_threaded_ir 969 ret = devm_request_threaded_irq(&pdev->dev, priv->accdet_irq,
966 970 NULL, mt6359_accdet_irq,
967 971 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
968 972 "ACCDET_IRQ", priv);
969 if (ret) { 973 if (ret) {
970 dev_err(&pdev->dev, 974 dev_err(&pdev->dev,
971 "Failed to req 975 "Failed to request IRQ: (%d)\n", ret);
972 return ret; 976 return ret;
973 } 977 }
974 } 978 }
975 979
976 if (priv->caps & ACCDET_PMIC_EINT0) { 980 if (priv->caps & ACCDET_PMIC_EINT0) {
977 priv->accdet_eint0 = platform_ 981 priv->accdet_eint0 = platform_get_irq(pdev, 1);
978 if (priv->accdet_eint0 >= 0) { 982 if (priv->accdet_eint0 >= 0) {
979 ret = devm_request_thr 983 ret = devm_request_threaded_irq(&pdev->dev,
980 984 priv->accdet_eint0,
981 985 NULL, mt6359_accdet_irq,
982 986 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
983 987 "ACCDET_EINT0", priv);
984 if (ret) { 988 if (ret) {
985 dev_err(&pdev- 989 dev_err(&pdev->dev,
986 "Faile 990 "Failed to request eint0 IRQ (%d)\n",
987 ret); 991 ret);
988 return ret; 992 return ret;
989 } 993 }
990 } 994 }
991 } else if (priv->caps & ACCDET_PMIC_EI 995 } else if (priv->caps & ACCDET_PMIC_EINT1) {
992 priv->accdet_eint1 = platform_ 996 priv->accdet_eint1 = platform_get_irq(pdev, 2);
993 if (priv->accdet_eint1 >= 0) { 997 if (priv->accdet_eint1 >= 0) {
994 ret = devm_request_thr 998 ret = devm_request_threaded_irq(&pdev->dev,
995 999 priv->accdet_eint1,
996 1000 NULL, mt6359_accdet_irq,
997 1001 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
998 1002 "ACCDET_EINT1", priv);
999 if (ret) { 1003 if (ret) {
1000 dev_err(&pdev 1004 dev_err(&pdev->dev,
1001 "Fail 1005 "Failed to request eint1 IRQ (%d)\n",
1002 ret); 1006 ret);
1003 return ret; 1007 return ret;
1004 } 1008 }
1005 } 1009 }
1006 } 1010 }
1007 1011
1008 priv->accdet_workqueue = create_singl 1012 priv->accdet_workqueue = create_singlethread_workqueue("accdet");
1009 INIT_WORK(&priv->accdet_work, mt6359_ 1013 INIT_WORK(&priv->accdet_work, mt6359_accdet_work);
1010 if (!priv->accdet_workqueue) { 1014 if (!priv->accdet_workqueue) {
1011 dev_err(&pdev->dev, "Failed t 1015 dev_err(&pdev->dev, "Failed to create accdet workqueue\n");
1012 ret = -1; 1016 ret = -1;
1013 goto err_accdet_wq; 1017 goto err_accdet_wq;
1014 } 1018 }
1015 1019
1016 priv->jd_workqueue = create_singlethr 1020 priv->jd_workqueue = create_singlethread_workqueue("mt6359_accdet_jd");
1017 INIT_WORK(&priv->jd_work, mt6359_accd 1021 INIT_WORK(&priv->jd_work, mt6359_accdet_jd_work);
1018 if (!priv->jd_workqueue) { 1022 if (!priv->jd_workqueue) {
1019 dev_err(&pdev->dev, "Failed t 1023 dev_err(&pdev->dev, "Failed to create jack detect workqueue\n");
1020 ret = -1; 1024 ret = -1;
1021 goto err_eint_wq; 1025 goto err_eint_wq;
1022 } 1026 }
1023 1027
1024 platform_set_drvdata(pdev, priv); 1028 platform_set_drvdata(pdev, priv);
1025 ret = devm_snd_soc_register_component 1029 ret = devm_snd_soc_register_component(&pdev->dev,
1026 1030 &mt6359_accdet_soc_driver,
1027 1031 NULL, 0);
1028 if (ret) { 1032 if (ret) {
1029 dev_err(&pdev->dev, "Failed t 1033 dev_err(&pdev->dev, "Failed to register component\n");
1030 return ret; 1034 return ret;
1031 } 1035 }
1032 1036
1033 priv->jd_sts = M_PLUG_OUT; 1037 priv->jd_sts = M_PLUG_OUT;
1034 priv->jack_type = 0; 1038 priv->jack_type = 0;
1035 priv->btn_type = 0; 1039 priv->btn_type = 0;
1036 priv->accdet_status = 0x3; 1040 priv->accdet_status = 0x3;
1037 mt6359_accdet_init(priv); 1041 mt6359_accdet_init(priv);
1038 1042
1039 mt6359_accdet_jack_report(priv); 1043 mt6359_accdet_jack_report(priv);
1040 1044
1041 return 0; 1045 return 0;
1042 1046
1043 err_eint_wq: 1047 err_eint_wq:
1044 destroy_workqueue(priv->accdet_workqu 1048 destroy_workqueue(priv->accdet_workqueue);
1045 err_accdet_wq: 1049 err_accdet_wq:
1046 dev_err(&pdev->dev, "%s error. now ex 1050 dev_err(&pdev->dev, "%s error. now exit.!\n", __func__);
1047 return ret; 1051 return ret;
1048 } 1052 }
1049 1053
1050 static struct platform_driver mt6359_accdet_d 1054 static struct platform_driver mt6359_accdet_driver = {
1051 .driver = { 1055 .driver = {
1052 .name = "pmic-codec-accdet", 1056 .name = "pmic-codec-accdet",
1053 }, 1057 },
1054 .probe = mt6359_accdet_probe, 1058 .probe = mt6359_accdet_probe,
1055 }; 1059 };
1056 1060
1057 module_platform_driver(mt6359_accdet_driver) 1061 module_platform_driver(mt6359_accdet_driver)
1058 1062
1059 /* Module information */ 1063 /* Module information */
1060 MODULE_DESCRIPTION("MT6359 ALSA SoC codec jac 1064 MODULE_DESCRIPTION("MT6359 ALSA SoC codec jack driver");
1061 MODULE_AUTHOR("Argus Lin <argus.lin@mediatek. 1065 MODULE_AUTHOR("Argus Lin <argus.lin@mediatek.com>");
1062 MODULE_LICENSE("GPL v2"); 1066 MODULE_LICENSE("GPL v2");
1063 1067
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