1 /* SPDX-License-Identifier: GPL-2.0-only */ <<
2 /* 1 /*
3 * Driver for the PCM512x CODECs 2 * Driver for the PCM512x CODECs
4 * 3 *
5 * Author: Mark Brown <broonie@kernel.org 4 * Author: Mark Brown <broonie@kernel.org>
6 * Copyright 2014 Linaro Ltd 5 * Copyright 2014 Linaro Ltd
>> 6 *
>> 7 * This program is free software; you can redistribute it and/or
>> 8 * modify it under the terms of the GNU General Public License
>> 9 * version 2 as published by the Free Software Foundation.
>> 10 *
>> 11 * This program is distributed in the hope that it will be useful, but
>> 12 * WITHOUT ANY WARRANTY; without even the implied warranty of
>> 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
>> 14 * General Public License for more details.
7 */ 15 */
8 16
9 #ifndef _SND_SOC_PCM512X 17 #ifndef _SND_SOC_PCM512X
10 #define _SND_SOC_PCM512X 18 #define _SND_SOC_PCM512X
11 19
12 #include <linux/pm.h> 20 #include <linux/pm.h>
13 #include <linux/regmap.h> 21 #include <linux/regmap.h>
14 22
15 #define PCM512x_VIRT_BASE 0x100 23 #define PCM512x_VIRT_BASE 0x100
16 #define PCM512x_PAGE_LEN 0x100 24 #define PCM512x_PAGE_LEN 0x100
17 #define PCM512x_PAGE_BASE(n) (PCM512x_VIRT_BA 25 #define PCM512x_PAGE_BASE(n) (PCM512x_VIRT_BASE + (PCM512x_PAGE_LEN * n))
18 26
19 #define PCM512x_PAGE 0 27 #define PCM512x_PAGE 0
20 28
21 #define PCM512x_RESET (PCM512x_PAG 29 #define PCM512x_RESET (PCM512x_PAGE_BASE(0) + 1)
22 #define PCM512x_POWER (PCM512x_PAG 30 #define PCM512x_POWER (PCM512x_PAGE_BASE(0) + 2)
23 #define PCM512x_MUTE (PCM512x_PAG 31 #define PCM512x_MUTE (PCM512x_PAGE_BASE(0) + 3)
24 #define PCM512x_PLL_EN (PCM512x_PAG 32 #define PCM512x_PLL_EN (PCM512x_PAGE_BASE(0) + 4)
25 #define PCM512x_SPI_MISO_FUNCTION (PCM512x_PAG 33 #define PCM512x_SPI_MISO_FUNCTION (PCM512x_PAGE_BASE(0) + 6)
26 #define PCM512x_DSP (PCM512x_PAG 34 #define PCM512x_DSP (PCM512x_PAGE_BASE(0) + 7)
27 #define PCM512x_GPIO_EN (PCM512x_PAG 35 #define PCM512x_GPIO_EN (PCM512x_PAGE_BASE(0) + 8)
28 #define PCM512x_BCLK_LRCLK_CFG (PCM512x_PAG 36 #define PCM512x_BCLK_LRCLK_CFG (PCM512x_PAGE_BASE(0) + 9)
29 #define PCM512x_DSP_GPIO_INPUT (PCM512x_PAG 37 #define PCM512x_DSP_GPIO_INPUT (PCM512x_PAGE_BASE(0) + 10)
30 #define PCM512x_MASTER_MODE (PCM512x_PAG 38 #define PCM512x_MASTER_MODE (PCM512x_PAGE_BASE(0) + 12)
31 #define PCM512x_PLL_REF (PCM512x_PAG 39 #define PCM512x_PLL_REF (PCM512x_PAGE_BASE(0) + 13)
32 #define PCM512x_DAC_REF (PCM512x_PAG 40 #define PCM512x_DAC_REF (PCM512x_PAGE_BASE(0) + 14)
33 #define PCM512x_GPIO_DACIN (PCM512x_PAG 41 #define PCM512x_GPIO_DACIN (PCM512x_PAGE_BASE(0) + 16)
34 #define PCM512x_GPIO_PLLIN (PCM512x_PAG 42 #define PCM512x_GPIO_PLLIN (PCM512x_PAGE_BASE(0) + 18)
35 #define PCM512x_SYNCHRONIZE (PCM512x_PAG 43 #define PCM512x_SYNCHRONIZE (PCM512x_PAGE_BASE(0) + 19)
36 #define PCM512x_PLL_COEFF_0 (PCM512x_PAG 44 #define PCM512x_PLL_COEFF_0 (PCM512x_PAGE_BASE(0) + 20)
37 #define PCM512x_PLL_COEFF_1 (PCM512x_PAG 45 #define PCM512x_PLL_COEFF_1 (PCM512x_PAGE_BASE(0) + 21)
38 #define PCM512x_PLL_COEFF_2 (PCM512x_PAG 46 #define PCM512x_PLL_COEFF_2 (PCM512x_PAGE_BASE(0) + 22)
39 #define PCM512x_PLL_COEFF_3 (PCM512x_PAG 47 #define PCM512x_PLL_COEFF_3 (PCM512x_PAGE_BASE(0) + 23)
40 #define PCM512x_PLL_COEFF_4 (PCM512x_PAG 48 #define PCM512x_PLL_COEFF_4 (PCM512x_PAGE_BASE(0) + 24)
41 #define PCM512x_DSP_CLKDIV (PCM512x_PAG 49 #define PCM512x_DSP_CLKDIV (PCM512x_PAGE_BASE(0) + 27)
42 #define PCM512x_DAC_CLKDIV (PCM512x_PAG 50 #define PCM512x_DAC_CLKDIV (PCM512x_PAGE_BASE(0) + 28)
43 #define PCM512x_NCP_CLKDIV (PCM512x_PAG 51 #define PCM512x_NCP_CLKDIV (PCM512x_PAGE_BASE(0) + 29)
44 #define PCM512x_OSR_CLKDIV (PCM512x_PAG 52 #define PCM512x_OSR_CLKDIV (PCM512x_PAGE_BASE(0) + 30)
45 #define PCM512x_MASTER_CLKDIV_1 (PCM512x_PAG 53 #define PCM512x_MASTER_CLKDIV_1 (PCM512x_PAGE_BASE(0) + 32)
46 #define PCM512x_MASTER_CLKDIV_2 (PCM512x_PAG 54 #define PCM512x_MASTER_CLKDIV_2 (PCM512x_PAGE_BASE(0) + 33)
47 #define PCM512x_FS_SPEED_MODE (PCM512x_PAG 55 #define PCM512x_FS_SPEED_MODE (PCM512x_PAGE_BASE(0) + 34)
48 #define PCM512x_IDAC_1 (PCM512x_PAG 56 #define PCM512x_IDAC_1 (PCM512x_PAGE_BASE(0) + 35)
49 #define PCM512x_IDAC_2 (PCM512x_PAG 57 #define PCM512x_IDAC_2 (PCM512x_PAGE_BASE(0) + 36)
50 #define PCM512x_ERROR_DETECT (PCM512x_PAG 58 #define PCM512x_ERROR_DETECT (PCM512x_PAGE_BASE(0) + 37)
51 #define PCM512x_I2S_1 (PCM512x_PAG 59 #define PCM512x_I2S_1 (PCM512x_PAGE_BASE(0) + 40)
52 #define PCM512x_I2S_2 (PCM512x_PAG 60 #define PCM512x_I2S_2 (PCM512x_PAGE_BASE(0) + 41)
53 #define PCM512x_DAC_ROUTING (PCM512x_PAG 61 #define PCM512x_DAC_ROUTING (PCM512x_PAGE_BASE(0) + 42)
54 #define PCM512x_DSP_PROGRAM (PCM512x_PAG 62 #define PCM512x_DSP_PROGRAM (PCM512x_PAGE_BASE(0) + 43)
55 #define PCM512x_CLKDET (PCM512x_PAG 63 #define PCM512x_CLKDET (PCM512x_PAGE_BASE(0) + 44)
56 #define PCM512x_AUTO_MUTE (PCM512x_PAG 64 #define PCM512x_AUTO_MUTE (PCM512x_PAGE_BASE(0) + 59)
57 #define PCM512x_DIGITAL_VOLUME_1 (PCM512x_PAG 65 #define PCM512x_DIGITAL_VOLUME_1 (PCM512x_PAGE_BASE(0) + 60)
58 #define PCM512x_DIGITAL_VOLUME_2 (PCM512x_PAG 66 #define PCM512x_DIGITAL_VOLUME_2 (PCM512x_PAGE_BASE(0) + 61)
59 #define PCM512x_DIGITAL_VOLUME_3 (PCM512x_PAG 67 #define PCM512x_DIGITAL_VOLUME_3 (PCM512x_PAGE_BASE(0) + 62)
60 #define PCM512x_DIGITAL_MUTE_1 (PCM512x_PAG 68 #define PCM512x_DIGITAL_MUTE_1 (PCM512x_PAGE_BASE(0) + 63)
61 #define PCM512x_DIGITAL_MUTE_2 (PCM512x_PAG 69 #define PCM512x_DIGITAL_MUTE_2 (PCM512x_PAGE_BASE(0) + 64)
62 #define PCM512x_DIGITAL_MUTE_3 (PCM512x_PAG 70 #define PCM512x_DIGITAL_MUTE_3 (PCM512x_PAGE_BASE(0) + 65)
63 #define PCM512x_GPIO_OUTPUT_1 (PCM512x_PAG 71 #define PCM512x_GPIO_OUTPUT_1 (PCM512x_PAGE_BASE(0) + 80)
64 #define PCM512x_GPIO_OUTPUT_2 (PCM512x_PAG 72 #define PCM512x_GPIO_OUTPUT_2 (PCM512x_PAGE_BASE(0) + 81)
65 #define PCM512x_GPIO_OUTPUT_3 (PCM512x_PAG 73 #define PCM512x_GPIO_OUTPUT_3 (PCM512x_PAGE_BASE(0) + 82)
66 #define PCM512x_GPIO_OUTPUT_4 (PCM512x_PAG 74 #define PCM512x_GPIO_OUTPUT_4 (PCM512x_PAGE_BASE(0) + 83)
67 #define PCM512x_GPIO_OUTPUT_5 (PCM512x_PAG 75 #define PCM512x_GPIO_OUTPUT_5 (PCM512x_PAGE_BASE(0) + 84)
68 #define PCM512x_GPIO_OUTPUT_6 (PCM512x_PAG 76 #define PCM512x_GPIO_OUTPUT_6 (PCM512x_PAGE_BASE(0) + 85)
69 #define PCM512x_GPIO_CONTROL_1 (PCM512x_PAG 77 #define PCM512x_GPIO_CONTROL_1 (PCM512x_PAGE_BASE(0) + 86)
70 #define PCM512x_GPIO_CONTROL_2 (PCM512x_PAG 78 #define PCM512x_GPIO_CONTROL_2 (PCM512x_PAGE_BASE(0) + 87)
71 #define PCM512x_OVERFLOW (PCM512x_PAG 79 #define PCM512x_OVERFLOW (PCM512x_PAGE_BASE(0) + 90)
72 #define PCM512x_RATE_DET_1 (PCM512x_PAG 80 #define PCM512x_RATE_DET_1 (PCM512x_PAGE_BASE(0) + 91)
73 #define PCM512x_RATE_DET_2 (PCM512x_PAG 81 #define PCM512x_RATE_DET_2 (PCM512x_PAGE_BASE(0) + 92)
74 #define PCM512x_RATE_DET_3 (PCM512x_PAG 82 #define PCM512x_RATE_DET_3 (PCM512x_PAGE_BASE(0) + 93)
75 #define PCM512x_RATE_DET_4 (PCM512x_PAG 83 #define PCM512x_RATE_DET_4 (PCM512x_PAGE_BASE(0) + 94)
76 #define PCM512x_CLOCK_STATUS (PCM512x_PAG 84 #define PCM512x_CLOCK_STATUS (PCM512x_PAGE_BASE(0) + 95)
77 #define PCM512x_ANALOG_MUTE_DET (PCM512x_PAG 85 #define PCM512x_ANALOG_MUTE_DET (PCM512x_PAGE_BASE(0) + 108)
78 #define PCM512x_GPIN (PCM512x_PAG 86 #define PCM512x_GPIN (PCM512x_PAGE_BASE(0) + 119)
79 #define PCM512x_DIGITAL_MUTE_DET (PCM512x_PAG 87 #define PCM512x_DIGITAL_MUTE_DET (PCM512x_PAGE_BASE(0) + 120)
80 88
81 #define PCM512x_OUTPUT_AMPLITUDE (PCM512x_PAG 89 #define PCM512x_OUTPUT_AMPLITUDE (PCM512x_PAGE_BASE(1) + 1)
82 #define PCM512x_ANALOG_GAIN_CTRL (PCM512x_PAG 90 #define PCM512x_ANALOG_GAIN_CTRL (PCM512x_PAGE_BASE(1) + 2)
83 #define PCM512x_UNDERVOLTAGE_PROT (PCM512x_PAG 91 #define PCM512x_UNDERVOLTAGE_PROT (PCM512x_PAGE_BASE(1) + 5)
84 #define PCM512x_ANALOG_MUTE_CTRL (PCM512x_PAG 92 #define PCM512x_ANALOG_MUTE_CTRL (PCM512x_PAGE_BASE(1) + 6)
85 #define PCM512x_ANALOG_GAIN_BOOST (PCM512x_PAG 93 #define PCM512x_ANALOG_GAIN_BOOST (PCM512x_PAGE_BASE(1) + 7)
86 #define PCM512x_VCOM_CTRL_1 (PCM512x_PAG 94 #define PCM512x_VCOM_CTRL_1 (PCM512x_PAGE_BASE(1) + 8)
87 #define PCM512x_VCOM_CTRL_2 (PCM512x_PAG 95 #define PCM512x_VCOM_CTRL_2 (PCM512x_PAGE_BASE(1) + 9)
88 96
89 #define PCM512x_CRAM_CTRL (PCM512x_PAG 97 #define PCM512x_CRAM_CTRL (PCM512x_PAGE_BASE(44) + 1)
90 98
91 #define PCM512x_FLEX_A (PCM512x_PAG 99 #define PCM512x_FLEX_A (PCM512x_PAGE_BASE(253) + 63)
92 #define PCM512x_FLEX_B (PCM512x_PAG 100 #define PCM512x_FLEX_B (PCM512x_PAGE_BASE(253) + 64)
93 101
94 #define PCM512x_MAX_REGISTER (PCM512x_PAG 102 #define PCM512x_MAX_REGISTER (PCM512x_PAGE_BASE(253) + 64)
95 103
96 /* Page 0, Register 1 - reset */ 104 /* Page 0, Register 1 - reset */
97 #define PCM512x_RSTR (1 << 0) 105 #define PCM512x_RSTR (1 << 0)
98 #define PCM512x_RSTM (1 << 4) 106 #define PCM512x_RSTM (1 << 4)
99 107
100 /* Page 0, Register 2 - power */ 108 /* Page 0, Register 2 - power */
101 #define PCM512x_RQPD (1 << 0) 109 #define PCM512x_RQPD (1 << 0)
102 #define PCM512x_RQPD_SHIFT 0 110 #define PCM512x_RQPD_SHIFT 0
103 #define PCM512x_RQST (1 << 4) 111 #define PCM512x_RQST (1 << 4)
104 #define PCM512x_RQST_SHIFT 4 112 #define PCM512x_RQST_SHIFT 4
105 113
106 /* Page 0, Register 3 - mute */ 114 /* Page 0, Register 3 - mute */
107 #define PCM512x_RQMR (1 << 0) 115 #define PCM512x_RQMR (1 << 0)
108 #define PCM512x_RQMR_SHIFT 0 116 #define PCM512x_RQMR_SHIFT 0
109 #define PCM512x_RQML (1 << 4) 117 #define PCM512x_RQML (1 << 4)
110 #define PCM512x_RQML_SHIFT 4 118 #define PCM512x_RQML_SHIFT 4
111 119
112 /* Page 0, Register 4 - PLL */ 120 /* Page 0, Register 4 - PLL */
113 #define PCM512x_PLLE (1 << 0) 121 #define PCM512x_PLLE (1 << 0)
114 #define PCM512x_PLLE_SHIFT 0 122 #define PCM512x_PLLE_SHIFT 0
115 #define PCM512x_PLCK (1 << 4) 123 #define PCM512x_PLCK (1 << 4)
116 #define PCM512x_PLCK_SHIFT 4 124 #define PCM512x_PLCK_SHIFT 4
117 125
118 /* Page 0, Register 7 - DSP */ 126 /* Page 0, Register 7 - DSP */
119 #define PCM512x_SDSL (1 << 0) 127 #define PCM512x_SDSL (1 << 0)
120 #define PCM512x_SDSL_SHIFT 0 128 #define PCM512x_SDSL_SHIFT 0
121 #define PCM512x_DEMP (1 << 4) 129 #define PCM512x_DEMP (1 << 4)
122 #define PCM512x_DEMP_SHIFT 4 130 #define PCM512x_DEMP_SHIFT 4
123 131
124 /* Page 0, Register 8 - GPIO output enable */ 132 /* Page 0, Register 8 - GPIO output enable */
125 #define PCM512x_G1OE (1 << 0) 133 #define PCM512x_G1OE (1 << 0)
126 #define PCM512x_G2OE (1 << 1) 134 #define PCM512x_G2OE (1 << 1)
127 #define PCM512x_G3OE (1 << 2) 135 #define PCM512x_G3OE (1 << 2)
128 #define PCM512x_G4OE (1 << 3) 136 #define PCM512x_G4OE (1 << 3)
129 #define PCM512x_G5OE (1 << 4) 137 #define PCM512x_G5OE (1 << 4)
130 #define PCM512x_G6OE (1 << 5) 138 #define PCM512x_G6OE (1 << 5)
131 139
132 /* Page 0, Register 9 - BCK, LRCLK configurati 140 /* Page 0, Register 9 - BCK, LRCLK configuration */
133 #define PCM512x_LRKO (1 << 0) 141 #define PCM512x_LRKO (1 << 0)
134 #define PCM512x_LRKO_SHIFT 0 142 #define PCM512x_LRKO_SHIFT 0
135 #define PCM512x_BCKO (1 << 4) 143 #define PCM512x_BCKO (1 << 4)
136 #define PCM512x_BCKO_SHIFT 4 144 #define PCM512x_BCKO_SHIFT 4
137 #define PCM512x_BCKP (1 << 5) 145 #define PCM512x_BCKP (1 << 5)
138 #define PCM512x_BCKP_SHIFT 5 146 #define PCM512x_BCKP_SHIFT 5
139 147
140 /* Page 0, Register 12 - Master mode BCK, LRCL 148 /* Page 0, Register 12 - Master mode BCK, LRCLK reset */
141 #define PCM512x_RLRK (1 << 0) 149 #define PCM512x_RLRK (1 << 0)
142 #define PCM512x_RLRK_SHIFT 0 150 #define PCM512x_RLRK_SHIFT 0
143 #define PCM512x_RBCK (1 << 1) 151 #define PCM512x_RBCK (1 << 1)
144 #define PCM512x_RBCK_SHIFT 1 152 #define PCM512x_RBCK_SHIFT 1
145 153
146 /* Page 0, Register 13 - PLL reference */ 154 /* Page 0, Register 13 - PLL reference */
147 #define PCM512x_SREF (7 << 4) 155 #define PCM512x_SREF (7 << 4)
148 #define PCM512x_SREF_SHIFT 4 156 #define PCM512x_SREF_SHIFT 4
149 #define PCM512x_SREF_SCK (0 << 4) 157 #define PCM512x_SREF_SCK (0 << 4)
150 #define PCM512x_SREF_BCK (1 << 4) 158 #define PCM512x_SREF_BCK (1 << 4)
151 #define PCM512x_SREF_GPIO (3 << 4) 159 #define PCM512x_SREF_GPIO (3 << 4)
152 160
153 /* Page 0, Register 14 - DAC reference */ 161 /* Page 0, Register 14 - DAC reference */
154 #define PCM512x_SDAC (7 << 4) 162 #define PCM512x_SDAC (7 << 4)
155 #define PCM512x_SDAC_SHIFT 4 163 #define PCM512x_SDAC_SHIFT 4
156 #define PCM512x_SDAC_MCK (0 << 4) 164 #define PCM512x_SDAC_MCK (0 << 4)
157 #define PCM512x_SDAC_PLL (1 << 4) 165 #define PCM512x_SDAC_PLL (1 << 4)
158 #define PCM512x_SDAC_SCK (3 << 4) 166 #define PCM512x_SDAC_SCK (3 << 4)
159 #define PCM512x_SDAC_BCK (4 << 4) 167 #define PCM512x_SDAC_BCK (4 << 4)
160 #define PCM512x_SDAC_GPIO (5 << 4) 168 #define PCM512x_SDAC_GPIO (5 << 4)
161 169
162 /* Page 0, Register 16, 18 - GPIO source for D 170 /* Page 0, Register 16, 18 - GPIO source for DAC, PLL */
163 #define PCM512x_GREF (7 << 0) 171 #define PCM512x_GREF (7 << 0)
164 #define PCM512x_GREF_SHIFT 0 172 #define PCM512x_GREF_SHIFT 0
165 #define PCM512x_GREF_GPIO1 (0 << 0) 173 #define PCM512x_GREF_GPIO1 (0 << 0)
166 #define PCM512x_GREF_GPIO2 (1 << 0) 174 #define PCM512x_GREF_GPIO2 (1 << 0)
167 #define PCM512x_GREF_GPIO3 (2 << 0) 175 #define PCM512x_GREF_GPIO3 (2 << 0)
168 #define PCM512x_GREF_GPIO4 (3 << 0) 176 #define PCM512x_GREF_GPIO4 (3 << 0)
169 #define PCM512x_GREF_GPIO5 (4 << 0) 177 #define PCM512x_GREF_GPIO5 (4 << 0)
170 #define PCM512x_GREF_GPIO6 (5 << 0) 178 #define PCM512x_GREF_GPIO6 (5 << 0)
171 179
172 /* Page 0, Register 19 - synchronize */ 180 /* Page 0, Register 19 - synchronize */
173 #define PCM512x_RQSY (1 << 0) 181 #define PCM512x_RQSY (1 << 0)
174 #define PCM512x_RQSY_RESUME (0 << 0) 182 #define PCM512x_RQSY_RESUME (0 << 0)
175 #define PCM512x_RQSY_HALT (1 << 0) 183 #define PCM512x_RQSY_HALT (1 << 0)
176 184
177 /* Page 0, Register 34 - fs speed mode */ 185 /* Page 0, Register 34 - fs speed mode */
178 #define PCM512x_FSSP (3 << 0) 186 #define PCM512x_FSSP (3 << 0)
179 #define PCM512x_FSSP_SHIFT 0 187 #define PCM512x_FSSP_SHIFT 0
180 #define PCM512x_FSSP_48KHZ (0 << 0) 188 #define PCM512x_FSSP_48KHZ (0 << 0)
181 #define PCM512x_FSSP_96KHZ (1 << 0) 189 #define PCM512x_FSSP_96KHZ (1 << 0)
182 #define PCM512x_FSSP_192KHZ (2 << 0) 190 #define PCM512x_FSSP_192KHZ (2 << 0)
183 #define PCM512x_FSSP_384KHZ (3 << 0) 191 #define PCM512x_FSSP_384KHZ (3 << 0)
184 192
185 /* Page 0, Register 37 - Error detection */ 193 /* Page 0, Register 37 - Error detection */
186 #define PCM512x_IPLK (1 << 0) 194 #define PCM512x_IPLK (1 << 0)
187 #define PCM512x_DCAS (1 << 1) 195 #define PCM512x_DCAS (1 << 1)
188 #define PCM512x_IDCM (1 << 2) 196 #define PCM512x_IDCM (1 << 2)
189 #define PCM512x_IDCH (1 << 3) 197 #define PCM512x_IDCH (1 << 3)
190 #define PCM512x_IDSK (1 << 4) 198 #define PCM512x_IDSK (1 << 4)
191 #define PCM512x_IDBK (1 << 5) 199 #define PCM512x_IDBK (1 << 5)
192 #define PCM512x_IDFS (1 << 6) 200 #define PCM512x_IDFS (1 << 6)
193 201
194 /* Page 0, Register 40 - I2S configuration */ 202 /* Page 0, Register 40 - I2S configuration */
195 #define PCM512x_ALEN (3 << 0) 203 #define PCM512x_ALEN (3 << 0)
196 #define PCM512x_ALEN_SHIFT 0 204 #define PCM512x_ALEN_SHIFT 0
197 #define PCM512x_ALEN_16 (0 << 0) 205 #define PCM512x_ALEN_16 (0 << 0)
198 #define PCM512x_ALEN_20 (1 << 0) 206 #define PCM512x_ALEN_20 (1 << 0)
199 #define PCM512x_ALEN_24 (2 << 0) 207 #define PCM512x_ALEN_24 (2 << 0)
200 #define PCM512x_ALEN_32 (3 << 0) 208 #define PCM512x_ALEN_32 (3 << 0)
201 #define PCM512x_AFMT (3 << 4) 209 #define PCM512x_AFMT (3 << 4)
202 #define PCM512x_AFMT_SHIFT 4 210 #define PCM512x_AFMT_SHIFT 4
203 #define PCM512x_AFMT_I2S (0 << 4) 211 #define PCM512x_AFMT_I2S (0 << 4)
204 #define PCM512x_AFMT_DSP (1 << 4) 212 #define PCM512x_AFMT_DSP (1 << 4)
205 #define PCM512x_AFMT_RTJ (2 << 4) 213 #define PCM512x_AFMT_RTJ (2 << 4)
206 #define PCM512x_AFMT_LTJ (3 << 4) 214 #define PCM512x_AFMT_LTJ (3 << 4)
207 215
208 /* Page 0, Register 42 - DAC routing */ 216 /* Page 0, Register 42 - DAC routing */
209 #define PCM512x_AUPR_SHIFT 0 217 #define PCM512x_AUPR_SHIFT 0
210 #define PCM512x_AUPL_SHIFT 4 218 #define PCM512x_AUPL_SHIFT 4
211 219
212 /* Page 0, Register 59 - auto mute */ 220 /* Page 0, Register 59 - auto mute */
213 #define PCM512x_ATMR_SHIFT 0 221 #define PCM512x_ATMR_SHIFT 0
214 #define PCM512x_ATML_SHIFT 4 222 #define PCM512x_ATML_SHIFT 4
215 223
216 /* Page 0, Register 63 - ramp rates */ 224 /* Page 0, Register 63 - ramp rates */
217 #define PCM512x_VNDF_SHIFT 6 225 #define PCM512x_VNDF_SHIFT 6
218 #define PCM512x_VNDS_SHIFT 4 226 #define PCM512x_VNDS_SHIFT 4
219 #define PCM512x_VNUF_SHIFT 2 227 #define PCM512x_VNUF_SHIFT 2
220 #define PCM512x_VNUS_SHIFT 0 228 #define PCM512x_VNUS_SHIFT 0
221 229
222 /* Page 0, Register 64 - emergency ramp rates 230 /* Page 0, Register 64 - emergency ramp rates */
223 #define PCM512x_VEDF_SHIFT 6 231 #define PCM512x_VEDF_SHIFT 6
224 #define PCM512x_VEDS_SHIFT 4 232 #define PCM512x_VEDS_SHIFT 4
225 233
226 /* Page 0, Register 65 - Digital mute enables 234 /* Page 0, Register 65 - Digital mute enables */
227 #define PCM512x_ACTL_SHIFT 2 235 #define PCM512x_ACTL_SHIFT 2
228 #define PCM512x_AMLE_SHIFT 1 236 #define PCM512x_AMLE_SHIFT 1
229 #define PCM512x_AMRE_SHIFT 0 237 #define PCM512x_AMRE_SHIFT 0
230 238
231 /* Page 0, Register 80-85, GPIO output selecti 239 /* Page 0, Register 80-85, GPIO output selection */
232 #define PCM512x_GxSL (31 << 0) 240 #define PCM512x_GxSL (31 << 0)
233 #define PCM512x_GxSL_SHIFT 0 241 #define PCM512x_GxSL_SHIFT 0
234 #define PCM512x_GxSL_OFF (0 << 0) 242 #define PCM512x_GxSL_OFF (0 << 0)
235 #define PCM512x_GxSL_DSP (1 << 0) 243 #define PCM512x_GxSL_DSP (1 << 0)
236 #define PCM512x_GxSL_REG (2 << 0) 244 #define PCM512x_GxSL_REG (2 << 0)
237 #define PCM512x_GxSL_AMUTB (3 << 0) 245 #define PCM512x_GxSL_AMUTB (3 << 0)
238 #define PCM512x_GxSL_AMUTL (4 << 0) 246 #define PCM512x_GxSL_AMUTL (4 << 0)
239 #define PCM512x_GxSL_AMUTR (5 << 0) 247 #define PCM512x_GxSL_AMUTR (5 << 0)
240 #define PCM512x_GxSL_CLKI (6 << 0) 248 #define PCM512x_GxSL_CLKI (6 << 0)
241 #define PCM512x_GxSL_SDOUT (7 << 0) 249 #define PCM512x_GxSL_SDOUT (7 << 0)
242 #define PCM512x_GxSL_ANMUL (8 << 0) 250 #define PCM512x_GxSL_ANMUL (8 << 0)
243 #define PCM512x_GxSL_ANMUR (9 << 0) 251 #define PCM512x_GxSL_ANMUR (9 << 0)
244 #define PCM512x_GxSL_PLLLK (10 << 0) 252 #define PCM512x_GxSL_PLLLK (10 << 0)
245 #define PCM512x_GxSL_CPCLK (11 << 0) 253 #define PCM512x_GxSL_CPCLK (11 << 0)
246 #define PCM512x_GxSL_UV0_7 (14 << 0) 254 #define PCM512x_GxSL_UV0_7 (14 << 0)
247 #define PCM512x_GxSL_UV0_3 (15 << 0) 255 #define PCM512x_GxSL_UV0_3 (15 << 0)
248 #define PCM512x_GxSL_PLLCK (16 << 0) 256 #define PCM512x_GxSL_PLLCK (16 << 0)
249 257
250 /* Page 1, Register 2 - analog volume control 258 /* Page 1, Register 2 - analog volume control */
251 #define PCM512x_RAGN_SHIFT 0 259 #define PCM512x_RAGN_SHIFT 0
252 #define PCM512x_LAGN_SHIFT 4 260 #define PCM512x_LAGN_SHIFT 4
253 261
254 /* Page 1, Register 7 - analog boost control * 262 /* Page 1, Register 7 - analog boost control */
255 #define PCM512x_AGBR_SHIFT 0 263 #define PCM512x_AGBR_SHIFT 0
256 #define PCM512x_AGBL_SHIFT 4 264 #define PCM512x_AGBL_SHIFT 4
257 265
258 extern const struct dev_pm_ops pcm512x_pm_ops; 266 extern const struct dev_pm_ops pcm512x_pm_ops;
259 extern const struct regmap_config pcm512x_regm 267 extern const struct regmap_config pcm512x_regmap;
260 268
261 int pcm512x_probe(struct device *dev, struct r 269 int pcm512x_probe(struct device *dev, struct regmap *regmap);
262 void pcm512x_remove(struct device *dev); 270 void pcm512x_remove(struct device *dev);
263 271
264 #endif 272 #endif
265 273
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