1 /* SPDX-License-Identifier: GPL-2.0 */ 1
2 //
3 // ALSA SoC Texas Instruments PCM6240 Family A
4 //
5 // Copyright (C) 2022 - 2024 Texas Instruments
6 // https://www.ti.com
7 //
8 // The PCM6240 driver implements a flexible an
9 // algo coefficient setting for one, two, or e
10 // PCM6240 Family Audio chips.
11 //
12 // Author: Shenghao Ding <shenghao-ding@ti.com
13 //
14
15 #ifndef __PCM6240_H__
16 #define __PCM6240_H__
17
18 enum pcm_device {
19 ADC3120,
20 ADC5120,
21 ADC6120,
22 DIX4192,
23 PCM1690,
24 PCM3120,
25 PCM3140,
26 PCM5120,
27 PCM5140,
28 PCM6120,
29 PCM6140,
30 PCM6240,
31 PCM6260,
32 PCM9211,
33 PCMD3140,
34 PCMD3180,
35 PCMD512X,
36 TAA5212,
37 TAA5412,
38 TAD5212,
39 TAD5412,
40 MAX_DEVICE,
41 };
42
43 #define PCMDEV_GENERIC_VOL_CTRL
44 #define PCMDEV_PCM1690_VOL_CTRL
45 #define PCMDEV_PCM1690_FINE_VOL_CTRL
46
47 /* Maximum number of I2C addresses */
48 #define PCMDEVICE_MAX_I2C_DEVICES
49 /* Maximum number defined in REGBIN protocol *
50 #define PCMDEVICE_MAX_REGBIN_DEVICES
51 #define PCMDEVICE_CONFIG_SUM
52 #define PCMDEVICE_BIN_FILENAME_LEN
53
54 #define PCMDEVICE_RATES (SNDRV_PCM_RATE_44100
55 SNDRV_PCM_RATE_48000)
56 #define PCMDEVICE_MAX_CHANNELS
57 #define PCMDEVICE_FORMATS (SNDRV_PCM_FMT
58 SNDRV_PCM_FMTBIT_S20_3LE | \
59 SNDRV_PCM_FMTBIT_S24_3LE | \
60 SNDRV_PCM_FMTBIT_S24_LE | \
61 SNDRV_PCM_FMTBIT_S32_LE)
62
63 /* PAGE Control Register (available in page0 o
64 #define PCMDEVICE_PAGE_SELECT
65 #define PCMDEVICE_REG(page, reg)
66 #define PCMDEVICE_REG_SWRESET
67 #define PCMDEVICE_REG_SWRESET_RESET
68
69 #define ADC5120_REG_CH1_ANALOG_GAIN
70 #define ADC5120_REG_CH1_DIGITAL_GAIN
71 #define ADC5120_REG_CH2_ANALOG_GAIN
72 #define ADC5120_REG_CH2_DIGITAL_GAIN
73
74 #define PCM1690_REG_MODE_CTRL
75 #define PCM1690_REG_MODE_CTRL_DAMS_MSK
76 #define PCM1690_REG_MODE_CTRL_DAMS_FINE_STEP
77 #define PCM1690_REG_MODE_CTRL_DAMS_WIDE_RANGE
78
79 #define PCM1690_REG_CH1_DIGITAL_GAIN
80 #define PCM1690_REG_CH2_DIGITAL_GAIN
81 #define PCM1690_REG_CH3_DIGITAL_GAIN
82 #define PCM1690_REG_CH4_DIGITAL_GAIN
83 #define PCM1690_REG_CH5_DIGITAL_GAIN
84 #define PCM1690_REG_CH6_DIGITAL_GAIN
85 #define PCM1690_REG_CH7_DIGITAL_GAIN
86 #define PCM1690_REG_CH8_DIGITAL_GAIN
87
88 #define PCM6240_REG_CH1_ANALOG_GAIN
89 #define PCM6240_REG_CH1_DIGITAL_GAIN
90 #define PCM6240_REG_CH2_ANALOG_GAIN
91 #define PCM6240_REG_CH2_DIGITAL_GAIN
92 #define PCM6240_REG_CH3_ANALOG_GAIN
93 #define PCM6240_REG_CH3_DIGITAL_GAIN
94 #define PCM6240_REG_CH4_ANALOG_GAIN
95 #define PCM6240_REG_CH4_DIGITAL_GAIN
96
97 #define PCM6260_REG_CH1_ANALOG_GAIN
98 #define PCM6260_REG_CH1_DIGITAL_GAIN
99 #define PCM6260_REG_CH2_ANALOG_GAIN
100 #define PCM6260_REG_CH2_DIGITAL_GAIN
101 #define PCM6260_REG_CH3_ANALOG_GAIN
102 #define PCM6260_REG_CH3_DIGITAL_GAIN
103 #define PCM6260_REG_CH4_ANALOG_GAIN
104 #define PCM6260_REG_CH4_DIGITAL_GAIN
105 #define PCM6260_REG_CH5_ANALOG_GAIN
106 #define PCM6260_REG_CH5_DIGITAL_GAIN
107 #define PCM6260_REG_CH6_ANALOG_GAIN
108 #define PCM6260_REG_CH6_DIGITAL_GAIN
109
110 #define PCM9211_REG_SW_CTRL
111 #define PCM9211_REG_SW_CTRL_MRST_MSK
112 #define PCM9211_REG_SW_CTRL_MRST
113
114 #define PCM9211_REG_CH1_DIGITAL_GAIN
115 #define PCM9211_REG_CH2_DIGITAL_GAIN
116
117 #define PCMD3140_REG_CH1_DIGITAL_GAIN
118 #define PCMD3140_REG_CH2_DIGITAL_GAIN
119 #define PCMD3140_REG_CH3_DIGITAL_GAIN
120 #define PCMD3140_REG_CH4_DIGITAL_GAIN
121
122 #define PCMD3140_REG_CH1_FINE_GAIN
123 #define PCMD3140_REG_CH2_FINE_GAIN
124 #define PCMD3140_REG_CH3_FINE_GAIN
125 #define PCMD3140_REG_CH4_FINE_GAIN
126
127 #define PCMD3180_REG_CH1_DIGITAL_GAIN
128 #define PCMD3180_REG_CH2_DIGITAL_GAIN
129 #define PCMD3180_REG_CH3_DIGITAL_GAIN
130 #define PCMD3180_REG_CH4_DIGITAL_GAIN
131 #define PCMD3180_REG_CH5_DIGITAL_GAIN
132 #define PCMD3180_REG_CH6_DIGITAL_GAIN
133 #define PCMD3180_REG_CH7_DIGITAL_GAIN
134 #define PCMD3180_REG_CH8_DIGITAL_GAIN
135
136 #define PCMD3180_REG_CH1_FINE_GAIN
137 #define PCMD3180_REG_CH2_FINE_GAIN
138 #define PCMD3180_REG_CH3_FINE_GAIN
139 #define PCMD3180_REG_CH4_FINE_GAIN
140 #define PCMD3180_REG_CH5_FINE_GAIN
141 #define PCMD3180_REG_CH6_FINE_GAIN
142 #define PCMD3180_REG_CH7_FINE_GAIN
143 #define PCMD3180_REG_CH8_FINE_GAIN
144
145 #define TAA5412_REG_CH1_DIGITAL_VOLUME
146 #define TAA5412_REG_CH2_DIGITAL_VOLUME
147 #define TAA5412_REG_CH3_DIGITAL_VOLUME
148 #define TAA5412_REG_CH4_DIGITAL_VOLUME
149
150 #define TAA5412_REG_CH1_FINE_GAIN
151 #define TAA5412_REG_CH2_FINE_GAIN
152 #define TAA5412_REG_CH3_FINE_GAIN
153 #define TAA5412_REG_CH4_FINE_GAIN
154
155 #define PCMDEVICE_CMD_SING_W 0x1
156 #define PCMDEVICE_CMD_BURST 0x2
157 #define PCMDEVICE_CMD_DELAY 0x3
158 #define PCMDEVICE_CMD_FIELD_W 0x4
159
160 enum pcmdevice_bin_blk_type {
161 PCMDEVICE_BIN_BLK_COEFF = 1,
162 PCMDEVICE_BIN_BLK_POST_POWER_UP,
163 PCMDEVICE_BIN_BLK_PRE_SHUTDOWN,
164 PCMDEVICE_BIN_BLK_PRE_POWER_UP,
165 PCMDEVICE_BIN_BLK_POST_SHUTDOWN
166 };
167
168 enum pcmdevice_fw_state {
169 PCMDEVICE_FW_LOAD_OK = 0,
170 PCMDEVICE_FW_LOAD_FAILED
171 };
172
173 struct pcmdevice_regbin_hdr {
174 unsigned int img_sz;
175 unsigned int checksum;
176 unsigned int binary_version_num;
177 unsigned int drv_fw_version;
178 unsigned int timestamp;
179 unsigned char plat_type;
180 unsigned char dev_family;
181 unsigned char reserve;
182 unsigned char ndev;
183 unsigned char devs[PCMDEVICE_MAX_REGBI
184 unsigned int nconfig;
185 unsigned int config_size[PCMDEVICE_CON
186 };
187
188 struct pcmdevice_block_data {
189 unsigned char dev_idx;
190 unsigned char block_type;
191 unsigned short yram_checksum;
192 unsigned int block_size;
193 unsigned int n_subblks;
194 unsigned char *regdata;
195 };
196
197 struct pcmdevice_config_info {
198 char cfg_name[64];
199 unsigned int nblocks;
200 unsigned int real_nblocks;
201 unsigned char active_dev;
202 struct pcmdevice_block_data **blk_data
203 };
204
205 struct pcmdevice_regbin {
206 struct pcmdevice_regbin_hdr fw_hdr;
207 int ncfgs;
208 struct pcmdevice_config_info **cfg_inf
209 };
210
211 struct pcmdevice_irqinfo {
212 int gpio;
213 int nmb;
214 };
215
216 struct pcmdevice_priv {
217 struct snd_soc_component *component;
218 struct i2c_client *client;
219 struct device *dev;
220 struct mutex codec_lock;
221 struct gpio_desc *hw_rst;
222 struct regmap *regmap;
223 struct pcmdevice_regbin regbin;
224 struct pcmdevice_irqinfo irq_info;
225 unsigned int addr[PCMDEVICE_MAX_I2C_DE
226 unsigned int chip_id;
227 int cur_conf;
228 int fw_state;
229 int ndev;
230 unsigned char bin_name[PCMDEVICE_BIN_F
231 /* used for kcontrol name */
232 unsigned char upper_dev_name[I2C_NAME_
233 unsigned char dev_name[I2C_NAME_SIZE];
234 };
235
236 /* mixer control */
237 struct pcmdevice_mixer_control {
238 int max;
239 int reg;
240 unsigned int dev_no;
241 unsigned int shift;
242 unsigned int invert;
243 };
244 struct pcmdev_ctrl_info {
245 const unsigned int *gain;
246 const struct pcmdevice_mixer_control *
247 unsigned int ctrl_array_size;
248 snd_kcontrol_get_t *get;
249 snd_kcontrol_put_t *put;
250 int pcmdev_ctrl_name_id;
251 };
252 #endif /* __PCM6240_H__ */
253
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