1 /* SPDX-License-Identifier: GPL-2.0-only */ 1
2 /*
3 * rt1318.h -- Platform data for RT1318
4 *
5 * Copyright 2024 Realtek Semiconductor Corp.
6 */
7 #include <sound/rt1318.h>
8
9 #ifndef __RT1318_H__
10 #define __RT1318_H__
11
12 struct rt1318_priv {
13 struct snd_soc_component *component;
14 struct rt1318_platform_data pdata;
15 struct work_struct cali_work;
16 struct regmap *regmap;
17
18 unsigned int r0_l_integer;
19 unsigned int r0_l_factor;
20 unsigned int r0_r_integer;
21 unsigned int r0_r_factor;
22 int rt1318_init;
23 int rt1318_dvol;
24 int sysclk_src;
25 int sysclk;
26 int lrck;
27 int bclk;
28 int master;
29 int pll_src;
30 int pll_in;
31 int pll_out;
32 };
33
34 #define RT1318_PLL_INP_MAX 40000000
35 #define RT1318_PLL_INP_MIN 256000
36 #define RT1318_PLL_N_MAX 0x1ff
37 #define RT1318_PLL_K_MAX 0x1f
38 #define RT1318_PLL_M_MAX 0x1f
39
40 #define RT1318_LRCLK_192000 192000
41 #define RT1318_LRCLK_96000 96000
42 #define RT1318_LRCLK_48000 48000
43 #define RT1318_LRCLK_44100 44100
44 #define RT1318_LRCLK_16000 16000
45 #define RT1318_DVOL_STEP 383
46
47 #define RT1318_CLK1
48 #define RT1318_CLK2
49 #define RT1318_CLK3
50 #define RT1318_CLK4
51 #define RT1318_CLK5
52 #define RT1318_CLK6
53 #define RT1318_CLK7
54 #define RT1318_PWR_STA1
55 #define RT1318_SPK_VOL_TH
56 #define RT1318_TCON
57 #define RT1318_SRC_TCON
58 #define RT1318_TCON_RELATE
59 #define RT1318_DA_VOL_L_8
60 #define RT1318_DA_VOL_L_1_7
61 #define RT1318_DA_VOL_R_8
62 #define RT1318_DA_VOL_R_1_7
63 #define RT1318_FEEDBACK_PATH
64 #define RT1318_STP_TEMP_L
65 #define RT1318_STP_SEL_L
66 #define RT1318_STP_R0_EN_L
67 #define RT1318_R0_CMP_L_FLAG
68 #define RT1318_PRE_R0_L_24
69 #define RT1318_PRE_R0_L_23_16
70 #define RT1318_PRE_R0_L_15_8
71 #define RT1318_PRE_R0_L_7_0
72 #define RT1318_R0_L_24
73 #define RT1318_R0_L_23_16
74 #define RT1318_R0_L_15_8
75 #define RT1318_R0_L_7_0
76 #define RT1318_STP_SEL_R
77 #define RT1318_STP_R0_EN_R
78 #define RT1318_R0_CMP_R_FLAG
79 #define RT1318_PRE_R0_R_24
80 #define RT1318_PRE_R0_R_23_16
81 #define RT1318_PRE_R0_R_15_8
82 #define RT1318_PRE_R0_R_7_0
83 #define RT1318_R0_R_24
84 #define RT1318_R0_R_23_16
85 #define RT1318_R0_R_15_8
86 #define RT1318_R0_R_7_0
87 #define RT1318_DEV_ID1
88 #define RT1318_DEV_ID2
89 #define RT1318_PLL1_K
90 #define RT1318_PLL1_M
91 #define RT1318_PLL1_N_8
92 #define RT1318_PLL1_N_7_0
93 #define RT1318_SINE_GEN0
94 #define RT1318_TDM_CTRL1
95 #define RT1318_TDM_CTRL2
96 #define RT1318_TDM_CTRL3
97 #define RT1318_TDM_CTRL9
98
99
100 /* Clock-1 (0xC001) */
101 #define RT1318_PLLIN_MASK
102 #define RT1318_PLLIN_BCLK0
103 #define RT1318_PLLIN_BCLK1
104 #define RT1318_PLLIN_RC
105 #define RT1318_PLLIN_MCLK
106 #define RT1318_PLLIN_SDW1
107 #define RT1318_PLLIN_SDW2
108 #define RT1318_PLLIN_SDW3
109 #define RT1318_PLLIN_SDW4
110 #define RT1318_SYSCLK_SEL_MASK
111 #define RT1318_SYSCLK_BCLK
112 #define RT1318_SYSCLK_SDW
113 #define RT1318_SYSCLK_PLL2F
114 #define RT1318_SYSCLK_PLL2B
115 #define RT1318_SYSCLK_MCLK
116 #define RT1318_SYSCLK_RC1
117 #define RT1318_SYSCLK_RC2
118 #define RT1318_SYSCLK_RC3
119 /* Clock-2 (0xC003) */
120 #define RT1318_DIV_AP_MASK
121 #define RT1318_DIV_AP_SFT
122 #define RT1318_DIV_AP_DIV1
123 #define RT1318_DIV_AP_DIV2
124 #define RT1318_DIV_AP_DIV4
125 #define RT1318_DIV_AP_DIV8
126 #define RT1318_DIV_DAMOD_MASK
127 #define RT1318_DIV_DAMOD_SFT
128 #define RT1318_DIV_DAMOD_DIV1
129 #define RT1318_DIV_DAMOD_DIV2
130 #define RT1318_DIV_DAMOD_DIV4
131 #define RT1318_DIV_DAMOD_DIV8
132 /* Clock-3 (0xC004) */
133 #define RT1318_AD_STO1_MASK
134 #define RT1318_AD_STO1_SFT
135 #define RT1318_AD_STO1_DIV1
136 #define RT1318_AD_STO1_DIV2
137 #define RT1318_AD_STO1_DIV4
138 #define RT1318_AD_STO1_DIV8
139 #define RT1318_AD_STO1_DIV16
140 #define RT1318_AD_STO2_MASK
141 #define RT1318_AD_STO2_SFT
142 #define RT1318_AD_STO2_DIV1
143 #define RT1318_AD_STO2_DIV2
144 #define RT1318_AD_STO2_DIV4
145 #define RT1318_AD_STO2_DIV8
146 #define RT1318_AD_STO2_DIV16
147 #define RT1318_AD_STO2_SFT
148 /* Clock-4 (0xC005) */
149 #define RT1318_AD_ANA_STO1_MASK
150 #define RT1318_AD_ANA_STO1_SFT
151 #define RT1318_AD_ANA_STO1_DIV1
152 #define RT1318_AD_ANA_STO1_DIV2
153 #define RT1318_AD_ANA_STO1_DIV4
154 #define RT1318_AD_ANA_STO1_DIV8
155 #define RT1318_AD_ANA_STO1_DIV16
156 #define RT1318_AD_ANA_STO2_MASK
157 #define RT1318_AD_ANA_STO2_DIV1
158 #define RT1318_AD_ANA_STO2_DIV2
159 #define RT1318_AD_ANA_STO2_DIV4
160 #define RT1318_AD_ANA_STO2_DIV8
161 #define RT1318_AD_ANA_STO2_DIV16
162 #define RT1318_AD_ANA_STO2_SFT
163 /* Clock-5 (0xC006) */
164 #define RT1318_DIV_FIFO_IN_MASK
165 #define RT1318_DIV_FIFO_IN_SFT
166 #define RT1318_DIV_FIFO_IN_DIV1
167 #define RT1318_DIV_FIFO_IN_DIV2
168 #define RT1318_DIV_FIFO_IN_DIV4
169 #define RT1318_DIV_FIFO_IN_DIV8
170 #define RT1318_DIV_FIFO_OUT_MASK
171 #define RT1318_DIV_FIFO_OUT_DIV1
172 #define RT1318_DIV_FIFO_OUT_DIV2
173 #define RT1318_DIV_FIFO_OUT_DIV4
174 #define RT1318_DIV_FIFO_OUT_DIV8
175 #define RT1318_DIV_FIFO_OUT_SFT
176 /* Clock-6 (0xC007) */
177 #define RT1318_DIV_NLMS_MASK
178 #define RT1318_DIV_NLMS_SFT
179 #define RT1318_DIV_NLMS_DIV1
180 #define RT1318_DIV_NLMS_DIV2
181 #define RT1318_DIV_NLMS_DIV4
182 #define RT1318_DIV_NLMS_DIV8
183 #define RT1318_DIV_AD_MONO_MASK
184 #define RT1318_DIV_AD_MONO_SFT
185 #define RT1318_DIV_AD_MONO_DIV1
186 #define RT1318_DIV_AD_MONO_DIV2
187 #define RT1318_DIV_AD_MONO_DIV4
188 #define RT1318_DIV_AD_MONO_DIV8
189 #define RT1318_DIV_AD_MONO_DIV16
190 #define RT1318_DIV_POST_G_MASK
191 #define RT1318_DIV_POST_G_SFT
192 #define RT1318_DIV_POST_G_DIV1
193 #define RT1318_DIV_POST_G_DIV2
194 #define RT1318_DIV_POST_G_DIV4
195 #define RT1318_DIV_POST_G_DIV8
196 #define RT1318_DIV_POST_G_DIV16
197 /* Power Status 1 (0xC121) */
198 #define RT1318_PDB_CTRL_MASK
199 #define RT1318_PDB_CTRL_LOW
200 #define RT1318_PDB_CTRL_HIGH
201 #define RT1318_PDB_CTRL_SFT
202 /* SRC Tcon(0xc204) */
203 #define RT1318_SRCIN_IN_SEL_MASK
204 #define RT1318_SRCIN_IN_48K
205 #define RT1318_SRCIN_IN_44P1
206 #define RT1318_SRCIN_IN_32K
207 #define RT1318_SRCIN_IN_16K
208 #define RT1318_SRCIN_F12288_MASK
209 #define RT1318_SRCIN_TCON1
210 #define RT1318_SRCIN_TCON2
211 #define RT1318_SRCIN_TCON4
212 #define RT1318_SRCIN_TCON8
213 #define RT1318_SRCIN_DACLK_MASK
214 #define RT1318_DACLK_TCON1
215 #define RT1318_DACLK_TCON2
216 #define RT1318_DACLK_TCON4
217 #define RT1318_DACLK_TCON8
218 /* R0 Compare Flag (0xDB35) */
219 #define RT1318_R0_RANGE_MASK
220 #define RT1318_R0_OUTOFRANGE
221 #define RT1318_R0_INRANGE
222 /* PLL internal setting (0xF20D), K value */
223 #define RT1318_K_PLL1_MASK
224 /* PLL internal setting (0xF20F), M value */
225 #define RT1318_M_PLL1_MASK
226 /* PLL internal setting (0xF211), N_8 value */
227 #define RT1318_N_8_PLL1_MASK
228 /* PLL internal setting (0xF212), N_7_0 value
229 #define RT1318_N_7_0_PLL1_MASK
230 /* TDM CTRL 1 (0xf900) */
231 #define RT1318_TDM_BCLK_MASK
232 #define RT1318_TDM_BCLK_NORM
233 #define RT1318_TDM_BCLK_INV
234 #define RT1318_I2S_FMT_MASK
235 #define RT1318_FMT_I2S
236 #define RT1318_FMT_LEFT_J
237 #define RT1318_FMT_PCM_A_R
238 #define RT1318_FMT_PCM_B_R
239 #define RT1318_FMT_PCM_A_F
240 #define RT1318_FMT_PCM_B_F
241 #define RT1318_I2S_FMT_SFT
242 /* TDM CTRL 2 (0xf901) */
243 #define RT1318_I2S_CH_TX_MASK
244 #define RT1318_I2S_CH_TX_2CH
245 #define RT1318_I2S_CH_TX_4CH
246 #define RT1318_I2S_CH_TX_6CH
247 #define RT1318_I2S_CH_TX_8CH
248 #define RT1318_I2S_CH_RX_MASK
249 #define RT1318_I2S_CH_RX_2CH
250 #define RT1318_I2S_CH_RX_4CH
251 #define RT1318_I2S_CH_RX_6CH
252 #define RT1318_I2S_CH_RX_8CH
253 #define RT1318_I2S_DL_MASK
254 #define RT1318_I2S_DL_SFT
255 #define RT1318_I2S_DL_16
256 #define RT1318_I2S_DL_20
257 #define RT1318_I2S_DL_24
258 #define RT1318_I2S_DL_32
259 #define RT1318_I2S_DL_8
260 /* TDM CTRL 3 (0xf902) */
261 #define RT1318_I2S_TX_CHL_MASK
262 #define RT1318_I2S_TX_CHL_SFT
263 #define RT1318_I2S_TX_CHL_16
264 #define RT1318_I2S_TX_CHL_20
265 #define RT1318_I2S_TX_CHL_24
266 #define RT1318_I2S_TX_CHL_32
267 #define RT1318_I2S_TX_CHL_8
268 #define RT1318_I2S_RX_CHL_MASK
269 #define RT1318_I2S_RX_CHL_SFT
270 #define RT1318_I2S_RX_CHL_16
271 #define RT1318_I2S_RX_CHL_20
272 #define RT1318_I2S_RX_CHL_24
273 #define RT1318_I2S_RX_CHL_32
274 #define RT1318_I2S_RX_CHL_8
275 /* TDM CTRL 9 (0xf908) */
276 #define RT1318_TDM_I2S_TX_L_DAC1_1_MASK
277 #define RT1318_TDM_I2S_TX_R_DAC1_1_MASK
278 #define RT1318_TDM_I2S_TX_L_DAC1_1_SFT
279 #define RT1318_TDM_I2S_TX_R_DAC1_1_SFT
280
281 #define RT1318_REG_DISP_LEN 23
282
283 /* System Clock Source */
284 enum {
285 RT1318_SCLK_S_BCLK,
286 RT1318_SCLK_S_SDW,
287 RT1318_SCLK_S_PLL2F,
288 RT1318_SCLK_S_PLL2B,
289 RT1318_SCLK_S_MCLK,
290 RT1318_SCLK_S_RC0,
291 RT1318_SCLK_S_RC1,
292 RT1318_SCLK_S_RC2,
293 };
294
295 /* PLL Source */
296 enum {
297 RT1318_PLL_S_BCLK0,
298 RT1318_PLL_S_BCLK1,
299 RT1318_PLL_S_RC,
300 RT1318_PLL_S_MCLK,
301 RT1318_PLL_S_SDW_IN_PLL,
302 RT1318_PLL_S_SDW_0,
303 RT1318_PLL_S_SDW_1,
304 RT1318_PLL_S_SDW_2,
305 };
306
307 /* TDM channel */
308 enum {
309 RT1318_2CH,
310 RT1318_4CH,
311 RT1318_6CH,
312 RT1318_8CH,
313 };
314
315 /* R0 calibration result */
316 enum {
317 RT1318_R0_OUT_OF_RANGE,
318 RT1318_R0_IN_RANGE,
319 RT1318_R0_CALIB_NOT_DONE,
320 };
321
322 /* PLL pre-defined M/N/K */
323
324 struct pll_calc_map {
325 unsigned int pll_in;
326 unsigned int pll_out;
327 int k;
328 int n;
329 int m;
330 bool m_bp;
331 bool k_bp;
332 };
333
334 struct rt1318_pll_code {
335 bool m_bp; /* Indicates bypass m code
336 bool k_bp; /* Indicates bypass k code
337 int m_code;
338 int n_code;
339 int k_code;
340 };
341
342 #endif /* __RT1318_H__ */
343
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