1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* 2 /*
3 * rt5640.h -- RT5640 ALSA SoC audio driver 3 * rt5640.h -- RT5640 ALSA SoC audio driver
4 * 4 *
5 * Copyright 2011 Realtek Microelectronics 5 * Copyright 2011 Realtek Microelectronics
6 * Author: Johnny Hsu <johnnyhsu@realtek.com> 6 * Author: Johnny Hsu <johnnyhsu@realtek.com>
7 */ 7 */
8 8
9 #ifndef _RT5640_H 9 #ifndef _RT5640_H
10 #define _RT5640_H 10 #define _RT5640_H
11 11
12 #include <linux/clk.h> 12 #include <linux/clk.h>
13 #include <linux/gpio/consumer.h> 13 #include <linux/gpio/consumer.h>
14 #include <linux/workqueue.h> 14 #include <linux/workqueue.h>
15 #include <dt-bindings/sound/rt5640.h> 15 #include <dt-bindings/sound/rt5640.h>
16 16
17 /* Info */ 17 /* Info */
18 #define RT5640_RESET 18 #define RT5640_RESET 0x00
19 #define RT5640_VENDOR_ID 19 #define RT5640_VENDOR_ID 0xfd
20 #define RT5640_VENDOR_ID1 20 #define RT5640_VENDOR_ID1 0xfe
21 #define RT5640_VENDOR_ID2 21 #define RT5640_VENDOR_ID2 0xff
22 /* I/O - Output */ 22 /* I/O - Output */
23 #define RT5640_SPK_VOL 23 #define RT5640_SPK_VOL 0x01
24 #define RT5640_HP_VOL 24 #define RT5640_HP_VOL 0x02
25 #define RT5640_OUTPUT 25 #define RT5640_OUTPUT 0x03
26 #define RT5640_MONO_OUT 26 #define RT5640_MONO_OUT 0x04
27 /* I/O - Input */ 27 /* I/O - Input */
28 #define RT5640_IN1_IN2 28 #define RT5640_IN1_IN2 0x0d
29 #define RT5640_IN3_IN4 29 #define RT5640_IN3_IN4 0x0e
30 #define RT5640_INL_INR_VOL 30 #define RT5640_INL_INR_VOL 0x0f
31 /* I/O - ADC/DAC/DMIC */ 31 /* I/O - ADC/DAC/DMIC */
32 #define RT5640_DAC1_DIG_VOL 32 #define RT5640_DAC1_DIG_VOL 0x19
33 #define RT5640_DAC2_DIG_VOL 33 #define RT5640_DAC2_DIG_VOL 0x1a
34 #define RT5640_DAC2_CTRL 34 #define RT5640_DAC2_CTRL 0x1b
35 #define RT5640_ADC_DIG_VOL 35 #define RT5640_ADC_DIG_VOL 0x1c
36 #define RT5640_ADC_DATA 36 #define RT5640_ADC_DATA 0x1d
37 #define RT5640_ADC_BST_VOL 37 #define RT5640_ADC_BST_VOL 0x1e
38 /* Mixer - D-D */ 38 /* Mixer - D-D */
39 #define RT5640_STO_ADC_MIXER 39 #define RT5640_STO_ADC_MIXER 0x27
40 #define RT5640_MONO_ADC_MIXER 40 #define RT5640_MONO_ADC_MIXER 0x28
41 #define RT5640_AD_DA_MIXER 41 #define RT5640_AD_DA_MIXER 0x29
42 #define RT5640_STO_DAC_MIXER 42 #define RT5640_STO_DAC_MIXER 0x2a
43 #define RT5640_MONO_DAC_MIXER 43 #define RT5640_MONO_DAC_MIXER 0x2b
44 #define RT5640_DIG_MIXER 44 #define RT5640_DIG_MIXER 0x2c
45 #define RT5640_DSP_PATH1 45 #define RT5640_DSP_PATH1 0x2d
46 #define RT5640_DSP_PATH2 46 #define RT5640_DSP_PATH2 0x2e
47 #define RT5640_DIG_INF_DATA 47 #define RT5640_DIG_INF_DATA 0x2f
48 /* Mixer - ADC */ 48 /* Mixer - ADC */
49 #define RT5640_REC_L1_MIXER 49 #define RT5640_REC_L1_MIXER 0x3b
50 #define RT5640_REC_L2_MIXER 50 #define RT5640_REC_L2_MIXER 0x3c
51 #define RT5640_REC_R1_MIXER 51 #define RT5640_REC_R1_MIXER 0x3d
52 #define RT5640_REC_R2_MIXER 52 #define RT5640_REC_R2_MIXER 0x3e
53 /* Mixer - DAC */ 53 /* Mixer - DAC */
54 #define RT5640_HPO_MIXER 54 #define RT5640_HPO_MIXER 0x45
55 #define RT5640_SPK_L_MIXER 55 #define RT5640_SPK_L_MIXER 0x46
56 #define RT5640_SPK_R_MIXER 56 #define RT5640_SPK_R_MIXER 0x47
57 #define RT5640_SPO_L_MIXER 57 #define RT5640_SPO_L_MIXER 0x48
58 #define RT5640_SPO_R_MIXER 58 #define RT5640_SPO_R_MIXER 0x49
59 #define RT5640_SPO_CLSD_RATIO 59 #define RT5640_SPO_CLSD_RATIO 0x4a
60 #define RT5640_MONO_MIXER 60 #define RT5640_MONO_MIXER 0x4c
61 #define RT5640_OUT_L1_MIXER 61 #define RT5640_OUT_L1_MIXER 0x4d
62 #define RT5640_OUT_L2_MIXER 62 #define RT5640_OUT_L2_MIXER 0x4e
63 #define RT5640_OUT_L3_MIXER 63 #define RT5640_OUT_L3_MIXER 0x4f
64 #define RT5640_OUT_R1_MIXER 64 #define RT5640_OUT_R1_MIXER 0x50
65 #define RT5640_OUT_R2_MIXER 65 #define RT5640_OUT_R2_MIXER 0x51
66 #define RT5640_OUT_R3_MIXER 66 #define RT5640_OUT_R3_MIXER 0x52
67 #define RT5640_LOUT_MIXER 67 #define RT5640_LOUT_MIXER 0x53
68 /* Power */ 68 /* Power */
69 #define RT5640_PWR_DIG1 69 #define RT5640_PWR_DIG1 0x61
70 #define RT5640_PWR_DIG2 70 #define RT5640_PWR_DIG2 0x62
71 #define RT5640_PWR_ANLG1 71 #define RT5640_PWR_ANLG1 0x63
72 #define RT5640_PWR_ANLG2 72 #define RT5640_PWR_ANLG2 0x64
73 #define RT5640_PWR_MIXER 73 #define RT5640_PWR_MIXER 0x65
74 #define RT5640_PWR_VOL 74 #define RT5640_PWR_VOL 0x66
75 /* Private Register Control */ 75 /* Private Register Control */
76 #define RT5640_PRIV_INDEX 76 #define RT5640_PRIV_INDEX 0x6a
77 #define RT5640_PRIV_DATA 77 #define RT5640_PRIV_DATA 0x6c
78 /* Format - ADC/DAC */ 78 /* Format - ADC/DAC */
79 #define RT5640_I2S1_SDP 79 #define RT5640_I2S1_SDP 0x70
80 #define RT5640_I2S2_SDP 80 #define RT5640_I2S2_SDP 0x71
81 #define RT5640_ADDA_CLK1 81 #define RT5640_ADDA_CLK1 0x73
82 #define RT5640_ADDA_CLK2 82 #define RT5640_ADDA_CLK2 0x74
83 #define RT5640_DMIC 83 #define RT5640_DMIC 0x75
84 /* Function - Analog */ 84 /* Function - Analog */
85 #define RT5640_GLB_CLK 85 #define RT5640_GLB_CLK 0x80
86 #define RT5640_PLL_CTRL1 86 #define RT5640_PLL_CTRL1 0x81
87 #define RT5640_PLL_CTRL2 87 #define RT5640_PLL_CTRL2 0x82
88 #define RT5640_ASRC_1 88 #define RT5640_ASRC_1 0x83
89 #define RT5640_ASRC_2 89 #define RT5640_ASRC_2 0x84
90 #define RT5640_ASRC_3 90 #define RT5640_ASRC_3 0x85
91 #define RT5640_ASRC_4 91 #define RT5640_ASRC_4 0x89
92 #define RT5640_ASRC_5 92 #define RT5640_ASRC_5 0x8a
93 #define RT5640_HP_OVCD 93 #define RT5640_HP_OVCD 0x8b
94 #define RT5640_CLS_D_OVCD 94 #define RT5640_CLS_D_OVCD 0x8c
95 #define RT5640_CLS_D_OUT 95 #define RT5640_CLS_D_OUT 0x8d
96 #define RT5640_DEPOP_M1 96 #define RT5640_DEPOP_M1 0x8e
97 #define RT5640_DEPOP_M2 97 #define RT5640_DEPOP_M2 0x8f
98 #define RT5640_DEPOP_M3 98 #define RT5640_DEPOP_M3 0x90
99 #define RT5640_CHARGE_PUMP 99 #define RT5640_CHARGE_PUMP 0x91
100 #define RT5640_PV_DET_SPK_G 100 #define RT5640_PV_DET_SPK_G 0x92
101 #define RT5640_MICBIAS 101 #define RT5640_MICBIAS 0x93
102 /* Function - Digital */ 102 /* Function - Digital */
103 #define RT5640_EQ_CTRL1 103 #define RT5640_EQ_CTRL1 0xb0
104 #define RT5640_EQ_CTRL2 104 #define RT5640_EQ_CTRL2 0xb1
105 #define RT5640_WIND_FILTER 105 #define RT5640_WIND_FILTER 0xb2
106 #define RT5640_DRC_AGC_1 106 #define RT5640_DRC_AGC_1 0xb4
107 #define RT5640_DRC_AGC_2 107 #define RT5640_DRC_AGC_2 0xb5
108 #define RT5640_DRC_AGC_3 108 #define RT5640_DRC_AGC_3 0xb6
109 #define RT5640_SVOL_ZC 109 #define RT5640_SVOL_ZC 0xb7
110 #define RT5640_ANC_CTRL1 110 #define RT5640_ANC_CTRL1 0xb8
111 #define RT5640_ANC_CTRL2 111 #define RT5640_ANC_CTRL2 0xb9
112 #define RT5640_ANC_CTRL3 112 #define RT5640_ANC_CTRL3 0xba
113 #define RT5640_JD_CTRL 113 #define RT5640_JD_CTRL 0xbb
114 #define RT5640_ANC_JD 114 #define RT5640_ANC_JD 0xbc
115 #define RT5640_IRQ_CTRL1 115 #define RT5640_IRQ_CTRL1 0xbd
116 #define RT5640_IRQ_CTRL2 116 #define RT5640_IRQ_CTRL2 0xbe
117 #define RT5640_INT_IRQ_ST 117 #define RT5640_INT_IRQ_ST 0xbf
118 #define RT5640_GPIO_CTRL1 118 #define RT5640_GPIO_CTRL1 0xc0
119 #define RT5640_GPIO_CTRL2 119 #define RT5640_GPIO_CTRL2 0xc1
120 #define RT5640_GPIO_CTRL3 120 #define RT5640_GPIO_CTRL3 0xc2
121 #define RT5640_DSP_CTRL1 121 #define RT5640_DSP_CTRL1 0xc4
122 #define RT5640_DSP_CTRL2 122 #define RT5640_DSP_CTRL2 0xc5
123 #define RT5640_DSP_CTRL3 123 #define RT5640_DSP_CTRL3 0xc6
124 #define RT5640_DSP_CTRL4 124 #define RT5640_DSP_CTRL4 0xc7
125 #define RT5640_PGM_REG_ARR1 125 #define RT5640_PGM_REG_ARR1 0xc8
126 #define RT5640_PGM_REG_ARR2 126 #define RT5640_PGM_REG_ARR2 0xc9
127 #define RT5640_PGM_REG_ARR3 127 #define RT5640_PGM_REG_ARR3 0xca
128 #define RT5640_PGM_REG_ARR4 128 #define RT5640_PGM_REG_ARR4 0xcb
129 #define RT5640_PGM_REG_ARR5 129 #define RT5640_PGM_REG_ARR5 0xcc
130 #define RT5640_SCB_FUNC 130 #define RT5640_SCB_FUNC 0xcd
131 #define RT5640_SCB_CTRL 131 #define RT5640_SCB_CTRL 0xce
132 #define RT5640_BASE_BACK 132 #define RT5640_BASE_BACK 0xcf
133 #define RT5640_MP3_PLUS1 133 #define RT5640_MP3_PLUS1 0xd0
134 #define RT5640_MP3_PLUS2 134 #define RT5640_MP3_PLUS2 0xd1
135 #define RT5640_3D_HP 135 #define RT5640_3D_HP 0xd2
136 #define RT5640_ADJ_HPF 136 #define RT5640_ADJ_HPF 0xd3
137 #define RT5640_HP_CALIB_AMP_DET 137 #define RT5640_HP_CALIB_AMP_DET 0xd6
138 #define RT5640_HP_CALIB2 138 #define RT5640_HP_CALIB2 0xd7
139 #define RT5640_SV_ZCD1 139 #define RT5640_SV_ZCD1 0xd9
140 #define RT5640_SV_ZCD2 140 #define RT5640_SV_ZCD2 0xda
141 /* Dummy Register */ 141 /* Dummy Register */
142 #define RT5640_DUMMY1 142 #define RT5640_DUMMY1 0xfa
143 #define RT5640_DUMMY2 143 #define RT5640_DUMMY2 0xfb
144 #define RT5640_DUMMY3 144 #define RT5640_DUMMY3 0xfc
145 145
146 146
147 /* Index of Codec Private Register definition 147 /* Index of Codec Private Register definition */
148 #define RT5640_BIAS_CUR4 148 #define RT5640_BIAS_CUR4 0x15
149 #define RT5640_CHPUMP_INT_REG1 149 #define RT5640_CHPUMP_INT_REG1 0x24
150 #define RT5640_MAMP_INT_REG2 150 #define RT5640_MAMP_INT_REG2 0x37
151 #define RT5640_3D_SPK 151 #define RT5640_3D_SPK 0x63
152 #define RT5640_WND_1 152 #define RT5640_WND_1 0x6c
153 #define RT5640_WND_2 153 #define RT5640_WND_2 0x6d
154 #define RT5640_WND_3 154 #define RT5640_WND_3 0x6e
155 #define RT5640_WND_4 155 #define RT5640_WND_4 0x6f
156 #define RT5640_WND_5 156 #define RT5640_WND_5 0x70
157 #define RT5640_WND_8 157 #define RT5640_WND_8 0x73
158 #define RT5640_DIP_SPK_INF 158 #define RT5640_DIP_SPK_INF 0x75
159 #define RT5640_HP_DCC_INT1 159 #define RT5640_HP_DCC_INT1 0x77
160 #define RT5640_EQ_BW_LOP 160 #define RT5640_EQ_BW_LOP 0xa0
161 #define RT5640_EQ_GN_LOP 161 #define RT5640_EQ_GN_LOP 0xa1
162 #define RT5640_EQ_FC_BP1 162 #define RT5640_EQ_FC_BP1 0xa2
163 #define RT5640_EQ_BW_BP1 163 #define RT5640_EQ_BW_BP1 0xa3
164 #define RT5640_EQ_GN_BP1 164 #define RT5640_EQ_GN_BP1 0xa4
165 #define RT5640_EQ_FC_BP2 165 #define RT5640_EQ_FC_BP2 0xa5
166 #define RT5640_EQ_BW_BP2 166 #define RT5640_EQ_BW_BP2 0xa6
167 #define RT5640_EQ_GN_BP2 167 #define RT5640_EQ_GN_BP2 0xa7
168 #define RT5640_EQ_FC_BP3 168 #define RT5640_EQ_FC_BP3 0xa8
169 #define RT5640_EQ_BW_BP3 169 #define RT5640_EQ_BW_BP3 0xa9
170 #define RT5640_EQ_GN_BP3 170 #define RT5640_EQ_GN_BP3 0xaa
171 #define RT5640_EQ_FC_BP4 171 #define RT5640_EQ_FC_BP4 0xab
172 #define RT5640_EQ_BW_BP4 172 #define RT5640_EQ_BW_BP4 0xac
173 #define RT5640_EQ_GN_BP4 173 #define RT5640_EQ_GN_BP4 0xad
174 #define RT5640_EQ_FC_HIP1 174 #define RT5640_EQ_FC_HIP1 0xae
175 #define RT5640_EQ_GN_HIP1 175 #define RT5640_EQ_GN_HIP1 0xaf
176 #define RT5640_EQ_FC_HIP2 176 #define RT5640_EQ_FC_HIP2 0xb0
177 #define RT5640_EQ_BW_HIP2 177 #define RT5640_EQ_BW_HIP2 0xb1
178 #define RT5640_EQ_GN_HIP2 178 #define RT5640_EQ_GN_HIP2 0xb2
179 #define RT5640_EQ_PRE_VOL 179 #define RT5640_EQ_PRE_VOL 0xb3
180 #define RT5640_EQ_PST_VOL 180 #define RT5640_EQ_PST_VOL 0xb4
181 181
182 /* global definition */ 182 /* global definition */
183 #define RT5640_L_MUTE 183 #define RT5640_L_MUTE (0x1 << 15)
184 #define RT5640_L_MUTE_SFT 184 #define RT5640_L_MUTE_SFT 15
185 #define RT5640_VOL_L_MUTE 185 #define RT5640_VOL_L_MUTE (0x1 << 14)
186 #define RT5640_VOL_L_SFT 186 #define RT5640_VOL_L_SFT 14
187 #define RT5640_R_MUTE 187 #define RT5640_R_MUTE (0x1 << 7)
188 #define RT5640_R_MUTE_SFT 188 #define RT5640_R_MUTE_SFT 7
189 #define RT5640_VOL_R_MUTE 189 #define RT5640_VOL_R_MUTE (0x1 << 6)
190 #define RT5640_VOL_R_SFT 190 #define RT5640_VOL_R_SFT 6
191 #define RT5640_L_VOL_MASK 191 #define RT5640_L_VOL_MASK (0x3f << 8)
192 #define RT5640_L_VOL_SFT 192 #define RT5640_L_VOL_SFT 8
193 #define RT5640_R_VOL_MASK 193 #define RT5640_R_VOL_MASK (0x3f)
194 #define RT5640_R_VOL_SFT 194 #define RT5640_R_VOL_SFT 0
195 195
196 /* SW Reset & Device ID (0x00) */ 196 /* SW Reset & Device ID (0x00) */
197 #define RT5640_ID_MASK 197 #define RT5640_ID_MASK (0x3 << 1)
198 #define RT5640_ID_5639 198 #define RT5640_ID_5639 (0x0 << 1)
199 #define RT5640_ID_5640 199 #define RT5640_ID_5640 (0x2 << 1)
200 #define RT5640_ID_5642 200 #define RT5640_ID_5642 (0x3 << 1)
201 201
202 202
203 /* IN1 and IN2 Control (0x0d) */ 203 /* IN1 and IN2 Control (0x0d) */
204 /* IN3 and IN4 Control (0x0e) */ 204 /* IN3 and IN4 Control (0x0e) */
205 #define RT5640_BST_SFT1 205 #define RT5640_BST_SFT1 12
206 #define RT5640_BST_SFT2 206 #define RT5640_BST_SFT2 8
207 #define RT5640_IN_DF1 207 #define RT5640_IN_DF1 (0x1 << 7)
208 #define RT5640_IN_SFT1 208 #define RT5640_IN_SFT1 7
209 #define RT5640_IN_DF2 209 #define RT5640_IN_DF2 (0x1 << 6)
210 #define RT5640_IN_SFT2 210 #define RT5640_IN_SFT2 6
211 211
212 /* INL and INR Volume Control (0x0f) */ 212 /* INL and INR Volume Control (0x0f) */
213 #define RT5640_INL_SEL_MASK 213 #define RT5640_INL_SEL_MASK (0x1 << 15)
214 #define RT5640_INL_SEL_SFT 214 #define RT5640_INL_SEL_SFT 15
215 #define RT5640_INL_SEL_IN4P 215 #define RT5640_INL_SEL_IN4P (0x0 << 15)
216 #define RT5640_INL_SEL_MONOP 216 #define RT5640_INL_SEL_MONOP (0x1 << 15)
217 #define RT5640_INL_VOL_MASK 217 #define RT5640_INL_VOL_MASK (0x1f << 8)
218 #define RT5640_INL_VOL_SFT 218 #define RT5640_INL_VOL_SFT 8
219 #define RT5640_INR_SEL_MASK 219 #define RT5640_INR_SEL_MASK (0x1 << 7)
220 #define RT5640_INR_SEL_SFT 220 #define RT5640_INR_SEL_SFT 7
221 #define RT5640_INR_SEL_IN4N 221 #define RT5640_INR_SEL_IN4N (0x0 << 7)
222 #define RT5640_INR_SEL_MONON 222 #define RT5640_INR_SEL_MONON (0x1 << 7)
223 #define RT5640_INR_VOL_MASK 223 #define RT5640_INR_VOL_MASK (0x1f)
224 #define RT5640_INR_VOL_SFT 224 #define RT5640_INR_VOL_SFT 0
225 225
226 /* DAC1 Digital Volume (0x19) */ 226 /* DAC1 Digital Volume (0x19) */
227 #define RT5640_DAC_L1_VOL_MASK 227 #define RT5640_DAC_L1_VOL_MASK (0xff << 8)
228 #define RT5640_DAC_L1_VOL_SFT 228 #define RT5640_DAC_L1_VOL_SFT 8
229 #define RT5640_DAC_R1_VOL_MASK 229 #define RT5640_DAC_R1_VOL_MASK (0xff)
230 #define RT5640_DAC_R1_VOL_SFT 230 #define RT5640_DAC_R1_VOL_SFT 0
231 231
232 /* DAC2 Digital Volume (0x1a) */ 232 /* DAC2 Digital Volume (0x1a) */
233 #define RT5640_DAC_L2_VOL_MASK 233 #define RT5640_DAC_L2_VOL_MASK (0xff << 8)
234 #define RT5640_DAC_L2_VOL_SFT 234 #define RT5640_DAC_L2_VOL_SFT 8
235 #define RT5640_DAC_R2_VOL_MASK 235 #define RT5640_DAC_R2_VOL_MASK (0xff)
236 #define RT5640_DAC_R2_VOL_SFT 236 #define RT5640_DAC_R2_VOL_SFT 0
237 237
238 /* DAC2 Control (0x1b) */ 238 /* DAC2 Control (0x1b) */
239 #define RT5640_M_DAC_L2_VOL 239 #define RT5640_M_DAC_L2_VOL (0x1 << 13)
240 #define RT5640_M_DAC_L2_VOL_SFT 240 #define RT5640_M_DAC_L2_VOL_SFT 13
241 #define RT5640_M_DAC_R2_VOL 241 #define RT5640_M_DAC_R2_VOL (0x1 << 12)
242 #define RT5640_M_DAC_R2_VOL_SFT 242 #define RT5640_M_DAC_R2_VOL_SFT 12
243 243
244 /* ADC Digital Volume Control (0x1c) */ 244 /* ADC Digital Volume Control (0x1c) */
245 #define RT5640_ADC_L_VOL_MASK 245 #define RT5640_ADC_L_VOL_MASK (0x7f << 8)
246 #define RT5640_ADC_L_VOL_SFT 246 #define RT5640_ADC_L_VOL_SFT 8
247 #define RT5640_ADC_R_VOL_MASK 247 #define RT5640_ADC_R_VOL_MASK (0x7f)
248 #define RT5640_ADC_R_VOL_SFT 248 #define RT5640_ADC_R_VOL_SFT 0
249 249
250 /* Mono ADC Digital Volume Control (0x1d) */ 250 /* Mono ADC Digital Volume Control (0x1d) */
251 #define RT5640_MONO_ADC_L_VOL_MASK 251 #define RT5640_MONO_ADC_L_VOL_MASK (0x7f << 8)
252 #define RT5640_MONO_ADC_L_VOL_SFT 252 #define RT5640_MONO_ADC_L_VOL_SFT 8
253 #define RT5640_MONO_ADC_R_VOL_MASK 253 #define RT5640_MONO_ADC_R_VOL_MASK (0x7f)
254 #define RT5640_MONO_ADC_R_VOL_SFT 254 #define RT5640_MONO_ADC_R_VOL_SFT 0
255 255
256 /* ADC Boost Volume Control (0x1e) */ 256 /* ADC Boost Volume Control (0x1e) */
257 #define RT5640_ADC_L_BST_MASK 257 #define RT5640_ADC_L_BST_MASK (0x3 << 14)
258 #define RT5640_ADC_L_BST_SFT 258 #define RT5640_ADC_L_BST_SFT 14
259 #define RT5640_ADC_R_BST_MASK 259 #define RT5640_ADC_R_BST_MASK (0x3 << 12)
260 #define RT5640_ADC_R_BST_SFT 260 #define RT5640_ADC_R_BST_SFT 12
261 #define RT5640_ADC_COMP_MASK 261 #define RT5640_ADC_COMP_MASK (0x3 << 10)
262 #define RT5640_ADC_COMP_SFT 262 #define RT5640_ADC_COMP_SFT 10
263 263
264 /* Stereo ADC Mixer Control (0x27) */ 264 /* Stereo ADC Mixer Control (0x27) */
265 #define RT5640_M_ADC_L1 265 #define RT5640_M_ADC_L1 (0x1 << 14)
266 #define RT5640_M_ADC_L1_SFT 266 #define RT5640_M_ADC_L1_SFT 14
267 #define RT5640_M_ADC_L2 267 #define RT5640_M_ADC_L2 (0x1 << 13)
268 #define RT5640_M_ADC_L2_SFT 268 #define RT5640_M_ADC_L2_SFT 13
269 #define RT5640_ADC_1_SRC_MASK 269 #define RT5640_ADC_1_SRC_MASK (0x1 << 12)
270 #define RT5640_ADC_1_SRC_SFT 270 #define RT5640_ADC_1_SRC_SFT 12
271 #define RT5640_ADC_1_SRC_ADC 271 #define RT5640_ADC_1_SRC_ADC (0x1 << 12)
272 #define RT5640_ADC_1_SRC_DACMIX 272 #define RT5640_ADC_1_SRC_DACMIX (0x0 << 12)
273 #define RT5640_ADC_2_SRC_MASK 273 #define RT5640_ADC_2_SRC_MASK (0x3 << 10)
274 #define RT5640_ADC_2_SRC_SFT 274 #define RT5640_ADC_2_SRC_SFT 10
275 #define RT5640_ADC_2_SRC_DMIC1 275 #define RT5640_ADC_2_SRC_DMIC1 (0x0 << 10)
276 #define RT5640_ADC_2_SRC_DMIC2 276 #define RT5640_ADC_2_SRC_DMIC2 (0x1 << 10)
277 #define RT5640_ADC_2_SRC_DACMIX 277 #define RT5640_ADC_2_SRC_DACMIX (0x2 << 10)
278 #define RT5640_M_ADC_R1 278 #define RT5640_M_ADC_R1 (0x1 << 6)
279 #define RT5640_M_ADC_R1_SFT 279 #define RT5640_M_ADC_R1_SFT 6
280 #define RT5640_M_ADC_R2 280 #define RT5640_M_ADC_R2 (0x1 << 5)
281 #define RT5640_M_ADC_R2_SFT 281 #define RT5640_M_ADC_R2_SFT 5
282 282
283 /* Mono ADC Mixer Control (0x28) */ 283 /* Mono ADC Mixer Control (0x28) */
284 #define RT5640_M_MONO_ADC_L1 284 #define RT5640_M_MONO_ADC_L1 (0x1 << 14)
285 #define RT5640_M_MONO_ADC_L1_SFT 285 #define RT5640_M_MONO_ADC_L1_SFT 14
286 #define RT5640_M_MONO_ADC_L2 286 #define RT5640_M_MONO_ADC_L2 (0x1 << 13)
287 #define RT5640_M_MONO_ADC_L2_SFT 287 #define RT5640_M_MONO_ADC_L2_SFT 13
288 #define RT5640_MONO_ADC_L1_SRC_MASK 288 #define RT5640_MONO_ADC_L1_SRC_MASK (0x1 << 12)
289 #define RT5640_MONO_ADC_L1_SRC_SFT 289 #define RT5640_MONO_ADC_L1_SRC_SFT 12
290 #define RT5640_MONO_ADC_L1_SRC_DACMIXL 290 #define RT5640_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
291 #define RT5640_MONO_ADC_L1_SRC_ADCL 291 #define RT5640_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
292 #define RT5640_MONO_ADC_L2_SRC_MASK 292 #define RT5640_MONO_ADC_L2_SRC_MASK (0x3 << 10)
293 #define RT5640_MONO_ADC_L2_SRC_SFT 293 #define RT5640_MONO_ADC_L2_SRC_SFT 10
294 #define RT5640_MONO_ADC_L2_SRC_DMIC_L1 294 #define RT5640_MONO_ADC_L2_SRC_DMIC_L1 (0x0 << 10)
295 #define RT5640_MONO_ADC_L2_SRC_DMIC_L2 295 #define RT5640_MONO_ADC_L2_SRC_DMIC_L2 (0x1 << 10)
296 #define RT5640_MONO_ADC_L2_SRC_DACMIXL 296 #define RT5640_MONO_ADC_L2_SRC_DACMIXL (0x2 << 10)
297 #define RT5640_M_MONO_ADC_R1 297 #define RT5640_M_MONO_ADC_R1 (0x1 << 6)
298 #define RT5640_M_MONO_ADC_R1_SFT 298 #define RT5640_M_MONO_ADC_R1_SFT 6
299 #define RT5640_M_MONO_ADC_R2 299 #define RT5640_M_MONO_ADC_R2 (0x1 << 5)
300 #define RT5640_M_MONO_ADC_R2_SFT 300 #define RT5640_M_MONO_ADC_R2_SFT 5
301 #define RT5640_MONO_ADC_R1_SRC_MASK 301 #define RT5640_MONO_ADC_R1_SRC_MASK (0x1 << 4)
302 #define RT5640_MONO_ADC_R1_SRC_SFT 302 #define RT5640_MONO_ADC_R1_SRC_SFT 4
303 #define RT5640_MONO_ADC_R1_SRC_ADCR 303 #define RT5640_MONO_ADC_R1_SRC_ADCR (0x1 << 4)
304 #define RT5640_MONO_ADC_R1_SRC_DACMIXR 304 #define RT5640_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4)
305 #define RT5640_MONO_ADC_R2_SRC_MASK 305 #define RT5640_MONO_ADC_R2_SRC_MASK (0x3 << 2)
306 #define RT5640_MONO_ADC_R2_SRC_SFT 306 #define RT5640_MONO_ADC_R2_SRC_SFT 2
307 #define RT5640_MONO_ADC_R2_SRC_DMIC_R1 307 #define RT5640_MONO_ADC_R2_SRC_DMIC_R1 (0x0 << 2)
308 #define RT5640_MONO_ADC_R2_SRC_DMIC_R2 308 #define RT5640_MONO_ADC_R2_SRC_DMIC_R2 (0x1 << 2)
309 #define RT5640_MONO_ADC_R2_SRC_DACMIXR 309 #define RT5640_MONO_ADC_R2_SRC_DACMIXR (0x2 << 2)
310 310
311 /* ADC Mixer to DAC Mixer Control (0x29) */ 311 /* ADC Mixer to DAC Mixer Control (0x29) */
312 #define RT5640_M_ADCMIX_L 312 #define RT5640_M_ADCMIX_L (0x1 << 15)
313 #define RT5640_M_ADCMIX_L_SFT 313 #define RT5640_M_ADCMIX_L_SFT 15
314 #define RT5640_M_IF1_DAC_L 314 #define RT5640_M_IF1_DAC_L (0x1 << 14)
315 #define RT5640_M_IF1_DAC_L_SFT 315 #define RT5640_M_IF1_DAC_L_SFT 14
316 #define RT5640_M_ADCMIX_R 316 #define RT5640_M_ADCMIX_R (0x1 << 7)
317 #define RT5640_M_ADCMIX_R_SFT 317 #define RT5640_M_ADCMIX_R_SFT 7
318 #define RT5640_M_IF1_DAC_R 318 #define RT5640_M_IF1_DAC_R (0x1 << 6)
319 #define RT5640_M_IF1_DAC_R_SFT 319 #define RT5640_M_IF1_DAC_R_SFT 6
320 320
321 /* Stereo DAC Mixer Control (0x2a) */ 321 /* Stereo DAC Mixer Control (0x2a) */
322 #define RT5640_M_DAC_L1 322 #define RT5640_M_DAC_L1 (0x1 << 14)
323 #define RT5640_M_DAC_L1_SFT 323 #define RT5640_M_DAC_L1_SFT 14
324 #define RT5640_DAC_L1_STO_L_VOL_MASK 324 #define RT5640_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
325 #define RT5640_DAC_L1_STO_L_VOL_SFT 325 #define RT5640_DAC_L1_STO_L_VOL_SFT 13
326 #define RT5640_M_DAC_L2 326 #define RT5640_M_DAC_L2 (0x1 << 12)
327 #define RT5640_M_DAC_L2_SFT 327 #define RT5640_M_DAC_L2_SFT 12
328 #define RT5640_DAC_L2_STO_L_VOL_MASK 328 #define RT5640_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
329 #define RT5640_DAC_L2_STO_L_VOL_SFT 329 #define RT5640_DAC_L2_STO_L_VOL_SFT 11
330 #define RT5640_M_ANC_DAC_L 330 #define RT5640_M_ANC_DAC_L (0x1 << 10)
331 #define RT5640_M_ANC_DAC_L_SFT 331 #define RT5640_M_ANC_DAC_L_SFT 10
332 #define RT5640_M_DAC_R1 332 #define RT5640_M_DAC_R1 (0x1 << 6)
333 #define RT5640_M_DAC_R1_SFT 333 #define RT5640_M_DAC_R1_SFT 6
334 #define RT5640_DAC_R1_STO_R_VOL_MASK 334 #define RT5640_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
335 #define RT5640_DAC_R1_STO_R_VOL_SFT 335 #define RT5640_DAC_R1_STO_R_VOL_SFT 5
336 #define RT5640_M_DAC_R2 336 #define RT5640_M_DAC_R2 (0x1 << 4)
337 #define RT5640_M_DAC_R2_SFT 337 #define RT5640_M_DAC_R2_SFT 4
338 #define RT5640_DAC_R2_STO_R_VOL_MASK 338 #define RT5640_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
339 #define RT5640_DAC_R2_STO_R_VOL_SFT 339 #define RT5640_DAC_R2_STO_R_VOL_SFT 3
340 #define RT5640_M_ANC_DAC_R 340 #define RT5640_M_ANC_DAC_R (0x1 << 2)
341 #define RT5640_M_ANC_DAC_R_SFT 2 341 #define RT5640_M_ANC_DAC_R_SFT 2
342 342
343 /* Mono DAC Mixer Control (0x2b) */ 343 /* Mono DAC Mixer Control (0x2b) */
344 #define RT5640_M_DAC_L1_MONO_L 344 #define RT5640_M_DAC_L1_MONO_L (0x1 << 14)
345 #define RT5640_M_DAC_L1_MONO_L_SFT 345 #define RT5640_M_DAC_L1_MONO_L_SFT 14
346 #define RT5640_DAC_L1_MONO_L_VOL_MASK 346 #define RT5640_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
347 #define RT5640_DAC_L1_MONO_L_VOL_SFT 347 #define RT5640_DAC_L1_MONO_L_VOL_SFT 13
348 #define RT5640_M_DAC_L2_MONO_L 348 #define RT5640_M_DAC_L2_MONO_L (0x1 << 12)
349 #define RT5640_M_DAC_L2_MONO_L_SFT 349 #define RT5640_M_DAC_L2_MONO_L_SFT 12
350 #define RT5640_DAC_L2_MONO_L_VOL_MASK 350 #define RT5640_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
351 #define RT5640_DAC_L2_MONO_L_VOL_SFT 351 #define RT5640_DAC_L2_MONO_L_VOL_SFT 11
352 #define RT5640_M_DAC_R2_MONO_L 352 #define RT5640_M_DAC_R2_MONO_L (0x1 << 10)
353 #define RT5640_M_DAC_R2_MONO_L_SFT 353 #define RT5640_M_DAC_R2_MONO_L_SFT 10
354 #define RT5640_DAC_R2_MONO_L_VOL_MASK 354 #define RT5640_DAC_R2_MONO_L_VOL_MASK (0x1 << 9)
355 #define RT5640_DAC_R2_MONO_L_VOL_SFT 355 #define RT5640_DAC_R2_MONO_L_VOL_SFT 9
356 #define RT5640_M_DAC_R1_MONO_R 356 #define RT5640_M_DAC_R1_MONO_R (0x1 << 6)
357 #define RT5640_M_DAC_R1_MONO_R_SFT 357 #define RT5640_M_DAC_R1_MONO_R_SFT 6
358 #define RT5640_DAC_R1_MONO_R_VOL_MASK 358 #define RT5640_DAC_R1_MONO_R_VOL_MASK (0x1 << 5)
359 #define RT5640_DAC_R1_MONO_R_VOL_SFT 359 #define RT5640_DAC_R1_MONO_R_VOL_SFT 5
360 #define RT5640_M_DAC_R2_MONO_R 360 #define RT5640_M_DAC_R2_MONO_R (0x1 << 4)
361 #define RT5640_M_DAC_R2_MONO_R_SFT 361 #define RT5640_M_DAC_R2_MONO_R_SFT 4
362 #define RT5640_DAC_R2_MONO_R_VOL_MASK 362 #define RT5640_DAC_R2_MONO_R_VOL_MASK (0x1 << 3)
363 #define RT5640_DAC_R2_MONO_R_VOL_SFT 363 #define RT5640_DAC_R2_MONO_R_VOL_SFT 3
364 #define RT5640_M_DAC_L2_MONO_R 364 #define RT5640_M_DAC_L2_MONO_R (0x1 << 2)
365 #define RT5640_M_DAC_L2_MONO_R_SFT 365 #define RT5640_M_DAC_L2_MONO_R_SFT 2
366 #define RT5640_DAC_L2_MONO_R_VOL_MASK 366 #define RT5640_DAC_L2_MONO_R_VOL_MASK (0x1 << 1)
367 #define RT5640_DAC_L2_MONO_R_VOL_SFT 367 #define RT5640_DAC_L2_MONO_R_VOL_SFT 1
368 368
369 /* Digital Mixer Control (0x2c) */ 369 /* Digital Mixer Control (0x2c) */
370 #define RT5640_M_STO_L_DAC_L 370 #define RT5640_M_STO_L_DAC_L (0x1 << 15)
371 #define RT5640_M_STO_L_DAC_L_SFT 371 #define RT5640_M_STO_L_DAC_L_SFT 15
372 #define RT5640_STO_L_DAC_L_VOL_MASK 372 #define RT5640_STO_L_DAC_L_VOL_MASK (0x1 << 14)
373 #define RT5640_STO_L_DAC_L_VOL_SFT 373 #define RT5640_STO_L_DAC_L_VOL_SFT 14
374 #define RT5640_M_DAC_L2_DAC_L 374 #define RT5640_M_DAC_L2_DAC_L (0x1 << 13)
375 #define RT5640_M_DAC_L2_DAC_L_SFT 375 #define RT5640_M_DAC_L2_DAC_L_SFT 13
376 #define RT5640_DAC_L2_DAC_L_VOL_MASK 376 #define RT5640_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
377 #define RT5640_DAC_L2_DAC_L_VOL_SFT 377 #define RT5640_DAC_L2_DAC_L_VOL_SFT 12
378 #define RT5640_M_STO_R_DAC_R 378 #define RT5640_M_STO_R_DAC_R (0x1 << 11)
379 #define RT5640_M_STO_R_DAC_R_SFT 379 #define RT5640_M_STO_R_DAC_R_SFT 11
380 #define RT5640_STO_R_DAC_R_VOL_MASK 380 #define RT5640_STO_R_DAC_R_VOL_MASK (0x1 << 10)
381 #define RT5640_STO_R_DAC_R_VOL_SFT 381 #define RT5640_STO_R_DAC_R_VOL_SFT 10
382 #define RT5640_M_DAC_R2_DAC_R 382 #define RT5640_M_DAC_R2_DAC_R (0x1 << 9)
383 #define RT5640_M_DAC_R2_DAC_R_SFT 383 #define RT5640_M_DAC_R2_DAC_R_SFT 9
384 #define RT5640_DAC_R2_DAC_R_VOL_MASK 384 #define RT5640_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
385 #define RT5640_DAC_R2_DAC_R_VOL_SFT 385 #define RT5640_DAC_R2_DAC_R_VOL_SFT 8
386 386
387 /* DSP Path Control 1 (0x2d) */ 387 /* DSP Path Control 1 (0x2d) */
388 #define RT5640_RXDP_SRC_MASK 388 #define RT5640_RXDP_SRC_MASK (0x1 << 15)
389 #define RT5640_RXDP_SRC_SFT 389 #define RT5640_RXDP_SRC_SFT 15
390 #define RT5640_RXDP_SRC_NOR 390 #define RT5640_RXDP_SRC_NOR (0x0 << 15)
391 #define RT5640_RXDP_SRC_DIV3 391 #define RT5640_RXDP_SRC_DIV3 (0x1 << 15)
392 #define RT5640_TXDP_SRC_MASK 392 #define RT5640_TXDP_SRC_MASK (0x1 << 14)
393 #define RT5640_TXDP_SRC_SFT 393 #define RT5640_TXDP_SRC_SFT 14
394 #define RT5640_TXDP_SRC_NOR 394 #define RT5640_TXDP_SRC_NOR (0x0 << 14)
395 #define RT5640_TXDP_SRC_DIV3 395 #define RT5640_TXDP_SRC_DIV3 (0x1 << 14)
396 396
397 /* DSP Path Control 2 (0x2e) */ 397 /* DSP Path Control 2 (0x2e) */
398 #define RT5640_DAC_L2_SEL_MASK 398 #define RT5640_DAC_L2_SEL_MASK (0x3 << 14)
399 #define RT5640_DAC_L2_SEL_SFT 399 #define RT5640_DAC_L2_SEL_SFT 14
400 #define RT5640_DAC_L2_SEL_IF2 400 #define RT5640_DAC_L2_SEL_IF2 (0x0 << 14)
401 #define RT5640_DAC_L2_SEL_IF3 401 #define RT5640_DAC_L2_SEL_IF3 (0x1 << 14)
402 #define RT5640_DAC_L2_SEL_TXDC 402 #define RT5640_DAC_L2_SEL_TXDC (0x2 << 14)
403 #define RT5640_DAC_L2_SEL_BASS 403 #define RT5640_DAC_L2_SEL_BASS (0x3 << 14)
404 #define RT5640_DAC_R2_SEL_MASK 404 #define RT5640_DAC_R2_SEL_MASK (0x3 << 12)
405 #define RT5640_DAC_R2_SEL_SFT 405 #define RT5640_DAC_R2_SEL_SFT 12
406 #define RT5640_DAC_R2_SEL_IF2 406 #define RT5640_DAC_R2_SEL_IF2 (0x0 << 12)
407 #define RT5640_DAC_R2_SEL_IF3 407 #define RT5640_DAC_R2_SEL_IF3 (0x1 << 12)
408 #define RT5640_DAC_R2_SEL_TXDC 408 #define RT5640_DAC_R2_SEL_TXDC (0x2 << 12)
409 #define RT5640_IF2_ADC_L_SEL_MASK 409 #define RT5640_IF2_ADC_L_SEL_MASK (0x1 << 11)
410 #define RT5640_IF2_ADC_L_SEL_SFT 410 #define RT5640_IF2_ADC_L_SEL_SFT 11
411 #define RT5640_IF2_ADC_L_SEL_TXDP 411 #define RT5640_IF2_ADC_L_SEL_TXDP (0x0 << 11)
412 #define RT5640_IF2_ADC_L_SEL_PASS 412 #define RT5640_IF2_ADC_L_SEL_PASS (0x1 << 11)
413 #define RT5640_IF2_ADC_R_SEL_MASK 413 #define RT5640_IF2_ADC_R_SEL_MASK (0x1 << 10)
414 #define RT5640_IF2_ADC_R_SEL_SFT 414 #define RT5640_IF2_ADC_R_SEL_SFT 10
415 #define RT5640_IF2_ADC_R_SEL_TXDP 415 #define RT5640_IF2_ADC_R_SEL_TXDP (0x0 << 10)
416 #define RT5640_IF2_ADC_R_SEL_PASS 416 #define RT5640_IF2_ADC_R_SEL_PASS (0x1 << 10)
417 #define RT5640_RXDC_SEL_MASK 417 #define RT5640_RXDC_SEL_MASK (0x3 << 8)
418 #define RT5640_RXDC_SEL_SFT 418 #define RT5640_RXDC_SEL_SFT 8
419 #define RT5640_RXDC_SEL_NOR 419 #define RT5640_RXDC_SEL_NOR (0x0 << 8)
420 #define RT5640_RXDC_SEL_L2R 420 #define RT5640_RXDC_SEL_L2R (0x1 << 8)
421 #define RT5640_RXDC_SEL_R2L 421 #define RT5640_RXDC_SEL_R2L (0x2 << 8)
422 #define RT5640_RXDC_SEL_SWAP 422 #define RT5640_RXDC_SEL_SWAP (0x3 << 8)
423 #define RT5640_RXDP_SEL_MASK 423 #define RT5640_RXDP_SEL_MASK (0x3 << 6)
424 #define RT5640_RXDP_SEL_SFT 424 #define RT5640_RXDP_SEL_SFT 6
425 #define RT5640_RXDP_SEL_NOR 425 #define RT5640_RXDP_SEL_NOR (0x0 << 6)
426 #define RT5640_RXDP_SEL_L2R 426 #define RT5640_RXDP_SEL_L2R (0x1 << 6)
427 #define RT5640_RXDP_SEL_R2L 427 #define RT5640_RXDP_SEL_R2L (0x2 << 6)
428 #define RT5640_RXDP_SEL_SWAP 428 #define RT5640_RXDP_SEL_SWAP (0x3 << 6)
429 #define RT5640_TXDC_SEL_MASK 429 #define RT5640_TXDC_SEL_MASK (0x3 << 4)
430 #define RT5640_TXDC_SEL_SFT 430 #define RT5640_TXDC_SEL_SFT 4
431 #define RT5640_TXDC_SEL_NOR 431 #define RT5640_TXDC_SEL_NOR (0x0 << 4)
432 #define RT5640_TXDC_SEL_L2R 432 #define RT5640_TXDC_SEL_L2R (0x1 << 4)
433 #define RT5640_TXDC_SEL_R2L 433 #define RT5640_TXDC_SEL_R2L (0x2 << 4)
434 #define RT5640_TXDC_SEL_SWAP 434 #define RT5640_TXDC_SEL_SWAP (0x3 << 4)
435 #define RT5640_TXDP_SEL_MASK 435 #define RT5640_TXDP_SEL_MASK (0x3 << 2)
436 #define RT5640_TXDP_SEL_SFT 436 #define RT5640_TXDP_SEL_SFT 2
437 #define RT5640_TXDP_SEL_NOR 437 #define RT5640_TXDP_SEL_NOR (0x0 << 2)
438 #define RT5640_TXDP_SEL_L2R 438 #define RT5640_TXDP_SEL_L2R (0x1 << 2)
439 #define RT5640_TXDP_SEL_R2L 439 #define RT5640_TXDP_SEL_R2L (0x2 << 2)
440 #define RT5640_TRXDP_SEL_SWAP 440 #define RT5640_TRXDP_SEL_SWAP (0x3 << 2)
441 441
442 /* Digital Interface Data Control (0x2f) */ 442 /* Digital Interface Data Control (0x2f) */
443 #define RT5640_IF1_DAC_SEL_MASK 443 #define RT5640_IF1_DAC_SEL_MASK (0x3 << 14)
444 #define RT5640_IF1_DAC_SEL_SFT 444 #define RT5640_IF1_DAC_SEL_SFT 14
445 #define RT5640_IF1_DAC_SEL_NOR 445 #define RT5640_IF1_DAC_SEL_NOR (0x0 << 14)
446 #define RT5640_IF1_DAC_SEL_SWAP 446 #define RT5640_IF1_DAC_SEL_SWAP (0x1 << 14)
447 #define RT5640_IF1_DAC_SEL_L2R 447 #define RT5640_IF1_DAC_SEL_L2R (0x2 << 14)
448 #define RT5640_IF1_DAC_SEL_R2L 448 #define RT5640_IF1_DAC_SEL_R2L (0x3 << 14)
449 #define RT5640_IF1_ADC_SEL_MASK 449 #define RT5640_IF1_ADC_SEL_MASK (0x3 << 12)
450 #define RT5640_IF1_ADC_SEL_SFT 450 #define RT5640_IF1_ADC_SEL_SFT 12
451 #define RT5640_IF1_ADC_SEL_NOR 451 #define RT5640_IF1_ADC_SEL_NOR (0x0 << 12)
452 #define RT5640_IF1_ADC_SEL_SWAP 452 #define RT5640_IF1_ADC_SEL_SWAP (0x1 << 12)
453 #define RT5640_IF1_ADC_SEL_L2R 453 #define RT5640_IF1_ADC_SEL_L2R (0x2 << 12)
454 #define RT5640_IF1_ADC_SEL_R2L 454 #define RT5640_IF1_ADC_SEL_R2L (0x3 << 12)
455 #define RT5640_IF2_DAC_SEL_MASK 455 #define RT5640_IF2_DAC_SEL_MASK (0x3 << 10)
456 #define RT5640_IF2_DAC_SEL_SFT 456 #define RT5640_IF2_DAC_SEL_SFT 10
457 #define RT5640_IF2_DAC_SEL_NOR 457 #define RT5640_IF2_DAC_SEL_NOR (0x0 << 10)
458 #define RT5640_IF2_DAC_SEL_SWAP 458 #define RT5640_IF2_DAC_SEL_SWAP (0x1 << 10)
459 #define RT5640_IF2_DAC_SEL_L2R 459 #define RT5640_IF2_DAC_SEL_L2R (0x2 << 10)
460 #define RT5640_IF2_DAC_SEL_R2L 460 #define RT5640_IF2_DAC_SEL_R2L (0x3 << 10)
461 #define RT5640_IF2_ADC_SEL_MASK 461 #define RT5640_IF2_ADC_SEL_MASK (0x3 << 8)
462 #define RT5640_IF2_ADC_SEL_SFT 462 #define RT5640_IF2_ADC_SEL_SFT 8
463 #define RT5640_IF2_ADC_SEL_NOR 463 #define RT5640_IF2_ADC_SEL_NOR (0x0 << 8)
464 #define RT5640_IF2_ADC_SEL_SWAP 464 #define RT5640_IF2_ADC_SEL_SWAP (0x1 << 8)
465 #define RT5640_IF2_ADC_SEL_L2R 465 #define RT5640_IF2_ADC_SEL_L2R (0x2 << 8)
466 #define RT5640_IF2_ADC_SEL_R2L 466 #define RT5640_IF2_ADC_SEL_R2L (0x3 << 8)
467 #define RT5640_IF3_DAC_SEL_MASK 467 #define RT5640_IF3_DAC_SEL_MASK (0x3 << 6)
468 #define RT5640_IF3_DAC_SEL_SFT 468 #define RT5640_IF3_DAC_SEL_SFT 6
469 #define RT5640_IF3_DAC_SEL_NOR 469 #define RT5640_IF3_DAC_SEL_NOR (0x0 << 6)
470 #define RT5640_IF3_DAC_SEL_SWAP 470 #define RT5640_IF3_DAC_SEL_SWAP (0x1 << 6)
471 #define RT5640_IF3_DAC_SEL_L2R 471 #define RT5640_IF3_DAC_SEL_L2R (0x2 << 6)
472 #define RT5640_IF3_DAC_SEL_R2L 472 #define RT5640_IF3_DAC_SEL_R2L (0x3 << 6)
473 #define RT5640_IF3_ADC_SEL_MASK 473 #define RT5640_IF3_ADC_SEL_MASK (0x3 << 4)
474 #define RT5640_IF3_ADC_SEL_SFT 474 #define RT5640_IF3_ADC_SEL_SFT 4
475 #define RT5640_IF3_ADC_SEL_NOR 475 #define RT5640_IF3_ADC_SEL_NOR (0x0 << 4)
476 #define RT5640_IF3_ADC_SEL_SWAP 476 #define RT5640_IF3_ADC_SEL_SWAP (0x1 << 4)
477 #define RT5640_IF3_ADC_SEL_L2R 477 #define RT5640_IF3_ADC_SEL_L2R (0x2 << 4)
478 #define RT5640_IF3_ADC_SEL_R2L 478 #define RT5640_IF3_ADC_SEL_R2L (0x3 << 4)
479 479
480 /* REC Left Mixer Control 1 (0x3b) */ 480 /* REC Left Mixer Control 1 (0x3b) */
481 #define RT5640_G_HP_L_RM_L_MASK 481 #define RT5640_G_HP_L_RM_L_MASK (0x7 << 13)
482 #define RT5640_G_HP_L_RM_L_SFT 482 #define RT5640_G_HP_L_RM_L_SFT 13
483 #define RT5640_G_IN_L_RM_L_MASK 483 #define RT5640_G_IN_L_RM_L_MASK (0x7 << 10)
484 #define RT5640_G_IN_L_RM_L_SFT 484 #define RT5640_G_IN_L_RM_L_SFT 10
485 #define RT5640_G_BST4_RM_L_MASK 485 #define RT5640_G_BST4_RM_L_MASK (0x7 << 7)
486 #define RT5640_G_BST4_RM_L_SFT 486 #define RT5640_G_BST4_RM_L_SFT 7
487 #define RT5640_G_BST3_RM_L_MASK 487 #define RT5640_G_BST3_RM_L_MASK (0x7 << 4)
488 #define RT5640_G_BST3_RM_L_SFT 488 #define RT5640_G_BST3_RM_L_SFT 4
489 #define RT5640_G_BST2_RM_L_MASK 489 #define RT5640_G_BST2_RM_L_MASK (0x7 << 1)
490 #define RT5640_G_BST2_RM_L_SFT 490 #define RT5640_G_BST2_RM_L_SFT 1
491 491
492 /* REC Left Mixer Control 2 (0x3c) */ 492 /* REC Left Mixer Control 2 (0x3c) */
493 #define RT5640_G_BST1_RM_L_MASK 493 #define RT5640_G_BST1_RM_L_MASK (0x7 << 13)
494 #define RT5640_G_BST1_RM_L_SFT 494 #define RT5640_G_BST1_RM_L_SFT 13
495 #define RT5640_G_OM_L_RM_L_MASK 495 #define RT5640_G_OM_L_RM_L_MASK (0x7 << 10)
496 #define RT5640_G_OM_L_RM_L_SFT 496 #define RT5640_G_OM_L_RM_L_SFT 10
497 #define RT5640_M_HP_L_RM_L 497 #define RT5640_M_HP_L_RM_L (0x1 << 6)
498 #define RT5640_M_HP_L_RM_L_SFT 498 #define RT5640_M_HP_L_RM_L_SFT 6
499 #define RT5640_M_IN_L_RM_L 499 #define RT5640_M_IN_L_RM_L (0x1 << 5)
500 #define RT5640_M_IN_L_RM_L_SFT 500 #define RT5640_M_IN_L_RM_L_SFT 5
501 #define RT5640_M_BST4_RM_L 501 #define RT5640_M_BST4_RM_L (0x1 << 4)
502 #define RT5640_M_BST4_RM_L_SFT 502 #define RT5640_M_BST4_RM_L_SFT 4
503 #define RT5640_M_BST3_RM_L 503 #define RT5640_M_BST3_RM_L (0x1 << 3)
504 #define RT5640_M_BST3_RM_L_SFT 504 #define RT5640_M_BST3_RM_L_SFT 3
505 #define RT5640_M_BST2_RM_L 505 #define RT5640_M_BST2_RM_L (0x1 << 2)
506 #define RT5640_M_BST2_RM_L_SFT 506 #define RT5640_M_BST2_RM_L_SFT 2
507 #define RT5640_M_BST1_RM_L 507 #define RT5640_M_BST1_RM_L (0x1 << 1)
508 #define RT5640_M_BST1_RM_L_SFT 508 #define RT5640_M_BST1_RM_L_SFT 1
509 #define RT5640_M_OM_L_RM_L 509 #define RT5640_M_OM_L_RM_L (0x1)
510 #define RT5640_M_OM_L_RM_L_SFT 510 #define RT5640_M_OM_L_RM_L_SFT 0
511 511
512 /* REC Right Mixer Control 1 (0x3d) */ 512 /* REC Right Mixer Control 1 (0x3d) */
513 #define RT5640_G_HP_R_RM_R_MASK 513 #define RT5640_G_HP_R_RM_R_MASK (0x7 << 13)
514 #define RT5640_G_HP_R_RM_R_SFT 514 #define RT5640_G_HP_R_RM_R_SFT 13
515 #define RT5640_G_IN_R_RM_R_MASK 515 #define RT5640_G_IN_R_RM_R_MASK (0x7 << 10)
516 #define RT5640_G_IN_R_RM_R_SFT 516 #define RT5640_G_IN_R_RM_R_SFT 10
517 #define RT5640_G_BST4_RM_R_MASK 517 #define RT5640_G_BST4_RM_R_MASK (0x7 << 7)
518 #define RT5640_G_BST4_RM_R_SFT 518 #define RT5640_G_BST4_RM_R_SFT 7
519 #define RT5640_G_BST3_RM_R_MASK 519 #define RT5640_G_BST3_RM_R_MASK (0x7 << 4)
520 #define RT5640_G_BST3_RM_R_SFT 520 #define RT5640_G_BST3_RM_R_SFT 4
521 #define RT5640_G_BST2_RM_R_MASK 521 #define RT5640_G_BST2_RM_R_MASK (0x7 << 1)
522 #define RT5640_G_BST2_RM_R_SFT 522 #define RT5640_G_BST2_RM_R_SFT 1
523 523
524 /* REC Right Mixer Control 2 (0x3e) */ 524 /* REC Right Mixer Control 2 (0x3e) */
525 #define RT5640_G_BST1_RM_R_MASK 525 #define RT5640_G_BST1_RM_R_MASK (0x7 << 13)
526 #define RT5640_G_BST1_RM_R_SFT 526 #define RT5640_G_BST1_RM_R_SFT 13
527 #define RT5640_G_OM_R_RM_R_MASK 527 #define RT5640_G_OM_R_RM_R_MASK (0x7 << 10)
528 #define RT5640_G_OM_R_RM_R_SFT 528 #define RT5640_G_OM_R_RM_R_SFT 10
529 #define RT5640_M_HP_R_RM_R 529 #define RT5640_M_HP_R_RM_R (0x1 << 6)
530 #define RT5640_M_HP_R_RM_R_SFT 530 #define RT5640_M_HP_R_RM_R_SFT 6
531 #define RT5640_M_IN_R_RM_R 531 #define RT5640_M_IN_R_RM_R (0x1 << 5)
532 #define RT5640_M_IN_R_RM_R_SFT 532 #define RT5640_M_IN_R_RM_R_SFT 5
533 #define RT5640_M_BST4_RM_R 533 #define RT5640_M_BST4_RM_R (0x1 << 4)
534 #define RT5640_M_BST4_RM_R_SFT 534 #define RT5640_M_BST4_RM_R_SFT 4
535 #define RT5640_M_BST3_RM_R 535 #define RT5640_M_BST3_RM_R (0x1 << 3)
536 #define RT5640_M_BST3_RM_R_SFT 536 #define RT5640_M_BST3_RM_R_SFT 3
537 #define RT5640_M_BST2_RM_R 537 #define RT5640_M_BST2_RM_R (0x1 << 2)
538 #define RT5640_M_BST2_RM_R_SFT 538 #define RT5640_M_BST2_RM_R_SFT 2
539 #define RT5640_M_BST1_RM_R 539 #define RT5640_M_BST1_RM_R (0x1 << 1)
540 #define RT5640_M_BST1_RM_R_SFT 540 #define RT5640_M_BST1_RM_R_SFT 1
541 #define RT5640_M_OM_R_RM_R 541 #define RT5640_M_OM_R_RM_R (0x1)
542 #define RT5640_M_OM_R_RM_R_SFT 542 #define RT5640_M_OM_R_RM_R_SFT 0
543 543
544 /* HPMIX Control (0x45) */ 544 /* HPMIX Control (0x45) */
545 #define RT5640_M_DAC2_HM 545 #define RT5640_M_DAC2_HM (0x1 << 15)
546 #define RT5640_M_DAC2_HM_SFT 546 #define RT5640_M_DAC2_HM_SFT 15
547 #define RT5640_M_DAC1_HM 547 #define RT5640_M_DAC1_HM (0x1 << 14)
548 #define RT5640_M_DAC1_HM_SFT 548 #define RT5640_M_DAC1_HM_SFT 14
549 #define RT5640_M_HPVOL_HM 549 #define RT5640_M_HPVOL_HM (0x1 << 13)
550 #define RT5640_M_HPVOL_HM_SFT 550 #define RT5640_M_HPVOL_HM_SFT 13
551 #define RT5640_G_HPOMIX_MASK 551 #define RT5640_G_HPOMIX_MASK (0x1 << 12)
552 #define RT5640_G_HPOMIX_SFT 552 #define RT5640_G_HPOMIX_SFT 12
553 553
554 /* SPK Left Mixer Control (0x46) */ 554 /* SPK Left Mixer Control (0x46) */
555 #define RT5640_G_RM_L_SM_L_MASK 555 #define RT5640_G_RM_L_SM_L_MASK (0x3 << 14)
556 #define RT5640_G_RM_L_SM_L_SFT 556 #define RT5640_G_RM_L_SM_L_SFT 14
557 #define RT5640_G_IN_L_SM_L_MASK 557 #define RT5640_G_IN_L_SM_L_MASK (0x3 << 12)
558 #define RT5640_G_IN_L_SM_L_SFT 558 #define RT5640_G_IN_L_SM_L_SFT 12
559 #define RT5640_G_DAC_L1_SM_L_MASK 559 #define RT5640_G_DAC_L1_SM_L_MASK (0x3 << 10)
560 #define RT5640_G_DAC_L1_SM_L_SFT 560 #define RT5640_G_DAC_L1_SM_L_SFT 10
561 #define RT5640_G_DAC_L2_SM_L_MASK 561 #define RT5640_G_DAC_L2_SM_L_MASK (0x3 << 8)
562 #define RT5640_G_DAC_L2_SM_L_SFT 562 #define RT5640_G_DAC_L2_SM_L_SFT 8
563 #define RT5640_G_OM_L_SM_L_MASK 563 #define RT5640_G_OM_L_SM_L_MASK (0x3 << 6)
564 #define RT5640_G_OM_L_SM_L_SFT 564 #define RT5640_G_OM_L_SM_L_SFT 6
565 #define RT5640_M_RM_L_SM_L 565 #define RT5640_M_RM_L_SM_L (0x1 << 5)
566 #define RT5640_M_RM_L_SM_L_SFT 566 #define RT5640_M_RM_L_SM_L_SFT 5
567 #define RT5640_M_IN_L_SM_L 567 #define RT5640_M_IN_L_SM_L (0x1 << 4)
568 #define RT5640_M_IN_L_SM_L_SFT 568 #define RT5640_M_IN_L_SM_L_SFT 4
569 #define RT5640_M_DAC_L1_SM_L 569 #define RT5640_M_DAC_L1_SM_L (0x1 << 3)
570 #define RT5640_M_DAC_L1_SM_L_SFT 570 #define RT5640_M_DAC_L1_SM_L_SFT 3
571 #define RT5640_M_DAC_L2_SM_L 571 #define RT5640_M_DAC_L2_SM_L (0x1 << 2)
572 #define RT5640_M_DAC_L2_SM_L_SFT 572 #define RT5640_M_DAC_L2_SM_L_SFT 2
573 #define RT5640_M_OM_L_SM_L 573 #define RT5640_M_OM_L_SM_L (0x1 << 1)
574 #define RT5640_M_OM_L_SM_L_SFT 1 574 #define RT5640_M_OM_L_SM_L_SFT 1
575 575
576 /* SPK Right Mixer Control (0x47) */ 576 /* SPK Right Mixer Control (0x47) */
577 #define RT5640_G_RM_R_SM_R_MASK 577 #define RT5640_G_RM_R_SM_R_MASK (0x3 << 14)
578 #define RT5640_G_RM_R_SM_R_SFT 578 #define RT5640_G_RM_R_SM_R_SFT 14
579 #define RT5640_G_IN_R_SM_R_MASK 579 #define RT5640_G_IN_R_SM_R_MASK (0x3 << 12)
580 #define RT5640_G_IN_R_SM_R_SFT 580 #define RT5640_G_IN_R_SM_R_SFT 12
581 #define RT5640_G_DAC_R1_SM_R_MASK 581 #define RT5640_G_DAC_R1_SM_R_MASK (0x3 << 10)
582 #define RT5640_G_DAC_R1_SM_R_SFT 582 #define RT5640_G_DAC_R1_SM_R_SFT 10
583 #define RT5640_G_DAC_R2_SM_R_MASK 583 #define RT5640_G_DAC_R2_SM_R_MASK (0x3 << 8)
584 #define RT5640_G_DAC_R2_SM_R_SFT 584 #define RT5640_G_DAC_R2_SM_R_SFT 8
585 #define RT5640_G_OM_R_SM_R_MASK 585 #define RT5640_G_OM_R_SM_R_MASK (0x3 << 6)
586 #define RT5640_G_OM_R_SM_R_SFT 586 #define RT5640_G_OM_R_SM_R_SFT 6
587 #define RT5640_M_RM_R_SM_R 587 #define RT5640_M_RM_R_SM_R (0x1 << 5)
588 #define RT5640_M_RM_R_SM_R_SFT 588 #define RT5640_M_RM_R_SM_R_SFT 5
589 #define RT5640_M_IN_R_SM_R 589 #define RT5640_M_IN_R_SM_R (0x1 << 4)
590 #define RT5640_M_IN_R_SM_R_SFT 590 #define RT5640_M_IN_R_SM_R_SFT 4
591 #define RT5640_M_DAC_R1_SM_R 591 #define RT5640_M_DAC_R1_SM_R (0x1 << 3)
592 #define RT5640_M_DAC_R1_SM_R_SFT 592 #define RT5640_M_DAC_R1_SM_R_SFT 3
593 #define RT5640_M_DAC_R2_SM_R 593 #define RT5640_M_DAC_R2_SM_R (0x1 << 2)
594 #define RT5640_M_DAC_R2_SM_R_SFT 594 #define RT5640_M_DAC_R2_SM_R_SFT 2
595 #define RT5640_M_OM_R_SM_R 595 #define RT5640_M_OM_R_SM_R (0x1 << 1)
596 #define RT5640_M_OM_R_SM_R_SFT 596 #define RT5640_M_OM_R_SM_R_SFT 1
597 597
598 /* SPOLMIX Control (0x48) */ 598 /* SPOLMIX Control (0x48) */
599 #define RT5640_M_DAC_R1_SPM_L 599 #define RT5640_M_DAC_R1_SPM_L (0x1 << 15)
600 #define RT5640_M_DAC_R1_SPM_L_SFT 600 #define RT5640_M_DAC_R1_SPM_L_SFT 15
601 #define RT5640_M_DAC_L1_SPM_L 601 #define RT5640_M_DAC_L1_SPM_L (0x1 << 14)
602 #define RT5640_M_DAC_L1_SPM_L_SFT 602 #define RT5640_M_DAC_L1_SPM_L_SFT 14
603 #define RT5640_M_SV_R_SPM_L 603 #define RT5640_M_SV_R_SPM_L (0x1 << 13)
604 #define RT5640_M_SV_R_SPM_L_SFT 604 #define RT5640_M_SV_R_SPM_L_SFT 13
605 #define RT5640_M_SV_L_SPM_L 605 #define RT5640_M_SV_L_SPM_L (0x1 << 12)
606 #define RT5640_M_SV_L_SPM_L_SFT 606 #define RT5640_M_SV_L_SPM_L_SFT 12
607 #define RT5640_M_BST1_SPM_L 607 #define RT5640_M_BST1_SPM_L (0x1 << 11)
608 #define RT5640_M_BST1_SPM_L_SFT 608 #define RT5640_M_BST1_SPM_L_SFT 11
609 609
610 /* SPORMIX Control (0x49) */ 610 /* SPORMIX Control (0x49) */
611 #define RT5640_M_DAC_R1_SPM_R 611 #define RT5640_M_DAC_R1_SPM_R (0x1 << 13)
612 #define RT5640_M_DAC_R1_SPM_R_SFT 612 #define RT5640_M_DAC_R1_SPM_R_SFT 13
613 #define RT5640_M_SV_R_SPM_R 613 #define RT5640_M_SV_R_SPM_R (0x1 << 12)
614 #define RT5640_M_SV_R_SPM_R_SFT 614 #define RT5640_M_SV_R_SPM_R_SFT 12
615 #define RT5640_M_BST1_SPM_R 615 #define RT5640_M_BST1_SPM_R (0x1 << 11)
616 #define RT5640_M_BST1_SPM_R_SFT 616 #define RT5640_M_BST1_SPM_R_SFT 11
617 617
618 /* SPOLMIX / SPORMIX Ratio Control (0x4a) */ 618 /* SPOLMIX / SPORMIX Ratio Control (0x4a) */
619 #define RT5640_SPO_CLSD_RATIO_MASK 619 #define RT5640_SPO_CLSD_RATIO_MASK (0x7)
620 #define RT5640_SPO_CLSD_RATIO_SFT 620 #define RT5640_SPO_CLSD_RATIO_SFT 0
621 621
622 /* Mono Output Mixer Control (0x4c) */ 622 /* Mono Output Mixer Control (0x4c) */
623 #define RT5640_M_DAC_R2_MM 623 #define RT5640_M_DAC_R2_MM (0x1 << 15)
624 #define RT5640_M_DAC_R2_MM_SFT 624 #define RT5640_M_DAC_R2_MM_SFT 15
625 #define RT5640_M_DAC_L2_MM 625 #define RT5640_M_DAC_L2_MM (0x1 << 14)
626 #define RT5640_M_DAC_L2_MM_SFT 626 #define RT5640_M_DAC_L2_MM_SFT 14
627 #define RT5640_M_OV_R_MM 627 #define RT5640_M_OV_R_MM (0x1 << 13)
628 #define RT5640_M_OV_R_MM_SFT 628 #define RT5640_M_OV_R_MM_SFT 13
629 #define RT5640_M_OV_L_MM 629 #define RT5640_M_OV_L_MM (0x1 << 12)
630 #define RT5640_M_OV_L_MM_SFT 630 #define RT5640_M_OV_L_MM_SFT 12
631 #define RT5640_M_BST1_MM 631 #define RT5640_M_BST1_MM (0x1 << 11)
632 #define RT5640_M_BST1_MM_SFT 632 #define RT5640_M_BST1_MM_SFT 11
633 #define RT5640_G_MONOMIX_MASK 633 #define RT5640_G_MONOMIX_MASK (0x1 << 10)
634 #define RT5640_G_MONOMIX_SFT 634 #define RT5640_G_MONOMIX_SFT 10
635 635
636 /* Output Left Mixer Control 1 (0x4d) */ 636 /* Output Left Mixer Control 1 (0x4d) */
637 #define RT5640_G_BST3_OM_L_MASK 637 #define RT5640_G_BST3_OM_L_MASK (0x7 << 13)
638 #define RT5640_G_BST3_OM_L_SFT 638 #define RT5640_G_BST3_OM_L_SFT 13
639 #define RT5640_G_BST2_OM_L_MASK 639 #define RT5640_G_BST2_OM_L_MASK (0x7 << 10)
640 #define RT5640_G_BST2_OM_L_SFT 640 #define RT5640_G_BST2_OM_L_SFT 10
641 #define RT5640_G_BST1_OM_L_MASK 641 #define RT5640_G_BST1_OM_L_MASK (0x7 << 7)
642 #define RT5640_G_BST1_OM_L_SFT 642 #define RT5640_G_BST1_OM_L_SFT 7
643 #define RT5640_G_IN_L_OM_L_MASK 643 #define RT5640_G_IN_L_OM_L_MASK (0x7 << 4)
644 #define RT5640_G_IN_L_OM_L_SFT 644 #define RT5640_G_IN_L_OM_L_SFT 4
645 #define RT5640_G_RM_L_OM_L_MASK 645 #define RT5640_G_RM_L_OM_L_MASK (0x7 << 1)
646 #define RT5640_G_RM_L_OM_L_SFT 646 #define RT5640_G_RM_L_OM_L_SFT 1
647 647
648 /* Output Left Mixer Control 2 (0x4e) */ 648 /* Output Left Mixer Control 2 (0x4e) */
649 #define RT5640_G_DAC_R2_OM_L_MASK 649 #define RT5640_G_DAC_R2_OM_L_MASK (0x7 << 13)
650 #define RT5640_G_DAC_R2_OM_L_SFT 650 #define RT5640_G_DAC_R2_OM_L_SFT 13
651 #define RT5640_G_DAC_L2_OM_L_MASK 651 #define RT5640_G_DAC_L2_OM_L_MASK (0x7 << 10)
652 #define RT5640_G_DAC_L2_OM_L_SFT 652 #define RT5640_G_DAC_L2_OM_L_SFT 10
653 #define RT5640_G_DAC_L1_OM_L_MASK 653 #define RT5640_G_DAC_L1_OM_L_MASK (0x7 << 7)
654 #define RT5640_G_DAC_L1_OM_L_SFT 654 #define RT5640_G_DAC_L1_OM_L_SFT 7
655 655
656 /* Output Left Mixer Control 3 (0x4f) */ 656 /* Output Left Mixer Control 3 (0x4f) */
657 #define RT5640_M_SM_L_OM_L 657 #define RT5640_M_SM_L_OM_L (0x1 << 8)
658 #define RT5640_M_SM_L_OM_L_SFT 658 #define RT5640_M_SM_L_OM_L_SFT 8
659 #define RT5640_M_BST3_OM_L 659 #define RT5640_M_BST3_OM_L (0x1 << 7)
660 #define RT5640_M_BST3_OM_L_SFT 660 #define RT5640_M_BST3_OM_L_SFT 7
661 #define RT5640_M_BST2_OM_L 661 #define RT5640_M_BST2_OM_L (0x1 << 6)
662 #define RT5640_M_BST2_OM_L_SFT 662 #define RT5640_M_BST2_OM_L_SFT 6
663 #define RT5640_M_BST1_OM_L 663 #define RT5640_M_BST1_OM_L (0x1 << 5)
664 #define RT5640_M_BST1_OM_L_SFT 664 #define RT5640_M_BST1_OM_L_SFT 5
665 #define RT5640_M_IN_L_OM_L 665 #define RT5640_M_IN_L_OM_L (0x1 << 4)
666 #define RT5640_M_IN_L_OM_L_SFT 666 #define RT5640_M_IN_L_OM_L_SFT 4
667 #define RT5640_M_RM_L_OM_L 667 #define RT5640_M_RM_L_OM_L (0x1 << 3)
668 #define RT5640_M_RM_L_OM_L_SFT 668 #define RT5640_M_RM_L_OM_L_SFT 3
669 #define RT5640_M_DAC_R2_OM_L 669 #define RT5640_M_DAC_R2_OM_L (0x1 << 2)
670 #define RT5640_M_DAC_R2_OM_L_SFT 670 #define RT5640_M_DAC_R2_OM_L_SFT 2
671 #define RT5640_M_DAC_L2_OM_L 671 #define RT5640_M_DAC_L2_OM_L (0x1 << 1)
672 #define RT5640_M_DAC_L2_OM_L_SFT 672 #define RT5640_M_DAC_L2_OM_L_SFT 1
673 #define RT5640_M_DAC_L1_OM_L 673 #define RT5640_M_DAC_L1_OM_L (0x1)
674 #define RT5640_M_DAC_L1_OM_L_SFT 674 #define RT5640_M_DAC_L1_OM_L_SFT 0
675 675
676 /* Output Right Mixer Control 1 (0x50) */ 676 /* Output Right Mixer Control 1 (0x50) */
677 #define RT5640_G_BST4_OM_R_MASK 677 #define RT5640_G_BST4_OM_R_MASK (0x7 << 13)
678 #define RT5640_G_BST4_OM_R_SFT 678 #define RT5640_G_BST4_OM_R_SFT 13
679 #define RT5640_G_BST2_OM_R_MASK 679 #define RT5640_G_BST2_OM_R_MASK (0x7 << 10)
680 #define RT5640_G_BST2_OM_R_SFT 680 #define RT5640_G_BST2_OM_R_SFT 10
681 #define RT5640_G_BST1_OM_R_MASK 681 #define RT5640_G_BST1_OM_R_MASK (0x7 << 7)
682 #define RT5640_G_BST1_OM_R_SFT 682 #define RT5640_G_BST1_OM_R_SFT 7
683 #define RT5640_G_IN_R_OM_R_MASK 683 #define RT5640_G_IN_R_OM_R_MASK (0x7 << 4)
684 #define RT5640_G_IN_R_OM_R_SFT 684 #define RT5640_G_IN_R_OM_R_SFT 4
685 #define RT5640_G_RM_R_OM_R_MASK 685 #define RT5640_G_RM_R_OM_R_MASK (0x7 << 1)
686 #define RT5640_G_RM_R_OM_R_SFT 686 #define RT5640_G_RM_R_OM_R_SFT 1
687 687
688 /* Output Right Mixer Control 2 (0x51) */ 688 /* Output Right Mixer Control 2 (0x51) */
689 #define RT5640_G_DAC_L2_OM_R_MASK 689 #define RT5640_G_DAC_L2_OM_R_MASK (0x7 << 13)
690 #define RT5640_G_DAC_L2_OM_R_SFT 690 #define RT5640_G_DAC_L2_OM_R_SFT 13
691 #define RT5640_G_DAC_R2_OM_R_MASK 691 #define RT5640_G_DAC_R2_OM_R_MASK (0x7 << 10)
692 #define RT5640_G_DAC_R2_OM_R_SFT 692 #define RT5640_G_DAC_R2_OM_R_SFT 10
693 #define RT5640_G_DAC_R1_OM_R_MASK 693 #define RT5640_G_DAC_R1_OM_R_MASK (0x7 << 7)
694 #define RT5640_G_DAC_R1_OM_R_SFT 694 #define RT5640_G_DAC_R1_OM_R_SFT 7
695 695
696 /* Output Right Mixer Control 3 (0x52) */ 696 /* Output Right Mixer Control 3 (0x52) */
697 #define RT5640_M_SM_L_OM_R 697 #define RT5640_M_SM_L_OM_R (0x1 << 8)
698 #define RT5640_M_SM_L_OM_R_SFT 698 #define RT5640_M_SM_L_OM_R_SFT 8
699 #define RT5640_M_BST4_OM_R 699 #define RT5640_M_BST4_OM_R (0x1 << 7)
700 #define RT5640_M_BST4_OM_R_SFT 700 #define RT5640_M_BST4_OM_R_SFT 7
701 #define RT5640_M_BST2_OM_R 701 #define RT5640_M_BST2_OM_R (0x1 << 6)
702 #define RT5640_M_BST2_OM_R_SFT 702 #define RT5640_M_BST2_OM_R_SFT 6
703 #define RT5640_M_BST1_OM_R 703 #define RT5640_M_BST1_OM_R (0x1 << 5)
704 #define RT5640_M_BST1_OM_R_SFT 704 #define RT5640_M_BST1_OM_R_SFT 5
705 #define RT5640_M_IN_R_OM_R 705 #define RT5640_M_IN_R_OM_R (0x1 << 4)
706 #define RT5640_M_IN_R_OM_R_SFT 706 #define RT5640_M_IN_R_OM_R_SFT 4
707 #define RT5640_M_RM_R_OM_R 707 #define RT5640_M_RM_R_OM_R (0x1 << 3)
708 #define RT5640_M_RM_R_OM_R_SFT 708 #define RT5640_M_RM_R_OM_R_SFT 3
709 #define RT5640_M_DAC_L2_OM_R 709 #define RT5640_M_DAC_L2_OM_R (0x1 << 2)
710 #define RT5640_M_DAC_L2_OM_R_SFT 710 #define RT5640_M_DAC_L2_OM_R_SFT 2
711 #define RT5640_M_DAC_R2_OM_R 711 #define RT5640_M_DAC_R2_OM_R (0x1 << 1)
712 #define RT5640_M_DAC_R2_OM_R_SFT 712 #define RT5640_M_DAC_R2_OM_R_SFT 1
713 #define RT5640_M_DAC_R1_OM_R 713 #define RT5640_M_DAC_R1_OM_R (0x1)
714 #define RT5640_M_DAC_R1_OM_R_SFT 714 #define RT5640_M_DAC_R1_OM_R_SFT 0
715 715
716 /* LOUT Mixer Control (0x53) */ 716 /* LOUT Mixer Control (0x53) */
717 #define RT5640_M_DAC_L1_LM 717 #define RT5640_M_DAC_L1_LM (0x1 << 15)
718 #define RT5640_M_DAC_L1_LM_SFT 718 #define RT5640_M_DAC_L1_LM_SFT 15
719 #define RT5640_M_DAC_R1_LM 719 #define RT5640_M_DAC_R1_LM (0x1 << 14)
720 #define RT5640_M_DAC_R1_LM_SFT 720 #define RT5640_M_DAC_R1_LM_SFT 14
721 #define RT5640_M_OV_L_LM 721 #define RT5640_M_OV_L_LM (0x1 << 13)
722 #define RT5640_M_OV_L_LM_SFT 722 #define RT5640_M_OV_L_LM_SFT 13
723 #define RT5640_M_OV_R_LM 723 #define RT5640_M_OV_R_LM (0x1 << 12)
724 #define RT5640_M_OV_R_LM_SFT 724 #define RT5640_M_OV_R_LM_SFT 12
725 #define RT5640_G_LOUTMIX_MASK 725 #define RT5640_G_LOUTMIX_MASK (0x1 << 11)
726 #define RT5640_G_LOUTMIX_SFT 726 #define RT5640_G_LOUTMIX_SFT 11
727 727
728 /* Power Management for Digital 1 (0x61) */ 728 /* Power Management for Digital 1 (0x61) */
729 #define RT5640_PWR_I2S1 729 #define RT5640_PWR_I2S1 (0x1 << 15)
730 #define RT5640_PWR_I2S1_BIT 730 #define RT5640_PWR_I2S1_BIT 15
731 #define RT5640_PWR_I2S2 731 #define RT5640_PWR_I2S2 (0x1 << 14)
732 #define RT5640_PWR_I2S2_BIT 732 #define RT5640_PWR_I2S2_BIT 14
733 #define RT5640_PWR_DAC_L1 733 #define RT5640_PWR_DAC_L1 (0x1 << 12)
734 #define RT5640_PWR_DAC_L1_BIT 734 #define RT5640_PWR_DAC_L1_BIT 12
735 #define RT5640_PWR_DAC_R1 735 #define RT5640_PWR_DAC_R1 (0x1 << 11)
736 #define RT5640_PWR_DAC_R1_BIT 736 #define RT5640_PWR_DAC_R1_BIT 11
737 #define RT5640_PWR_DAC_L2 737 #define RT5640_PWR_DAC_L2 (0x1 << 7)
738 #define RT5640_PWR_DAC_L2_BIT 738 #define RT5640_PWR_DAC_L2_BIT 7
739 #define RT5640_PWR_DAC_R2 739 #define RT5640_PWR_DAC_R2 (0x1 << 6)
740 #define RT5640_PWR_DAC_R2_BIT 740 #define RT5640_PWR_DAC_R2_BIT 6
741 #define RT5640_PWR_ADC_L 741 #define RT5640_PWR_ADC_L (0x1 << 2)
742 #define RT5640_PWR_ADC_L_BIT 742 #define RT5640_PWR_ADC_L_BIT 2
743 #define RT5640_PWR_ADC_R 743 #define RT5640_PWR_ADC_R (0x1 << 1)
744 #define RT5640_PWR_ADC_R_BIT 744 #define RT5640_PWR_ADC_R_BIT 1
745 #define RT5640_PWR_CLS_D 745 #define RT5640_PWR_CLS_D (0x1)
746 #define RT5640_PWR_CLS_D_BIT 746 #define RT5640_PWR_CLS_D_BIT 0
747 747
748 /* Power Management for Digital 2 (0x62) */ 748 /* Power Management for Digital 2 (0x62) */
749 #define RT5640_PWR_ADC_SF 749 #define RT5640_PWR_ADC_SF (0x1 << 15)
750 #define RT5640_PWR_ADC_SF_BIT 750 #define RT5640_PWR_ADC_SF_BIT 15
751 #define RT5640_PWR_ADC_MF_L 751 #define RT5640_PWR_ADC_MF_L (0x1 << 14)
752 #define RT5640_PWR_ADC_MF_L_BIT 752 #define RT5640_PWR_ADC_MF_L_BIT 14
753 #define RT5640_PWR_ADC_MF_R 753 #define RT5640_PWR_ADC_MF_R (0x1 << 13)
754 #define RT5640_PWR_ADC_MF_R_BIT 754 #define RT5640_PWR_ADC_MF_R_BIT 13
755 #define RT5640_PWR_I2S_DSP 755 #define RT5640_PWR_I2S_DSP (0x1 << 12)
756 #define RT5640_PWR_I2S_DSP_BIT 756 #define RT5640_PWR_I2S_DSP_BIT 12
757 757
758 /* Power Management for Analog 1 (0x63) */ 758 /* Power Management for Analog 1 (0x63) */
759 #define RT5640_PWR_VREF1 759 #define RT5640_PWR_VREF1 (0x1 << 15)
760 #define RT5640_PWR_VREF1_BIT 760 #define RT5640_PWR_VREF1_BIT 15
761 #define RT5640_PWR_FV1 761 #define RT5640_PWR_FV1 (0x1 << 14)
762 #define RT5640_PWR_FV1_BIT 762 #define RT5640_PWR_FV1_BIT 14
763 #define RT5640_PWR_MB 763 #define RT5640_PWR_MB (0x1 << 13)
764 #define RT5640_PWR_MB_BIT 764 #define RT5640_PWR_MB_BIT 13
765 #define RT5640_PWR_LM 765 #define RT5640_PWR_LM (0x1 << 12)
766 #define RT5640_PWR_LM_BIT 766 #define RT5640_PWR_LM_BIT 12
767 #define RT5640_PWR_BG 767 #define RT5640_PWR_BG (0x1 << 11)
768 #define RT5640_PWR_BG_BIT 768 #define RT5640_PWR_BG_BIT 11
769 #define RT5640_PWR_MM 769 #define RT5640_PWR_MM (0x1 << 10)
770 #define RT5640_PWR_MM_BIT 770 #define RT5640_PWR_MM_BIT 10
771 #define RT5640_PWR_MA 771 #define RT5640_PWR_MA (0x1 << 8)
772 #define RT5640_PWR_MA_BIT 772 #define RT5640_PWR_MA_BIT 8
773 #define RT5640_PWR_HP_L 773 #define RT5640_PWR_HP_L (0x1 << 7)
774 #define RT5640_PWR_HP_L_BIT 774 #define RT5640_PWR_HP_L_BIT 7
775 #define RT5640_PWR_HP_R 775 #define RT5640_PWR_HP_R (0x1 << 6)
776 #define RT5640_PWR_HP_R_BIT 776 #define RT5640_PWR_HP_R_BIT 6
777 #define RT5640_PWR_HA 777 #define RT5640_PWR_HA (0x1 << 5)
778 #define RT5640_PWR_HA_BIT 778 #define RT5640_PWR_HA_BIT 5
779 #define RT5640_PWR_VREF2 779 #define RT5640_PWR_VREF2 (0x1 << 4)
780 #define RT5640_PWR_VREF2_BIT 780 #define RT5640_PWR_VREF2_BIT 4
781 #define RT5640_PWR_FV2 781 #define RT5640_PWR_FV2 (0x1 << 3)
782 #define RT5640_PWR_FV2_BIT 782 #define RT5640_PWR_FV2_BIT 3
783 #define RT5640_PWR_LDO2 783 #define RT5640_PWR_LDO2 (0x1 << 2)
784 #define RT5640_PWR_LDO2_BIT 784 #define RT5640_PWR_LDO2_BIT 2
785 785
786 /* Power Management for Analog 2 (0x64) */ 786 /* Power Management for Analog 2 (0x64) */
787 #define RT5640_PWR_BST1 787 #define RT5640_PWR_BST1 (0x1 << 15)
788 #define RT5640_PWR_BST1_BIT 788 #define RT5640_PWR_BST1_BIT 15
789 #define RT5640_PWR_BST2 789 #define RT5640_PWR_BST2 (0x1 << 14)
790 #define RT5640_PWR_BST2_BIT 790 #define RT5640_PWR_BST2_BIT 14
791 #define RT5640_PWR_BST3 791 #define RT5640_PWR_BST3 (0x1 << 13)
792 #define RT5640_PWR_BST3_BIT 792 #define RT5640_PWR_BST3_BIT 13
793 #define RT5640_PWR_BST4 793 #define RT5640_PWR_BST4 (0x1 << 12)
794 #define RT5640_PWR_BST4_BIT 794 #define RT5640_PWR_BST4_BIT 12
795 #define RT5640_PWR_MB1 795 #define RT5640_PWR_MB1 (0x1 << 11)
796 #define RT5640_PWR_MB1_BIT 796 #define RT5640_PWR_MB1_BIT 11
797 #define RT5640_PWR_PLL 797 #define RT5640_PWR_PLL (0x1 << 9)
798 #define RT5640_PWR_PLL_BIT 798 #define RT5640_PWR_PLL_BIT 9
799 799
800 /* Power Management for Mixer (0x65) */ 800 /* Power Management for Mixer (0x65) */
801 #define RT5640_PWR_OM_L 801 #define RT5640_PWR_OM_L (0x1 << 15)
802 #define RT5640_PWR_OM_L_BIT 802 #define RT5640_PWR_OM_L_BIT 15
803 #define RT5640_PWR_OM_R 803 #define RT5640_PWR_OM_R (0x1 << 14)
804 #define RT5640_PWR_OM_R_BIT 804 #define RT5640_PWR_OM_R_BIT 14
805 #define RT5640_PWR_SM_L 805 #define RT5640_PWR_SM_L (0x1 << 13)
806 #define RT5640_PWR_SM_L_BIT 806 #define RT5640_PWR_SM_L_BIT 13
807 #define RT5640_PWR_SM_R 807 #define RT5640_PWR_SM_R (0x1 << 12)
808 #define RT5640_PWR_SM_R_BIT 808 #define RT5640_PWR_SM_R_BIT 12
809 #define RT5640_PWR_RM_L 809 #define RT5640_PWR_RM_L (0x1 << 11)
810 #define RT5640_PWR_RM_L_BIT 810 #define RT5640_PWR_RM_L_BIT 11
811 #define RT5640_PWR_RM_R 811 #define RT5640_PWR_RM_R (0x1 << 10)
812 #define RT5640_PWR_RM_R_BIT 812 #define RT5640_PWR_RM_R_BIT 10
813 813
814 /* Power Management for Volume (0x66) */ 814 /* Power Management for Volume (0x66) */
815 #define RT5640_PWR_SV_L 815 #define RT5640_PWR_SV_L (0x1 << 15)
816 #define RT5640_PWR_SV_L_BIT 816 #define RT5640_PWR_SV_L_BIT 15
817 #define RT5640_PWR_SV_R 817 #define RT5640_PWR_SV_R (0x1 << 14)
818 #define RT5640_PWR_SV_R_BIT 818 #define RT5640_PWR_SV_R_BIT 14
819 #define RT5640_PWR_OV_L 819 #define RT5640_PWR_OV_L (0x1 << 13)
820 #define RT5640_PWR_OV_L_BIT 820 #define RT5640_PWR_OV_L_BIT 13
821 #define RT5640_PWR_OV_R 821 #define RT5640_PWR_OV_R (0x1 << 12)
822 #define RT5640_PWR_OV_R_BIT 822 #define RT5640_PWR_OV_R_BIT 12
823 #define RT5640_PWR_HV_L 823 #define RT5640_PWR_HV_L (0x1 << 11)
824 #define RT5640_PWR_HV_L_BIT 824 #define RT5640_PWR_HV_L_BIT 11
825 #define RT5640_PWR_HV_R 825 #define RT5640_PWR_HV_R (0x1 << 10)
826 #define RT5640_PWR_HV_R_BIT 826 #define RT5640_PWR_HV_R_BIT 10
827 #define RT5640_PWR_IN_L 827 #define RT5640_PWR_IN_L (0x1 << 9)
828 #define RT5640_PWR_IN_L_BIT 828 #define RT5640_PWR_IN_L_BIT 9
829 #define RT5640_PWR_IN_R 829 #define RT5640_PWR_IN_R (0x1 << 8)
830 #define RT5640_PWR_IN_R_BIT 830 #define RT5640_PWR_IN_R_BIT 8
831 831
832 /* I2S1/2/3 Audio Serial Data Port Control (0x 832 /* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71 0x72) */
833 #define RT5640_I2S_MS_MASK 833 #define RT5640_I2S_MS_MASK (0x1 << 15)
834 #define RT5640_I2S_MS_SFT 834 #define RT5640_I2S_MS_SFT 15
835 #define RT5640_I2S_MS_M 835 #define RT5640_I2S_MS_M (0x0 << 15)
836 #define RT5640_I2S_MS_S 836 #define RT5640_I2S_MS_S (0x1 << 15)
837 #define RT5640_I2S_IF_MASK 837 #define RT5640_I2S_IF_MASK (0x7 << 12)
838 #define RT5640_I2S_IF_SFT 838 #define RT5640_I2S_IF_SFT 12
839 #define RT5640_I2S_O_CP_MASK 839 #define RT5640_I2S_O_CP_MASK (0x3 << 10)
840 #define RT5640_I2S_O_CP_SFT 840 #define RT5640_I2S_O_CP_SFT 10
841 #define RT5640_I2S_O_CP_OFF 841 #define RT5640_I2S_O_CP_OFF (0x0 << 10)
842 #define RT5640_I2S_O_CP_U_LAW 842 #define RT5640_I2S_O_CP_U_LAW (0x1 << 10)
843 #define RT5640_I2S_O_CP_A_LAW 843 #define RT5640_I2S_O_CP_A_LAW (0x2 << 10)
844 #define RT5640_I2S_I_CP_MASK 844 #define RT5640_I2S_I_CP_MASK (0x3 << 8)
845 #define RT5640_I2S_I_CP_SFT 845 #define RT5640_I2S_I_CP_SFT 8
846 #define RT5640_I2S_I_CP_OFF 846 #define RT5640_I2S_I_CP_OFF (0x0 << 8)
847 #define RT5640_I2S_I_CP_U_LAW 847 #define RT5640_I2S_I_CP_U_LAW (0x1 << 8)
848 #define RT5640_I2S_I_CP_A_LAW 848 #define RT5640_I2S_I_CP_A_LAW (0x2 << 8)
849 #define RT5640_I2S_BP_MASK 849 #define RT5640_I2S_BP_MASK (0x1 << 7)
850 #define RT5640_I2S_BP_SFT 850 #define RT5640_I2S_BP_SFT 7
851 #define RT5640_I2S_BP_NOR 851 #define RT5640_I2S_BP_NOR (0x0 << 7)
852 #define RT5640_I2S_BP_INV 852 #define RT5640_I2S_BP_INV (0x1 << 7)
853 #define RT5640_I2S_DL_MASK 853 #define RT5640_I2S_DL_MASK (0x3 << 2)
854 #define RT5640_I2S_DL_SFT 854 #define RT5640_I2S_DL_SFT 2
855 #define RT5640_I2S_DL_16 855 #define RT5640_I2S_DL_16 (0x0 << 2)
856 #define RT5640_I2S_DL_20 856 #define RT5640_I2S_DL_20 (0x1 << 2)
857 #define RT5640_I2S_DL_24 857 #define RT5640_I2S_DL_24 (0x2 << 2)
858 #define RT5640_I2S_DL_8 858 #define RT5640_I2S_DL_8 (0x3 << 2)
859 #define RT5640_I2S_DF_MASK 859 #define RT5640_I2S_DF_MASK (0x3)
860 #define RT5640_I2S_DF_SFT 860 #define RT5640_I2S_DF_SFT 0
861 #define RT5640_I2S_DF_I2S 861 #define RT5640_I2S_DF_I2S (0x0)
862 #define RT5640_I2S_DF_LEFT 862 #define RT5640_I2S_DF_LEFT (0x1)
863 #define RT5640_I2S_DF_PCM_A 863 #define RT5640_I2S_DF_PCM_A (0x2)
864 #define RT5640_I2S_DF_PCM_B 864 #define RT5640_I2S_DF_PCM_B (0x3)
865 865
866 /* I2S2 Audio Serial Data Port Control (0x71) 866 /* I2S2 Audio Serial Data Port Control (0x71) */
867 #define RT5640_I2S2_SDI_MASK 867 #define RT5640_I2S2_SDI_MASK (0x1 << 6)
868 #define RT5640_I2S2_SDI_SFT 868 #define RT5640_I2S2_SDI_SFT 6
869 #define RT5640_I2S2_SDI_I2S1 869 #define RT5640_I2S2_SDI_I2S1 (0x0 << 6)
870 #define RT5640_I2S2_SDI_I2S2 870 #define RT5640_I2S2_SDI_I2S2 (0x1 << 6)
871 871
872 /* ADC/DAC Clock Control 1 (0x73) */ 872 /* ADC/DAC Clock Control 1 (0x73) */
873 #define RT5640_I2S_BCLK_MS1_MASK 873 #define RT5640_I2S_BCLK_MS1_MASK (0x1 << 15)
874 #define RT5640_I2S_BCLK_MS1_SFT 874 #define RT5640_I2S_BCLK_MS1_SFT 15
875 #define RT5640_I2S_BCLK_MS1_32 875 #define RT5640_I2S_BCLK_MS1_32 (0x0 << 15)
876 #define RT5640_I2S_BCLK_MS1_64 876 #define RT5640_I2S_BCLK_MS1_64 (0x1 << 15)
877 #define RT5640_I2S_PD1_MASK 877 #define RT5640_I2S_PD1_MASK (0x7 << 12)
878 #define RT5640_I2S_PD1_SFT 878 #define RT5640_I2S_PD1_SFT 12
879 #define RT5640_I2S_PD1_1 879 #define RT5640_I2S_PD1_1 (0x0 << 12)
880 #define RT5640_I2S_PD1_2 880 #define RT5640_I2S_PD1_2 (0x1 << 12)
881 #define RT5640_I2S_PD1_3 881 #define RT5640_I2S_PD1_3 (0x2 << 12)
882 #define RT5640_I2S_PD1_4 882 #define RT5640_I2S_PD1_4 (0x3 << 12)
883 #define RT5640_I2S_PD1_6 883 #define RT5640_I2S_PD1_6 (0x4 << 12)
884 #define RT5640_I2S_PD1_8 884 #define RT5640_I2S_PD1_8 (0x5 << 12)
885 #define RT5640_I2S_PD1_12 885 #define RT5640_I2S_PD1_12 (0x6 << 12)
886 #define RT5640_I2S_PD1_16 886 #define RT5640_I2S_PD1_16 (0x7 << 12)
887 #define RT5640_I2S_BCLK_MS2_MASK 887 #define RT5640_I2S_BCLK_MS2_MASK (0x1 << 11)
888 #define RT5640_I2S_BCLK_MS2_SFT 888 #define RT5640_I2S_BCLK_MS2_SFT 11
889 #define RT5640_I2S_BCLK_MS2_32 889 #define RT5640_I2S_BCLK_MS2_32 (0x0 << 11)
890 #define RT5640_I2S_BCLK_MS2_64 890 #define RT5640_I2S_BCLK_MS2_64 (0x1 << 11)
891 #define RT5640_I2S_PD2_MASK 891 #define RT5640_I2S_PD2_MASK (0x7 << 8)
892 #define RT5640_I2S_PD2_SFT 892 #define RT5640_I2S_PD2_SFT 8
893 #define RT5640_I2S_PD2_1 893 #define RT5640_I2S_PD2_1 (0x0 << 8)
894 #define RT5640_I2S_PD2_2 894 #define RT5640_I2S_PD2_2 (0x1 << 8)
895 #define RT5640_I2S_PD2_3 895 #define RT5640_I2S_PD2_3 (0x2 << 8)
896 #define RT5640_I2S_PD2_4 896 #define RT5640_I2S_PD2_4 (0x3 << 8)
897 #define RT5640_I2S_PD2_6 897 #define RT5640_I2S_PD2_6 (0x4 << 8)
898 #define RT5640_I2S_PD2_8 898 #define RT5640_I2S_PD2_8 (0x5 << 8)
899 #define RT5640_I2S_PD2_12 899 #define RT5640_I2S_PD2_12 (0x6 << 8)
900 #define RT5640_I2S_PD2_16 900 #define RT5640_I2S_PD2_16 (0x7 << 8)
901 #define RT5640_I2S_BCLK_MS3_MASK 901 #define RT5640_I2S_BCLK_MS3_MASK (0x1 << 7)
902 #define RT5640_I2S_BCLK_MS3_SFT 902 #define RT5640_I2S_BCLK_MS3_SFT 7
903 #define RT5640_I2S_BCLK_MS3_32 903 #define RT5640_I2S_BCLK_MS3_32 (0x0 << 7)
904 #define RT5640_I2S_BCLK_MS3_64 904 #define RT5640_I2S_BCLK_MS3_64 (0x1 << 7)
905 #define RT5640_I2S_PD3_MASK 905 #define RT5640_I2S_PD3_MASK (0x7 << 4)
906 #define RT5640_I2S_PD3_SFT 906 #define RT5640_I2S_PD3_SFT 4
907 #define RT5640_I2S_PD3_1 907 #define RT5640_I2S_PD3_1 (0x0 << 4)
908 #define RT5640_I2S_PD3_2 908 #define RT5640_I2S_PD3_2 (0x1 << 4)
909 #define RT5640_I2S_PD3_3 909 #define RT5640_I2S_PD3_3 (0x2 << 4)
910 #define RT5640_I2S_PD3_4 910 #define RT5640_I2S_PD3_4 (0x3 << 4)
911 #define RT5640_I2S_PD3_6 911 #define RT5640_I2S_PD3_6 (0x4 << 4)
912 #define RT5640_I2S_PD3_8 912 #define RT5640_I2S_PD3_8 (0x5 << 4)
913 #define RT5640_I2S_PD3_12 913 #define RT5640_I2S_PD3_12 (0x6 << 4)
914 #define RT5640_I2S_PD3_16 914 #define RT5640_I2S_PD3_16 (0x7 << 4)
915 #define RT5640_DAC_OSR_MASK 915 #define RT5640_DAC_OSR_MASK (0x3 << 2)
916 #define RT5640_DAC_OSR_SFT 916 #define RT5640_DAC_OSR_SFT 2
917 #define RT5640_DAC_OSR_128 917 #define RT5640_DAC_OSR_128 (0x0 << 2)
918 #define RT5640_DAC_OSR_64 918 #define RT5640_DAC_OSR_64 (0x1 << 2)
919 #define RT5640_DAC_OSR_32 919 #define RT5640_DAC_OSR_32 (0x2 << 2)
920 #define RT5640_DAC_OSR_16 920 #define RT5640_DAC_OSR_16 (0x3 << 2)
921 #define RT5640_ADC_OSR_MASK 921 #define RT5640_ADC_OSR_MASK (0x3)
922 #define RT5640_ADC_OSR_SFT 922 #define RT5640_ADC_OSR_SFT 0
923 #define RT5640_ADC_OSR_128 923 #define RT5640_ADC_OSR_128 (0x0)
924 #define RT5640_ADC_OSR_64 924 #define RT5640_ADC_OSR_64 (0x1)
925 #define RT5640_ADC_OSR_32 925 #define RT5640_ADC_OSR_32 (0x2)
926 #define RT5640_ADC_OSR_16 926 #define RT5640_ADC_OSR_16 (0x3)
927 927
928 /* ADC/DAC Clock Control 2 (0x74) */ 928 /* ADC/DAC Clock Control 2 (0x74) */
929 #define RT5640_DAC_L_OSR_MASK 929 #define RT5640_DAC_L_OSR_MASK (0x3 << 14)
930 #define RT5640_DAC_L_OSR_SFT 930 #define RT5640_DAC_L_OSR_SFT 14
931 #define RT5640_DAC_L_OSR_128 931 #define RT5640_DAC_L_OSR_128 (0x0 << 14)
932 #define RT5640_DAC_L_OSR_64 932 #define RT5640_DAC_L_OSR_64 (0x1 << 14)
933 #define RT5640_DAC_L_OSR_32 933 #define RT5640_DAC_L_OSR_32 (0x2 << 14)
934 #define RT5640_DAC_L_OSR_16 934 #define RT5640_DAC_L_OSR_16 (0x3 << 14)
935 #define RT5640_ADC_R_OSR_MASK 935 #define RT5640_ADC_R_OSR_MASK (0x3 << 12)
936 #define RT5640_ADC_R_OSR_SFT 936 #define RT5640_ADC_R_OSR_SFT 12
937 #define RT5640_ADC_R_OSR_128 937 #define RT5640_ADC_R_OSR_128 (0x0 << 12)
938 #define RT5640_ADC_R_OSR_64 938 #define RT5640_ADC_R_OSR_64 (0x1 << 12)
939 #define RT5640_ADC_R_OSR_32 939 #define RT5640_ADC_R_OSR_32 (0x2 << 12)
940 #define RT5640_ADC_R_OSR_16 940 #define RT5640_ADC_R_OSR_16 (0x3 << 12)
941 #define RT5640_DAHPF_EN 941 #define RT5640_DAHPF_EN (0x1 << 11)
942 #define RT5640_DAHPF_EN_SFT 942 #define RT5640_DAHPF_EN_SFT 11
943 #define RT5640_ADHPF_EN 943 #define RT5640_ADHPF_EN (0x1 << 10)
944 #define RT5640_ADHPF_EN_SFT 944 #define RT5640_ADHPF_EN_SFT 10
945 945
946 /* Digital Microphone Control (0x75) */ 946 /* Digital Microphone Control (0x75) */
947 #define RT5640_DMIC_1_EN_MASK 947 #define RT5640_DMIC_1_EN_MASK (0x1 << 15)
948 #define RT5640_DMIC_1_EN_SFT 948 #define RT5640_DMIC_1_EN_SFT 15
949 #define RT5640_DMIC_1_DIS 949 #define RT5640_DMIC_1_DIS (0x0 << 15)
950 #define RT5640_DMIC_1_EN 950 #define RT5640_DMIC_1_EN (0x1 << 15)
951 #define RT5640_DMIC_2_EN_MASK 951 #define RT5640_DMIC_2_EN_MASK (0x1 << 14)
952 #define RT5640_DMIC_2_EN_SFT 952 #define RT5640_DMIC_2_EN_SFT 14
953 #define RT5640_DMIC_2_DIS 953 #define RT5640_DMIC_2_DIS (0x0 << 14)
954 #define RT5640_DMIC_2_EN 954 #define RT5640_DMIC_2_EN (0x1 << 14)
955 #define RT5640_DMIC_1L_LH_MASK 955 #define RT5640_DMIC_1L_LH_MASK (0x1 << 13)
956 #define RT5640_DMIC_1L_LH_SFT 956 #define RT5640_DMIC_1L_LH_SFT 13
957 #define RT5640_DMIC_1L_LH_FALLING 957 #define RT5640_DMIC_1L_LH_FALLING (0x0 << 13)
958 #define RT5640_DMIC_1L_LH_RISING 958 #define RT5640_DMIC_1L_LH_RISING (0x1 << 13)
959 #define RT5640_DMIC_1R_LH_MASK 959 #define RT5640_DMIC_1R_LH_MASK (0x1 << 12)
960 #define RT5640_DMIC_1R_LH_SFT 960 #define RT5640_DMIC_1R_LH_SFT 12
961 #define RT5640_DMIC_1R_LH_FALLING 961 #define RT5640_DMIC_1R_LH_FALLING (0x0 << 12)
962 #define RT5640_DMIC_1R_LH_RISING 962 #define RT5640_DMIC_1R_LH_RISING (0x1 << 12)
963 #define RT5640_DMIC_1_DP_MASK 963 #define RT5640_DMIC_1_DP_MASK (0x1 << 11)
964 #define RT5640_DMIC_1_DP_SFT 964 #define RT5640_DMIC_1_DP_SFT 11
965 #define RT5640_DMIC_1_DP_GPIO3 965 #define RT5640_DMIC_1_DP_GPIO3 (0x0 << 11)
966 #define RT5640_DMIC_1_DP_IN1P 966 #define RT5640_DMIC_1_DP_IN1P (0x1 << 11)
967 #define RT5640_DMIC_2_DP_MASK 967 #define RT5640_DMIC_2_DP_MASK (0x1 << 10)
968 #define RT5640_DMIC_2_DP_SFT 968 #define RT5640_DMIC_2_DP_SFT 10
969 #define RT5640_DMIC_2_DP_GPIO4 969 #define RT5640_DMIC_2_DP_GPIO4 (0x0 << 10)
970 #define RT5640_DMIC_2_DP_IN1N 970 #define RT5640_DMIC_2_DP_IN1N (0x1 << 10)
971 #define RT5640_DMIC_2L_LH_MASK 971 #define RT5640_DMIC_2L_LH_MASK (0x1 << 9)
972 #define RT5640_DMIC_2L_LH_SFT 972 #define RT5640_DMIC_2L_LH_SFT 9
973 #define RT5640_DMIC_2L_LH_FALLING 973 #define RT5640_DMIC_2L_LH_FALLING (0x0 << 9)
974 #define RT5640_DMIC_2L_LH_RISING 974 #define RT5640_DMIC_2L_LH_RISING (0x1 << 9)
975 #define RT5640_DMIC_2R_LH_MASK 975 #define RT5640_DMIC_2R_LH_MASK (0x1 << 8)
976 #define RT5640_DMIC_2R_LH_SFT 976 #define RT5640_DMIC_2R_LH_SFT 8
977 #define RT5640_DMIC_2R_LH_FALLING 977 #define RT5640_DMIC_2R_LH_FALLING (0x0 << 8)
978 #define RT5640_DMIC_2R_LH_RISING 978 #define RT5640_DMIC_2R_LH_RISING (0x1 << 8)
979 #define RT5640_DMIC_CLK_MASK 979 #define RT5640_DMIC_CLK_MASK (0x7 << 5)
980 #define RT5640_DMIC_CLK_SFT 980 #define RT5640_DMIC_CLK_SFT 5
981 981
982 /* Global Clock Control (0x80) */ 982 /* Global Clock Control (0x80) */
983 #define RT5640_SCLK_SRC_MASK 983 #define RT5640_SCLK_SRC_MASK (0x3 << 14)
984 #define RT5640_SCLK_SRC_SFT 984 #define RT5640_SCLK_SRC_SFT 14
985 #define RT5640_SCLK_SRC_MCLK 985 #define RT5640_SCLK_SRC_MCLK (0x0 << 14)
986 #define RT5640_SCLK_SRC_PLL1 986 #define RT5640_SCLK_SRC_PLL1 (0x1 << 14)
987 #define RT5640_SCLK_SRC_RCCLK 987 #define RT5640_SCLK_SRC_RCCLK (0x2 << 14)
988 #define RT5640_PLL1_SRC_MASK 988 #define RT5640_PLL1_SRC_MASK (0x3 << 12)
989 #define RT5640_PLL1_SRC_SFT 989 #define RT5640_PLL1_SRC_SFT 12
990 #define RT5640_PLL1_SRC_MCLK 990 #define RT5640_PLL1_SRC_MCLK (0x0 << 12)
991 #define RT5640_PLL1_SRC_BCLK1 991 #define RT5640_PLL1_SRC_BCLK1 (0x1 << 12)
992 #define RT5640_PLL1_SRC_BCLK2 992 #define RT5640_PLL1_SRC_BCLK2 (0x2 << 12)
993 #define RT5640_PLL1_SRC_BCLK3 993 #define RT5640_PLL1_SRC_BCLK3 (0x3 << 12)
994 #define RT5640_PLL1_PD_MASK 994 #define RT5640_PLL1_PD_MASK (0x1 << 3)
995 #define RT5640_PLL1_PD_SFT 995 #define RT5640_PLL1_PD_SFT 3
996 #define RT5640_PLL1_PD_1 996 #define RT5640_PLL1_PD_1 (0x0 << 3)
997 #define RT5640_PLL1_PD_2 997 #define RT5640_PLL1_PD_2 (0x1 << 3)
998 998
999 #define RT5640_PLL_INP_MAX 999 #define RT5640_PLL_INP_MAX 40000000
1000 #define RT5640_PLL_INP_MIN 1000 #define RT5640_PLL_INP_MIN 256000
1001 /* PLL M/N/K Code Control 1 (0x81) */ 1001 /* PLL M/N/K Code Control 1 (0x81) */
1002 #define RT5640_PLL_N_MAX 1002 #define RT5640_PLL_N_MAX 0x1ff
1003 #define RT5640_PLL_N_MASK 1003 #define RT5640_PLL_N_MASK (RT5640_PLL_N_MAX << 7)
1004 #define RT5640_PLL_N_SFT 1004 #define RT5640_PLL_N_SFT 7
1005 #define RT5640_PLL_K_MAX 1005 #define RT5640_PLL_K_MAX 0x1f
1006 #define RT5640_PLL_K_MASK 1006 #define RT5640_PLL_K_MASK (RT5640_PLL_K_MAX)
1007 #define RT5640_PLL_K_SFT 1007 #define RT5640_PLL_K_SFT 0
1008 1008
1009 /* PLL M/N/K Code Control 2 (0x82) */ 1009 /* PLL M/N/K Code Control 2 (0x82) */
1010 #define RT5640_PLL_M_MAX 1010 #define RT5640_PLL_M_MAX 0xf
1011 #define RT5640_PLL_M_MASK 1011 #define RT5640_PLL_M_MASK (RT5640_PLL_M_MAX << 12)
1012 #define RT5640_PLL_M_SFT 1012 #define RT5640_PLL_M_SFT 12
1013 #define RT5640_PLL_M_BP 1013 #define RT5640_PLL_M_BP (0x1 << 11)
1014 #define RT5640_PLL_M_BP_SFT 1014 #define RT5640_PLL_M_BP_SFT 11
1015 1015
1016 /* ASRC Control 1 (0x83) */ 1016 /* ASRC Control 1 (0x83) */
1017 #define RT5640_STO_T_MASK 1017 #define RT5640_STO_T_MASK (0x1 << 15)
1018 #define RT5640_STO_T_SFT 1018 #define RT5640_STO_T_SFT 15
1019 #define RT5640_STO_T_SCLK 1019 #define RT5640_STO_T_SCLK (0x0 << 15)
1020 #define RT5640_STO_T_LRCK1 1020 #define RT5640_STO_T_LRCK1 (0x1 << 15)
1021 #define RT5640_M1_T_MASK 1021 #define RT5640_M1_T_MASK (0x1 << 14)
1022 #define RT5640_M1_T_SFT 1022 #define RT5640_M1_T_SFT 14
1023 #define RT5640_M1_T_I2S2 1023 #define RT5640_M1_T_I2S2 (0x0 << 14)
1024 #define RT5640_M1_T_I2S2_D3 1024 #define RT5640_M1_T_I2S2_D3 (0x1 << 14)
1025 #define RT5640_I2S2_F_MASK 1025 #define RT5640_I2S2_F_MASK (0x1 << 12)
1026 #define RT5640_I2S2_F_SFT 1026 #define RT5640_I2S2_F_SFT 12
1027 #define RT5640_I2S2_F_I2S2_D2 1027 #define RT5640_I2S2_F_I2S2_D2 (0x0 << 12)
1028 #define RT5640_I2S2_F_I2S1_TCLK 1028 #define RT5640_I2S2_F_I2S1_TCLK (0x1 << 12)
1029 #define RT5640_DMIC_1_M_MASK 1029 #define RT5640_DMIC_1_M_MASK (0x1 << 9)
1030 #define RT5640_DMIC_1_M_SFT 1030 #define RT5640_DMIC_1_M_SFT 9
1031 #define RT5640_DMIC_1_M_NOR 1031 #define RT5640_DMIC_1_M_NOR (0x0 << 9)
1032 #define RT5640_DMIC_1_M_ASYN 1032 #define RT5640_DMIC_1_M_ASYN (0x1 << 9)
1033 #define RT5640_DMIC_2_M_MASK 1033 #define RT5640_DMIC_2_M_MASK (0x1 << 8)
1034 #define RT5640_DMIC_2_M_SFT 1034 #define RT5640_DMIC_2_M_SFT 8
1035 #define RT5640_DMIC_2_M_NOR 1035 #define RT5640_DMIC_2_M_NOR (0x0 << 8)
1036 #define RT5640_DMIC_2_M_ASYN 1036 #define RT5640_DMIC_2_M_ASYN (0x1 << 8)
1037 1037
1038 /* ASRC clock source selection (0x84) */ 1038 /* ASRC clock source selection (0x84) */
1039 #define RT5640_CLK_SEL_SYS 1039 #define RT5640_CLK_SEL_SYS (0x0)
1040 #define RT5640_CLK_SEL_ASRC 1040 #define RT5640_CLK_SEL_ASRC (0x1)
1041 1041
1042 /* ASRC Control 2 (0x84) */ 1042 /* ASRC Control 2 (0x84) */
1043 #define RT5640_MDA_L_M_MASK 1043 #define RT5640_MDA_L_M_MASK (0x1 << 15)
1044 #define RT5640_MDA_L_M_SFT 1044 #define RT5640_MDA_L_M_SFT 15
1045 #define RT5640_MDA_L_M_NOR 1045 #define RT5640_MDA_L_M_NOR (0x0 << 15)
1046 #define RT5640_MDA_L_M_ASYN 1046 #define RT5640_MDA_L_M_ASYN (0x1 << 15)
1047 #define RT5640_MDA_R_M_MASK 1047 #define RT5640_MDA_R_M_MASK (0x1 << 14)
1048 #define RT5640_MDA_R_M_SFT 1048 #define RT5640_MDA_R_M_SFT 14
1049 #define RT5640_MDA_R_M_NOR 1049 #define RT5640_MDA_R_M_NOR (0x0 << 14)
1050 #define RT5640_MDA_R_M_ASYN 1050 #define RT5640_MDA_R_M_ASYN (0x1 << 14)
1051 #define RT5640_MAD_L_M_MASK 1051 #define RT5640_MAD_L_M_MASK (0x1 << 13)
1052 #define RT5640_MAD_L_M_SFT 1052 #define RT5640_MAD_L_M_SFT 13
1053 #define RT5640_MAD_L_M_NOR 1053 #define RT5640_MAD_L_M_NOR (0x0 << 13)
1054 #define RT5640_MAD_L_M_ASYN 1054 #define RT5640_MAD_L_M_ASYN (0x1 << 13)
1055 #define RT5640_MAD_R_M_MASK 1055 #define RT5640_MAD_R_M_MASK (0x1 << 12)
1056 #define RT5640_MAD_R_M_SFT 1056 #define RT5640_MAD_R_M_SFT 12
1057 #define RT5640_MAD_R_M_NOR 1057 #define RT5640_MAD_R_M_NOR (0x0 << 12)
1058 #define RT5640_MAD_R_M_ASYN 1058 #define RT5640_MAD_R_M_ASYN (0x1 << 12)
1059 #define RT5640_ADC_M_MASK 1059 #define RT5640_ADC_M_MASK (0x1 << 11)
1060 #define RT5640_ADC_M_SFT 1060 #define RT5640_ADC_M_SFT 11
1061 #define RT5640_ADC_M_NOR 1061 #define RT5640_ADC_M_NOR (0x0 << 11)
1062 #define RT5640_ADC_M_ASYN 1062 #define RT5640_ADC_M_ASYN (0x1 << 11)
1063 #define RT5640_STO_DAC_M_MASK 1063 #define RT5640_STO_DAC_M_MASK (0x1 << 5)
1064 #define RT5640_STO_DAC_M_SFT 1064 #define RT5640_STO_DAC_M_SFT 5
1065 #define RT5640_STO_DAC_M_NOR 1065 #define RT5640_STO_DAC_M_NOR (0x0 << 5)
1066 #define RT5640_STO_DAC_M_ASYN 1066 #define RT5640_STO_DAC_M_ASYN (0x1 << 5)
1067 #define RT5640_I2S1_R_D_MASK 1067 #define RT5640_I2S1_R_D_MASK (0x1 << 4)
1068 #define RT5640_I2S1_R_D_SFT 1068 #define RT5640_I2S1_R_D_SFT 4
1069 #define RT5640_I2S1_R_D_DIS 1069 #define RT5640_I2S1_R_D_DIS (0x0 << 4)
1070 #define RT5640_I2S1_R_D_EN 1070 #define RT5640_I2S1_R_D_EN (0x1 << 4)
1071 #define RT5640_I2S2_R_D_MASK 1071 #define RT5640_I2S2_R_D_MASK (0x1 << 3)
1072 #define RT5640_I2S2_R_D_SFT 1072 #define RT5640_I2S2_R_D_SFT 3
1073 #define RT5640_I2S2_R_D_DIS 1073 #define RT5640_I2S2_R_D_DIS (0x0 << 3)
1074 #define RT5640_I2S2_R_D_EN 1074 #define RT5640_I2S2_R_D_EN (0x1 << 3)
1075 #define RT5640_PRE_SCLK_MASK 1075 #define RT5640_PRE_SCLK_MASK (0x3)
1076 #define RT5640_PRE_SCLK_SFT 1076 #define RT5640_PRE_SCLK_SFT 0
1077 #define RT5640_PRE_SCLK_512 1077 #define RT5640_PRE_SCLK_512 (0x0)
1078 #define RT5640_PRE_SCLK_1024 1078 #define RT5640_PRE_SCLK_1024 (0x1)
1079 #define RT5640_PRE_SCLK_2048 1079 #define RT5640_PRE_SCLK_2048 (0x2)
1080 1080
1081 /* ASRC Control 3 (0x85) */ 1081 /* ASRC Control 3 (0x85) */
1082 #define RT5640_I2S1_RATE_MASK 1082 #define RT5640_I2S1_RATE_MASK (0xf << 12)
1083 #define RT5640_I2S1_RATE_SFT 1083 #define RT5640_I2S1_RATE_SFT 12
1084 #define RT5640_I2S2_RATE_MASK 1084 #define RT5640_I2S2_RATE_MASK (0xf << 8)
1085 #define RT5640_I2S2_RATE_SFT 1085 #define RT5640_I2S2_RATE_SFT 8
1086 1086
1087 /* ASRC Control 4 (0x89) */ 1087 /* ASRC Control 4 (0x89) */
1088 #define RT5640_I2S1_PD_MASK 1088 #define RT5640_I2S1_PD_MASK (0x7 << 12)
1089 #define RT5640_I2S1_PD_SFT 1089 #define RT5640_I2S1_PD_SFT 12
1090 #define RT5640_I2S2_PD_MASK 1090 #define RT5640_I2S2_PD_MASK (0x7 << 8)
1091 #define RT5640_I2S2_PD_SFT 1091 #define RT5640_I2S2_PD_SFT 8
1092 1092
1093 /* HPOUT Over Current Detection (0x8b) */ 1093 /* HPOUT Over Current Detection (0x8b) */
1094 #define RT5640_HP_OVCD_MASK 1094 #define RT5640_HP_OVCD_MASK (0x1 << 10)
1095 #define RT5640_HP_OVCD_SFT 1095 #define RT5640_HP_OVCD_SFT 10
1096 #define RT5640_HP_OVCD_DIS 1096 #define RT5640_HP_OVCD_DIS (0x0 << 10)
1097 #define RT5640_HP_OVCD_EN 1097 #define RT5640_HP_OVCD_EN (0x1 << 10)
1098 #define RT5640_HP_OC_TH_MASK 1098 #define RT5640_HP_OC_TH_MASK (0x3 << 8)
1099 #define RT5640_HP_OC_TH_SFT 1099 #define RT5640_HP_OC_TH_SFT 8
1100 #define RT5640_HP_OC_TH_90 1100 #define RT5640_HP_OC_TH_90 (0x0 << 8)
1101 #define RT5640_HP_OC_TH_105 1101 #define RT5640_HP_OC_TH_105 (0x1 << 8)
1102 #define RT5640_HP_OC_TH_120 1102 #define RT5640_HP_OC_TH_120 (0x2 << 8)
1103 #define RT5640_HP_OC_TH_135 1103 #define RT5640_HP_OC_TH_135 (0x3 << 8)
1104 1104
1105 /* Class D Over Current Control (0x8c) */ 1105 /* Class D Over Current Control (0x8c) */
1106 #define RT5640_CLSD_OC_MASK 1106 #define RT5640_CLSD_OC_MASK (0x1 << 9)
1107 #define RT5640_CLSD_OC_SFT 1107 #define RT5640_CLSD_OC_SFT 9
1108 #define RT5640_CLSD_OC_PU 1108 #define RT5640_CLSD_OC_PU (0x0 << 9)
1109 #define RT5640_CLSD_OC_PD 1109 #define RT5640_CLSD_OC_PD (0x1 << 9)
1110 #define RT5640_AUTO_PD_MASK 1110 #define RT5640_AUTO_PD_MASK (0x1 << 8)
1111 #define RT5640_AUTO_PD_SFT 1111 #define RT5640_AUTO_PD_SFT 8
1112 #define RT5640_AUTO_PD_DIS 1112 #define RT5640_AUTO_PD_DIS (0x0 << 8)
1113 #define RT5640_AUTO_PD_EN 1113 #define RT5640_AUTO_PD_EN (0x1 << 8)
1114 #define RT5640_CLSD_OC_TH_MASK 1114 #define RT5640_CLSD_OC_TH_MASK (0x3f)
1115 #define RT5640_CLSD_OC_TH_SFT 1115 #define RT5640_CLSD_OC_TH_SFT 0
1116 1116
1117 /* Class D Output Control (0x8d) */ 1117 /* Class D Output Control (0x8d) */
1118 #define RT5640_CLSD_RATIO_MASK 1118 #define RT5640_CLSD_RATIO_MASK (0xf << 12)
1119 #define RT5640_CLSD_RATIO_SFT 1119 #define RT5640_CLSD_RATIO_SFT 12
1120 #define RT5640_CLSD_OM_MASK 1120 #define RT5640_CLSD_OM_MASK (0x1 << 11)
1121 #define RT5640_CLSD_OM_SFT 1121 #define RT5640_CLSD_OM_SFT 11
1122 #define RT5640_CLSD_OM_MONO 1122 #define RT5640_CLSD_OM_MONO (0x0 << 11)
1123 #define RT5640_CLSD_OM_STO 1123 #define RT5640_CLSD_OM_STO (0x1 << 11)
1124 #define RT5640_CLSD_SCH_MASK 1124 #define RT5640_CLSD_SCH_MASK (0x1 << 10)
1125 #define RT5640_CLSD_SCH_SFT 1125 #define RT5640_CLSD_SCH_SFT 10
1126 #define RT5640_CLSD_SCH_L 1126 #define RT5640_CLSD_SCH_L (0x0 << 10)
1127 #define RT5640_CLSD_SCH_S 1127 #define RT5640_CLSD_SCH_S (0x1 << 10)
1128 1128
1129 /* Depop Mode Control 1 (0x8e) */ 1129 /* Depop Mode Control 1 (0x8e) */
1130 #define RT5640_SMT_TRIG_MASK 1130 #define RT5640_SMT_TRIG_MASK (0x1 << 15)
1131 #define RT5640_SMT_TRIG_SFT 1131 #define RT5640_SMT_TRIG_SFT 15
1132 #define RT5640_SMT_TRIG_DIS 1132 #define RT5640_SMT_TRIG_DIS (0x0 << 15)
1133 #define RT5640_SMT_TRIG_EN 1133 #define RT5640_SMT_TRIG_EN (0x1 << 15)
1134 #define RT5640_HP_L_SMT_MASK 1134 #define RT5640_HP_L_SMT_MASK (0x1 << 9)
1135 #define RT5640_HP_L_SMT_SFT 1135 #define RT5640_HP_L_SMT_SFT 9
1136 #define RT5640_HP_L_SMT_DIS 1136 #define RT5640_HP_L_SMT_DIS (0x0 << 9)
1137 #define RT5640_HP_L_SMT_EN 1137 #define RT5640_HP_L_SMT_EN (0x1 << 9)
1138 #define RT5640_HP_R_SMT_MASK 1138 #define RT5640_HP_R_SMT_MASK (0x1 << 8)
1139 #define RT5640_HP_R_SMT_SFT 1139 #define RT5640_HP_R_SMT_SFT 8
1140 #define RT5640_HP_R_SMT_DIS 1140 #define RT5640_HP_R_SMT_DIS (0x0 << 8)
1141 #define RT5640_HP_R_SMT_EN 1141 #define RT5640_HP_R_SMT_EN (0x1 << 8)
1142 #define RT5640_HP_CD_PD_MASK 1142 #define RT5640_HP_CD_PD_MASK (0x1 << 7)
1143 #define RT5640_HP_CD_PD_SFT 1143 #define RT5640_HP_CD_PD_SFT 7
1144 #define RT5640_HP_CD_PD_DIS 1144 #define RT5640_HP_CD_PD_DIS (0x0 << 7)
1145 #define RT5640_HP_CD_PD_EN 1145 #define RT5640_HP_CD_PD_EN (0x1 << 7)
1146 #define RT5640_RSTN_MASK 1146 #define RT5640_RSTN_MASK (0x1 << 6)
1147 #define RT5640_RSTN_SFT 1147 #define RT5640_RSTN_SFT 6
1148 #define RT5640_RSTN_DIS 1148 #define RT5640_RSTN_DIS (0x0 << 6)
1149 #define RT5640_RSTN_EN 1149 #define RT5640_RSTN_EN (0x1 << 6)
1150 #define RT5640_RSTP_MASK 1150 #define RT5640_RSTP_MASK (0x1 << 5)
1151 #define RT5640_RSTP_SFT 1151 #define RT5640_RSTP_SFT 5
1152 #define RT5640_RSTP_DIS 1152 #define RT5640_RSTP_DIS (0x0 << 5)
1153 #define RT5640_RSTP_EN 1153 #define RT5640_RSTP_EN (0x1 << 5)
1154 #define RT5640_HP_CO_MASK 1154 #define RT5640_HP_CO_MASK (0x1 << 4)
1155 #define RT5640_HP_CO_SFT 1155 #define RT5640_HP_CO_SFT 4
1156 #define RT5640_HP_CO_DIS 1156 #define RT5640_HP_CO_DIS (0x0 << 4)
1157 #define RT5640_HP_CO_EN 1157 #define RT5640_HP_CO_EN (0x1 << 4)
1158 #define RT5640_HP_CP_MASK 1158 #define RT5640_HP_CP_MASK (0x1 << 3)
1159 #define RT5640_HP_CP_SFT 1159 #define RT5640_HP_CP_SFT 3
1160 #define RT5640_HP_CP_PD 1160 #define RT5640_HP_CP_PD (0x0 << 3)
1161 #define RT5640_HP_CP_PU 1161 #define RT5640_HP_CP_PU (0x1 << 3)
1162 #define RT5640_HP_SG_MASK 1162 #define RT5640_HP_SG_MASK (0x1 << 2)
1163 #define RT5640_HP_SG_SFT 1163 #define RT5640_HP_SG_SFT 2
1164 #define RT5640_HP_SG_DIS 1164 #define RT5640_HP_SG_DIS (0x0 << 2)
1165 #define RT5640_HP_SG_EN 1165 #define RT5640_HP_SG_EN (0x1 << 2)
1166 #define RT5640_HP_DP_MASK 1166 #define RT5640_HP_DP_MASK (0x1 << 1)
1167 #define RT5640_HP_DP_SFT 1167 #define RT5640_HP_DP_SFT 1
1168 #define RT5640_HP_DP_PD 1168 #define RT5640_HP_DP_PD (0x0 << 1)
1169 #define RT5640_HP_DP_PU 1169 #define RT5640_HP_DP_PU (0x1 << 1)
1170 #define RT5640_HP_CB_MASK 1170 #define RT5640_HP_CB_MASK (0x1)
1171 #define RT5640_HP_CB_SFT 1171 #define RT5640_HP_CB_SFT 0
1172 #define RT5640_HP_CB_PD 1172 #define RT5640_HP_CB_PD (0x0)
1173 #define RT5640_HP_CB_PU 1173 #define RT5640_HP_CB_PU (0x1)
1174 1174
1175 /* Depop Mode Control 2 (0x8f) */ 1175 /* Depop Mode Control 2 (0x8f) */
1176 #define RT5640_DEPOP_MASK 1176 #define RT5640_DEPOP_MASK (0x1 << 13)
1177 #define RT5640_DEPOP_SFT 1177 #define RT5640_DEPOP_SFT 13
1178 #define RT5640_DEPOP_AUTO 1178 #define RT5640_DEPOP_AUTO (0x0 << 13)
1179 #define RT5640_DEPOP_MAN 1179 #define RT5640_DEPOP_MAN (0x1 << 13)
1180 #define RT5640_RAMP_MASK 1180 #define RT5640_RAMP_MASK (0x1 << 12)
1181 #define RT5640_RAMP_SFT 1181 #define RT5640_RAMP_SFT 12
1182 #define RT5640_RAMP_DIS 1182 #define RT5640_RAMP_DIS (0x0 << 12)
1183 #define RT5640_RAMP_EN 1183 #define RT5640_RAMP_EN (0x1 << 12)
1184 #define RT5640_BPS_MASK 1184 #define RT5640_BPS_MASK (0x1 << 11)
1185 #define RT5640_BPS_SFT 1185 #define RT5640_BPS_SFT 11
1186 #define RT5640_BPS_DIS 1186 #define RT5640_BPS_DIS (0x0 << 11)
1187 #define RT5640_BPS_EN 1187 #define RT5640_BPS_EN (0x1 << 11)
1188 #define RT5640_FAST_UPDN_MASK 1188 #define RT5640_FAST_UPDN_MASK (0x1 << 10)
1189 #define RT5640_FAST_UPDN_SFT 1189 #define RT5640_FAST_UPDN_SFT 10
1190 #define RT5640_FAST_UPDN_DIS 1190 #define RT5640_FAST_UPDN_DIS (0x0 << 10)
1191 #define RT5640_FAST_UPDN_EN 1191 #define RT5640_FAST_UPDN_EN (0x1 << 10)
1192 #define RT5640_MRES_MASK 1192 #define RT5640_MRES_MASK (0x3 << 8)
1193 #define RT5640_MRES_SFT 1193 #define RT5640_MRES_SFT 8
1194 #define RT5640_MRES_15MO 1194 #define RT5640_MRES_15MO (0x0 << 8)
1195 #define RT5640_MRES_25MO 1195 #define RT5640_MRES_25MO (0x1 << 8)
1196 #define RT5640_MRES_35MO 1196 #define RT5640_MRES_35MO (0x2 << 8)
1197 #define RT5640_MRES_45MO 1197 #define RT5640_MRES_45MO (0x3 << 8)
1198 #define RT5640_VLO_MASK 1198 #define RT5640_VLO_MASK (0x1 << 7)
1199 #define RT5640_VLO_SFT 1199 #define RT5640_VLO_SFT 7
1200 #define RT5640_VLO_3V 1200 #define RT5640_VLO_3V (0x0 << 7)
1201 #define RT5640_VLO_32V 1201 #define RT5640_VLO_32V (0x1 << 7)
1202 #define RT5640_DIG_DP_MASK 1202 #define RT5640_DIG_DP_MASK (0x1 << 6)
1203 #define RT5640_DIG_DP_SFT 1203 #define RT5640_DIG_DP_SFT 6
1204 #define RT5640_DIG_DP_DIS 1204 #define RT5640_DIG_DP_DIS (0x0 << 6)
1205 #define RT5640_DIG_DP_EN 1205 #define RT5640_DIG_DP_EN (0x1 << 6)
1206 #define RT5640_DP_TH_MASK 1206 #define RT5640_DP_TH_MASK (0x3 << 4)
1207 #define RT5640_DP_TH_SFT 1207 #define RT5640_DP_TH_SFT 4
1208 1208
1209 /* Depop Mode Control 3 (0x90) */ 1209 /* Depop Mode Control 3 (0x90) */
1210 #define RT5640_CP_SYS_MASK 1210 #define RT5640_CP_SYS_MASK (0x7 << 12)
1211 #define RT5640_CP_SYS_SFT 1211 #define RT5640_CP_SYS_SFT 12
1212 #define RT5640_CP_FQ1_MASK 1212 #define RT5640_CP_FQ1_MASK (0x7 << 8)
1213 #define RT5640_CP_FQ1_SFT 1213 #define RT5640_CP_FQ1_SFT 8
1214 #define RT5640_CP_FQ2_MASK 1214 #define RT5640_CP_FQ2_MASK (0x7 << 4)
1215 #define RT5640_CP_FQ2_SFT 1215 #define RT5640_CP_FQ2_SFT 4
1216 #define RT5640_CP_FQ3_MASK 1216 #define RT5640_CP_FQ3_MASK (0x7)
1217 #define RT5640_CP_FQ3_SFT 1217 #define RT5640_CP_FQ3_SFT 0
1218 #define RT5640_CP_FQ_1_5_KHZ 1218 #define RT5640_CP_FQ_1_5_KHZ 0
1219 #define RT5640_CP_FQ_3_KHZ 1219 #define RT5640_CP_FQ_3_KHZ 1
1220 #define RT5640_CP_FQ_6_KHZ 1220 #define RT5640_CP_FQ_6_KHZ 2
1221 #define RT5640_CP_FQ_12_KHZ 1221 #define RT5640_CP_FQ_12_KHZ 3
1222 #define RT5640_CP_FQ_24_KHZ 1222 #define RT5640_CP_FQ_24_KHZ 4
1223 #define RT5640_CP_FQ_48_KHZ 1223 #define RT5640_CP_FQ_48_KHZ 5
1224 #define RT5640_CP_FQ_96_KHZ 1224 #define RT5640_CP_FQ_96_KHZ 6
1225 #define RT5640_CP_FQ_192_KHZ 1225 #define RT5640_CP_FQ_192_KHZ 7
1226 1226
1227 /* HPOUT charge pump (0x91) */ 1227 /* HPOUT charge pump (0x91) */
1228 #define RT5640_OSW_L_MASK 1228 #define RT5640_OSW_L_MASK (0x1 << 11)
1229 #define RT5640_OSW_L_SFT 1229 #define RT5640_OSW_L_SFT 11
1230 #define RT5640_OSW_L_DIS 1230 #define RT5640_OSW_L_DIS (0x0 << 11)
1231 #define RT5640_OSW_L_EN 1231 #define RT5640_OSW_L_EN (0x1 << 11)
1232 #define RT5640_OSW_R_MASK 1232 #define RT5640_OSW_R_MASK (0x1 << 10)
1233 #define RT5640_OSW_R_SFT 1233 #define RT5640_OSW_R_SFT 10
1234 #define RT5640_OSW_R_DIS 1234 #define RT5640_OSW_R_DIS (0x0 << 10)
1235 #define RT5640_OSW_R_EN 1235 #define RT5640_OSW_R_EN (0x1 << 10)
1236 #define RT5640_PM_HP_MASK 1236 #define RT5640_PM_HP_MASK (0x3 << 8)
1237 #define RT5640_PM_HP_SFT 1237 #define RT5640_PM_HP_SFT 8
1238 #define RT5640_PM_HP_LV 1238 #define RT5640_PM_HP_LV (0x0 << 8)
1239 #define RT5640_PM_HP_MV 1239 #define RT5640_PM_HP_MV (0x1 << 8)
1240 #define RT5640_PM_HP_HV 1240 #define RT5640_PM_HP_HV (0x2 << 8)
1241 #define RT5640_IB_HP_MASK 1241 #define RT5640_IB_HP_MASK (0x3 << 6)
1242 #define RT5640_IB_HP_SFT 1242 #define RT5640_IB_HP_SFT 6
1243 #define RT5640_IB_HP_125IL 1243 #define RT5640_IB_HP_125IL (0x0 << 6)
1244 #define RT5640_IB_HP_25IL 1244 #define RT5640_IB_HP_25IL (0x1 << 6)
1245 #define RT5640_IB_HP_5IL 1245 #define RT5640_IB_HP_5IL (0x2 << 6)
1246 #define RT5640_IB_HP_1IL 1246 #define RT5640_IB_HP_1IL (0x3 << 6)
1247 1247
1248 /* PV detection and SPK gain control (0x92) * 1248 /* PV detection and SPK gain control (0x92) */
1249 #define RT5640_PVDD_DET_MASK 1249 #define RT5640_PVDD_DET_MASK (0x1 << 15)
1250 #define RT5640_PVDD_DET_SFT 1250 #define RT5640_PVDD_DET_SFT 15
1251 #define RT5640_PVDD_DET_DIS 1251 #define RT5640_PVDD_DET_DIS (0x0 << 15)
1252 #define RT5640_PVDD_DET_EN 1252 #define RT5640_PVDD_DET_EN (0x1 << 15)
1253 #define RT5640_SPK_AG_MASK 1253 #define RT5640_SPK_AG_MASK (0x1 << 14)
1254 #define RT5640_SPK_AG_SFT 1254 #define RT5640_SPK_AG_SFT 14
1255 #define RT5640_SPK_AG_DIS 1255 #define RT5640_SPK_AG_DIS (0x0 << 14)
1256 #define RT5640_SPK_AG_EN 1256 #define RT5640_SPK_AG_EN (0x1 << 14)
1257 1257
1258 /* Micbias Control (0x93) */ 1258 /* Micbias Control (0x93) */
1259 #define RT5640_MIC1_BS_MASK 1259 #define RT5640_MIC1_BS_MASK (0x1 << 15)
1260 #define RT5640_MIC1_BS_SFT 1260 #define RT5640_MIC1_BS_SFT 15
1261 #define RT5640_MIC1_BS_9AV 1261 #define RT5640_MIC1_BS_9AV (0x0 << 15)
1262 #define RT5640_MIC1_BS_75AV 1262 #define RT5640_MIC1_BS_75AV (0x1 << 15)
1263 #define RT5640_MIC2_BS_MASK 1263 #define RT5640_MIC2_BS_MASK (0x1 << 14)
1264 #define RT5640_MIC2_BS_SFT 1264 #define RT5640_MIC2_BS_SFT 14
1265 #define RT5640_MIC2_BS_9AV 1265 #define RT5640_MIC2_BS_9AV (0x0 << 14)
1266 #define RT5640_MIC2_BS_75AV 1266 #define RT5640_MIC2_BS_75AV (0x1 << 14)
1267 #define RT5640_MIC1_CLK_MASK 1267 #define RT5640_MIC1_CLK_MASK (0x1 << 13)
1268 #define RT5640_MIC1_CLK_SFT 1268 #define RT5640_MIC1_CLK_SFT 13
1269 #define RT5640_MIC1_CLK_DIS 1269 #define RT5640_MIC1_CLK_DIS (0x0 << 13)
1270 #define RT5640_MIC1_CLK_EN 1270 #define RT5640_MIC1_CLK_EN (0x1 << 13)
1271 #define RT5640_MIC2_CLK_MASK 1271 #define RT5640_MIC2_CLK_MASK (0x1 << 12)
1272 #define RT5640_MIC2_CLK_SFT 1272 #define RT5640_MIC2_CLK_SFT 12
1273 #define RT5640_MIC2_CLK_DIS 1273 #define RT5640_MIC2_CLK_DIS (0x0 << 12)
1274 #define RT5640_MIC2_CLK_EN 1274 #define RT5640_MIC2_CLK_EN (0x1 << 12)
1275 #define RT5640_MIC1_OVCD_MASK 1275 #define RT5640_MIC1_OVCD_MASK (0x1 << 11)
1276 #define RT5640_MIC1_OVCD_SFT 1276 #define RT5640_MIC1_OVCD_SFT 11
1277 #define RT5640_MIC1_OVCD_DIS 1277 #define RT5640_MIC1_OVCD_DIS (0x0 << 11)
1278 #define RT5640_MIC1_OVCD_EN 1278 #define RT5640_MIC1_OVCD_EN (0x1 << 11)
1279 #define RT5640_MIC1_OVTH_MASK 1279 #define RT5640_MIC1_OVTH_MASK (0x3 << 9)
1280 #define RT5640_MIC1_OVTH_SFT 1280 #define RT5640_MIC1_OVTH_SFT 9
1281 #define RT5640_MIC1_OVTH_600UA 1281 #define RT5640_MIC1_OVTH_600UA (0x0 << 9)
1282 #define RT5640_MIC1_OVTH_1500UA 1282 #define RT5640_MIC1_OVTH_1500UA (0x1 << 9)
1283 #define RT5640_MIC1_OVTH_2000UA 1283 #define RT5640_MIC1_OVTH_2000UA (0x2 << 9)
1284 #define RT5640_MIC2_OVCD_MASK 1284 #define RT5640_MIC2_OVCD_MASK (0x1 << 8)
1285 #define RT5640_MIC2_OVCD_SFT 1285 #define RT5640_MIC2_OVCD_SFT 8
1286 #define RT5640_MIC2_OVCD_DIS 1286 #define RT5640_MIC2_OVCD_DIS (0x0 << 8)
1287 #define RT5640_MIC2_OVCD_EN 1287 #define RT5640_MIC2_OVCD_EN (0x1 << 8)
1288 #define RT5640_MIC2_OVTH_MASK 1288 #define RT5640_MIC2_OVTH_MASK (0x3 << 6)
1289 #define RT5640_MIC2_OVTH_SFT 1289 #define RT5640_MIC2_OVTH_SFT 6
1290 #define RT5640_MIC2_OVTH_600UA 1290 #define RT5640_MIC2_OVTH_600UA (0x0 << 6)
1291 #define RT5640_MIC2_OVTH_1500UA 1291 #define RT5640_MIC2_OVTH_1500UA (0x1 << 6)
1292 #define RT5640_MIC2_OVTH_2000UA 1292 #define RT5640_MIC2_OVTH_2000UA (0x2 << 6)
1293 #define RT5640_PWR_MB_MASK 1293 #define RT5640_PWR_MB_MASK (0x1 << 5)
1294 #define RT5640_PWR_MB_SFT 1294 #define RT5640_PWR_MB_SFT 5
1295 #define RT5640_PWR_MB_PD 1295 #define RT5640_PWR_MB_PD (0x0 << 5)
1296 #define RT5640_PWR_MB_PU 1296 #define RT5640_PWR_MB_PU (0x1 << 5)
1297 #define RT5640_PWR_CLK25M_MASK 1297 #define RT5640_PWR_CLK25M_MASK (0x1 << 4)
1298 #define RT5640_PWR_CLK25M_SFT 1298 #define RT5640_PWR_CLK25M_SFT 4
1299 #define RT5640_PWR_CLK25M_PD 1299 #define RT5640_PWR_CLK25M_PD (0x0 << 4)
1300 #define RT5640_PWR_CLK25M_PU 1300 #define RT5640_PWR_CLK25M_PU (0x1 << 4)
1301 1301
1302 /* EQ Control 1 (0xb0) */ 1302 /* EQ Control 1 (0xb0) */
1303 #define RT5640_EQ_SRC_MASK 1303 #define RT5640_EQ_SRC_MASK (0x1 << 15)
1304 #define RT5640_EQ_SRC_SFT 1304 #define RT5640_EQ_SRC_SFT 15
1305 #define RT5640_EQ_SRC_DAC 1305 #define RT5640_EQ_SRC_DAC (0x0 << 15)
1306 #define RT5640_EQ_SRC_ADC 1306 #define RT5640_EQ_SRC_ADC (0x1 << 15)
1307 #define RT5640_EQ_UPD 1307 #define RT5640_EQ_UPD (0x1 << 14)
1308 #define RT5640_EQ_UPD_BIT 1308 #define RT5640_EQ_UPD_BIT 14
1309 #define RT5640_EQ_CD_MASK 1309 #define RT5640_EQ_CD_MASK (0x1 << 13)
1310 #define RT5640_EQ_CD_SFT 1310 #define RT5640_EQ_CD_SFT 13
1311 #define RT5640_EQ_CD_DIS 1311 #define RT5640_EQ_CD_DIS (0x0 << 13)
1312 #define RT5640_EQ_CD_EN 1312 #define RT5640_EQ_CD_EN (0x1 << 13)
1313 #define RT5640_EQ_DITH_MASK 1313 #define RT5640_EQ_DITH_MASK (0x3 << 8)
1314 #define RT5640_EQ_DITH_SFT 1314 #define RT5640_EQ_DITH_SFT 8
1315 #define RT5640_EQ_DITH_NOR 1315 #define RT5640_EQ_DITH_NOR (0x0 << 8)
1316 #define RT5640_EQ_DITH_LSB 1316 #define RT5640_EQ_DITH_LSB (0x1 << 8)
1317 #define RT5640_EQ_DITH_LSB_1 1317 #define RT5640_EQ_DITH_LSB_1 (0x2 << 8)
1318 #define RT5640_EQ_DITH_LSB_2 1318 #define RT5640_EQ_DITH_LSB_2 (0x3 << 8)
1319 1319
1320 /* EQ Control 2 (0xb1) */ 1320 /* EQ Control 2 (0xb1) */
1321 #define RT5640_EQ_HPF1_M_MASK 1321 #define RT5640_EQ_HPF1_M_MASK (0x1 << 8)
1322 #define RT5640_EQ_HPF1_M_SFT 1322 #define RT5640_EQ_HPF1_M_SFT 8
1323 #define RT5640_EQ_HPF1_M_HI 1323 #define RT5640_EQ_HPF1_M_HI (0x0 << 8)
1324 #define RT5640_EQ_HPF1_M_1ST 1324 #define RT5640_EQ_HPF1_M_1ST (0x1 << 8)
1325 #define RT5640_EQ_LPF1_M_MASK 1325 #define RT5640_EQ_LPF1_M_MASK (0x1 << 7)
1326 #define RT5640_EQ_LPF1_M_SFT 1326 #define RT5640_EQ_LPF1_M_SFT 7
1327 #define RT5640_EQ_LPF1_M_LO 1327 #define RT5640_EQ_LPF1_M_LO (0x0 << 7)
1328 #define RT5640_EQ_LPF1_M_1ST 1328 #define RT5640_EQ_LPF1_M_1ST (0x1 << 7)
1329 #define RT5640_EQ_HPF2_MASK 1329 #define RT5640_EQ_HPF2_MASK (0x1 << 6)
1330 #define RT5640_EQ_HPF2_SFT 1330 #define RT5640_EQ_HPF2_SFT 6
1331 #define RT5640_EQ_HPF2_DIS 1331 #define RT5640_EQ_HPF2_DIS (0x0 << 6)
1332 #define RT5640_EQ_HPF2_EN 1332 #define RT5640_EQ_HPF2_EN (0x1 << 6)
1333 #define RT5640_EQ_HPF1_MASK 1333 #define RT5640_EQ_HPF1_MASK (0x1 << 5)
1334 #define RT5640_EQ_HPF1_SFT 1334 #define RT5640_EQ_HPF1_SFT 5
1335 #define RT5640_EQ_HPF1_DIS 1335 #define RT5640_EQ_HPF1_DIS (0x0 << 5)
1336 #define RT5640_EQ_HPF1_EN 1336 #define RT5640_EQ_HPF1_EN (0x1 << 5)
1337 #define RT5640_EQ_BPF4_MASK 1337 #define RT5640_EQ_BPF4_MASK (0x1 << 4)
1338 #define RT5640_EQ_BPF4_SFT 1338 #define RT5640_EQ_BPF4_SFT 4
1339 #define RT5640_EQ_BPF4_DIS 1339 #define RT5640_EQ_BPF4_DIS (0x0 << 4)
1340 #define RT5640_EQ_BPF4_EN 1340 #define RT5640_EQ_BPF4_EN (0x1 << 4)
1341 #define RT5640_EQ_BPF3_MASK 1341 #define RT5640_EQ_BPF3_MASK (0x1 << 3)
1342 #define RT5640_EQ_BPF3_SFT 1342 #define RT5640_EQ_BPF3_SFT 3
1343 #define RT5640_EQ_BPF3_DIS 1343 #define RT5640_EQ_BPF3_DIS (0x0 << 3)
1344 #define RT5640_EQ_BPF3_EN 1344 #define RT5640_EQ_BPF3_EN (0x1 << 3)
1345 #define RT5640_EQ_BPF2_MASK 1345 #define RT5640_EQ_BPF2_MASK (0x1 << 2)
1346 #define RT5640_EQ_BPF2_SFT 1346 #define RT5640_EQ_BPF2_SFT 2
1347 #define RT5640_EQ_BPF2_DIS 1347 #define RT5640_EQ_BPF2_DIS (0x0 << 2)
1348 #define RT5640_EQ_BPF2_EN 1348 #define RT5640_EQ_BPF2_EN (0x1 << 2)
1349 #define RT5640_EQ_BPF1_MASK 1349 #define RT5640_EQ_BPF1_MASK (0x1 << 1)
1350 #define RT5640_EQ_BPF1_SFT 1350 #define RT5640_EQ_BPF1_SFT 1
1351 #define RT5640_EQ_BPF1_DIS 1351 #define RT5640_EQ_BPF1_DIS (0x0 << 1)
1352 #define RT5640_EQ_BPF1_EN 1352 #define RT5640_EQ_BPF1_EN (0x1 << 1)
1353 #define RT5640_EQ_LPF_MASK 1353 #define RT5640_EQ_LPF_MASK (0x1)
1354 #define RT5640_EQ_LPF_SFT 1354 #define RT5640_EQ_LPF_SFT 0
1355 #define RT5640_EQ_LPF_DIS 1355 #define RT5640_EQ_LPF_DIS (0x0)
1356 #define RT5640_EQ_LPF_EN 1356 #define RT5640_EQ_LPF_EN (0x1)
1357 1357
1358 /* Memory Test (0xb2) */ 1358 /* Memory Test (0xb2) */
1359 #define RT5640_MT_MASK 1359 #define RT5640_MT_MASK (0x1 << 15)
1360 #define RT5640_MT_SFT 1360 #define RT5640_MT_SFT 15
1361 #define RT5640_MT_DIS 1361 #define RT5640_MT_DIS (0x0 << 15)
1362 #define RT5640_MT_EN 1362 #define RT5640_MT_EN (0x1 << 15)
1363 1363
1364 /* DRC/AGC Control 1 (0xb4) */ 1364 /* DRC/AGC Control 1 (0xb4) */
1365 #define RT5640_DRC_AGC_P_MASK 1365 #define RT5640_DRC_AGC_P_MASK (0x1 << 15)
1366 #define RT5640_DRC_AGC_P_SFT 1366 #define RT5640_DRC_AGC_P_SFT 15
1367 #define RT5640_DRC_AGC_P_DAC 1367 #define RT5640_DRC_AGC_P_DAC (0x0 << 15)
1368 #define RT5640_DRC_AGC_P_ADC 1368 #define RT5640_DRC_AGC_P_ADC (0x1 << 15)
1369 #define RT5640_DRC_AGC_MASK 1369 #define RT5640_DRC_AGC_MASK (0x1 << 14)
1370 #define RT5640_DRC_AGC_SFT 1370 #define RT5640_DRC_AGC_SFT 14
1371 #define RT5640_DRC_AGC_DIS 1371 #define RT5640_DRC_AGC_DIS (0x0 << 14)
1372 #define RT5640_DRC_AGC_EN 1372 #define RT5640_DRC_AGC_EN (0x1 << 14)
1373 #define RT5640_DRC_AGC_UPD 1373 #define RT5640_DRC_AGC_UPD (0x1 << 13)
1374 #define RT5640_DRC_AGC_UPD_BIT 1374 #define RT5640_DRC_AGC_UPD_BIT 13
1375 #define RT5640_DRC_AGC_AR_MASK 1375 #define RT5640_DRC_AGC_AR_MASK (0x1f << 8)
1376 #define RT5640_DRC_AGC_AR_SFT 1376 #define RT5640_DRC_AGC_AR_SFT 8
1377 #define RT5640_DRC_AGC_R_MASK 1377 #define RT5640_DRC_AGC_R_MASK (0x7 << 5)
1378 #define RT5640_DRC_AGC_R_SFT 1378 #define RT5640_DRC_AGC_R_SFT 5
1379 #define RT5640_DRC_AGC_R_48K 1379 #define RT5640_DRC_AGC_R_48K (0x1 << 5)
1380 #define RT5640_DRC_AGC_R_96K 1380 #define RT5640_DRC_AGC_R_96K (0x2 << 5)
1381 #define RT5640_DRC_AGC_R_192K 1381 #define RT5640_DRC_AGC_R_192K (0x3 << 5)
1382 #define RT5640_DRC_AGC_R_441K 1382 #define RT5640_DRC_AGC_R_441K (0x5 << 5)
1383 #define RT5640_DRC_AGC_R_882K 1383 #define RT5640_DRC_AGC_R_882K (0x6 << 5)
1384 #define RT5640_DRC_AGC_R_1764K 1384 #define RT5640_DRC_AGC_R_1764K (0x7 << 5)
1385 #define RT5640_DRC_AGC_RC_MASK 1385 #define RT5640_DRC_AGC_RC_MASK (0x1f)
1386 #define RT5640_DRC_AGC_RC_SFT 1386 #define RT5640_DRC_AGC_RC_SFT 0
1387 1387
1388 /* DRC/AGC Control 2 (0xb5) */ 1388 /* DRC/AGC Control 2 (0xb5) */
1389 #define RT5640_DRC_AGC_POB_MASK 1389 #define RT5640_DRC_AGC_POB_MASK (0x3f << 8)
1390 #define RT5640_DRC_AGC_POB_SFT 1390 #define RT5640_DRC_AGC_POB_SFT 8
1391 #define RT5640_DRC_AGC_CP_MASK 1391 #define RT5640_DRC_AGC_CP_MASK (0x1 << 7)
1392 #define RT5640_DRC_AGC_CP_SFT 1392 #define RT5640_DRC_AGC_CP_SFT 7
1393 #define RT5640_DRC_AGC_CP_DIS 1393 #define RT5640_DRC_AGC_CP_DIS (0x0 << 7)
1394 #define RT5640_DRC_AGC_CP_EN 1394 #define RT5640_DRC_AGC_CP_EN (0x1 << 7)
1395 #define RT5640_DRC_AGC_CPR_MASK 1395 #define RT5640_DRC_AGC_CPR_MASK (0x3 << 5)
1396 #define RT5640_DRC_AGC_CPR_SFT 1396 #define RT5640_DRC_AGC_CPR_SFT 5
1397 #define RT5640_DRC_AGC_CPR_1_1 1397 #define RT5640_DRC_AGC_CPR_1_1 (0x0 << 5)
1398 #define RT5640_DRC_AGC_CPR_1_2 1398 #define RT5640_DRC_AGC_CPR_1_2 (0x1 << 5)
1399 #define RT5640_DRC_AGC_CPR_1_3 1399 #define RT5640_DRC_AGC_CPR_1_3 (0x2 << 5)
1400 #define RT5640_DRC_AGC_CPR_1_4 1400 #define RT5640_DRC_AGC_CPR_1_4 (0x3 << 5)
1401 #define RT5640_DRC_AGC_PRB_MASK 1401 #define RT5640_DRC_AGC_PRB_MASK (0x1f)
1402 #define RT5640_DRC_AGC_PRB_SFT 1402 #define RT5640_DRC_AGC_PRB_SFT 0
1403 1403
1404 /* DRC/AGC Control 3 (0xb6) */ 1404 /* DRC/AGC Control 3 (0xb6) */
1405 #define RT5640_DRC_AGC_NGB_MASK 1405 #define RT5640_DRC_AGC_NGB_MASK (0xf << 12)
1406 #define RT5640_DRC_AGC_NGB_SFT 1406 #define RT5640_DRC_AGC_NGB_SFT 12
1407 #define RT5640_DRC_AGC_TAR_MASK 1407 #define RT5640_DRC_AGC_TAR_MASK (0x1f << 7)
1408 #define RT5640_DRC_AGC_TAR_SFT 1408 #define RT5640_DRC_AGC_TAR_SFT 7
1409 #define RT5640_DRC_AGC_NG_MASK 1409 #define RT5640_DRC_AGC_NG_MASK (0x1 << 6)
1410 #define RT5640_DRC_AGC_NG_SFT 1410 #define RT5640_DRC_AGC_NG_SFT 6
1411 #define RT5640_DRC_AGC_NG_DIS 1411 #define RT5640_DRC_AGC_NG_DIS (0x0 << 6)
1412 #define RT5640_DRC_AGC_NG_EN 1412 #define RT5640_DRC_AGC_NG_EN (0x1 << 6)
1413 #define RT5640_DRC_AGC_NGH_MASK 1413 #define RT5640_DRC_AGC_NGH_MASK (0x1 << 5)
1414 #define RT5640_DRC_AGC_NGH_SFT 1414 #define RT5640_DRC_AGC_NGH_SFT 5
1415 #define RT5640_DRC_AGC_NGH_DIS 1415 #define RT5640_DRC_AGC_NGH_DIS (0x0 << 5)
1416 #define RT5640_DRC_AGC_NGH_EN 1416 #define RT5640_DRC_AGC_NGH_EN (0x1 << 5)
1417 #define RT5640_DRC_AGC_NGT_MASK 1417 #define RT5640_DRC_AGC_NGT_MASK (0x1f)
1418 #define RT5640_DRC_AGC_NGT_SFT 1418 #define RT5640_DRC_AGC_NGT_SFT 0
1419 1419
1420 /* ANC Control 1 (0xb8) */ 1420 /* ANC Control 1 (0xb8) */
1421 #define RT5640_ANC_M_MASK 1421 #define RT5640_ANC_M_MASK (0x1 << 15)
1422 #define RT5640_ANC_M_SFT 1422 #define RT5640_ANC_M_SFT 15
1423 #define RT5640_ANC_M_NOR 1423 #define RT5640_ANC_M_NOR (0x0 << 15)
1424 #define RT5640_ANC_M_REV 1424 #define RT5640_ANC_M_REV (0x1 << 15)
1425 #define RT5640_ANC_MASK 1425 #define RT5640_ANC_MASK (0x1 << 14)
1426 #define RT5640_ANC_SFT 1426 #define RT5640_ANC_SFT 14
1427 #define RT5640_ANC_DIS 1427 #define RT5640_ANC_DIS (0x0 << 14)
1428 #define RT5640_ANC_EN 1428 #define RT5640_ANC_EN (0x1 << 14)
1429 #define RT5640_ANC_MD_MASK 1429 #define RT5640_ANC_MD_MASK (0x3 << 12)
1430 #define RT5640_ANC_MD_SFT 1430 #define RT5640_ANC_MD_SFT 12
1431 #define RT5640_ANC_MD_DIS 1431 #define RT5640_ANC_MD_DIS (0x0 << 12)
1432 #define RT5640_ANC_MD_67MS 1432 #define RT5640_ANC_MD_67MS (0x1 << 12)
1433 #define RT5640_ANC_MD_267MS 1433 #define RT5640_ANC_MD_267MS (0x2 << 12)
1434 #define RT5640_ANC_MD_1067MS 1434 #define RT5640_ANC_MD_1067MS (0x3 << 12)
1435 #define RT5640_ANC_SN_MASK 1435 #define RT5640_ANC_SN_MASK (0x1 << 11)
1436 #define RT5640_ANC_SN_SFT 1436 #define RT5640_ANC_SN_SFT 11
1437 #define RT5640_ANC_SN_DIS 1437 #define RT5640_ANC_SN_DIS (0x0 << 11)
1438 #define RT5640_ANC_SN_EN 1438 #define RT5640_ANC_SN_EN (0x1 << 11)
1439 #define RT5640_ANC_CLK_MASK 1439 #define RT5640_ANC_CLK_MASK (0x1 << 10)
1440 #define RT5640_ANC_CLK_SFT 1440 #define RT5640_ANC_CLK_SFT 10
1441 #define RT5640_ANC_CLK_ANC 1441 #define RT5640_ANC_CLK_ANC (0x0 << 10)
1442 #define RT5640_ANC_CLK_REG 1442 #define RT5640_ANC_CLK_REG (0x1 << 10)
1443 #define RT5640_ANC_ZCD_MASK 1443 #define RT5640_ANC_ZCD_MASK (0x3 << 8)
1444 #define RT5640_ANC_ZCD_SFT 1444 #define RT5640_ANC_ZCD_SFT 8
1445 #define RT5640_ANC_ZCD_DIS 1445 #define RT5640_ANC_ZCD_DIS (0x0 << 8)
1446 #define RT5640_ANC_ZCD_T1 1446 #define RT5640_ANC_ZCD_T1 (0x1 << 8)
1447 #define RT5640_ANC_ZCD_T2 1447 #define RT5640_ANC_ZCD_T2 (0x2 << 8)
1448 #define RT5640_ANC_ZCD_WT 1448 #define RT5640_ANC_ZCD_WT (0x3 << 8)
1449 #define RT5640_ANC_CS_MASK 1449 #define RT5640_ANC_CS_MASK (0x1 << 7)
1450 #define RT5640_ANC_CS_SFT 1450 #define RT5640_ANC_CS_SFT 7
1451 #define RT5640_ANC_CS_DIS 1451 #define RT5640_ANC_CS_DIS (0x0 << 7)
1452 #define RT5640_ANC_CS_EN 1452 #define RT5640_ANC_CS_EN (0x1 << 7)
1453 #define RT5640_ANC_SW_MASK 1453 #define RT5640_ANC_SW_MASK (0x1 << 6)
1454 #define RT5640_ANC_SW_SFT 1454 #define RT5640_ANC_SW_SFT 6
1455 #define RT5640_ANC_SW_NOR 1455 #define RT5640_ANC_SW_NOR (0x0 << 6)
1456 #define RT5640_ANC_SW_AUTO 1456 #define RT5640_ANC_SW_AUTO (0x1 << 6)
1457 #define RT5640_ANC_CO_L_MASK 1457 #define RT5640_ANC_CO_L_MASK (0x3f)
1458 #define RT5640_ANC_CO_L_SFT 1458 #define RT5640_ANC_CO_L_SFT 0
1459 1459
1460 /* ANC Control 2 (0xb6) */ 1460 /* ANC Control 2 (0xb6) */
1461 #define RT5640_ANC_FG_R_MASK 1461 #define RT5640_ANC_FG_R_MASK (0xf << 12)
1462 #define RT5640_ANC_FG_R_SFT 1462 #define RT5640_ANC_FG_R_SFT 12
1463 #define RT5640_ANC_FG_L_MASK 1463 #define RT5640_ANC_FG_L_MASK (0xf << 8)
1464 #define RT5640_ANC_FG_L_SFT 1464 #define RT5640_ANC_FG_L_SFT 8
1465 #define RT5640_ANC_CG_R_MASK 1465 #define RT5640_ANC_CG_R_MASK (0xf << 4)
1466 #define RT5640_ANC_CG_R_SFT 1466 #define RT5640_ANC_CG_R_SFT 4
1467 #define RT5640_ANC_CG_L_MASK 1467 #define RT5640_ANC_CG_L_MASK (0xf)
1468 #define RT5640_ANC_CG_L_SFT 1468 #define RT5640_ANC_CG_L_SFT 0
1469 1469
1470 /* ANC Control 3 (0xb6) */ 1470 /* ANC Control 3 (0xb6) */
1471 #define RT5640_ANC_CD_MASK 1471 #define RT5640_ANC_CD_MASK (0x1 << 6)
1472 #define RT5640_ANC_CD_SFT 1472 #define RT5640_ANC_CD_SFT 6
1473 #define RT5640_ANC_CD_BOTH 1473 #define RT5640_ANC_CD_BOTH (0x0 << 6)
1474 #define RT5640_ANC_CD_IND 1474 #define RT5640_ANC_CD_IND (0x1 << 6)
1475 #define RT5640_ANC_CO_R_MASK 1475 #define RT5640_ANC_CO_R_MASK (0x3f)
1476 #define RT5640_ANC_CO_R_SFT 1476 #define RT5640_ANC_CO_R_SFT 0
1477 1477
1478 /* Jack Detect Control (0xbb) */ 1478 /* Jack Detect Control (0xbb) */
1479 #define RT5640_JD_MASK 1479 #define RT5640_JD_MASK (0x7 << 13)
1480 #define RT5640_JD_SFT 1480 #define RT5640_JD_SFT 13
1481 #define RT5640_JD_DIS 1481 #define RT5640_JD_DIS (0x0 << 13)
1482 #define RT5640_JD_GPIO1 1482 #define RT5640_JD_GPIO1 (0x1 << 13)
1483 #define RT5640_JD_JD1_IN4P 1483 #define RT5640_JD_JD1_IN4P (0x2 << 13)
1484 #define RT5640_JD_JD2_IN4N 1484 #define RT5640_JD_JD2_IN4N (0x3 << 13)
1485 #define RT5640_JD_GPIO2 1485 #define RT5640_JD_GPIO2 (0x4 << 13)
1486 #define RT5640_JD_GPIO3 1486 #define RT5640_JD_GPIO3 (0x5 << 13)
1487 #define RT5640_JD_GPIO4 1487 #define RT5640_JD_GPIO4 (0x6 << 13)
1488 #define RT5640_JD_HP_MASK 1488 #define RT5640_JD_HP_MASK (0x1 << 11)
1489 #define RT5640_JD_HP_SFT 1489 #define RT5640_JD_HP_SFT 11
1490 #define RT5640_JD_HP_DIS 1490 #define RT5640_JD_HP_DIS (0x0 << 11)
1491 #define RT5640_JD_HP_EN 1491 #define RT5640_JD_HP_EN (0x1 << 11)
1492 #define RT5640_JD_HP_TRG_MASK 1492 #define RT5640_JD_HP_TRG_MASK (0x1 << 10)
1493 #define RT5640_JD_HP_TRG_SFT 1493 #define RT5640_JD_HP_TRG_SFT 10
1494 #define RT5640_JD_HP_TRG_LO 1494 #define RT5640_JD_HP_TRG_LO (0x0 << 10)
1495 #define RT5640_JD_HP_TRG_HI 1495 #define RT5640_JD_HP_TRG_HI (0x1 << 10)
1496 #define RT5640_JD_SPL_MASK 1496 #define RT5640_JD_SPL_MASK (0x1 << 9)
1497 #define RT5640_JD_SPL_SFT 1497 #define RT5640_JD_SPL_SFT 9
1498 #define RT5640_JD_SPL_DIS 1498 #define RT5640_JD_SPL_DIS (0x0 << 9)
1499 #define RT5640_JD_SPL_EN 1499 #define RT5640_JD_SPL_EN (0x1 << 9)
1500 #define RT5640_JD_SPL_TRG_MASK 1500 #define RT5640_JD_SPL_TRG_MASK (0x1 << 8)
1501 #define RT5640_JD_SPL_TRG_SFT 1501 #define RT5640_JD_SPL_TRG_SFT 8
1502 #define RT5640_JD_SPL_TRG_LO 1502 #define RT5640_JD_SPL_TRG_LO (0x0 << 8)
1503 #define RT5640_JD_SPL_TRG_HI 1503 #define RT5640_JD_SPL_TRG_HI (0x1 << 8)
1504 #define RT5640_JD_SPR_MASK 1504 #define RT5640_JD_SPR_MASK (0x1 << 7)
1505 #define RT5640_JD_SPR_SFT 1505 #define RT5640_JD_SPR_SFT 7
1506 #define RT5640_JD_SPR_DIS 1506 #define RT5640_JD_SPR_DIS (0x0 << 7)
1507 #define RT5640_JD_SPR_EN 1507 #define RT5640_JD_SPR_EN (0x1 << 7)
1508 #define RT5640_JD_SPR_TRG_MASK 1508 #define RT5640_JD_SPR_TRG_MASK (0x1 << 6)
1509 #define RT5640_JD_SPR_TRG_SFT 1509 #define RT5640_JD_SPR_TRG_SFT 6
1510 #define RT5640_JD_SPR_TRG_LO 1510 #define RT5640_JD_SPR_TRG_LO (0x0 << 6)
1511 #define RT5640_JD_SPR_TRG_HI 1511 #define RT5640_JD_SPR_TRG_HI (0x1 << 6)
1512 #define RT5640_JD_MO_MASK 1512 #define RT5640_JD_MO_MASK (0x1 << 5)
1513 #define RT5640_JD_MO_SFT 1513 #define RT5640_JD_MO_SFT 5
1514 #define RT5640_JD_MO_DIS 1514 #define RT5640_JD_MO_DIS (0x0 << 5)
1515 #define RT5640_JD_MO_EN 1515 #define RT5640_JD_MO_EN (0x1 << 5)
1516 #define RT5640_JD_MO_TRG_MASK 1516 #define RT5640_JD_MO_TRG_MASK (0x1 << 4)
1517 #define RT5640_JD_MO_TRG_SFT 1517 #define RT5640_JD_MO_TRG_SFT 4
1518 #define RT5640_JD_MO_TRG_LO 1518 #define RT5640_JD_MO_TRG_LO (0x0 << 4)
1519 #define RT5640_JD_MO_TRG_HI 1519 #define RT5640_JD_MO_TRG_HI (0x1 << 4)
1520 #define RT5640_JD_LO_MASK 1520 #define RT5640_JD_LO_MASK (0x1 << 3)
1521 #define RT5640_JD_LO_SFT 1521 #define RT5640_JD_LO_SFT 3
1522 #define RT5640_JD_LO_DIS 1522 #define RT5640_JD_LO_DIS (0x0 << 3)
1523 #define RT5640_JD_LO_EN 1523 #define RT5640_JD_LO_EN (0x1 << 3)
1524 #define RT5640_JD_LO_TRG_MASK 1524 #define RT5640_JD_LO_TRG_MASK (0x1 << 2)
1525 #define RT5640_JD_LO_TRG_SFT 1525 #define RT5640_JD_LO_TRG_SFT 2
1526 #define RT5640_JD_LO_TRG_LO 1526 #define RT5640_JD_LO_TRG_LO (0x0 << 2)
1527 #define RT5640_JD_LO_TRG_HI 1527 #define RT5640_JD_LO_TRG_HI (0x1 << 2)
1528 #define RT5640_JD1_IN4P_MASK 1528 #define RT5640_JD1_IN4P_MASK (0x1 << 1)
1529 #define RT5640_JD1_IN4P_SFT 1529 #define RT5640_JD1_IN4P_SFT 1
1530 #define RT5640_JD1_IN4P_DIS 1530 #define RT5640_JD1_IN4P_DIS (0x0 << 1)
1531 #define RT5640_JD1_IN4P_EN 1531 #define RT5640_JD1_IN4P_EN (0x1 << 1)
1532 #define RT5640_JD2_IN4N_MASK 1532 #define RT5640_JD2_IN4N_MASK (0x1)
1533 #define RT5640_JD2_IN4N_SFT 1533 #define RT5640_JD2_IN4N_SFT 0
1534 #define RT5640_JD2_IN4N_DIS 1534 #define RT5640_JD2_IN4N_DIS (0x0)
1535 #define RT5640_JD2_IN4N_EN 1535 #define RT5640_JD2_IN4N_EN (0x1)
1536 1536
1537 /* Jack detect for ANC (0xbc) */ 1537 /* Jack detect for ANC (0xbc) */
1538 #define RT5640_ANC_DET_MASK 1538 #define RT5640_ANC_DET_MASK (0x3 << 4)
1539 #define RT5640_ANC_DET_SFT 1539 #define RT5640_ANC_DET_SFT 4
1540 #define RT5640_ANC_DET_DIS 1540 #define RT5640_ANC_DET_DIS (0x0 << 4)
1541 #define RT5640_ANC_DET_MB1 1541 #define RT5640_ANC_DET_MB1 (0x1 << 4)
1542 #define RT5640_ANC_DET_MB2 1542 #define RT5640_ANC_DET_MB2 (0x2 << 4)
1543 #define RT5640_ANC_DET_JD 1543 #define RT5640_ANC_DET_JD (0x3 << 4)
1544 #define RT5640_AD_TRG_MASK 1544 #define RT5640_AD_TRG_MASK (0x1 << 3)
1545 #define RT5640_AD_TRG_SFT 1545 #define RT5640_AD_TRG_SFT 3
1546 #define RT5640_AD_TRG_LO 1546 #define RT5640_AD_TRG_LO (0x0 << 3)
1547 #define RT5640_AD_TRG_HI 1547 #define RT5640_AD_TRG_HI (0x1 << 3)
1548 #define RT5640_ANCM_DET_MASK 1548 #define RT5640_ANCM_DET_MASK (0x3 << 4)
1549 #define RT5640_ANCM_DET_SFT 1549 #define RT5640_ANCM_DET_SFT 4
1550 #define RT5640_ANCM_DET_DIS 1550 #define RT5640_ANCM_DET_DIS (0x0 << 4)
1551 #define RT5640_ANCM_DET_MB1 1551 #define RT5640_ANCM_DET_MB1 (0x1 << 4)
1552 #define RT5640_ANCM_DET_MB2 1552 #define RT5640_ANCM_DET_MB2 (0x2 << 4)
1553 #define RT5640_ANCM_DET_JD 1553 #define RT5640_ANCM_DET_JD (0x3 << 4)
1554 #define RT5640_AMD_TRG_MASK 1554 #define RT5640_AMD_TRG_MASK (0x1 << 3)
1555 #define RT5640_AMD_TRG_SFT 1555 #define RT5640_AMD_TRG_SFT 3
1556 #define RT5640_AMD_TRG_LO 1556 #define RT5640_AMD_TRG_LO (0x0 << 3)
1557 #define RT5640_AMD_TRG_HI 1557 #define RT5640_AMD_TRG_HI (0x1 << 3)
1558 1558
1559 /* IRQ Control 1 (0xbd) */ 1559 /* IRQ Control 1 (0xbd) */
1560 #define RT5640_IRQ_JD_MASK 1560 #define RT5640_IRQ_JD_MASK (0x1 << 15)
1561 #define RT5640_IRQ_JD_SFT 1561 #define RT5640_IRQ_JD_SFT 15
1562 #define RT5640_IRQ_JD_BP 1562 #define RT5640_IRQ_JD_BP (0x0 << 15)
1563 #define RT5640_IRQ_JD_NOR 1563 #define RT5640_IRQ_JD_NOR (0x1 << 15)
1564 #define RT5640_IRQ_OT_MASK 1564 #define RT5640_IRQ_OT_MASK (0x1 << 14)
1565 #define RT5640_IRQ_OT_SFT 1565 #define RT5640_IRQ_OT_SFT 14
1566 #define RT5640_IRQ_OT_BP 1566 #define RT5640_IRQ_OT_BP (0x0 << 14)
1567 #define RT5640_IRQ_OT_NOR 1567 #define RT5640_IRQ_OT_NOR (0x1 << 14)
1568 #define RT5640_JD_STKY_MASK 1568 #define RT5640_JD_STKY_MASK (0x1 << 13)
1569 #define RT5640_JD_STKY_SFT 1569 #define RT5640_JD_STKY_SFT 13
1570 #define RT5640_JD_STKY_DIS 1570 #define RT5640_JD_STKY_DIS (0x0 << 13)
1571 #define RT5640_JD_STKY_EN 1571 #define RT5640_JD_STKY_EN (0x1 << 13)
1572 #define RT5640_OT_STKY_MASK 1572 #define RT5640_OT_STKY_MASK (0x1 << 12)
1573 #define RT5640_OT_STKY_SFT 1573 #define RT5640_OT_STKY_SFT 12
1574 #define RT5640_OT_STKY_DIS 1574 #define RT5640_OT_STKY_DIS (0x0 << 12)
1575 #define RT5640_OT_STKY_EN 1575 #define RT5640_OT_STKY_EN (0x1 << 12)
1576 #define RT5640_JD_P_MASK 1576 #define RT5640_JD_P_MASK (0x1 << 11)
1577 #define RT5640_JD_P_SFT 1577 #define RT5640_JD_P_SFT 11
1578 #define RT5640_JD_P_NOR 1578 #define RT5640_JD_P_NOR (0x0 << 11)
1579 #define RT5640_JD_P_INV 1579 #define RT5640_JD_P_INV (0x1 << 11)
1580 #define RT5640_OT_P_MASK 1580 #define RT5640_OT_P_MASK (0x1 << 10)
1581 #define RT5640_OT_P_SFT 1581 #define RT5640_OT_P_SFT 10
1582 #define RT5640_OT_P_NOR 1582 #define RT5640_OT_P_NOR (0x0 << 10)
1583 #define RT5640_OT_P_INV 1583 #define RT5640_OT_P_INV (0x1 << 10)
1584 1584
1585 /* IRQ Control 2 (0xbe) */ 1585 /* IRQ Control 2 (0xbe) */
1586 #define RT5640_IRQ_MB1_OC_MASK 1586 #define RT5640_IRQ_MB1_OC_MASK (0x1 << 15)
1587 #define RT5640_IRQ_MB1_OC_SFT 1587 #define RT5640_IRQ_MB1_OC_SFT 15
1588 #define RT5640_IRQ_MB1_OC_BP 1588 #define RT5640_IRQ_MB1_OC_BP (0x0 << 15)
1589 #define RT5640_IRQ_MB1_OC_NOR 1589 #define RT5640_IRQ_MB1_OC_NOR (0x1 << 15)
1590 #define RT5640_IRQ_MB2_OC_MASK 1590 #define RT5640_IRQ_MB2_OC_MASK (0x1 << 14)
1591 #define RT5640_IRQ_MB2_OC_SFT 1591 #define RT5640_IRQ_MB2_OC_SFT 14
1592 #define RT5640_IRQ_MB2_OC_BP 1592 #define RT5640_IRQ_MB2_OC_BP (0x0 << 14)
1593 #define RT5640_IRQ_MB2_OC_NOR 1593 #define RT5640_IRQ_MB2_OC_NOR (0x1 << 14)
1594 #define RT5640_MB1_OC_STKY_MASK 1594 #define RT5640_MB1_OC_STKY_MASK (0x1 << 11)
1595 #define RT5640_MB1_OC_STKY_SFT 1595 #define RT5640_MB1_OC_STKY_SFT 11
1596 #define RT5640_MB1_OC_STKY_DIS 1596 #define RT5640_MB1_OC_STKY_DIS (0x0 << 11)
1597 #define RT5640_MB1_OC_STKY_EN 1597 #define RT5640_MB1_OC_STKY_EN (0x1 << 11)
1598 #define RT5640_MB2_OC_STKY_MASK 1598 #define RT5640_MB2_OC_STKY_MASK (0x1 << 10)
1599 #define RT5640_MB2_OC_STKY_SFT 1599 #define RT5640_MB2_OC_STKY_SFT 10
1600 #define RT5640_MB2_OC_STKY_DIS 1600 #define RT5640_MB2_OC_STKY_DIS (0x0 << 10)
1601 #define RT5640_MB2_OC_STKY_EN 1601 #define RT5640_MB2_OC_STKY_EN (0x1 << 10)
1602 #define RT5640_MB1_OC_P_MASK 1602 #define RT5640_MB1_OC_P_MASK (0x1 << 7)
1603 #define RT5640_MB1_OC_P_SFT 1603 #define RT5640_MB1_OC_P_SFT 7
1604 #define RT5640_MB1_OC_P_NOR 1604 #define RT5640_MB1_OC_P_NOR (0x0 << 7)
1605 #define RT5640_MB1_OC_P_INV 1605 #define RT5640_MB1_OC_P_INV (0x1 << 7)
1606 #define RT5640_MB2_OC_P_MASK 1606 #define RT5640_MB2_OC_P_MASK (0x1 << 6)
1607 #define RT5640_MB2_OC_P_SFT 1607 #define RT5640_MB2_OC_P_SFT 6
1608 #define RT5640_MB2_OC_P_NOR 1608 #define RT5640_MB2_OC_P_NOR (0x0 << 6)
1609 #define RT5640_MB2_OC_P_INV 1609 #define RT5640_MB2_OC_P_INV (0x1 << 6)
1610 #define RT5640_MB1_OC_STATUS 1610 #define RT5640_MB1_OC_STATUS (0x1 << 3)
1611 #define RT5640_MB1_OC_STATUS_SFT 1611 #define RT5640_MB1_OC_STATUS_SFT 3
1612 #define RT5640_MB2_OC_STATUS 1612 #define RT5640_MB2_OC_STATUS (0x1 << 2)
1613 #define RT5640_MB2_OC_STATUS_SFT 1613 #define RT5640_MB2_OC_STATUS_SFT 2
1614 1614
1615 /* GPIO and Internal Status (0xbf) */ 1615 /* GPIO and Internal Status (0xbf) */
1616 #define RT5640_GPIO1_STATUS 1616 #define RT5640_GPIO1_STATUS (0x1 << 8)
1617 #define RT5640_GPIO2_STATUS 1617 #define RT5640_GPIO2_STATUS (0x1 << 7)
1618 #define RT5640_JD_STATUS 1618 #define RT5640_JD_STATUS (0x1 << 4)
1619 #define RT5640_OVT_STATUS 1619 #define RT5640_OVT_STATUS (0x1 << 3)
1620 #define RT5640_CLS_D_OVCD_STATUS 1620 #define RT5640_CLS_D_OVCD_STATUS (0x1 << 0)
1621 1621
1622 /* GPIO Control 1 (0xc0) */ 1622 /* GPIO Control 1 (0xc0) */
1623 #define RT5640_GP1_PIN_MASK 1623 #define RT5640_GP1_PIN_MASK (0x1 << 15)
1624 #define RT5640_GP1_PIN_SFT 1624 #define RT5640_GP1_PIN_SFT 15
1625 #define RT5640_GP1_PIN_GPIO1 1625 #define RT5640_GP1_PIN_GPIO1 (0x0 << 15)
1626 #define RT5640_GP1_PIN_IRQ 1626 #define RT5640_GP1_PIN_IRQ (0x1 << 15)
1627 #define RT5640_GP2_PIN_MASK 1627 #define RT5640_GP2_PIN_MASK (0x1 << 14)
1628 #define RT5640_GP2_PIN_SFT 1628 #define RT5640_GP2_PIN_SFT 14
1629 #define RT5640_GP2_PIN_GPIO2 1629 #define RT5640_GP2_PIN_GPIO2 (0x0 << 14)
1630 #define RT5640_GP2_PIN_DMIC1_SCL 1630 #define RT5640_GP2_PIN_DMIC1_SCL (0x1 << 14)
1631 #define RT5640_GP3_PIN_MASK 1631 #define RT5640_GP3_PIN_MASK (0x3 << 12)
1632 #define RT5640_GP3_PIN_SFT 1632 #define RT5640_GP3_PIN_SFT 12
1633 #define RT5640_GP3_PIN_GPIO3 1633 #define RT5640_GP3_PIN_GPIO3 (0x0 << 12)
1634 #define RT5640_GP3_PIN_DMIC1_SDA 1634 #define RT5640_GP3_PIN_DMIC1_SDA (0x1 << 12)
1635 #define RT5640_GP3_PIN_IRQ 1635 #define RT5640_GP3_PIN_IRQ (0x2 << 12)
1636 #define RT5640_GP4_PIN_MASK 1636 #define RT5640_GP4_PIN_MASK (0x1 << 11)
1637 #define RT5640_GP4_PIN_SFT 1637 #define RT5640_GP4_PIN_SFT 11
1638 #define RT5640_GP4_PIN_GPIO4 1638 #define RT5640_GP4_PIN_GPIO4 (0x0 << 11)
1639 #define RT5640_GP4_PIN_DMIC2_SDA 1639 #define RT5640_GP4_PIN_DMIC2_SDA (0x1 << 11)
1640 #define RT5640_DP_SIG_MASK 1640 #define RT5640_DP_SIG_MASK (0x1 << 10)
1641 #define RT5640_DP_SIG_SFT 1641 #define RT5640_DP_SIG_SFT 10
1642 #define RT5640_DP_SIG_TEST 1642 #define RT5640_DP_SIG_TEST (0x0 << 10)
1643 #define RT5640_DP_SIG_AP 1643 #define RT5640_DP_SIG_AP (0x1 << 10)
1644 #define RT5640_GPIO_M_MASK 1644 #define RT5640_GPIO_M_MASK (0x1 << 9)
1645 #define RT5640_GPIO_M_SFT 1645 #define RT5640_GPIO_M_SFT 9
1646 #define RT5640_GPIO_M_FLT 1646 #define RT5640_GPIO_M_FLT (0x0 << 9)
1647 #define RT5640_GPIO_M_PH 1647 #define RT5640_GPIO_M_PH (0x1 << 9)
1648 1648
1649 /* GPIO Control 3 (0xc2) */ 1649 /* GPIO Control 3 (0xc2) */
1650 #define RT5640_GP4_PF_MASK 1650 #define RT5640_GP4_PF_MASK (0x1 << 11)
1651 #define RT5640_GP4_PF_SFT 1651 #define RT5640_GP4_PF_SFT 11
1652 #define RT5640_GP4_PF_IN 1652 #define RT5640_GP4_PF_IN (0x0 << 11)
1653 #define RT5640_GP4_PF_OUT 1653 #define RT5640_GP4_PF_OUT (0x1 << 11)
1654 #define RT5640_GP4_OUT_MASK 1654 #define RT5640_GP4_OUT_MASK (0x1 << 10)
1655 #define RT5640_GP4_OUT_SFT 1655 #define RT5640_GP4_OUT_SFT 10
1656 #define RT5640_GP4_OUT_LO 1656 #define RT5640_GP4_OUT_LO (0x0 << 10)
1657 #define RT5640_GP4_OUT_HI 1657 #define RT5640_GP4_OUT_HI (0x1 << 10)
1658 #define RT5640_GP4_P_MASK 1658 #define RT5640_GP4_P_MASK (0x1 << 9)
1659 #define RT5640_GP4_P_SFT 1659 #define RT5640_GP4_P_SFT 9
1660 #define RT5640_GP4_P_NOR 1660 #define RT5640_GP4_P_NOR (0x0 << 9)
1661 #define RT5640_GP4_P_INV 1661 #define RT5640_GP4_P_INV (0x1 << 9)
1662 #define RT5640_GP3_PF_MASK 1662 #define RT5640_GP3_PF_MASK (0x1 << 8)
1663 #define RT5640_GP3_PF_SFT 1663 #define RT5640_GP3_PF_SFT 8
1664 #define RT5640_GP3_PF_IN 1664 #define RT5640_GP3_PF_IN (0x0 << 8)
1665 #define RT5640_GP3_PF_OUT 1665 #define RT5640_GP3_PF_OUT (0x1 << 8)
1666 #define RT5640_GP3_OUT_MASK 1666 #define RT5640_GP3_OUT_MASK (0x1 << 7)
1667 #define RT5640_GP3_OUT_SFT 1667 #define RT5640_GP3_OUT_SFT 7
1668 #define RT5640_GP3_OUT_LO 1668 #define RT5640_GP3_OUT_LO (0x0 << 7)
1669 #define RT5640_GP3_OUT_HI 1669 #define RT5640_GP3_OUT_HI (0x1 << 7)
1670 #define RT5640_GP3_P_MASK 1670 #define RT5640_GP3_P_MASK (0x1 << 6)
1671 #define RT5640_GP3_P_SFT 1671 #define RT5640_GP3_P_SFT 6
1672 #define RT5640_GP3_P_NOR 1672 #define RT5640_GP3_P_NOR (0x0 << 6)
1673 #define RT5640_GP3_P_INV 1673 #define RT5640_GP3_P_INV (0x1 << 6)
1674 #define RT5640_GP2_PF_MASK 1674 #define RT5640_GP2_PF_MASK (0x1 << 5)
1675 #define RT5640_GP2_PF_SFT 1675 #define RT5640_GP2_PF_SFT 5
1676 #define RT5640_GP2_PF_IN 1676 #define RT5640_GP2_PF_IN (0x0 << 5)
1677 #define RT5640_GP2_PF_OUT 1677 #define RT5640_GP2_PF_OUT (0x1 << 5)
1678 #define RT5640_GP2_OUT_MASK 1678 #define RT5640_GP2_OUT_MASK (0x1 << 4)
1679 #define RT5640_GP2_OUT_SFT 1679 #define RT5640_GP2_OUT_SFT 4
1680 #define RT5640_GP2_OUT_LO 1680 #define RT5640_GP2_OUT_LO (0x0 << 4)
1681 #define RT5640_GP2_OUT_HI 1681 #define RT5640_GP2_OUT_HI (0x1 << 4)
1682 #define RT5640_GP2_P_MASK 1682 #define RT5640_GP2_P_MASK (0x1 << 3)
1683 #define RT5640_GP2_P_SFT 1683 #define RT5640_GP2_P_SFT 3
1684 #define RT5640_GP2_P_NOR 1684 #define RT5640_GP2_P_NOR (0x0 << 3)
1685 #define RT5640_GP2_P_INV 1685 #define RT5640_GP2_P_INV (0x1 << 3)
1686 #define RT5640_GP1_PF_MASK 1686 #define RT5640_GP1_PF_MASK (0x1 << 2)
1687 #define RT5640_GP1_PF_SFT 1687 #define RT5640_GP1_PF_SFT 2
1688 #define RT5640_GP1_PF_IN 1688 #define RT5640_GP1_PF_IN (0x0 << 2)
1689 #define RT5640_GP1_PF_OUT 1689 #define RT5640_GP1_PF_OUT (0x1 << 2)
1690 #define RT5640_GP1_OUT_MASK 1690 #define RT5640_GP1_OUT_MASK (0x1 << 1)
1691 #define RT5640_GP1_OUT_SFT 1691 #define RT5640_GP1_OUT_SFT 1
1692 #define RT5640_GP1_OUT_LO 1692 #define RT5640_GP1_OUT_LO (0x0 << 1)
1693 #define RT5640_GP1_OUT_HI 1693 #define RT5640_GP1_OUT_HI (0x1 << 1)
1694 #define RT5640_GP1_P_MASK 1694 #define RT5640_GP1_P_MASK (0x1)
1695 #define RT5640_GP1_P_SFT 1695 #define RT5640_GP1_P_SFT 0
1696 #define RT5640_GP1_P_NOR 1696 #define RT5640_GP1_P_NOR (0x0)
1697 #define RT5640_GP1_P_INV 1697 #define RT5640_GP1_P_INV (0x1)
1698 1698
1699 /* FM34-500 Register Control 1 (0xc4) */ 1699 /* FM34-500 Register Control 1 (0xc4) */
1700 #define RT5640_DSP_ADD_SFT 1700 #define RT5640_DSP_ADD_SFT 0
1701 1701
1702 /* FM34-500 Register Control 2 (0xc5) */ 1702 /* FM34-500 Register Control 2 (0xc5) */
1703 #define RT5640_DSP_DAT_SFT 1703 #define RT5640_DSP_DAT_SFT 0
1704 1704
1705 /* FM34-500 Register Control 3 (0xc6) */ 1705 /* FM34-500 Register Control 3 (0xc6) */
1706 #define RT5640_DSP_BUSY_MASK 1706 #define RT5640_DSP_BUSY_MASK (0x1 << 15)
1707 #define RT5640_DSP_BUSY_BIT 1707 #define RT5640_DSP_BUSY_BIT 15
1708 #define RT5640_DSP_DS_MASK 1708 #define RT5640_DSP_DS_MASK (0x1 << 14)
1709 #define RT5640_DSP_DS_SFT 1709 #define RT5640_DSP_DS_SFT 14
1710 #define RT5640_DSP_DS_FM3010 1710 #define RT5640_DSP_DS_FM3010 (0x1 << 14)
1711 #define RT5640_DSP_DS_TEMP 1711 #define RT5640_DSP_DS_TEMP (0x1 << 14)
1712 #define RT5640_DSP_CLK_MASK 1712 #define RT5640_DSP_CLK_MASK (0x3 << 12)
1713 #define RT5640_DSP_CLK_SFT 1713 #define RT5640_DSP_CLK_SFT 12
1714 #define RT5640_DSP_CLK_384K 1714 #define RT5640_DSP_CLK_384K (0x0 << 12)
1715 #define RT5640_DSP_CLK_192K 1715 #define RT5640_DSP_CLK_192K (0x1 << 12)
1716 #define RT5640_DSP_CLK_96K 1716 #define RT5640_DSP_CLK_96K (0x2 << 12)
1717 #define RT5640_DSP_CLK_64K 1717 #define RT5640_DSP_CLK_64K (0x3 << 12)
1718 #define RT5640_DSP_PD_PIN_MASK 1718 #define RT5640_DSP_PD_PIN_MASK (0x1 << 11)
1719 #define RT5640_DSP_PD_PIN_SFT 1719 #define RT5640_DSP_PD_PIN_SFT 11
1720 #define RT5640_DSP_PD_PIN_LO 1720 #define RT5640_DSP_PD_PIN_LO (0x0 << 11)
1721 #define RT5640_DSP_PD_PIN_HI 1721 #define RT5640_DSP_PD_PIN_HI (0x1 << 11)
1722 #define RT5640_DSP_RST_PIN_MASK 1722 #define RT5640_DSP_RST_PIN_MASK (0x1 << 10)
1723 #define RT5640_DSP_RST_PIN_SFT 1723 #define RT5640_DSP_RST_PIN_SFT 10
1724 #define RT5640_DSP_RST_PIN_LO 1724 #define RT5640_DSP_RST_PIN_LO (0x0 << 10)
1725 #define RT5640_DSP_RST_PIN_HI 1725 #define RT5640_DSP_RST_PIN_HI (0x1 << 10)
1726 #define RT5640_DSP_R_EN 1726 #define RT5640_DSP_R_EN (0x1 << 9)
1727 #define RT5640_DSP_R_EN_BIT 1727 #define RT5640_DSP_R_EN_BIT 9
1728 #define RT5640_DSP_W_EN 1728 #define RT5640_DSP_W_EN (0x1 << 8)
1729 #define RT5640_DSP_W_EN_BIT 1729 #define RT5640_DSP_W_EN_BIT 8
1730 #define RT5640_DSP_CMD_MASK 1730 #define RT5640_DSP_CMD_MASK (0xff)
1731 #define RT5640_DSP_CMD_SFT 1731 #define RT5640_DSP_CMD_SFT 0
1732 #define RT5640_DSP_CMD_MW 1732 #define RT5640_DSP_CMD_MW (0x3B) /* Memory Write */
1733 #define RT5640_DSP_CMD_MR 1733 #define RT5640_DSP_CMD_MR (0x37) /* Memory Read */
1734 #define RT5640_DSP_CMD_RR 1734 #define RT5640_DSP_CMD_RR (0x60) /* Register Read */
1735 #define RT5640_DSP_CMD_RW 1735 #define RT5640_DSP_CMD_RW (0x68) /* Register Write */
1736 1736
1737 /* Programmable Register Array Control 1 (0xc 1737 /* Programmable Register Array Control 1 (0xc8) */
1738 #define RT5640_REG_SEQ_MASK 1738 #define RT5640_REG_SEQ_MASK (0xf << 12)
1739 #define RT5640_REG_SEQ_SFT 1739 #define RT5640_REG_SEQ_SFT 12
1740 #define RT5640_SEQ1_ST_MASK 1740 #define RT5640_SEQ1_ST_MASK (0x1 << 11) /*RO*/
1741 #define RT5640_SEQ1_ST_SFT 1741 #define RT5640_SEQ1_ST_SFT 11
1742 #define RT5640_SEQ1_ST_RUN 1742 #define RT5640_SEQ1_ST_RUN (0x0 << 11)
1743 #define RT5640_SEQ1_ST_FIN 1743 #define RT5640_SEQ1_ST_FIN (0x1 << 11)
1744 #define RT5640_SEQ2_ST_MASK 1744 #define RT5640_SEQ2_ST_MASK (0x1 << 10) /*RO*/
1745 #define RT5640_SEQ2_ST_SFT 1745 #define RT5640_SEQ2_ST_SFT 10
1746 #define RT5640_SEQ2_ST_RUN 1746 #define RT5640_SEQ2_ST_RUN (0x0 << 10)
1747 #define RT5640_SEQ2_ST_FIN 1747 #define RT5640_SEQ2_ST_FIN (0x1 << 10)
1748 #define RT5640_REG_LV_MASK 1748 #define RT5640_REG_LV_MASK (0x1 << 9)
1749 #define RT5640_REG_LV_SFT 1749 #define RT5640_REG_LV_SFT 9
1750 #define RT5640_REG_LV_MX 1750 #define RT5640_REG_LV_MX (0x0 << 9)
1751 #define RT5640_REG_LV_PR 1751 #define RT5640_REG_LV_PR (0x1 << 9)
1752 #define RT5640_SEQ_2_PT_MASK 1752 #define RT5640_SEQ_2_PT_MASK (0x1 << 8)
1753 #define RT5640_SEQ_2_PT_BIT 1753 #define RT5640_SEQ_2_PT_BIT 8
1754 #define RT5640_REG_IDX_MASK 1754 #define RT5640_REG_IDX_MASK (0xff)
1755 #define RT5640_REG_IDX_SFT 1755 #define RT5640_REG_IDX_SFT 0
1756 1756
1757 /* Programmable Register Array Control 2 (0xc 1757 /* Programmable Register Array Control 2 (0xc9) */
1758 #define RT5640_REG_DAT_MASK 1758 #define RT5640_REG_DAT_MASK (0xffff)
1759 #define RT5640_REG_DAT_SFT 1759 #define RT5640_REG_DAT_SFT 0
1760 1760
1761 /* Programmable Register Array Control 3 (0xc 1761 /* Programmable Register Array Control 3 (0xca) */
1762 #define RT5640_SEQ_DLY_MASK 1762 #define RT5640_SEQ_DLY_MASK (0xff << 8)
1763 #define RT5640_SEQ_DLY_SFT 1763 #define RT5640_SEQ_DLY_SFT 8
1764 #define RT5640_PROG_MASK 1764 #define RT5640_PROG_MASK (0x1 << 7)
1765 #define RT5640_PROG_SFT 1765 #define RT5640_PROG_SFT 7
1766 #define RT5640_PROG_DIS 1766 #define RT5640_PROG_DIS (0x0 << 7)
1767 #define RT5640_PROG_EN 1767 #define RT5640_PROG_EN (0x1 << 7)
1768 #define RT5640_SEQ1_PT_RUN 1768 #define RT5640_SEQ1_PT_RUN (0x1 << 6)
1769 #define RT5640_SEQ1_PT_RUN_BIT 1769 #define RT5640_SEQ1_PT_RUN_BIT 6
1770 #define RT5640_SEQ2_PT_RUN 1770 #define RT5640_SEQ2_PT_RUN (0x1 << 5)
1771 #define RT5640_SEQ2_PT_RUN_BIT 1771 #define RT5640_SEQ2_PT_RUN_BIT 5
1772 1772
1773 /* Programmable Register Array Control 4 (0xc 1773 /* Programmable Register Array Control 4 (0xcb) */
1774 #define RT5640_SEQ1_START_MASK 1774 #define RT5640_SEQ1_START_MASK (0xf << 8)
1775 #define RT5640_SEQ1_START_SFT 1775 #define RT5640_SEQ1_START_SFT 8
1776 #define RT5640_SEQ1_END_MASK 1776 #define RT5640_SEQ1_END_MASK (0xf)
1777 #define RT5640_SEQ1_END_SFT 1777 #define RT5640_SEQ1_END_SFT 0
1778 1778
1779 /* Programmable Register Array Control 5 (0xc 1779 /* Programmable Register Array Control 5 (0xcc) */
1780 #define RT5640_SEQ2_START_MASK 1780 #define RT5640_SEQ2_START_MASK (0xf << 8)
1781 #define RT5640_SEQ2_START_SFT 1781 #define RT5640_SEQ2_START_SFT 8
1782 #define RT5640_SEQ2_END_MASK 1782 #define RT5640_SEQ2_END_MASK (0xf)
1783 #define RT5640_SEQ2_END_SFT 1783 #define RT5640_SEQ2_END_SFT 0
1784 1784
1785 /* Scramble Function (0xcd) */ 1785 /* Scramble Function (0xcd) */
1786 #define RT5640_SCB_KEY_MASK 1786 #define RT5640_SCB_KEY_MASK (0xff)
1787 #define RT5640_SCB_KEY_SFT 1787 #define RT5640_SCB_KEY_SFT 0
1788 1788
1789 /* Scramble Control (0xce) */ 1789 /* Scramble Control (0xce) */
1790 #define RT5640_SCB_SWAP_MASK 1790 #define RT5640_SCB_SWAP_MASK (0x1 << 15)
1791 #define RT5640_SCB_SWAP_SFT 1791 #define RT5640_SCB_SWAP_SFT 15
1792 #define RT5640_SCB_SWAP_DIS 1792 #define RT5640_SCB_SWAP_DIS (0x0 << 15)
1793 #define RT5640_SCB_SWAP_EN 1793 #define RT5640_SCB_SWAP_EN (0x1 << 15)
1794 #define RT5640_SCB_MASK 1794 #define RT5640_SCB_MASK (0x1 << 14)
1795 #define RT5640_SCB_SFT 1795 #define RT5640_SCB_SFT 14
1796 #define RT5640_SCB_DIS 1796 #define RT5640_SCB_DIS (0x0 << 14)
1797 #define RT5640_SCB_EN 1797 #define RT5640_SCB_EN (0x1 << 14)
1798 1798
1799 /* Baseback Control (0xcf) */ 1799 /* Baseback Control (0xcf) */
1800 #define RT5640_BB_MASK 1800 #define RT5640_BB_MASK (0x1 << 15)
1801 #define RT5640_BB_SFT 1801 #define RT5640_BB_SFT 15
1802 #define RT5640_BB_DIS 1802 #define RT5640_BB_DIS (0x0 << 15)
1803 #define RT5640_BB_EN 1803 #define RT5640_BB_EN (0x1 << 15)
1804 #define RT5640_BB_CT_MASK 1804 #define RT5640_BB_CT_MASK (0x7 << 12)
1805 #define RT5640_BB_CT_SFT 1805 #define RT5640_BB_CT_SFT 12
1806 #define RT5640_BB_CT_A 1806 #define RT5640_BB_CT_A (0x0 << 12)
1807 #define RT5640_BB_CT_B 1807 #define RT5640_BB_CT_B (0x1 << 12)
1808 #define RT5640_BB_CT_C 1808 #define RT5640_BB_CT_C (0x2 << 12)
1809 #define RT5640_BB_CT_D 1809 #define RT5640_BB_CT_D (0x3 << 12)
1810 #define RT5640_M_BB_L_MASK 1810 #define RT5640_M_BB_L_MASK (0x1 << 9)
1811 #define RT5640_M_BB_L_SFT 1811 #define RT5640_M_BB_L_SFT 9
1812 #define RT5640_M_BB_R_MASK 1812 #define RT5640_M_BB_R_MASK (0x1 << 8)
1813 #define RT5640_M_BB_R_SFT 1813 #define RT5640_M_BB_R_SFT 8
1814 #define RT5640_M_BB_HPF_L_MASK 1814 #define RT5640_M_BB_HPF_L_MASK (0x1 << 7)
1815 #define RT5640_M_BB_HPF_L_SFT 1815 #define RT5640_M_BB_HPF_L_SFT 7
1816 #define RT5640_M_BB_HPF_R_MASK 1816 #define RT5640_M_BB_HPF_R_MASK (0x1 << 6)
1817 #define RT5640_M_BB_HPF_R_SFT 1817 #define RT5640_M_BB_HPF_R_SFT 6
1818 #define RT5640_G_BB_BST_MASK 1818 #define RT5640_G_BB_BST_MASK (0x3f)
1819 #define RT5640_G_BB_BST_SFT 1819 #define RT5640_G_BB_BST_SFT 0
1820 1820
1821 /* MP3 Plus Control 1 (0xd0) */ 1821 /* MP3 Plus Control 1 (0xd0) */
1822 #define RT5640_M_MP3_L_MASK 1822 #define RT5640_M_MP3_L_MASK (0x1 << 15)
1823 #define RT5640_M_MP3_L_SFT 1823 #define RT5640_M_MP3_L_SFT 15
1824 #define RT5640_M_MP3_R_MASK 1824 #define RT5640_M_MP3_R_MASK (0x1 << 14)
1825 #define RT5640_M_MP3_R_SFT 1825 #define RT5640_M_MP3_R_SFT 14
1826 #define RT5640_M_MP3_MASK 1826 #define RT5640_M_MP3_MASK (0x1 << 13)
1827 #define RT5640_M_MP3_SFT 1827 #define RT5640_M_MP3_SFT 13
1828 #define RT5640_M_MP3_DIS 1828 #define RT5640_M_MP3_DIS (0x0 << 13)
1829 #define RT5640_M_MP3_EN 1829 #define RT5640_M_MP3_EN (0x1 << 13)
1830 #define RT5640_EG_MP3_MASK 1830 #define RT5640_EG_MP3_MASK (0x1f << 8)
1831 #define RT5640_EG_MP3_SFT 1831 #define RT5640_EG_MP3_SFT 8
1832 #define RT5640_MP3_HLP_MASK 1832 #define RT5640_MP3_HLP_MASK (0x1 << 7)
1833 #define RT5640_MP3_HLP_SFT 1833 #define RT5640_MP3_HLP_SFT 7
1834 #define RT5640_MP3_HLP_DIS 1834 #define RT5640_MP3_HLP_DIS (0x0 << 7)
1835 #define RT5640_MP3_HLP_EN 1835 #define RT5640_MP3_HLP_EN (0x1 << 7)
1836 #define RT5640_M_MP3_ORG_L_MASK 1836 #define RT5640_M_MP3_ORG_L_MASK (0x1 << 6)
1837 #define RT5640_M_MP3_ORG_L_SFT 1837 #define RT5640_M_MP3_ORG_L_SFT 6
1838 #define RT5640_M_MP3_ORG_R_MASK 1838 #define RT5640_M_MP3_ORG_R_MASK (0x1 << 5)
1839 #define RT5640_M_MP3_ORG_R_SFT 1839 #define RT5640_M_MP3_ORG_R_SFT 5
1840 1840
1841 /* MP3 Plus Control 2 (0xd1) */ 1841 /* MP3 Plus Control 2 (0xd1) */
1842 #define RT5640_MP3_WT_MASK 1842 #define RT5640_MP3_WT_MASK (0x1 << 13)
1843 #define RT5640_MP3_WT_SFT 1843 #define RT5640_MP3_WT_SFT 13
1844 #define RT5640_MP3_WT_1_4 1844 #define RT5640_MP3_WT_1_4 (0x0 << 13)
1845 #define RT5640_MP3_WT_1_2 1845 #define RT5640_MP3_WT_1_2 (0x1 << 13)
1846 #define RT5640_OG_MP3_MASK 1846 #define RT5640_OG_MP3_MASK (0x1f << 8)
1847 #define RT5640_OG_MP3_SFT 1847 #define RT5640_OG_MP3_SFT 8
1848 #define RT5640_HG_MP3_MASK 1848 #define RT5640_HG_MP3_MASK (0x3f)
1849 #define RT5640_HG_MP3_SFT 1849 #define RT5640_HG_MP3_SFT 0
1850 1850
1851 /* 3D HP Control 1 (0xd2) */ 1851 /* 3D HP Control 1 (0xd2) */
1852 #define RT5640_3D_CF_MASK 1852 #define RT5640_3D_CF_MASK (0x1 << 15)
1853 #define RT5640_3D_CF_SFT 1853 #define RT5640_3D_CF_SFT 15
1854 #define RT5640_3D_CF_DIS 1854 #define RT5640_3D_CF_DIS (0x0 << 15)
1855 #define RT5640_3D_CF_EN 1855 #define RT5640_3D_CF_EN (0x1 << 15)
1856 #define RT5640_3D_HP_MASK 1856 #define RT5640_3D_HP_MASK (0x1 << 14)
1857 #define RT5640_3D_HP_SFT 1857 #define RT5640_3D_HP_SFT 14
1858 #define RT5640_3D_HP_DIS 1858 #define RT5640_3D_HP_DIS (0x0 << 14)
1859 #define RT5640_3D_HP_EN 1859 #define RT5640_3D_HP_EN (0x1 << 14)
1860 #define RT5640_3D_BT_MASK 1860 #define RT5640_3D_BT_MASK (0x1 << 13)
1861 #define RT5640_3D_BT_SFT 1861 #define RT5640_3D_BT_SFT 13
1862 #define RT5640_3D_BT_DIS 1862 #define RT5640_3D_BT_DIS (0x0 << 13)
1863 #define RT5640_3D_BT_EN 1863 #define RT5640_3D_BT_EN (0x1 << 13)
1864 #define RT5640_3D_1F_MIX_MASK 1864 #define RT5640_3D_1F_MIX_MASK (0x3 << 11)
1865 #define RT5640_3D_1F_MIX_SFT 1865 #define RT5640_3D_1F_MIX_SFT 11
1866 #define RT5640_3D_HP_M_MASK 1866 #define RT5640_3D_HP_M_MASK (0x1 << 10)
1867 #define RT5640_3D_HP_M_SFT 1867 #define RT5640_3D_HP_M_SFT 10
1868 #define RT5640_3D_HP_M_SUR 1868 #define RT5640_3D_HP_M_SUR (0x0 << 10)
1869 #define RT5640_3D_HP_M_FRO 1869 #define RT5640_3D_HP_M_FRO (0x1 << 10)
1870 #define RT5640_M_3D_HRTF_MASK 1870 #define RT5640_M_3D_HRTF_MASK (0x1 << 9)
1871 #define RT5640_M_3D_HRTF_SFT 1871 #define RT5640_M_3D_HRTF_SFT 9
1872 #define RT5640_M_3D_D2H_MASK 1872 #define RT5640_M_3D_D2H_MASK (0x1 << 8)
1873 #define RT5640_M_3D_D2H_SFT 1873 #define RT5640_M_3D_D2H_SFT 8
1874 #define RT5640_M_3D_D2R_MASK 1874 #define RT5640_M_3D_D2R_MASK (0x1 << 7)
1875 #define RT5640_M_3D_D2R_SFT 1875 #define RT5640_M_3D_D2R_SFT 7
1876 #define RT5640_M_3D_REVB_MASK 1876 #define RT5640_M_3D_REVB_MASK (0x1 << 6)
1877 #define RT5640_M_3D_REVB_SFT 1877 #define RT5640_M_3D_REVB_SFT 6
1878 1878
1879 /* Adjustable high pass filter control 1 (0xd 1879 /* Adjustable high pass filter control 1 (0xd3) */
1880 #define RT5640_2ND_HPF_MASK 1880 #define RT5640_2ND_HPF_MASK (0x1 << 15)
1881 #define RT5640_2ND_HPF_SFT 1881 #define RT5640_2ND_HPF_SFT 15
1882 #define RT5640_2ND_HPF_DIS 1882 #define RT5640_2ND_HPF_DIS (0x0 << 15)
1883 #define RT5640_2ND_HPF_EN 1883 #define RT5640_2ND_HPF_EN (0x1 << 15)
1884 #define RT5640_HPF_CF_L_MASK 1884 #define RT5640_HPF_CF_L_MASK (0x7 << 12)
1885 #define RT5640_HPF_CF_L_SFT 1885 #define RT5640_HPF_CF_L_SFT 12
1886 #define RT5640_1ST_HPF_MASK 1886 #define RT5640_1ST_HPF_MASK (0x1 << 11)
1887 #define RT5640_1ST_HPF_SFT 1887 #define RT5640_1ST_HPF_SFT 11
1888 #define RT5640_1ST_HPF_DIS 1888 #define RT5640_1ST_HPF_DIS (0x0 << 11)
1889 #define RT5640_1ST_HPF_EN 1889 #define RT5640_1ST_HPF_EN (0x1 << 11)
1890 #define RT5640_HPF_CF_R_MASK 1890 #define RT5640_HPF_CF_R_MASK (0x7 << 8)
1891 #define RT5640_HPF_CF_R_SFT 1891 #define RT5640_HPF_CF_R_SFT 8
1892 #define RT5640_ZD_T_MASK 1892 #define RT5640_ZD_T_MASK (0x3 << 6)
1893 #define RT5640_ZD_T_SFT 1893 #define RT5640_ZD_T_SFT 6
1894 #define RT5640_ZD_F_MASK 1894 #define RT5640_ZD_F_MASK (0x3 << 4)
1895 #define RT5640_ZD_F_SFT 1895 #define RT5640_ZD_F_SFT 4
1896 #define RT5640_ZD_F_IM 1896 #define RT5640_ZD_F_IM (0x0 << 4)
1897 #define RT5640_ZD_F_ZC_IM 1897 #define RT5640_ZD_F_ZC_IM (0x1 << 4)
1898 #define RT5640_ZD_F_ZC_IOD 1898 #define RT5640_ZD_F_ZC_IOD (0x2 << 4)
1899 #define RT5640_ZD_F_UN 1899 #define RT5640_ZD_F_UN (0x3 << 4)
1900 1900
1901 /* HP calibration control and Amp detection ( 1901 /* HP calibration control and Amp detection (0xd6) */
1902 #define RT5640_SI_DAC_MASK 1902 #define RT5640_SI_DAC_MASK (0x1 << 11)
1903 #define RT5640_SI_DAC_SFT 1903 #define RT5640_SI_DAC_SFT 11
1904 #define RT5640_SI_DAC_AUTO 1904 #define RT5640_SI_DAC_AUTO (0x0 << 11)
1905 #define RT5640_SI_DAC_TEST 1905 #define RT5640_SI_DAC_TEST (0x1 << 11)
1906 #define RT5640_DC_CAL_M_MASK 1906 #define RT5640_DC_CAL_M_MASK (0x1 << 10)
1907 #define RT5640_DC_CAL_M_SFT 1907 #define RT5640_DC_CAL_M_SFT 10
1908 #define RT5640_DC_CAL_M_CAL 1908 #define RT5640_DC_CAL_M_CAL (0x0 << 10)
1909 #define RT5640_DC_CAL_M_NOR 1909 #define RT5640_DC_CAL_M_NOR (0x1 << 10)
1910 #define RT5640_DC_CAL_MASK 1910 #define RT5640_DC_CAL_MASK (0x1 << 9)
1911 #define RT5640_DC_CAL_SFT 1911 #define RT5640_DC_CAL_SFT 9
1912 #define RT5640_DC_CAL_DIS 1912 #define RT5640_DC_CAL_DIS (0x0 << 9)
1913 #define RT5640_DC_CAL_EN 1913 #define RT5640_DC_CAL_EN (0x1 << 9)
1914 #define RT5640_HPD_RCV_MASK 1914 #define RT5640_HPD_RCV_MASK (0x7 << 6)
1915 #define RT5640_HPD_RCV_SFT 1915 #define RT5640_HPD_RCV_SFT 6
1916 #define RT5640_HPD_PS_MASK 1916 #define RT5640_HPD_PS_MASK (0x1 << 5)
1917 #define RT5640_HPD_PS_SFT 1917 #define RT5640_HPD_PS_SFT 5
1918 #define RT5640_HPD_PS_DIS 1918 #define RT5640_HPD_PS_DIS (0x0 << 5)
1919 #define RT5640_HPD_PS_EN 1919 #define RT5640_HPD_PS_EN (0x1 << 5)
1920 #define RT5640_CAL_M_MASK 1920 #define RT5640_CAL_M_MASK (0x1 << 4)
1921 #define RT5640_CAL_M_SFT 1921 #define RT5640_CAL_M_SFT 4
1922 #define RT5640_CAL_M_DEP 1922 #define RT5640_CAL_M_DEP (0x0 << 4)
1923 #define RT5640_CAL_M_CAL 1923 #define RT5640_CAL_M_CAL (0x1 << 4)
1924 #define RT5640_CAL_MASK 1924 #define RT5640_CAL_MASK (0x1 << 3)
1925 #define RT5640_CAL_SFT 1925 #define RT5640_CAL_SFT 3
1926 #define RT5640_CAL_DIS 1926 #define RT5640_CAL_DIS (0x0 << 3)
1927 #define RT5640_CAL_EN 1927 #define RT5640_CAL_EN (0x1 << 3)
1928 #define RT5640_CAL_TEST_MASK 1928 #define RT5640_CAL_TEST_MASK (0x1 << 2)
1929 #define RT5640_CAL_TEST_SFT 1929 #define RT5640_CAL_TEST_SFT 2
1930 #define RT5640_CAL_TEST_DIS 1930 #define RT5640_CAL_TEST_DIS (0x0 << 2)
1931 #define RT5640_CAL_TEST_EN 1931 #define RT5640_CAL_TEST_EN (0x1 << 2)
1932 #define RT5640_CAL_P_MASK 1932 #define RT5640_CAL_P_MASK (0x3)
1933 #define RT5640_CAL_P_SFT 1933 #define RT5640_CAL_P_SFT 0
1934 #define RT5640_CAL_P_NONE 1934 #define RT5640_CAL_P_NONE (0x0)
1935 #define RT5640_CAL_P_CAL 1935 #define RT5640_CAL_P_CAL (0x1)
1936 #define RT5640_CAL_P_DAC_CAL 1936 #define RT5640_CAL_P_DAC_CAL (0x2)
1937 1937
1938 /* Soft volume and zero cross control 1 (0xd9 1938 /* Soft volume and zero cross control 1 (0xd9) */
1939 #define RT5640_SV_MASK 1939 #define RT5640_SV_MASK (0x1 << 15)
1940 #define RT5640_SV_SFT 1940 #define RT5640_SV_SFT 15
1941 #define RT5640_SV_DIS 1941 #define RT5640_SV_DIS (0x0 << 15)
1942 #define RT5640_SV_EN 1942 #define RT5640_SV_EN (0x1 << 15)
1943 #define RT5640_SPO_SV_MASK 1943 #define RT5640_SPO_SV_MASK (0x1 << 14)
1944 #define RT5640_SPO_SV_SFT 1944 #define RT5640_SPO_SV_SFT 14
1945 #define RT5640_SPO_SV_DIS 1945 #define RT5640_SPO_SV_DIS (0x0 << 14)
1946 #define RT5640_SPO_SV_EN 1946 #define RT5640_SPO_SV_EN (0x1 << 14)
1947 #define RT5640_OUT_SV_MASK 1947 #define RT5640_OUT_SV_MASK (0x1 << 13)
1948 #define RT5640_OUT_SV_SFT 1948 #define RT5640_OUT_SV_SFT 13
1949 #define RT5640_OUT_SV_DIS 1949 #define RT5640_OUT_SV_DIS (0x0 << 13)
1950 #define RT5640_OUT_SV_EN 1950 #define RT5640_OUT_SV_EN (0x1 << 13)
1951 #define RT5640_HP_SV_MASK 1951 #define RT5640_HP_SV_MASK (0x1 << 12)
1952 #define RT5640_HP_SV_SFT 1952 #define RT5640_HP_SV_SFT 12
1953 #define RT5640_HP_SV_DIS 1953 #define RT5640_HP_SV_DIS (0x0 << 12)
1954 #define RT5640_HP_SV_EN 1954 #define RT5640_HP_SV_EN (0x1 << 12)
1955 #define RT5640_ZCD_DIG_MASK 1955 #define RT5640_ZCD_DIG_MASK (0x1 << 11)
1956 #define RT5640_ZCD_DIG_SFT 1956 #define RT5640_ZCD_DIG_SFT 11
1957 #define RT5640_ZCD_DIG_DIS 1957 #define RT5640_ZCD_DIG_DIS (0x0 << 11)
1958 #define RT5640_ZCD_DIG_EN 1958 #define RT5640_ZCD_DIG_EN (0x1 << 11)
1959 #define RT5640_ZCD_MASK 1959 #define RT5640_ZCD_MASK (0x1 << 10)
1960 #define RT5640_ZCD_SFT 1960 #define RT5640_ZCD_SFT 10
1961 #define RT5640_ZCD_PD 1961 #define RT5640_ZCD_PD (0x0 << 10)
1962 #define RT5640_ZCD_PU 1962 #define RT5640_ZCD_PU (0x1 << 10)
1963 #define RT5640_M_ZCD_MASK 1963 #define RT5640_M_ZCD_MASK (0x3f << 4)
1964 #define RT5640_M_ZCD_SFT 1964 #define RT5640_M_ZCD_SFT 4
1965 #define RT5640_M_ZCD_RM_L 1965 #define RT5640_M_ZCD_RM_L (0x1 << 9)
1966 #define RT5640_M_ZCD_RM_R 1966 #define RT5640_M_ZCD_RM_R (0x1 << 8)
1967 #define RT5640_M_ZCD_SM_L 1967 #define RT5640_M_ZCD_SM_L (0x1 << 7)
1968 #define RT5640_M_ZCD_SM_R 1968 #define RT5640_M_ZCD_SM_R (0x1 << 6)
1969 #define RT5640_M_ZCD_OM_L 1969 #define RT5640_M_ZCD_OM_L (0x1 << 5)
1970 #define RT5640_M_ZCD_OM_R 1970 #define RT5640_M_ZCD_OM_R (0x1 << 4)
1971 #define RT5640_SV_DLY_MASK 1971 #define RT5640_SV_DLY_MASK (0xf)
1972 #define RT5640_SV_DLY_SFT 1972 #define RT5640_SV_DLY_SFT 0
1973 1973
1974 /* Soft volume and zero cross control 2 (0xda 1974 /* Soft volume and zero cross control 2 (0xda) */
1975 #define RT5640_ZCD_HP_MASK 1975 #define RT5640_ZCD_HP_MASK (0x1 << 15)
1976 #define RT5640_ZCD_HP_SFT 1976 #define RT5640_ZCD_HP_SFT 15
1977 #define RT5640_ZCD_HP_DIS 1977 #define RT5640_ZCD_HP_DIS (0x0 << 15)
1978 #define RT5640_ZCD_HP_EN 1978 #define RT5640_ZCD_HP_EN (0x1 << 15)
1979 1979
1980 /* General Control 1 (0xfa) */ 1980 /* General Control 1 (0xfa) */
1981 #define RT5640_EN_LOUT_DF 1981 #define RT5640_EN_LOUT_DF (0x1 << 14)
1982 #define RT5640_EN_LOUT_DF_SFT 1982 #define RT5640_EN_LOUT_DF_SFT 14
1983 #define RT5640_M_MONO_ADC_L 1983 #define RT5640_M_MONO_ADC_L (0x1 << 13)
1984 #define RT5640_M_MONO_ADC_L_SFT 1984 #define RT5640_M_MONO_ADC_L_SFT 13
1985 #define RT5640_M_MONO_ADC_R 1985 #define RT5640_M_MONO_ADC_R (0x1 << 12)
1986 #define RT5640_M_MONO_ADC_R_SFT 1986 #define RT5640_M_MONO_ADC_R_SFT 12
1987 #define RT5640_MCLK_DET 1987 #define RT5640_MCLK_DET (0x1 << 11)
1988 1988
1989 /* General Control 1 (0xfb) */ 1989 /* General Control 1 (0xfb) */
1990 #define RT5640_IRQ_JD2_MASK 1990 #define RT5640_IRQ_JD2_MASK (0x1 << 12)
1991 #define RT5640_IRQ_JD2_SFT 1991 #define RT5640_IRQ_JD2_SFT 12
1992 #define RT5640_IRQ_JD2_BP 1992 #define RT5640_IRQ_JD2_BP (0x0 << 12)
1993 #define RT5640_IRQ_JD2_NOR 1993 #define RT5640_IRQ_JD2_NOR (0x1 << 12)
1994 #define RT5640_JD2_P_MASK 1994 #define RT5640_JD2_P_MASK (0x1 << 10)
1995 #define RT5640_JD2_P_SFT 1995 #define RT5640_JD2_P_SFT 10
1996 #define RT5640_JD2_P_NOR 1996 #define RT5640_JD2_P_NOR (0x0 << 10)
1997 #define RT5640_JD2_P_INV 1997 #define RT5640_JD2_P_INV (0x1 << 10)
1998 #define RT5640_JD2_MASK 1998 #define RT5640_JD2_MASK (0x1 << 8)
1999 #define RT5640_JD2_SFT 1999 #define RT5640_JD2_SFT 8
2000 #define RT5640_JD2_DIS 2000 #define RT5640_JD2_DIS (0x0 << 8)
2001 #define RT5640_JD2_EN 2001 #define RT5640_JD2_EN (0x1 << 8)
2002 2002
2003 /* Codec Private Register definition */ 2003 /* Codec Private Register definition */
2004 2004
2005 /* MIC Over current threshold scale factor (0 2005 /* MIC Over current threshold scale factor (0x15) */
2006 #define RT5640_MIC_OVCD_SF_MASK 2006 #define RT5640_MIC_OVCD_SF_MASK (0x3 << 8)
2007 #define RT5640_MIC_OVCD_SF_SFT 2007 #define RT5640_MIC_OVCD_SF_SFT 8
2008 #define RT5640_MIC_OVCD_SF_0P5 2008 #define RT5640_MIC_OVCD_SF_0P5 (0x0 << 8)
2009 #define RT5640_MIC_OVCD_SF_0P75 2009 #define RT5640_MIC_OVCD_SF_0P75 (0x1 << 8)
2010 #define RT5640_MIC_OVCD_SF_1P0 2010 #define RT5640_MIC_OVCD_SF_1P0 (0x2 << 8)
2011 #define RT5640_MIC_OVCD_SF_1P5 2011 #define RT5640_MIC_OVCD_SF_1P5 (0x3 << 8)
2012 2012
2013 /* 3D Speaker Control (0x63) */ 2013 /* 3D Speaker Control (0x63) */
2014 #define RT5640_3D_SPK_MASK 2014 #define RT5640_3D_SPK_MASK (0x1 << 15)
2015 #define RT5640_3D_SPK_SFT 2015 #define RT5640_3D_SPK_SFT 15
2016 #define RT5640_3D_SPK_DIS 2016 #define RT5640_3D_SPK_DIS (0x0 << 15)
2017 #define RT5640_3D_SPK_EN 2017 #define RT5640_3D_SPK_EN (0x1 << 15)
2018 #define RT5640_3D_SPK_M_MASK 2018 #define RT5640_3D_SPK_M_MASK (0x3 << 13)
2019 #define RT5640_3D_SPK_M_SFT 2019 #define RT5640_3D_SPK_M_SFT 13
2020 #define RT5640_3D_SPK_CG_MASK 2020 #define RT5640_3D_SPK_CG_MASK (0x1f << 8)
2021 #define RT5640_3D_SPK_CG_SFT 2021 #define RT5640_3D_SPK_CG_SFT 8
2022 #define RT5640_3D_SPK_SG_MASK 2022 #define RT5640_3D_SPK_SG_MASK (0x1f)
2023 #define RT5640_3D_SPK_SG_SFT 2023 #define RT5640_3D_SPK_SG_SFT 0
2024 2024
2025 /* Wind Noise Detection Control 1 (0x6c) */ 2025 /* Wind Noise Detection Control 1 (0x6c) */
2026 #define RT5640_WND_MASK 2026 #define RT5640_WND_MASK (0x1 << 15)
2027 #define RT5640_WND_SFT 2027 #define RT5640_WND_SFT 15
2028 #define RT5640_WND_DIS 2028 #define RT5640_WND_DIS (0x0 << 15)
2029 #define RT5640_WND_EN 2029 #define RT5640_WND_EN (0x1 << 15)
2030 2030
2031 /* Wind Noise Detection Control 2 (0x6d) */ 2031 /* Wind Noise Detection Control 2 (0x6d) */
2032 #define RT5640_WND_FC_NW_MASK 2032 #define RT5640_WND_FC_NW_MASK (0x3f << 10)
2033 #define RT5640_WND_FC_NW_SFT 2033 #define RT5640_WND_FC_NW_SFT 10
2034 #define RT5640_WND_FC_WK_MASK 2034 #define RT5640_WND_FC_WK_MASK (0x3f << 4)
2035 #define RT5640_WND_FC_WK_SFT 2035 #define RT5640_WND_FC_WK_SFT 4
2036 2036
2037 /* Wind Noise Detection Control 3 (0x6e) */ 2037 /* Wind Noise Detection Control 3 (0x6e) */
2038 #define RT5640_HPF_FC_MASK 2038 #define RT5640_HPF_FC_MASK (0x3f << 6)
2039 #define RT5640_HPF_FC_SFT 2039 #define RT5640_HPF_FC_SFT 6
2040 #define RT5640_WND_FC_ST_MASK 2040 #define RT5640_WND_FC_ST_MASK (0x3f)
2041 #define RT5640_WND_FC_ST_SFT 2041 #define RT5640_WND_FC_ST_SFT 0
2042 2042
2043 /* Wind Noise Detection Control 4 (0x6f) */ 2043 /* Wind Noise Detection Control 4 (0x6f) */
2044 #define RT5640_WND_TH_LO_MASK 2044 #define RT5640_WND_TH_LO_MASK (0x3ff)
2045 #define RT5640_WND_TH_LO_SFT 2045 #define RT5640_WND_TH_LO_SFT 0
2046 2046
2047 /* Wind Noise Detection Control 5 (0x70) */ 2047 /* Wind Noise Detection Control 5 (0x70) */
2048 #define RT5640_WND_TH_HI_MASK 2048 #define RT5640_WND_TH_HI_MASK (0x3ff)
2049 #define RT5640_WND_TH_HI_SFT 2049 #define RT5640_WND_TH_HI_SFT 0
2050 2050
2051 /* Wind Noise Detection Control 8 (0x73) */ 2051 /* Wind Noise Detection Control 8 (0x73) */
2052 #define RT5640_WND_WIND_MASK 2052 #define RT5640_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2053 #define RT5640_WND_WIND_SFT 2053 #define RT5640_WND_WIND_SFT 13
2054 #define RT5640_WND_STRONG_MASK 2054 #define RT5640_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2055 #define RT5640_WND_STRONG_SFT 2055 #define RT5640_WND_STRONG_SFT 12
2056 enum { 2056 enum {
2057 RT5640_NO_WIND, 2057 RT5640_NO_WIND,
2058 RT5640_BREEZE, 2058 RT5640_BREEZE,
2059 RT5640_STORM, 2059 RT5640_STORM,
2060 }; 2060 };
2061 2061
2062 /* Dipole Speaker Interface (0x75) */ 2062 /* Dipole Speaker Interface (0x75) */
2063 #define RT5640_DP_ATT_MASK 2063 #define RT5640_DP_ATT_MASK (0x3 << 14)
2064 #define RT5640_DP_ATT_SFT 2064 #define RT5640_DP_ATT_SFT 14
2065 #define RT5640_DP_SPK_MASK 2065 #define RT5640_DP_SPK_MASK (0x1 << 10)
2066 #define RT5640_DP_SPK_SFT 2066 #define RT5640_DP_SPK_SFT 10
2067 #define RT5640_DP_SPK_DIS 2067 #define RT5640_DP_SPK_DIS (0x0 << 10)
2068 #define RT5640_DP_SPK_EN 2068 #define RT5640_DP_SPK_EN (0x1 << 10)
2069 2069
2070 /* EQ Pre Volume Control (0xb3) */ 2070 /* EQ Pre Volume Control (0xb3) */
2071 #define RT5640_EQ_PRE_VOL_MASK 2071 #define RT5640_EQ_PRE_VOL_MASK (0xffff)
2072 #define RT5640_EQ_PRE_VOL_SFT 2072 #define RT5640_EQ_PRE_VOL_SFT 0
2073 2073
2074 /* EQ Post Volume Control (0xb4) */ 2074 /* EQ Post Volume Control (0xb4) */
2075 #define RT5640_EQ_PST_VOL_MASK 2075 #define RT5640_EQ_PST_VOL_MASK (0xffff)
2076 #define RT5640_EQ_PST_VOL_SFT 2076 #define RT5640_EQ_PST_VOL_SFT 0
2077 2077
2078 #define RT5640_NO_JACK BIT(0) 2078 #define RT5640_NO_JACK BIT(0)
2079 #define RT5640_HEADSET_DET BIT(1) 2079 #define RT5640_HEADSET_DET BIT(1)
2080 #define RT5640_HEADPHO_DET BIT(2) 2080 #define RT5640_HEADPHO_DET BIT(2)
2081 2081
2082 /* System Clock Source */ 2082 /* System Clock Source */
2083 #define RT5640_SCLK_S_MCLK 0 2083 #define RT5640_SCLK_S_MCLK 0
2084 #define RT5640_SCLK_S_PLL1 1 2084 #define RT5640_SCLK_S_PLL1 1
2085 #define RT5640_SCLK_S_PLL1_TK 2 2085 #define RT5640_SCLK_S_PLL1_TK 2
2086 #define RT5640_SCLK_S_RCCLK 3 2086 #define RT5640_SCLK_S_RCCLK 3
2087 2087
2088 /* PLL1 Source */ 2088 /* PLL1 Source */
2089 #define RT5640_PLL1_S_MCLK 0 2089 #define RT5640_PLL1_S_MCLK 0
2090 #define RT5640_PLL1_S_BCLK1 1 2090 #define RT5640_PLL1_S_BCLK1 1
2091 #define RT5640_PLL1_S_BCLK2 2 2091 #define RT5640_PLL1_S_BCLK2 2
2092 #define RT5640_PLL1_S_BCLK3 3 2092 #define RT5640_PLL1_S_BCLK3 3
2093 2093
2094 2094
2095 enum { 2095 enum {
2096 RT5640_AIF1, 2096 RT5640_AIF1,
2097 RT5640_AIF2, 2097 RT5640_AIF2,
2098 RT5640_AIF3, 2098 RT5640_AIF3,
2099 RT5640_AIFS, 2099 RT5640_AIFS,
2100 }; 2100 };
2101 2101
2102 enum { 2102 enum {
2103 RT5640_U_IF1 = 0x1, 2103 RT5640_U_IF1 = 0x1,
2104 RT5640_U_IF2 = 0x2, 2104 RT5640_U_IF2 = 0x2,
2105 RT5640_U_IF3 = 0x4, 2105 RT5640_U_IF3 = 0x4,
2106 }; 2106 };
2107 2107
2108 enum { 2108 enum {
2109 RT5640_IF_123, 2109 RT5640_IF_123,
2110 RT5640_IF_132, 2110 RT5640_IF_132,
2111 RT5640_IF_312, 2111 RT5640_IF_312,
2112 RT5640_IF_321, 2112 RT5640_IF_321,
2113 RT5640_IF_231, 2113 RT5640_IF_231,
2114 RT5640_IF_213, 2114 RT5640_IF_213,
2115 RT5640_IF_113, 2115 RT5640_IF_113,
2116 RT5640_IF_223, 2116 RT5640_IF_223,
2117 RT5640_IF_ALL, 2117 RT5640_IF_ALL,
2118 }; 2118 };
2119 2119
2120 enum { 2120 enum {
2121 RT5640_DMIC_DIS, 2121 RT5640_DMIC_DIS,
2122 RT5640_DMIC1, 2122 RT5640_DMIC1,
2123 RT5640_DMIC2, 2123 RT5640_DMIC2,
2124 }; 2124 };
2125 2125
2126 /* filter mask */ 2126 /* filter mask */
2127 enum { 2127 enum {
2128 RT5640_DA_STEREO_FILTER = 0x1, 2128 RT5640_DA_STEREO_FILTER = 0x1,
2129 RT5640_DA_MONO_L_FILTER = (0x1 << 1), 2129 RT5640_DA_MONO_L_FILTER = (0x1 << 1),
2130 RT5640_DA_MONO_R_FILTER = (0x1 << 2), 2130 RT5640_DA_MONO_R_FILTER = (0x1 << 2),
2131 RT5640_AD_STEREO_FILTER = (0x1 << 3), 2131 RT5640_AD_STEREO_FILTER = (0x1 << 3),
2132 RT5640_AD_MONO_L_FILTER = (0x1 << 4), 2132 RT5640_AD_MONO_L_FILTER = (0x1 << 4),
2133 RT5640_AD_MONO_R_FILTER = (0x1 << 5), 2133 RT5640_AD_MONO_R_FILTER = (0x1 << 5),
2134 }; 2134 };
2135 2135
2136 struct rt5640_priv { 2136 struct rt5640_priv {
2137 struct snd_soc_component *component; 2137 struct snd_soc_component *component;
2138 struct regmap *regmap; 2138 struct regmap *regmap;
2139 struct clk *mclk; 2139 struct clk *mclk;
2140 2140
2141 struct gpio_desc *ldo1_en; /* GPIO fo 2141 struct gpio_desc *ldo1_en; /* GPIO for LDO1_EN */
2142 int irq; 2142 int irq;
2143 int jd_gpio_irq; 2143 int jd_gpio_irq;
2144 int sysclk; 2144 int sysclk;
2145 int sysclk_src; 2145 int sysclk_src;
2146 int lrck[RT5640_AIFS]; 2146 int lrck[RT5640_AIFS];
2147 int bclk[RT5640_AIFS]; 2147 int bclk[RT5640_AIFS];
2148 int master[RT5640_AIFS]; 2148 int master[RT5640_AIFS];
2149 2149
2150 int pll_src; 2150 int pll_src;
2151 int pll_in; 2151 int pll_in;
2152 int pll_out; 2152 int pll_out;
2153 2153
2154 bool hp_mute; 2154 bool hp_mute;
2155 bool asrc_en; 2155 bool asrc_en;
2156 bool irq_requested; 2156 bool irq_requested;
2157 bool jd_gpio_irq_requested; 2157 bool jd_gpio_irq_requested;
2158 2158
2159 /* Jack and button detect data */ 2159 /* Jack and button detect data */
2160 bool ovcd_irq_enabled; 2160 bool ovcd_irq_enabled;
2161 bool pressed; 2161 bool pressed;
2162 bool press_reported; 2162 bool press_reported;
2163 int press_count; 2163 int press_count;
2164 int release_count; 2164 int release_count;
2165 int poll_count; 2165 int poll_count;
2166 struct delayed_work bp_work; 2166 struct delayed_work bp_work;
2167 struct delayed_work jack_work; 2167 struct delayed_work jack_work;
2168 struct snd_soc_jack *jack; 2168 struct snd_soc_jack *jack;
2169 struct gpio_desc *jd_gpio; 2169 struct gpio_desc *jd_gpio;
2170 unsigned int jd_src; 2170 unsigned int jd_src;
2171 bool jd_inverted; 2171 bool jd_inverted;
2172 unsigned int ovcd_th; 2172 unsigned int ovcd_th;
2173 unsigned int ovcd_sf; 2173 unsigned int ovcd_sf;
2174 bool use_platform_clock; 2174 bool use_platform_clock;
2175 }; 2175 };
2176 2176
2177 struct rt5640_set_jack_data { 2177 struct rt5640_set_jack_data {
2178 int codec_irq_override; 2178 int codec_irq_override;
2179 struct gpio_desc *jd_gpio; 2179 struct gpio_desc *jd_gpio;
2180 bool use_platform_clock; 2180 bool use_platform_clock;
2181 }; 2181 };
2182 2182
2183 int rt5640_dmic_enable(struct snd_soc_compone 2183 int rt5640_dmic_enable(struct snd_soc_component *component,
2184 bool dmic1_data_pin, b 2184 bool dmic1_data_pin, bool dmic2_data_pin);
2185 int rt5640_sel_asrc_clk_src(struct snd_soc_co 2185 int rt5640_sel_asrc_clk_src(struct snd_soc_component *component,
2186 unsigned int filter_mask, uns 2186 unsigned int filter_mask, unsigned int clk_src);
2187 2187
2188 void rt5640_set_ovcd_params(struct snd_soc_co 2188 void rt5640_set_ovcd_params(struct snd_soc_component *component);
2189 void rt5640_enable_micbias1_for_ovcd(struct s 2189 void rt5640_enable_micbias1_for_ovcd(struct snd_soc_component *component);
2190 void rt5640_disable_micbias1_for_ovcd(struct 2190 void rt5640_disable_micbias1_for_ovcd(struct snd_soc_component *component);
2191 int rt5640_detect_headset(struct snd_soc_comp 2191 int rt5640_detect_headset(struct snd_soc_component *component, struct gpio_desc *hp_det_gpio);
2192 2192
2193 #endif 2193 #endif
2194 2194
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