1 /* SPDX-License-Identifier: GPL-2.0-only */ 1
2 /*
3 * rt5640.h -- RT5640 ALSA SoC audio driver
4 *
5 * Copyright 2011 Realtek Microelectronics
6 * Author: Johnny Hsu <johnnyhsu@realtek.com>
7 */
8
9 #ifndef _RT5640_H
10 #define _RT5640_H
11
12 #include <linux/clk.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/workqueue.h>
15 #include <dt-bindings/sound/rt5640.h>
16
17 /* Info */
18 #define RT5640_RESET
19 #define RT5640_VENDOR_ID
20 #define RT5640_VENDOR_ID1
21 #define RT5640_VENDOR_ID2
22 /* I/O - Output */
23 #define RT5640_SPK_VOL
24 #define RT5640_HP_VOL
25 #define RT5640_OUTPUT
26 #define RT5640_MONO_OUT
27 /* I/O - Input */
28 #define RT5640_IN1_IN2
29 #define RT5640_IN3_IN4
30 #define RT5640_INL_INR_VOL
31 /* I/O - ADC/DAC/DMIC */
32 #define RT5640_DAC1_DIG_VOL
33 #define RT5640_DAC2_DIG_VOL
34 #define RT5640_DAC2_CTRL
35 #define RT5640_ADC_DIG_VOL
36 #define RT5640_ADC_DATA
37 #define RT5640_ADC_BST_VOL
38 /* Mixer - D-D */
39 #define RT5640_STO_ADC_MIXER
40 #define RT5640_MONO_ADC_MIXER
41 #define RT5640_AD_DA_MIXER
42 #define RT5640_STO_DAC_MIXER
43 #define RT5640_MONO_DAC_MIXER
44 #define RT5640_DIG_MIXER
45 #define RT5640_DSP_PATH1
46 #define RT5640_DSP_PATH2
47 #define RT5640_DIG_INF_DATA
48 /* Mixer - ADC */
49 #define RT5640_REC_L1_MIXER
50 #define RT5640_REC_L2_MIXER
51 #define RT5640_REC_R1_MIXER
52 #define RT5640_REC_R2_MIXER
53 /* Mixer - DAC */
54 #define RT5640_HPO_MIXER
55 #define RT5640_SPK_L_MIXER
56 #define RT5640_SPK_R_MIXER
57 #define RT5640_SPO_L_MIXER
58 #define RT5640_SPO_R_MIXER
59 #define RT5640_SPO_CLSD_RATIO
60 #define RT5640_MONO_MIXER
61 #define RT5640_OUT_L1_MIXER
62 #define RT5640_OUT_L2_MIXER
63 #define RT5640_OUT_L3_MIXER
64 #define RT5640_OUT_R1_MIXER
65 #define RT5640_OUT_R2_MIXER
66 #define RT5640_OUT_R3_MIXER
67 #define RT5640_LOUT_MIXER
68 /* Power */
69 #define RT5640_PWR_DIG1
70 #define RT5640_PWR_DIG2
71 #define RT5640_PWR_ANLG1
72 #define RT5640_PWR_ANLG2
73 #define RT5640_PWR_MIXER
74 #define RT5640_PWR_VOL
75 /* Private Register Control */
76 #define RT5640_PRIV_INDEX
77 #define RT5640_PRIV_DATA
78 /* Format - ADC/DAC */
79 #define RT5640_I2S1_SDP
80 #define RT5640_I2S2_SDP
81 #define RT5640_ADDA_CLK1
82 #define RT5640_ADDA_CLK2
83 #define RT5640_DMIC
84 /* Function - Analog */
85 #define RT5640_GLB_CLK
86 #define RT5640_PLL_CTRL1
87 #define RT5640_PLL_CTRL2
88 #define RT5640_ASRC_1
89 #define RT5640_ASRC_2
90 #define RT5640_ASRC_3
91 #define RT5640_ASRC_4
92 #define RT5640_ASRC_5
93 #define RT5640_HP_OVCD
94 #define RT5640_CLS_D_OVCD
95 #define RT5640_CLS_D_OUT
96 #define RT5640_DEPOP_M1
97 #define RT5640_DEPOP_M2
98 #define RT5640_DEPOP_M3
99 #define RT5640_CHARGE_PUMP
100 #define RT5640_PV_DET_SPK_G
101 #define RT5640_MICBIAS
102 /* Function - Digital */
103 #define RT5640_EQ_CTRL1
104 #define RT5640_EQ_CTRL2
105 #define RT5640_WIND_FILTER
106 #define RT5640_DRC_AGC_1
107 #define RT5640_DRC_AGC_2
108 #define RT5640_DRC_AGC_3
109 #define RT5640_SVOL_ZC
110 #define RT5640_ANC_CTRL1
111 #define RT5640_ANC_CTRL2
112 #define RT5640_ANC_CTRL3
113 #define RT5640_JD_CTRL
114 #define RT5640_ANC_JD
115 #define RT5640_IRQ_CTRL1
116 #define RT5640_IRQ_CTRL2
117 #define RT5640_INT_IRQ_ST
118 #define RT5640_GPIO_CTRL1
119 #define RT5640_GPIO_CTRL2
120 #define RT5640_GPIO_CTRL3
121 #define RT5640_DSP_CTRL1
122 #define RT5640_DSP_CTRL2
123 #define RT5640_DSP_CTRL3
124 #define RT5640_DSP_CTRL4
125 #define RT5640_PGM_REG_ARR1
126 #define RT5640_PGM_REG_ARR2
127 #define RT5640_PGM_REG_ARR3
128 #define RT5640_PGM_REG_ARR4
129 #define RT5640_PGM_REG_ARR5
130 #define RT5640_SCB_FUNC
131 #define RT5640_SCB_CTRL
132 #define RT5640_BASE_BACK
133 #define RT5640_MP3_PLUS1
134 #define RT5640_MP3_PLUS2
135 #define RT5640_3D_HP
136 #define RT5640_ADJ_HPF
137 #define RT5640_HP_CALIB_AMP_DET
138 #define RT5640_HP_CALIB2
139 #define RT5640_SV_ZCD1
140 #define RT5640_SV_ZCD2
141 /* Dummy Register */
142 #define RT5640_DUMMY1
143 #define RT5640_DUMMY2
144 #define RT5640_DUMMY3
145
146
147 /* Index of Codec Private Register definition
148 #define RT5640_BIAS_CUR4
149 #define RT5640_CHPUMP_INT_REG1
150 #define RT5640_MAMP_INT_REG2
151 #define RT5640_3D_SPK
152 #define RT5640_WND_1
153 #define RT5640_WND_2
154 #define RT5640_WND_3
155 #define RT5640_WND_4
156 #define RT5640_WND_5
157 #define RT5640_WND_8
158 #define RT5640_DIP_SPK_INF
159 #define RT5640_HP_DCC_INT1
160 #define RT5640_EQ_BW_LOP
161 #define RT5640_EQ_GN_LOP
162 #define RT5640_EQ_FC_BP1
163 #define RT5640_EQ_BW_BP1
164 #define RT5640_EQ_GN_BP1
165 #define RT5640_EQ_FC_BP2
166 #define RT5640_EQ_BW_BP2
167 #define RT5640_EQ_GN_BP2
168 #define RT5640_EQ_FC_BP3
169 #define RT5640_EQ_BW_BP3
170 #define RT5640_EQ_GN_BP3
171 #define RT5640_EQ_FC_BP4
172 #define RT5640_EQ_BW_BP4
173 #define RT5640_EQ_GN_BP4
174 #define RT5640_EQ_FC_HIP1
175 #define RT5640_EQ_GN_HIP1
176 #define RT5640_EQ_FC_HIP2
177 #define RT5640_EQ_BW_HIP2
178 #define RT5640_EQ_GN_HIP2
179 #define RT5640_EQ_PRE_VOL
180 #define RT5640_EQ_PST_VOL
181
182 /* global definition */
183 #define RT5640_L_MUTE
184 #define RT5640_L_MUTE_SFT
185 #define RT5640_VOL_L_MUTE
186 #define RT5640_VOL_L_SFT
187 #define RT5640_R_MUTE
188 #define RT5640_R_MUTE_SFT
189 #define RT5640_VOL_R_MUTE
190 #define RT5640_VOL_R_SFT
191 #define RT5640_L_VOL_MASK
192 #define RT5640_L_VOL_SFT
193 #define RT5640_R_VOL_MASK
194 #define RT5640_R_VOL_SFT
195
196 /* SW Reset & Device ID (0x00) */
197 #define RT5640_ID_MASK
198 #define RT5640_ID_5639
199 #define RT5640_ID_5640
200 #define RT5640_ID_5642
201
202
203 /* IN1 and IN2 Control (0x0d) */
204 /* IN3 and IN4 Control (0x0e) */
205 #define RT5640_BST_SFT1
206 #define RT5640_BST_SFT2
207 #define RT5640_IN_DF1
208 #define RT5640_IN_SFT1
209 #define RT5640_IN_DF2
210 #define RT5640_IN_SFT2
211
212 /* INL and INR Volume Control (0x0f) */
213 #define RT5640_INL_SEL_MASK
214 #define RT5640_INL_SEL_SFT
215 #define RT5640_INL_SEL_IN4P
216 #define RT5640_INL_SEL_MONOP
217 #define RT5640_INL_VOL_MASK
218 #define RT5640_INL_VOL_SFT
219 #define RT5640_INR_SEL_MASK
220 #define RT5640_INR_SEL_SFT
221 #define RT5640_INR_SEL_IN4N
222 #define RT5640_INR_SEL_MONON
223 #define RT5640_INR_VOL_MASK
224 #define RT5640_INR_VOL_SFT
225
226 /* DAC1 Digital Volume (0x19) */
227 #define RT5640_DAC_L1_VOL_MASK
228 #define RT5640_DAC_L1_VOL_SFT
229 #define RT5640_DAC_R1_VOL_MASK
230 #define RT5640_DAC_R1_VOL_SFT
231
232 /* DAC2 Digital Volume (0x1a) */
233 #define RT5640_DAC_L2_VOL_MASK
234 #define RT5640_DAC_L2_VOL_SFT
235 #define RT5640_DAC_R2_VOL_MASK
236 #define RT5640_DAC_R2_VOL_SFT
237
238 /* DAC2 Control (0x1b) */
239 #define RT5640_M_DAC_L2_VOL
240 #define RT5640_M_DAC_L2_VOL_SFT
241 #define RT5640_M_DAC_R2_VOL
242 #define RT5640_M_DAC_R2_VOL_SFT
243
244 /* ADC Digital Volume Control (0x1c) */
245 #define RT5640_ADC_L_VOL_MASK
246 #define RT5640_ADC_L_VOL_SFT
247 #define RT5640_ADC_R_VOL_MASK
248 #define RT5640_ADC_R_VOL_SFT
249
250 /* Mono ADC Digital Volume Control (0x1d) */
251 #define RT5640_MONO_ADC_L_VOL_MASK
252 #define RT5640_MONO_ADC_L_VOL_SFT
253 #define RT5640_MONO_ADC_R_VOL_MASK
254 #define RT5640_MONO_ADC_R_VOL_SFT
255
256 /* ADC Boost Volume Control (0x1e) */
257 #define RT5640_ADC_L_BST_MASK
258 #define RT5640_ADC_L_BST_SFT
259 #define RT5640_ADC_R_BST_MASK
260 #define RT5640_ADC_R_BST_SFT
261 #define RT5640_ADC_COMP_MASK
262 #define RT5640_ADC_COMP_SFT
263
264 /* Stereo ADC Mixer Control (0x27) */
265 #define RT5640_M_ADC_L1
266 #define RT5640_M_ADC_L1_SFT
267 #define RT5640_M_ADC_L2
268 #define RT5640_M_ADC_L2_SFT
269 #define RT5640_ADC_1_SRC_MASK
270 #define RT5640_ADC_1_SRC_SFT
271 #define RT5640_ADC_1_SRC_ADC
272 #define RT5640_ADC_1_SRC_DACMIX
273 #define RT5640_ADC_2_SRC_MASK
274 #define RT5640_ADC_2_SRC_SFT
275 #define RT5640_ADC_2_SRC_DMIC1
276 #define RT5640_ADC_2_SRC_DMIC2
277 #define RT5640_ADC_2_SRC_DACMIX
278 #define RT5640_M_ADC_R1
279 #define RT5640_M_ADC_R1_SFT
280 #define RT5640_M_ADC_R2
281 #define RT5640_M_ADC_R2_SFT
282
283 /* Mono ADC Mixer Control (0x28) */
284 #define RT5640_M_MONO_ADC_L1
285 #define RT5640_M_MONO_ADC_L1_SFT
286 #define RT5640_M_MONO_ADC_L2
287 #define RT5640_M_MONO_ADC_L2_SFT
288 #define RT5640_MONO_ADC_L1_SRC_MASK
289 #define RT5640_MONO_ADC_L1_SRC_SFT
290 #define RT5640_MONO_ADC_L1_SRC_DACMIXL
291 #define RT5640_MONO_ADC_L1_SRC_ADCL
292 #define RT5640_MONO_ADC_L2_SRC_MASK
293 #define RT5640_MONO_ADC_L2_SRC_SFT
294 #define RT5640_MONO_ADC_L2_SRC_DMIC_L1
295 #define RT5640_MONO_ADC_L2_SRC_DMIC_L2
296 #define RT5640_MONO_ADC_L2_SRC_DACMIXL
297 #define RT5640_M_MONO_ADC_R1
298 #define RT5640_M_MONO_ADC_R1_SFT
299 #define RT5640_M_MONO_ADC_R2
300 #define RT5640_M_MONO_ADC_R2_SFT
301 #define RT5640_MONO_ADC_R1_SRC_MASK
302 #define RT5640_MONO_ADC_R1_SRC_SFT
303 #define RT5640_MONO_ADC_R1_SRC_ADCR
304 #define RT5640_MONO_ADC_R1_SRC_DACMIXR
305 #define RT5640_MONO_ADC_R2_SRC_MASK
306 #define RT5640_MONO_ADC_R2_SRC_SFT
307 #define RT5640_MONO_ADC_R2_SRC_DMIC_R1
308 #define RT5640_MONO_ADC_R2_SRC_DMIC_R2
309 #define RT5640_MONO_ADC_R2_SRC_DACMIXR
310
311 /* ADC Mixer to DAC Mixer Control (0x29) */
312 #define RT5640_M_ADCMIX_L
313 #define RT5640_M_ADCMIX_L_SFT
314 #define RT5640_M_IF1_DAC_L
315 #define RT5640_M_IF1_DAC_L_SFT
316 #define RT5640_M_ADCMIX_R
317 #define RT5640_M_ADCMIX_R_SFT
318 #define RT5640_M_IF1_DAC_R
319 #define RT5640_M_IF1_DAC_R_SFT
320
321 /* Stereo DAC Mixer Control (0x2a) */
322 #define RT5640_M_DAC_L1
323 #define RT5640_M_DAC_L1_SFT
324 #define RT5640_DAC_L1_STO_L_VOL_MASK
325 #define RT5640_DAC_L1_STO_L_VOL_SFT
326 #define RT5640_M_DAC_L2
327 #define RT5640_M_DAC_L2_SFT
328 #define RT5640_DAC_L2_STO_L_VOL_MASK
329 #define RT5640_DAC_L2_STO_L_VOL_SFT
330 #define RT5640_M_ANC_DAC_L
331 #define RT5640_M_ANC_DAC_L_SFT
332 #define RT5640_M_DAC_R1
333 #define RT5640_M_DAC_R1_SFT
334 #define RT5640_DAC_R1_STO_R_VOL_MASK
335 #define RT5640_DAC_R1_STO_R_VOL_SFT
336 #define RT5640_M_DAC_R2
337 #define RT5640_M_DAC_R2_SFT
338 #define RT5640_DAC_R2_STO_R_VOL_MASK
339 #define RT5640_DAC_R2_STO_R_VOL_SFT
340 #define RT5640_M_ANC_DAC_R
341 #define RT5640_M_ANC_DAC_R_SFT 2
342
343 /* Mono DAC Mixer Control (0x2b) */
344 #define RT5640_M_DAC_L1_MONO_L
345 #define RT5640_M_DAC_L1_MONO_L_SFT
346 #define RT5640_DAC_L1_MONO_L_VOL_MASK
347 #define RT5640_DAC_L1_MONO_L_VOL_SFT
348 #define RT5640_M_DAC_L2_MONO_L
349 #define RT5640_M_DAC_L2_MONO_L_SFT
350 #define RT5640_DAC_L2_MONO_L_VOL_MASK
351 #define RT5640_DAC_L2_MONO_L_VOL_SFT
352 #define RT5640_M_DAC_R2_MONO_L
353 #define RT5640_M_DAC_R2_MONO_L_SFT
354 #define RT5640_DAC_R2_MONO_L_VOL_MASK
355 #define RT5640_DAC_R2_MONO_L_VOL_SFT
356 #define RT5640_M_DAC_R1_MONO_R
357 #define RT5640_M_DAC_R1_MONO_R_SFT
358 #define RT5640_DAC_R1_MONO_R_VOL_MASK
359 #define RT5640_DAC_R1_MONO_R_VOL_SFT
360 #define RT5640_M_DAC_R2_MONO_R
361 #define RT5640_M_DAC_R2_MONO_R_SFT
362 #define RT5640_DAC_R2_MONO_R_VOL_MASK
363 #define RT5640_DAC_R2_MONO_R_VOL_SFT
364 #define RT5640_M_DAC_L2_MONO_R
365 #define RT5640_M_DAC_L2_MONO_R_SFT
366 #define RT5640_DAC_L2_MONO_R_VOL_MASK
367 #define RT5640_DAC_L2_MONO_R_VOL_SFT
368
369 /* Digital Mixer Control (0x2c) */
370 #define RT5640_M_STO_L_DAC_L
371 #define RT5640_M_STO_L_DAC_L_SFT
372 #define RT5640_STO_L_DAC_L_VOL_MASK
373 #define RT5640_STO_L_DAC_L_VOL_SFT
374 #define RT5640_M_DAC_L2_DAC_L
375 #define RT5640_M_DAC_L2_DAC_L_SFT
376 #define RT5640_DAC_L2_DAC_L_VOL_MASK
377 #define RT5640_DAC_L2_DAC_L_VOL_SFT
378 #define RT5640_M_STO_R_DAC_R
379 #define RT5640_M_STO_R_DAC_R_SFT
380 #define RT5640_STO_R_DAC_R_VOL_MASK
381 #define RT5640_STO_R_DAC_R_VOL_SFT
382 #define RT5640_M_DAC_R2_DAC_R
383 #define RT5640_M_DAC_R2_DAC_R_SFT
384 #define RT5640_DAC_R2_DAC_R_VOL_MASK
385 #define RT5640_DAC_R2_DAC_R_VOL_SFT
386
387 /* DSP Path Control 1 (0x2d) */
388 #define RT5640_RXDP_SRC_MASK
389 #define RT5640_RXDP_SRC_SFT
390 #define RT5640_RXDP_SRC_NOR
391 #define RT5640_RXDP_SRC_DIV3
392 #define RT5640_TXDP_SRC_MASK
393 #define RT5640_TXDP_SRC_SFT
394 #define RT5640_TXDP_SRC_NOR
395 #define RT5640_TXDP_SRC_DIV3
396
397 /* DSP Path Control 2 (0x2e) */
398 #define RT5640_DAC_L2_SEL_MASK
399 #define RT5640_DAC_L2_SEL_SFT
400 #define RT5640_DAC_L2_SEL_IF2
401 #define RT5640_DAC_L2_SEL_IF3
402 #define RT5640_DAC_L2_SEL_TXDC
403 #define RT5640_DAC_L2_SEL_BASS
404 #define RT5640_DAC_R2_SEL_MASK
405 #define RT5640_DAC_R2_SEL_SFT
406 #define RT5640_DAC_R2_SEL_IF2
407 #define RT5640_DAC_R2_SEL_IF3
408 #define RT5640_DAC_R2_SEL_TXDC
409 #define RT5640_IF2_ADC_L_SEL_MASK
410 #define RT5640_IF2_ADC_L_SEL_SFT
411 #define RT5640_IF2_ADC_L_SEL_TXDP
412 #define RT5640_IF2_ADC_L_SEL_PASS
413 #define RT5640_IF2_ADC_R_SEL_MASK
414 #define RT5640_IF2_ADC_R_SEL_SFT
415 #define RT5640_IF2_ADC_R_SEL_TXDP
416 #define RT5640_IF2_ADC_R_SEL_PASS
417 #define RT5640_RXDC_SEL_MASK
418 #define RT5640_RXDC_SEL_SFT
419 #define RT5640_RXDC_SEL_NOR
420 #define RT5640_RXDC_SEL_L2R
421 #define RT5640_RXDC_SEL_R2L
422 #define RT5640_RXDC_SEL_SWAP
423 #define RT5640_RXDP_SEL_MASK
424 #define RT5640_RXDP_SEL_SFT
425 #define RT5640_RXDP_SEL_NOR
426 #define RT5640_RXDP_SEL_L2R
427 #define RT5640_RXDP_SEL_R2L
428 #define RT5640_RXDP_SEL_SWAP
429 #define RT5640_TXDC_SEL_MASK
430 #define RT5640_TXDC_SEL_SFT
431 #define RT5640_TXDC_SEL_NOR
432 #define RT5640_TXDC_SEL_L2R
433 #define RT5640_TXDC_SEL_R2L
434 #define RT5640_TXDC_SEL_SWAP
435 #define RT5640_TXDP_SEL_MASK
436 #define RT5640_TXDP_SEL_SFT
437 #define RT5640_TXDP_SEL_NOR
438 #define RT5640_TXDP_SEL_L2R
439 #define RT5640_TXDP_SEL_R2L
440 #define RT5640_TRXDP_SEL_SWAP
441
442 /* Digital Interface Data Control (0x2f) */
443 #define RT5640_IF1_DAC_SEL_MASK
444 #define RT5640_IF1_DAC_SEL_SFT
445 #define RT5640_IF1_DAC_SEL_NOR
446 #define RT5640_IF1_DAC_SEL_SWAP
447 #define RT5640_IF1_DAC_SEL_L2R
448 #define RT5640_IF1_DAC_SEL_R2L
449 #define RT5640_IF1_ADC_SEL_MASK
450 #define RT5640_IF1_ADC_SEL_SFT
451 #define RT5640_IF1_ADC_SEL_NOR
452 #define RT5640_IF1_ADC_SEL_SWAP
453 #define RT5640_IF1_ADC_SEL_L2R
454 #define RT5640_IF1_ADC_SEL_R2L
455 #define RT5640_IF2_DAC_SEL_MASK
456 #define RT5640_IF2_DAC_SEL_SFT
457 #define RT5640_IF2_DAC_SEL_NOR
458 #define RT5640_IF2_DAC_SEL_SWAP
459 #define RT5640_IF2_DAC_SEL_L2R
460 #define RT5640_IF2_DAC_SEL_R2L
461 #define RT5640_IF2_ADC_SEL_MASK
462 #define RT5640_IF2_ADC_SEL_SFT
463 #define RT5640_IF2_ADC_SEL_NOR
464 #define RT5640_IF2_ADC_SEL_SWAP
465 #define RT5640_IF2_ADC_SEL_L2R
466 #define RT5640_IF2_ADC_SEL_R2L
467 #define RT5640_IF3_DAC_SEL_MASK
468 #define RT5640_IF3_DAC_SEL_SFT
469 #define RT5640_IF3_DAC_SEL_NOR
470 #define RT5640_IF3_DAC_SEL_SWAP
471 #define RT5640_IF3_DAC_SEL_L2R
472 #define RT5640_IF3_DAC_SEL_R2L
473 #define RT5640_IF3_ADC_SEL_MASK
474 #define RT5640_IF3_ADC_SEL_SFT
475 #define RT5640_IF3_ADC_SEL_NOR
476 #define RT5640_IF3_ADC_SEL_SWAP
477 #define RT5640_IF3_ADC_SEL_L2R
478 #define RT5640_IF3_ADC_SEL_R2L
479
480 /* REC Left Mixer Control 1 (0x3b) */
481 #define RT5640_G_HP_L_RM_L_MASK
482 #define RT5640_G_HP_L_RM_L_SFT
483 #define RT5640_G_IN_L_RM_L_MASK
484 #define RT5640_G_IN_L_RM_L_SFT
485 #define RT5640_G_BST4_RM_L_MASK
486 #define RT5640_G_BST4_RM_L_SFT
487 #define RT5640_G_BST3_RM_L_MASK
488 #define RT5640_G_BST3_RM_L_SFT
489 #define RT5640_G_BST2_RM_L_MASK
490 #define RT5640_G_BST2_RM_L_SFT
491
492 /* REC Left Mixer Control 2 (0x3c) */
493 #define RT5640_G_BST1_RM_L_MASK
494 #define RT5640_G_BST1_RM_L_SFT
495 #define RT5640_G_OM_L_RM_L_MASK
496 #define RT5640_G_OM_L_RM_L_SFT
497 #define RT5640_M_HP_L_RM_L
498 #define RT5640_M_HP_L_RM_L_SFT
499 #define RT5640_M_IN_L_RM_L
500 #define RT5640_M_IN_L_RM_L_SFT
501 #define RT5640_M_BST4_RM_L
502 #define RT5640_M_BST4_RM_L_SFT
503 #define RT5640_M_BST3_RM_L
504 #define RT5640_M_BST3_RM_L_SFT
505 #define RT5640_M_BST2_RM_L
506 #define RT5640_M_BST2_RM_L_SFT
507 #define RT5640_M_BST1_RM_L
508 #define RT5640_M_BST1_RM_L_SFT
509 #define RT5640_M_OM_L_RM_L
510 #define RT5640_M_OM_L_RM_L_SFT
511
512 /* REC Right Mixer Control 1 (0x3d) */
513 #define RT5640_G_HP_R_RM_R_MASK
514 #define RT5640_G_HP_R_RM_R_SFT
515 #define RT5640_G_IN_R_RM_R_MASK
516 #define RT5640_G_IN_R_RM_R_SFT
517 #define RT5640_G_BST4_RM_R_MASK
518 #define RT5640_G_BST4_RM_R_SFT
519 #define RT5640_G_BST3_RM_R_MASK
520 #define RT5640_G_BST3_RM_R_SFT
521 #define RT5640_G_BST2_RM_R_MASK
522 #define RT5640_G_BST2_RM_R_SFT
523
524 /* REC Right Mixer Control 2 (0x3e) */
525 #define RT5640_G_BST1_RM_R_MASK
526 #define RT5640_G_BST1_RM_R_SFT
527 #define RT5640_G_OM_R_RM_R_MASK
528 #define RT5640_G_OM_R_RM_R_SFT
529 #define RT5640_M_HP_R_RM_R
530 #define RT5640_M_HP_R_RM_R_SFT
531 #define RT5640_M_IN_R_RM_R
532 #define RT5640_M_IN_R_RM_R_SFT
533 #define RT5640_M_BST4_RM_R
534 #define RT5640_M_BST4_RM_R_SFT
535 #define RT5640_M_BST3_RM_R
536 #define RT5640_M_BST3_RM_R_SFT
537 #define RT5640_M_BST2_RM_R
538 #define RT5640_M_BST2_RM_R_SFT
539 #define RT5640_M_BST1_RM_R
540 #define RT5640_M_BST1_RM_R_SFT
541 #define RT5640_M_OM_R_RM_R
542 #define RT5640_M_OM_R_RM_R_SFT
543
544 /* HPMIX Control (0x45) */
545 #define RT5640_M_DAC2_HM
546 #define RT5640_M_DAC2_HM_SFT
547 #define RT5640_M_DAC1_HM
548 #define RT5640_M_DAC1_HM_SFT
549 #define RT5640_M_HPVOL_HM
550 #define RT5640_M_HPVOL_HM_SFT
551 #define RT5640_G_HPOMIX_MASK
552 #define RT5640_G_HPOMIX_SFT
553
554 /* SPK Left Mixer Control (0x46) */
555 #define RT5640_G_RM_L_SM_L_MASK
556 #define RT5640_G_RM_L_SM_L_SFT
557 #define RT5640_G_IN_L_SM_L_MASK
558 #define RT5640_G_IN_L_SM_L_SFT
559 #define RT5640_G_DAC_L1_SM_L_MASK
560 #define RT5640_G_DAC_L1_SM_L_SFT
561 #define RT5640_G_DAC_L2_SM_L_MASK
562 #define RT5640_G_DAC_L2_SM_L_SFT
563 #define RT5640_G_OM_L_SM_L_MASK
564 #define RT5640_G_OM_L_SM_L_SFT
565 #define RT5640_M_RM_L_SM_L
566 #define RT5640_M_RM_L_SM_L_SFT
567 #define RT5640_M_IN_L_SM_L
568 #define RT5640_M_IN_L_SM_L_SFT
569 #define RT5640_M_DAC_L1_SM_L
570 #define RT5640_M_DAC_L1_SM_L_SFT
571 #define RT5640_M_DAC_L2_SM_L
572 #define RT5640_M_DAC_L2_SM_L_SFT
573 #define RT5640_M_OM_L_SM_L
574 #define RT5640_M_OM_L_SM_L_SFT 1
575
576 /* SPK Right Mixer Control (0x47) */
577 #define RT5640_G_RM_R_SM_R_MASK
578 #define RT5640_G_RM_R_SM_R_SFT
579 #define RT5640_G_IN_R_SM_R_MASK
580 #define RT5640_G_IN_R_SM_R_SFT
581 #define RT5640_G_DAC_R1_SM_R_MASK
582 #define RT5640_G_DAC_R1_SM_R_SFT
583 #define RT5640_G_DAC_R2_SM_R_MASK
584 #define RT5640_G_DAC_R2_SM_R_SFT
585 #define RT5640_G_OM_R_SM_R_MASK
586 #define RT5640_G_OM_R_SM_R_SFT
587 #define RT5640_M_RM_R_SM_R
588 #define RT5640_M_RM_R_SM_R_SFT
589 #define RT5640_M_IN_R_SM_R
590 #define RT5640_M_IN_R_SM_R_SFT
591 #define RT5640_M_DAC_R1_SM_R
592 #define RT5640_M_DAC_R1_SM_R_SFT
593 #define RT5640_M_DAC_R2_SM_R
594 #define RT5640_M_DAC_R2_SM_R_SFT
595 #define RT5640_M_OM_R_SM_R
596 #define RT5640_M_OM_R_SM_R_SFT
597
598 /* SPOLMIX Control (0x48) */
599 #define RT5640_M_DAC_R1_SPM_L
600 #define RT5640_M_DAC_R1_SPM_L_SFT
601 #define RT5640_M_DAC_L1_SPM_L
602 #define RT5640_M_DAC_L1_SPM_L_SFT
603 #define RT5640_M_SV_R_SPM_L
604 #define RT5640_M_SV_R_SPM_L_SFT
605 #define RT5640_M_SV_L_SPM_L
606 #define RT5640_M_SV_L_SPM_L_SFT
607 #define RT5640_M_BST1_SPM_L
608 #define RT5640_M_BST1_SPM_L_SFT
609
610 /* SPORMIX Control (0x49) */
611 #define RT5640_M_DAC_R1_SPM_R
612 #define RT5640_M_DAC_R1_SPM_R_SFT
613 #define RT5640_M_SV_R_SPM_R
614 #define RT5640_M_SV_R_SPM_R_SFT
615 #define RT5640_M_BST1_SPM_R
616 #define RT5640_M_BST1_SPM_R_SFT
617
618 /* SPOLMIX / SPORMIX Ratio Control (0x4a) */
619 #define RT5640_SPO_CLSD_RATIO_MASK
620 #define RT5640_SPO_CLSD_RATIO_SFT
621
622 /* Mono Output Mixer Control (0x4c) */
623 #define RT5640_M_DAC_R2_MM
624 #define RT5640_M_DAC_R2_MM_SFT
625 #define RT5640_M_DAC_L2_MM
626 #define RT5640_M_DAC_L2_MM_SFT
627 #define RT5640_M_OV_R_MM
628 #define RT5640_M_OV_R_MM_SFT
629 #define RT5640_M_OV_L_MM
630 #define RT5640_M_OV_L_MM_SFT
631 #define RT5640_M_BST1_MM
632 #define RT5640_M_BST1_MM_SFT
633 #define RT5640_G_MONOMIX_MASK
634 #define RT5640_G_MONOMIX_SFT
635
636 /* Output Left Mixer Control 1 (0x4d) */
637 #define RT5640_G_BST3_OM_L_MASK
638 #define RT5640_G_BST3_OM_L_SFT
639 #define RT5640_G_BST2_OM_L_MASK
640 #define RT5640_G_BST2_OM_L_SFT
641 #define RT5640_G_BST1_OM_L_MASK
642 #define RT5640_G_BST1_OM_L_SFT
643 #define RT5640_G_IN_L_OM_L_MASK
644 #define RT5640_G_IN_L_OM_L_SFT
645 #define RT5640_G_RM_L_OM_L_MASK
646 #define RT5640_G_RM_L_OM_L_SFT
647
648 /* Output Left Mixer Control 2 (0x4e) */
649 #define RT5640_G_DAC_R2_OM_L_MASK
650 #define RT5640_G_DAC_R2_OM_L_SFT
651 #define RT5640_G_DAC_L2_OM_L_MASK
652 #define RT5640_G_DAC_L2_OM_L_SFT
653 #define RT5640_G_DAC_L1_OM_L_MASK
654 #define RT5640_G_DAC_L1_OM_L_SFT
655
656 /* Output Left Mixer Control 3 (0x4f) */
657 #define RT5640_M_SM_L_OM_L
658 #define RT5640_M_SM_L_OM_L_SFT
659 #define RT5640_M_BST3_OM_L
660 #define RT5640_M_BST3_OM_L_SFT
661 #define RT5640_M_BST2_OM_L
662 #define RT5640_M_BST2_OM_L_SFT
663 #define RT5640_M_BST1_OM_L
664 #define RT5640_M_BST1_OM_L_SFT
665 #define RT5640_M_IN_L_OM_L
666 #define RT5640_M_IN_L_OM_L_SFT
667 #define RT5640_M_RM_L_OM_L
668 #define RT5640_M_RM_L_OM_L_SFT
669 #define RT5640_M_DAC_R2_OM_L
670 #define RT5640_M_DAC_R2_OM_L_SFT
671 #define RT5640_M_DAC_L2_OM_L
672 #define RT5640_M_DAC_L2_OM_L_SFT
673 #define RT5640_M_DAC_L1_OM_L
674 #define RT5640_M_DAC_L1_OM_L_SFT
675
676 /* Output Right Mixer Control 1 (0x50) */
677 #define RT5640_G_BST4_OM_R_MASK
678 #define RT5640_G_BST4_OM_R_SFT
679 #define RT5640_G_BST2_OM_R_MASK
680 #define RT5640_G_BST2_OM_R_SFT
681 #define RT5640_G_BST1_OM_R_MASK
682 #define RT5640_G_BST1_OM_R_SFT
683 #define RT5640_G_IN_R_OM_R_MASK
684 #define RT5640_G_IN_R_OM_R_SFT
685 #define RT5640_G_RM_R_OM_R_MASK
686 #define RT5640_G_RM_R_OM_R_SFT
687
688 /* Output Right Mixer Control 2 (0x51) */
689 #define RT5640_G_DAC_L2_OM_R_MASK
690 #define RT5640_G_DAC_L2_OM_R_SFT
691 #define RT5640_G_DAC_R2_OM_R_MASK
692 #define RT5640_G_DAC_R2_OM_R_SFT
693 #define RT5640_G_DAC_R1_OM_R_MASK
694 #define RT5640_G_DAC_R1_OM_R_SFT
695
696 /* Output Right Mixer Control 3 (0x52) */
697 #define RT5640_M_SM_L_OM_R
698 #define RT5640_M_SM_L_OM_R_SFT
699 #define RT5640_M_BST4_OM_R
700 #define RT5640_M_BST4_OM_R_SFT
701 #define RT5640_M_BST2_OM_R
702 #define RT5640_M_BST2_OM_R_SFT
703 #define RT5640_M_BST1_OM_R
704 #define RT5640_M_BST1_OM_R_SFT
705 #define RT5640_M_IN_R_OM_R
706 #define RT5640_M_IN_R_OM_R_SFT
707 #define RT5640_M_RM_R_OM_R
708 #define RT5640_M_RM_R_OM_R_SFT
709 #define RT5640_M_DAC_L2_OM_R
710 #define RT5640_M_DAC_L2_OM_R_SFT
711 #define RT5640_M_DAC_R2_OM_R
712 #define RT5640_M_DAC_R2_OM_R_SFT
713 #define RT5640_M_DAC_R1_OM_R
714 #define RT5640_M_DAC_R1_OM_R_SFT
715
716 /* LOUT Mixer Control (0x53) */
717 #define RT5640_M_DAC_L1_LM
718 #define RT5640_M_DAC_L1_LM_SFT
719 #define RT5640_M_DAC_R1_LM
720 #define RT5640_M_DAC_R1_LM_SFT
721 #define RT5640_M_OV_L_LM
722 #define RT5640_M_OV_L_LM_SFT
723 #define RT5640_M_OV_R_LM
724 #define RT5640_M_OV_R_LM_SFT
725 #define RT5640_G_LOUTMIX_MASK
726 #define RT5640_G_LOUTMIX_SFT
727
728 /* Power Management for Digital 1 (0x61) */
729 #define RT5640_PWR_I2S1
730 #define RT5640_PWR_I2S1_BIT
731 #define RT5640_PWR_I2S2
732 #define RT5640_PWR_I2S2_BIT
733 #define RT5640_PWR_DAC_L1
734 #define RT5640_PWR_DAC_L1_BIT
735 #define RT5640_PWR_DAC_R1
736 #define RT5640_PWR_DAC_R1_BIT
737 #define RT5640_PWR_DAC_L2
738 #define RT5640_PWR_DAC_L2_BIT
739 #define RT5640_PWR_DAC_R2
740 #define RT5640_PWR_DAC_R2_BIT
741 #define RT5640_PWR_ADC_L
742 #define RT5640_PWR_ADC_L_BIT
743 #define RT5640_PWR_ADC_R
744 #define RT5640_PWR_ADC_R_BIT
745 #define RT5640_PWR_CLS_D
746 #define RT5640_PWR_CLS_D_BIT
747
748 /* Power Management for Digital 2 (0x62) */
749 #define RT5640_PWR_ADC_SF
750 #define RT5640_PWR_ADC_SF_BIT
751 #define RT5640_PWR_ADC_MF_L
752 #define RT5640_PWR_ADC_MF_L_BIT
753 #define RT5640_PWR_ADC_MF_R
754 #define RT5640_PWR_ADC_MF_R_BIT
755 #define RT5640_PWR_I2S_DSP
756 #define RT5640_PWR_I2S_DSP_BIT
757
758 /* Power Management for Analog 1 (0x63) */
759 #define RT5640_PWR_VREF1
760 #define RT5640_PWR_VREF1_BIT
761 #define RT5640_PWR_FV1
762 #define RT5640_PWR_FV1_BIT
763 #define RT5640_PWR_MB
764 #define RT5640_PWR_MB_BIT
765 #define RT5640_PWR_LM
766 #define RT5640_PWR_LM_BIT
767 #define RT5640_PWR_BG
768 #define RT5640_PWR_BG_BIT
769 #define RT5640_PWR_MM
770 #define RT5640_PWR_MM_BIT
771 #define RT5640_PWR_MA
772 #define RT5640_PWR_MA_BIT
773 #define RT5640_PWR_HP_L
774 #define RT5640_PWR_HP_L_BIT
775 #define RT5640_PWR_HP_R
776 #define RT5640_PWR_HP_R_BIT
777 #define RT5640_PWR_HA
778 #define RT5640_PWR_HA_BIT
779 #define RT5640_PWR_VREF2
780 #define RT5640_PWR_VREF2_BIT
781 #define RT5640_PWR_FV2
782 #define RT5640_PWR_FV2_BIT
783 #define RT5640_PWR_LDO2
784 #define RT5640_PWR_LDO2_BIT
785
786 /* Power Management for Analog 2 (0x64) */
787 #define RT5640_PWR_BST1
788 #define RT5640_PWR_BST1_BIT
789 #define RT5640_PWR_BST2
790 #define RT5640_PWR_BST2_BIT
791 #define RT5640_PWR_BST3
792 #define RT5640_PWR_BST3_BIT
793 #define RT5640_PWR_BST4
794 #define RT5640_PWR_BST4_BIT
795 #define RT5640_PWR_MB1
796 #define RT5640_PWR_MB1_BIT
797 #define RT5640_PWR_PLL
798 #define RT5640_PWR_PLL_BIT
799
800 /* Power Management for Mixer (0x65) */
801 #define RT5640_PWR_OM_L
802 #define RT5640_PWR_OM_L_BIT
803 #define RT5640_PWR_OM_R
804 #define RT5640_PWR_OM_R_BIT
805 #define RT5640_PWR_SM_L
806 #define RT5640_PWR_SM_L_BIT
807 #define RT5640_PWR_SM_R
808 #define RT5640_PWR_SM_R_BIT
809 #define RT5640_PWR_RM_L
810 #define RT5640_PWR_RM_L_BIT
811 #define RT5640_PWR_RM_R
812 #define RT5640_PWR_RM_R_BIT
813
814 /* Power Management for Volume (0x66) */
815 #define RT5640_PWR_SV_L
816 #define RT5640_PWR_SV_L_BIT
817 #define RT5640_PWR_SV_R
818 #define RT5640_PWR_SV_R_BIT
819 #define RT5640_PWR_OV_L
820 #define RT5640_PWR_OV_L_BIT
821 #define RT5640_PWR_OV_R
822 #define RT5640_PWR_OV_R_BIT
823 #define RT5640_PWR_HV_L
824 #define RT5640_PWR_HV_L_BIT
825 #define RT5640_PWR_HV_R
826 #define RT5640_PWR_HV_R_BIT
827 #define RT5640_PWR_IN_L
828 #define RT5640_PWR_IN_L_BIT
829 #define RT5640_PWR_IN_R
830 #define RT5640_PWR_IN_R_BIT
831
832 /* I2S1/2/3 Audio Serial Data Port Control (0x
833 #define RT5640_I2S_MS_MASK
834 #define RT5640_I2S_MS_SFT
835 #define RT5640_I2S_MS_M
836 #define RT5640_I2S_MS_S
837 #define RT5640_I2S_IF_MASK
838 #define RT5640_I2S_IF_SFT
839 #define RT5640_I2S_O_CP_MASK
840 #define RT5640_I2S_O_CP_SFT
841 #define RT5640_I2S_O_CP_OFF
842 #define RT5640_I2S_O_CP_U_LAW
843 #define RT5640_I2S_O_CP_A_LAW
844 #define RT5640_I2S_I_CP_MASK
845 #define RT5640_I2S_I_CP_SFT
846 #define RT5640_I2S_I_CP_OFF
847 #define RT5640_I2S_I_CP_U_LAW
848 #define RT5640_I2S_I_CP_A_LAW
849 #define RT5640_I2S_BP_MASK
850 #define RT5640_I2S_BP_SFT
851 #define RT5640_I2S_BP_NOR
852 #define RT5640_I2S_BP_INV
853 #define RT5640_I2S_DL_MASK
854 #define RT5640_I2S_DL_SFT
855 #define RT5640_I2S_DL_16
856 #define RT5640_I2S_DL_20
857 #define RT5640_I2S_DL_24
858 #define RT5640_I2S_DL_8
859 #define RT5640_I2S_DF_MASK
860 #define RT5640_I2S_DF_SFT
861 #define RT5640_I2S_DF_I2S
862 #define RT5640_I2S_DF_LEFT
863 #define RT5640_I2S_DF_PCM_A
864 #define RT5640_I2S_DF_PCM_B
865
866 /* I2S2 Audio Serial Data Port Control (0x71)
867 #define RT5640_I2S2_SDI_MASK
868 #define RT5640_I2S2_SDI_SFT
869 #define RT5640_I2S2_SDI_I2S1
870 #define RT5640_I2S2_SDI_I2S2
871
872 /* ADC/DAC Clock Control 1 (0x73) */
873 #define RT5640_I2S_BCLK_MS1_MASK
874 #define RT5640_I2S_BCLK_MS1_SFT
875 #define RT5640_I2S_BCLK_MS1_32
876 #define RT5640_I2S_BCLK_MS1_64
877 #define RT5640_I2S_PD1_MASK
878 #define RT5640_I2S_PD1_SFT
879 #define RT5640_I2S_PD1_1
880 #define RT5640_I2S_PD1_2
881 #define RT5640_I2S_PD1_3
882 #define RT5640_I2S_PD1_4
883 #define RT5640_I2S_PD1_6
884 #define RT5640_I2S_PD1_8
885 #define RT5640_I2S_PD1_12
886 #define RT5640_I2S_PD1_16
887 #define RT5640_I2S_BCLK_MS2_MASK
888 #define RT5640_I2S_BCLK_MS2_SFT
889 #define RT5640_I2S_BCLK_MS2_32
890 #define RT5640_I2S_BCLK_MS2_64
891 #define RT5640_I2S_PD2_MASK
892 #define RT5640_I2S_PD2_SFT
893 #define RT5640_I2S_PD2_1
894 #define RT5640_I2S_PD2_2
895 #define RT5640_I2S_PD2_3
896 #define RT5640_I2S_PD2_4
897 #define RT5640_I2S_PD2_6
898 #define RT5640_I2S_PD2_8
899 #define RT5640_I2S_PD2_12
900 #define RT5640_I2S_PD2_16
901 #define RT5640_I2S_BCLK_MS3_MASK
902 #define RT5640_I2S_BCLK_MS3_SFT
903 #define RT5640_I2S_BCLK_MS3_32
904 #define RT5640_I2S_BCLK_MS3_64
905 #define RT5640_I2S_PD3_MASK
906 #define RT5640_I2S_PD3_SFT
907 #define RT5640_I2S_PD3_1
908 #define RT5640_I2S_PD3_2
909 #define RT5640_I2S_PD3_3
910 #define RT5640_I2S_PD3_4
911 #define RT5640_I2S_PD3_6
912 #define RT5640_I2S_PD3_8
913 #define RT5640_I2S_PD3_12
914 #define RT5640_I2S_PD3_16
915 #define RT5640_DAC_OSR_MASK
916 #define RT5640_DAC_OSR_SFT
917 #define RT5640_DAC_OSR_128
918 #define RT5640_DAC_OSR_64
919 #define RT5640_DAC_OSR_32
920 #define RT5640_DAC_OSR_16
921 #define RT5640_ADC_OSR_MASK
922 #define RT5640_ADC_OSR_SFT
923 #define RT5640_ADC_OSR_128
924 #define RT5640_ADC_OSR_64
925 #define RT5640_ADC_OSR_32
926 #define RT5640_ADC_OSR_16
927
928 /* ADC/DAC Clock Control 2 (0x74) */
929 #define RT5640_DAC_L_OSR_MASK
930 #define RT5640_DAC_L_OSR_SFT
931 #define RT5640_DAC_L_OSR_128
932 #define RT5640_DAC_L_OSR_64
933 #define RT5640_DAC_L_OSR_32
934 #define RT5640_DAC_L_OSR_16
935 #define RT5640_ADC_R_OSR_MASK
936 #define RT5640_ADC_R_OSR_SFT
937 #define RT5640_ADC_R_OSR_128
938 #define RT5640_ADC_R_OSR_64
939 #define RT5640_ADC_R_OSR_32
940 #define RT5640_ADC_R_OSR_16
941 #define RT5640_DAHPF_EN
942 #define RT5640_DAHPF_EN_SFT
943 #define RT5640_ADHPF_EN
944 #define RT5640_ADHPF_EN_SFT
945
946 /* Digital Microphone Control (0x75) */
947 #define RT5640_DMIC_1_EN_MASK
948 #define RT5640_DMIC_1_EN_SFT
949 #define RT5640_DMIC_1_DIS
950 #define RT5640_DMIC_1_EN
951 #define RT5640_DMIC_2_EN_MASK
952 #define RT5640_DMIC_2_EN_SFT
953 #define RT5640_DMIC_2_DIS
954 #define RT5640_DMIC_2_EN
955 #define RT5640_DMIC_1L_LH_MASK
956 #define RT5640_DMIC_1L_LH_SFT
957 #define RT5640_DMIC_1L_LH_FALLING
958 #define RT5640_DMIC_1L_LH_RISING
959 #define RT5640_DMIC_1R_LH_MASK
960 #define RT5640_DMIC_1R_LH_SFT
961 #define RT5640_DMIC_1R_LH_FALLING
962 #define RT5640_DMIC_1R_LH_RISING
963 #define RT5640_DMIC_1_DP_MASK
964 #define RT5640_DMIC_1_DP_SFT
965 #define RT5640_DMIC_1_DP_GPIO3
966 #define RT5640_DMIC_1_DP_IN1P
967 #define RT5640_DMIC_2_DP_MASK
968 #define RT5640_DMIC_2_DP_SFT
969 #define RT5640_DMIC_2_DP_GPIO4
970 #define RT5640_DMIC_2_DP_IN1N
971 #define RT5640_DMIC_2L_LH_MASK
972 #define RT5640_DMIC_2L_LH_SFT
973 #define RT5640_DMIC_2L_LH_FALLING
974 #define RT5640_DMIC_2L_LH_RISING
975 #define RT5640_DMIC_2R_LH_MASK
976 #define RT5640_DMIC_2R_LH_SFT
977 #define RT5640_DMIC_2R_LH_FALLING
978 #define RT5640_DMIC_2R_LH_RISING
979 #define RT5640_DMIC_CLK_MASK
980 #define RT5640_DMIC_CLK_SFT
981
982 /* Global Clock Control (0x80) */
983 #define RT5640_SCLK_SRC_MASK
984 #define RT5640_SCLK_SRC_SFT
985 #define RT5640_SCLK_SRC_MCLK
986 #define RT5640_SCLK_SRC_PLL1
987 #define RT5640_SCLK_SRC_RCCLK
988 #define RT5640_PLL1_SRC_MASK
989 #define RT5640_PLL1_SRC_SFT
990 #define RT5640_PLL1_SRC_MCLK
991 #define RT5640_PLL1_SRC_BCLK1
992 #define RT5640_PLL1_SRC_BCLK2
993 #define RT5640_PLL1_SRC_BCLK3
994 #define RT5640_PLL1_PD_MASK
995 #define RT5640_PLL1_PD_SFT
996 #define RT5640_PLL1_PD_1
997 #define RT5640_PLL1_PD_2
998
999 #define RT5640_PLL_INP_MAX
1000 #define RT5640_PLL_INP_MIN
1001 /* PLL M/N/K Code Control 1 (0x81) */
1002 #define RT5640_PLL_N_MAX
1003 #define RT5640_PLL_N_MASK
1004 #define RT5640_PLL_N_SFT
1005 #define RT5640_PLL_K_MAX
1006 #define RT5640_PLL_K_MASK
1007 #define RT5640_PLL_K_SFT
1008
1009 /* PLL M/N/K Code Control 2 (0x82) */
1010 #define RT5640_PLL_M_MAX
1011 #define RT5640_PLL_M_MASK
1012 #define RT5640_PLL_M_SFT
1013 #define RT5640_PLL_M_BP
1014 #define RT5640_PLL_M_BP_SFT
1015
1016 /* ASRC Control 1 (0x83) */
1017 #define RT5640_STO_T_MASK
1018 #define RT5640_STO_T_SFT
1019 #define RT5640_STO_T_SCLK
1020 #define RT5640_STO_T_LRCK1
1021 #define RT5640_M1_T_MASK
1022 #define RT5640_M1_T_SFT
1023 #define RT5640_M1_T_I2S2
1024 #define RT5640_M1_T_I2S2_D3
1025 #define RT5640_I2S2_F_MASK
1026 #define RT5640_I2S2_F_SFT
1027 #define RT5640_I2S2_F_I2S2_D2
1028 #define RT5640_I2S2_F_I2S1_TCLK
1029 #define RT5640_DMIC_1_M_MASK
1030 #define RT5640_DMIC_1_M_SFT
1031 #define RT5640_DMIC_1_M_NOR
1032 #define RT5640_DMIC_1_M_ASYN
1033 #define RT5640_DMIC_2_M_MASK
1034 #define RT5640_DMIC_2_M_SFT
1035 #define RT5640_DMIC_2_M_NOR
1036 #define RT5640_DMIC_2_M_ASYN
1037
1038 /* ASRC clock source selection (0x84) */
1039 #define RT5640_CLK_SEL_SYS
1040 #define RT5640_CLK_SEL_ASRC
1041
1042 /* ASRC Control 2 (0x84) */
1043 #define RT5640_MDA_L_M_MASK
1044 #define RT5640_MDA_L_M_SFT
1045 #define RT5640_MDA_L_M_NOR
1046 #define RT5640_MDA_L_M_ASYN
1047 #define RT5640_MDA_R_M_MASK
1048 #define RT5640_MDA_R_M_SFT
1049 #define RT5640_MDA_R_M_NOR
1050 #define RT5640_MDA_R_M_ASYN
1051 #define RT5640_MAD_L_M_MASK
1052 #define RT5640_MAD_L_M_SFT
1053 #define RT5640_MAD_L_M_NOR
1054 #define RT5640_MAD_L_M_ASYN
1055 #define RT5640_MAD_R_M_MASK
1056 #define RT5640_MAD_R_M_SFT
1057 #define RT5640_MAD_R_M_NOR
1058 #define RT5640_MAD_R_M_ASYN
1059 #define RT5640_ADC_M_MASK
1060 #define RT5640_ADC_M_SFT
1061 #define RT5640_ADC_M_NOR
1062 #define RT5640_ADC_M_ASYN
1063 #define RT5640_STO_DAC_M_MASK
1064 #define RT5640_STO_DAC_M_SFT
1065 #define RT5640_STO_DAC_M_NOR
1066 #define RT5640_STO_DAC_M_ASYN
1067 #define RT5640_I2S1_R_D_MASK
1068 #define RT5640_I2S1_R_D_SFT
1069 #define RT5640_I2S1_R_D_DIS
1070 #define RT5640_I2S1_R_D_EN
1071 #define RT5640_I2S2_R_D_MASK
1072 #define RT5640_I2S2_R_D_SFT
1073 #define RT5640_I2S2_R_D_DIS
1074 #define RT5640_I2S2_R_D_EN
1075 #define RT5640_PRE_SCLK_MASK
1076 #define RT5640_PRE_SCLK_SFT
1077 #define RT5640_PRE_SCLK_512
1078 #define RT5640_PRE_SCLK_1024
1079 #define RT5640_PRE_SCLK_2048
1080
1081 /* ASRC Control 3 (0x85) */
1082 #define RT5640_I2S1_RATE_MASK
1083 #define RT5640_I2S1_RATE_SFT
1084 #define RT5640_I2S2_RATE_MASK
1085 #define RT5640_I2S2_RATE_SFT
1086
1087 /* ASRC Control 4 (0x89) */
1088 #define RT5640_I2S1_PD_MASK
1089 #define RT5640_I2S1_PD_SFT
1090 #define RT5640_I2S2_PD_MASK
1091 #define RT5640_I2S2_PD_SFT
1092
1093 /* HPOUT Over Current Detection (0x8b) */
1094 #define RT5640_HP_OVCD_MASK
1095 #define RT5640_HP_OVCD_SFT
1096 #define RT5640_HP_OVCD_DIS
1097 #define RT5640_HP_OVCD_EN
1098 #define RT5640_HP_OC_TH_MASK
1099 #define RT5640_HP_OC_TH_SFT
1100 #define RT5640_HP_OC_TH_90
1101 #define RT5640_HP_OC_TH_105
1102 #define RT5640_HP_OC_TH_120
1103 #define RT5640_HP_OC_TH_135
1104
1105 /* Class D Over Current Control (0x8c) */
1106 #define RT5640_CLSD_OC_MASK
1107 #define RT5640_CLSD_OC_SFT
1108 #define RT5640_CLSD_OC_PU
1109 #define RT5640_CLSD_OC_PD
1110 #define RT5640_AUTO_PD_MASK
1111 #define RT5640_AUTO_PD_SFT
1112 #define RT5640_AUTO_PD_DIS
1113 #define RT5640_AUTO_PD_EN
1114 #define RT5640_CLSD_OC_TH_MASK
1115 #define RT5640_CLSD_OC_TH_SFT
1116
1117 /* Class D Output Control (0x8d) */
1118 #define RT5640_CLSD_RATIO_MASK
1119 #define RT5640_CLSD_RATIO_SFT
1120 #define RT5640_CLSD_OM_MASK
1121 #define RT5640_CLSD_OM_SFT
1122 #define RT5640_CLSD_OM_MONO
1123 #define RT5640_CLSD_OM_STO
1124 #define RT5640_CLSD_SCH_MASK
1125 #define RT5640_CLSD_SCH_SFT
1126 #define RT5640_CLSD_SCH_L
1127 #define RT5640_CLSD_SCH_S
1128
1129 /* Depop Mode Control 1 (0x8e) */
1130 #define RT5640_SMT_TRIG_MASK
1131 #define RT5640_SMT_TRIG_SFT
1132 #define RT5640_SMT_TRIG_DIS
1133 #define RT5640_SMT_TRIG_EN
1134 #define RT5640_HP_L_SMT_MASK
1135 #define RT5640_HP_L_SMT_SFT
1136 #define RT5640_HP_L_SMT_DIS
1137 #define RT5640_HP_L_SMT_EN
1138 #define RT5640_HP_R_SMT_MASK
1139 #define RT5640_HP_R_SMT_SFT
1140 #define RT5640_HP_R_SMT_DIS
1141 #define RT5640_HP_R_SMT_EN
1142 #define RT5640_HP_CD_PD_MASK
1143 #define RT5640_HP_CD_PD_SFT
1144 #define RT5640_HP_CD_PD_DIS
1145 #define RT5640_HP_CD_PD_EN
1146 #define RT5640_RSTN_MASK
1147 #define RT5640_RSTN_SFT
1148 #define RT5640_RSTN_DIS
1149 #define RT5640_RSTN_EN
1150 #define RT5640_RSTP_MASK
1151 #define RT5640_RSTP_SFT
1152 #define RT5640_RSTP_DIS
1153 #define RT5640_RSTP_EN
1154 #define RT5640_HP_CO_MASK
1155 #define RT5640_HP_CO_SFT
1156 #define RT5640_HP_CO_DIS
1157 #define RT5640_HP_CO_EN
1158 #define RT5640_HP_CP_MASK
1159 #define RT5640_HP_CP_SFT
1160 #define RT5640_HP_CP_PD
1161 #define RT5640_HP_CP_PU
1162 #define RT5640_HP_SG_MASK
1163 #define RT5640_HP_SG_SFT
1164 #define RT5640_HP_SG_DIS
1165 #define RT5640_HP_SG_EN
1166 #define RT5640_HP_DP_MASK
1167 #define RT5640_HP_DP_SFT
1168 #define RT5640_HP_DP_PD
1169 #define RT5640_HP_DP_PU
1170 #define RT5640_HP_CB_MASK
1171 #define RT5640_HP_CB_SFT
1172 #define RT5640_HP_CB_PD
1173 #define RT5640_HP_CB_PU
1174
1175 /* Depop Mode Control 2 (0x8f) */
1176 #define RT5640_DEPOP_MASK
1177 #define RT5640_DEPOP_SFT
1178 #define RT5640_DEPOP_AUTO
1179 #define RT5640_DEPOP_MAN
1180 #define RT5640_RAMP_MASK
1181 #define RT5640_RAMP_SFT
1182 #define RT5640_RAMP_DIS
1183 #define RT5640_RAMP_EN
1184 #define RT5640_BPS_MASK
1185 #define RT5640_BPS_SFT
1186 #define RT5640_BPS_DIS
1187 #define RT5640_BPS_EN
1188 #define RT5640_FAST_UPDN_MASK
1189 #define RT5640_FAST_UPDN_SFT
1190 #define RT5640_FAST_UPDN_DIS
1191 #define RT5640_FAST_UPDN_EN
1192 #define RT5640_MRES_MASK
1193 #define RT5640_MRES_SFT
1194 #define RT5640_MRES_15MO
1195 #define RT5640_MRES_25MO
1196 #define RT5640_MRES_35MO
1197 #define RT5640_MRES_45MO
1198 #define RT5640_VLO_MASK
1199 #define RT5640_VLO_SFT
1200 #define RT5640_VLO_3V
1201 #define RT5640_VLO_32V
1202 #define RT5640_DIG_DP_MASK
1203 #define RT5640_DIG_DP_SFT
1204 #define RT5640_DIG_DP_DIS
1205 #define RT5640_DIG_DP_EN
1206 #define RT5640_DP_TH_MASK
1207 #define RT5640_DP_TH_SFT
1208
1209 /* Depop Mode Control 3 (0x90) */
1210 #define RT5640_CP_SYS_MASK
1211 #define RT5640_CP_SYS_SFT
1212 #define RT5640_CP_FQ1_MASK
1213 #define RT5640_CP_FQ1_SFT
1214 #define RT5640_CP_FQ2_MASK
1215 #define RT5640_CP_FQ2_SFT
1216 #define RT5640_CP_FQ3_MASK
1217 #define RT5640_CP_FQ3_SFT
1218 #define RT5640_CP_FQ_1_5_KHZ
1219 #define RT5640_CP_FQ_3_KHZ
1220 #define RT5640_CP_FQ_6_KHZ
1221 #define RT5640_CP_FQ_12_KHZ
1222 #define RT5640_CP_FQ_24_KHZ
1223 #define RT5640_CP_FQ_48_KHZ
1224 #define RT5640_CP_FQ_96_KHZ
1225 #define RT5640_CP_FQ_192_KHZ
1226
1227 /* HPOUT charge pump (0x91) */
1228 #define RT5640_OSW_L_MASK
1229 #define RT5640_OSW_L_SFT
1230 #define RT5640_OSW_L_DIS
1231 #define RT5640_OSW_L_EN
1232 #define RT5640_OSW_R_MASK
1233 #define RT5640_OSW_R_SFT
1234 #define RT5640_OSW_R_DIS
1235 #define RT5640_OSW_R_EN
1236 #define RT5640_PM_HP_MASK
1237 #define RT5640_PM_HP_SFT
1238 #define RT5640_PM_HP_LV
1239 #define RT5640_PM_HP_MV
1240 #define RT5640_PM_HP_HV
1241 #define RT5640_IB_HP_MASK
1242 #define RT5640_IB_HP_SFT
1243 #define RT5640_IB_HP_125IL
1244 #define RT5640_IB_HP_25IL
1245 #define RT5640_IB_HP_5IL
1246 #define RT5640_IB_HP_1IL
1247
1248 /* PV detection and SPK gain control (0x92) *
1249 #define RT5640_PVDD_DET_MASK
1250 #define RT5640_PVDD_DET_SFT
1251 #define RT5640_PVDD_DET_DIS
1252 #define RT5640_PVDD_DET_EN
1253 #define RT5640_SPK_AG_MASK
1254 #define RT5640_SPK_AG_SFT
1255 #define RT5640_SPK_AG_DIS
1256 #define RT5640_SPK_AG_EN
1257
1258 /* Micbias Control (0x93) */
1259 #define RT5640_MIC1_BS_MASK
1260 #define RT5640_MIC1_BS_SFT
1261 #define RT5640_MIC1_BS_9AV
1262 #define RT5640_MIC1_BS_75AV
1263 #define RT5640_MIC2_BS_MASK
1264 #define RT5640_MIC2_BS_SFT
1265 #define RT5640_MIC2_BS_9AV
1266 #define RT5640_MIC2_BS_75AV
1267 #define RT5640_MIC1_CLK_MASK
1268 #define RT5640_MIC1_CLK_SFT
1269 #define RT5640_MIC1_CLK_DIS
1270 #define RT5640_MIC1_CLK_EN
1271 #define RT5640_MIC2_CLK_MASK
1272 #define RT5640_MIC2_CLK_SFT
1273 #define RT5640_MIC2_CLK_DIS
1274 #define RT5640_MIC2_CLK_EN
1275 #define RT5640_MIC1_OVCD_MASK
1276 #define RT5640_MIC1_OVCD_SFT
1277 #define RT5640_MIC1_OVCD_DIS
1278 #define RT5640_MIC1_OVCD_EN
1279 #define RT5640_MIC1_OVTH_MASK
1280 #define RT5640_MIC1_OVTH_SFT
1281 #define RT5640_MIC1_OVTH_600UA
1282 #define RT5640_MIC1_OVTH_1500UA
1283 #define RT5640_MIC1_OVTH_2000UA
1284 #define RT5640_MIC2_OVCD_MASK
1285 #define RT5640_MIC2_OVCD_SFT
1286 #define RT5640_MIC2_OVCD_DIS
1287 #define RT5640_MIC2_OVCD_EN
1288 #define RT5640_MIC2_OVTH_MASK
1289 #define RT5640_MIC2_OVTH_SFT
1290 #define RT5640_MIC2_OVTH_600UA
1291 #define RT5640_MIC2_OVTH_1500UA
1292 #define RT5640_MIC2_OVTH_2000UA
1293 #define RT5640_PWR_MB_MASK
1294 #define RT5640_PWR_MB_SFT
1295 #define RT5640_PWR_MB_PD
1296 #define RT5640_PWR_MB_PU
1297 #define RT5640_PWR_CLK25M_MASK
1298 #define RT5640_PWR_CLK25M_SFT
1299 #define RT5640_PWR_CLK25M_PD
1300 #define RT5640_PWR_CLK25M_PU
1301
1302 /* EQ Control 1 (0xb0) */
1303 #define RT5640_EQ_SRC_MASK
1304 #define RT5640_EQ_SRC_SFT
1305 #define RT5640_EQ_SRC_DAC
1306 #define RT5640_EQ_SRC_ADC
1307 #define RT5640_EQ_UPD
1308 #define RT5640_EQ_UPD_BIT
1309 #define RT5640_EQ_CD_MASK
1310 #define RT5640_EQ_CD_SFT
1311 #define RT5640_EQ_CD_DIS
1312 #define RT5640_EQ_CD_EN
1313 #define RT5640_EQ_DITH_MASK
1314 #define RT5640_EQ_DITH_SFT
1315 #define RT5640_EQ_DITH_NOR
1316 #define RT5640_EQ_DITH_LSB
1317 #define RT5640_EQ_DITH_LSB_1
1318 #define RT5640_EQ_DITH_LSB_2
1319
1320 /* EQ Control 2 (0xb1) */
1321 #define RT5640_EQ_HPF1_M_MASK
1322 #define RT5640_EQ_HPF1_M_SFT
1323 #define RT5640_EQ_HPF1_M_HI
1324 #define RT5640_EQ_HPF1_M_1ST
1325 #define RT5640_EQ_LPF1_M_MASK
1326 #define RT5640_EQ_LPF1_M_SFT
1327 #define RT5640_EQ_LPF1_M_LO
1328 #define RT5640_EQ_LPF1_M_1ST
1329 #define RT5640_EQ_HPF2_MASK
1330 #define RT5640_EQ_HPF2_SFT
1331 #define RT5640_EQ_HPF2_DIS
1332 #define RT5640_EQ_HPF2_EN
1333 #define RT5640_EQ_HPF1_MASK
1334 #define RT5640_EQ_HPF1_SFT
1335 #define RT5640_EQ_HPF1_DIS
1336 #define RT5640_EQ_HPF1_EN
1337 #define RT5640_EQ_BPF4_MASK
1338 #define RT5640_EQ_BPF4_SFT
1339 #define RT5640_EQ_BPF4_DIS
1340 #define RT5640_EQ_BPF4_EN
1341 #define RT5640_EQ_BPF3_MASK
1342 #define RT5640_EQ_BPF3_SFT
1343 #define RT5640_EQ_BPF3_DIS
1344 #define RT5640_EQ_BPF3_EN
1345 #define RT5640_EQ_BPF2_MASK
1346 #define RT5640_EQ_BPF2_SFT
1347 #define RT5640_EQ_BPF2_DIS
1348 #define RT5640_EQ_BPF2_EN
1349 #define RT5640_EQ_BPF1_MASK
1350 #define RT5640_EQ_BPF1_SFT
1351 #define RT5640_EQ_BPF1_DIS
1352 #define RT5640_EQ_BPF1_EN
1353 #define RT5640_EQ_LPF_MASK
1354 #define RT5640_EQ_LPF_SFT
1355 #define RT5640_EQ_LPF_DIS
1356 #define RT5640_EQ_LPF_EN
1357
1358 /* Memory Test (0xb2) */
1359 #define RT5640_MT_MASK
1360 #define RT5640_MT_SFT
1361 #define RT5640_MT_DIS
1362 #define RT5640_MT_EN
1363
1364 /* DRC/AGC Control 1 (0xb4) */
1365 #define RT5640_DRC_AGC_P_MASK
1366 #define RT5640_DRC_AGC_P_SFT
1367 #define RT5640_DRC_AGC_P_DAC
1368 #define RT5640_DRC_AGC_P_ADC
1369 #define RT5640_DRC_AGC_MASK
1370 #define RT5640_DRC_AGC_SFT
1371 #define RT5640_DRC_AGC_DIS
1372 #define RT5640_DRC_AGC_EN
1373 #define RT5640_DRC_AGC_UPD
1374 #define RT5640_DRC_AGC_UPD_BIT
1375 #define RT5640_DRC_AGC_AR_MASK
1376 #define RT5640_DRC_AGC_AR_SFT
1377 #define RT5640_DRC_AGC_R_MASK
1378 #define RT5640_DRC_AGC_R_SFT
1379 #define RT5640_DRC_AGC_R_48K
1380 #define RT5640_DRC_AGC_R_96K
1381 #define RT5640_DRC_AGC_R_192K
1382 #define RT5640_DRC_AGC_R_441K
1383 #define RT5640_DRC_AGC_R_882K
1384 #define RT5640_DRC_AGC_R_1764K
1385 #define RT5640_DRC_AGC_RC_MASK
1386 #define RT5640_DRC_AGC_RC_SFT
1387
1388 /* DRC/AGC Control 2 (0xb5) */
1389 #define RT5640_DRC_AGC_POB_MASK
1390 #define RT5640_DRC_AGC_POB_SFT
1391 #define RT5640_DRC_AGC_CP_MASK
1392 #define RT5640_DRC_AGC_CP_SFT
1393 #define RT5640_DRC_AGC_CP_DIS
1394 #define RT5640_DRC_AGC_CP_EN
1395 #define RT5640_DRC_AGC_CPR_MASK
1396 #define RT5640_DRC_AGC_CPR_SFT
1397 #define RT5640_DRC_AGC_CPR_1_1
1398 #define RT5640_DRC_AGC_CPR_1_2
1399 #define RT5640_DRC_AGC_CPR_1_3
1400 #define RT5640_DRC_AGC_CPR_1_4
1401 #define RT5640_DRC_AGC_PRB_MASK
1402 #define RT5640_DRC_AGC_PRB_SFT
1403
1404 /* DRC/AGC Control 3 (0xb6) */
1405 #define RT5640_DRC_AGC_NGB_MASK
1406 #define RT5640_DRC_AGC_NGB_SFT
1407 #define RT5640_DRC_AGC_TAR_MASK
1408 #define RT5640_DRC_AGC_TAR_SFT
1409 #define RT5640_DRC_AGC_NG_MASK
1410 #define RT5640_DRC_AGC_NG_SFT
1411 #define RT5640_DRC_AGC_NG_DIS
1412 #define RT5640_DRC_AGC_NG_EN
1413 #define RT5640_DRC_AGC_NGH_MASK
1414 #define RT5640_DRC_AGC_NGH_SFT
1415 #define RT5640_DRC_AGC_NGH_DIS
1416 #define RT5640_DRC_AGC_NGH_EN
1417 #define RT5640_DRC_AGC_NGT_MASK
1418 #define RT5640_DRC_AGC_NGT_SFT
1419
1420 /* ANC Control 1 (0xb8) */
1421 #define RT5640_ANC_M_MASK
1422 #define RT5640_ANC_M_SFT
1423 #define RT5640_ANC_M_NOR
1424 #define RT5640_ANC_M_REV
1425 #define RT5640_ANC_MASK
1426 #define RT5640_ANC_SFT
1427 #define RT5640_ANC_DIS
1428 #define RT5640_ANC_EN
1429 #define RT5640_ANC_MD_MASK
1430 #define RT5640_ANC_MD_SFT
1431 #define RT5640_ANC_MD_DIS
1432 #define RT5640_ANC_MD_67MS
1433 #define RT5640_ANC_MD_267MS
1434 #define RT5640_ANC_MD_1067MS
1435 #define RT5640_ANC_SN_MASK
1436 #define RT5640_ANC_SN_SFT
1437 #define RT5640_ANC_SN_DIS
1438 #define RT5640_ANC_SN_EN
1439 #define RT5640_ANC_CLK_MASK
1440 #define RT5640_ANC_CLK_SFT
1441 #define RT5640_ANC_CLK_ANC
1442 #define RT5640_ANC_CLK_REG
1443 #define RT5640_ANC_ZCD_MASK
1444 #define RT5640_ANC_ZCD_SFT
1445 #define RT5640_ANC_ZCD_DIS
1446 #define RT5640_ANC_ZCD_T1
1447 #define RT5640_ANC_ZCD_T2
1448 #define RT5640_ANC_ZCD_WT
1449 #define RT5640_ANC_CS_MASK
1450 #define RT5640_ANC_CS_SFT
1451 #define RT5640_ANC_CS_DIS
1452 #define RT5640_ANC_CS_EN
1453 #define RT5640_ANC_SW_MASK
1454 #define RT5640_ANC_SW_SFT
1455 #define RT5640_ANC_SW_NOR
1456 #define RT5640_ANC_SW_AUTO
1457 #define RT5640_ANC_CO_L_MASK
1458 #define RT5640_ANC_CO_L_SFT
1459
1460 /* ANC Control 2 (0xb6) */
1461 #define RT5640_ANC_FG_R_MASK
1462 #define RT5640_ANC_FG_R_SFT
1463 #define RT5640_ANC_FG_L_MASK
1464 #define RT5640_ANC_FG_L_SFT
1465 #define RT5640_ANC_CG_R_MASK
1466 #define RT5640_ANC_CG_R_SFT
1467 #define RT5640_ANC_CG_L_MASK
1468 #define RT5640_ANC_CG_L_SFT
1469
1470 /* ANC Control 3 (0xb6) */
1471 #define RT5640_ANC_CD_MASK
1472 #define RT5640_ANC_CD_SFT
1473 #define RT5640_ANC_CD_BOTH
1474 #define RT5640_ANC_CD_IND
1475 #define RT5640_ANC_CO_R_MASK
1476 #define RT5640_ANC_CO_R_SFT
1477
1478 /* Jack Detect Control (0xbb) */
1479 #define RT5640_JD_MASK
1480 #define RT5640_JD_SFT
1481 #define RT5640_JD_DIS
1482 #define RT5640_JD_GPIO1
1483 #define RT5640_JD_JD1_IN4P
1484 #define RT5640_JD_JD2_IN4N
1485 #define RT5640_JD_GPIO2
1486 #define RT5640_JD_GPIO3
1487 #define RT5640_JD_GPIO4
1488 #define RT5640_JD_HP_MASK
1489 #define RT5640_JD_HP_SFT
1490 #define RT5640_JD_HP_DIS
1491 #define RT5640_JD_HP_EN
1492 #define RT5640_JD_HP_TRG_MASK
1493 #define RT5640_JD_HP_TRG_SFT
1494 #define RT5640_JD_HP_TRG_LO
1495 #define RT5640_JD_HP_TRG_HI
1496 #define RT5640_JD_SPL_MASK
1497 #define RT5640_JD_SPL_SFT
1498 #define RT5640_JD_SPL_DIS
1499 #define RT5640_JD_SPL_EN
1500 #define RT5640_JD_SPL_TRG_MASK
1501 #define RT5640_JD_SPL_TRG_SFT
1502 #define RT5640_JD_SPL_TRG_LO
1503 #define RT5640_JD_SPL_TRG_HI
1504 #define RT5640_JD_SPR_MASK
1505 #define RT5640_JD_SPR_SFT
1506 #define RT5640_JD_SPR_DIS
1507 #define RT5640_JD_SPR_EN
1508 #define RT5640_JD_SPR_TRG_MASK
1509 #define RT5640_JD_SPR_TRG_SFT
1510 #define RT5640_JD_SPR_TRG_LO
1511 #define RT5640_JD_SPR_TRG_HI
1512 #define RT5640_JD_MO_MASK
1513 #define RT5640_JD_MO_SFT
1514 #define RT5640_JD_MO_DIS
1515 #define RT5640_JD_MO_EN
1516 #define RT5640_JD_MO_TRG_MASK
1517 #define RT5640_JD_MO_TRG_SFT
1518 #define RT5640_JD_MO_TRG_LO
1519 #define RT5640_JD_MO_TRG_HI
1520 #define RT5640_JD_LO_MASK
1521 #define RT5640_JD_LO_SFT
1522 #define RT5640_JD_LO_DIS
1523 #define RT5640_JD_LO_EN
1524 #define RT5640_JD_LO_TRG_MASK
1525 #define RT5640_JD_LO_TRG_SFT
1526 #define RT5640_JD_LO_TRG_LO
1527 #define RT5640_JD_LO_TRG_HI
1528 #define RT5640_JD1_IN4P_MASK
1529 #define RT5640_JD1_IN4P_SFT
1530 #define RT5640_JD1_IN4P_DIS
1531 #define RT5640_JD1_IN4P_EN
1532 #define RT5640_JD2_IN4N_MASK
1533 #define RT5640_JD2_IN4N_SFT
1534 #define RT5640_JD2_IN4N_DIS
1535 #define RT5640_JD2_IN4N_EN
1536
1537 /* Jack detect for ANC (0xbc) */
1538 #define RT5640_ANC_DET_MASK
1539 #define RT5640_ANC_DET_SFT
1540 #define RT5640_ANC_DET_DIS
1541 #define RT5640_ANC_DET_MB1
1542 #define RT5640_ANC_DET_MB2
1543 #define RT5640_ANC_DET_JD
1544 #define RT5640_AD_TRG_MASK
1545 #define RT5640_AD_TRG_SFT
1546 #define RT5640_AD_TRG_LO
1547 #define RT5640_AD_TRG_HI
1548 #define RT5640_ANCM_DET_MASK
1549 #define RT5640_ANCM_DET_SFT
1550 #define RT5640_ANCM_DET_DIS
1551 #define RT5640_ANCM_DET_MB1
1552 #define RT5640_ANCM_DET_MB2
1553 #define RT5640_ANCM_DET_JD
1554 #define RT5640_AMD_TRG_MASK
1555 #define RT5640_AMD_TRG_SFT
1556 #define RT5640_AMD_TRG_LO
1557 #define RT5640_AMD_TRG_HI
1558
1559 /* IRQ Control 1 (0xbd) */
1560 #define RT5640_IRQ_JD_MASK
1561 #define RT5640_IRQ_JD_SFT
1562 #define RT5640_IRQ_JD_BP
1563 #define RT5640_IRQ_JD_NOR
1564 #define RT5640_IRQ_OT_MASK
1565 #define RT5640_IRQ_OT_SFT
1566 #define RT5640_IRQ_OT_BP
1567 #define RT5640_IRQ_OT_NOR
1568 #define RT5640_JD_STKY_MASK
1569 #define RT5640_JD_STKY_SFT
1570 #define RT5640_JD_STKY_DIS
1571 #define RT5640_JD_STKY_EN
1572 #define RT5640_OT_STKY_MASK
1573 #define RT5640_OT_STKY_SFT
1574 #define RT5640_OT_STKY_DIS
1575 #define RT5640_OT_STKY_EN
1576 #define RT5640_JD_P_MASK
1577 #define RT5640_JD_P_SFT
1578 #define RT5640_JD_P_NOR
1579 #define RT5640_JD_P_INV
1580 #define RT5640_OT_P_MASK
1581 #define RT5640_OT_P_SFT
1582 #define RT5640_OT_P_NOR
1583 #define RT5640_OT_P_INV
1584
1585 /* IRQ Control 2 (0xbe) */
1586 #define RT5640_IRQ_MB1_OC_MASK
1587 #define RT5640_IRQ_MB1_OC_SFT
1588 #define RT5640_IRQ_MB1_OC_BP
1589 #define RT5640_IRQ_MB1_OC_NOR
1590 #define RT5640_IRQ_MB2_OC_MASK
1591 #define RT5640_IRQ_MB2_OC_SFT
1592 #define RT5640_IRQ_MB2_OC_BP
1593 #define RT5640_IRQ_MB2_OC_NOR
1594 #define RT5640_MB1_OC_STKY_MASK
1595 #define RT5640_MB1_OC_STKY_SFT
1596 #define RT5640_MB1_OC_STKY_DIS
1597 #define RT5640_MB1_OC_STKY_EN
1598 #define RT5640_MB2_OC_STKY_MASK
1599 #define RT5640_MB2_OC_STKY_SFT
1600 #define RT5640_MB2_OC_STKY_DIS
1601 #define RT5640_MB2_OC_STKY_EN
1602 #define RT5640_MB1_OC_P_MASK
1603 #define RT5640_MB1_OC_P_SFT
1604 #define RT5640_MB1_OC_P_NOR
1605 #define RT5640_MB1_OC_P_INV
1606 #define RT5640_MB2_OC_P_MASK
1607 #define RT5640_MB2_OC_P_SFT
1608 #define RT5640_MB2_OC_P_NOR
1609 #define RT5640_MB2_OC_P_INV
1610 #define RT5640_MB1_OC_STATUS
1611 #define RT5640_MB1_OC_STATUS_SFT
1612 #define RT5640_MB2_OC_STATUS
1613 #define RT5640_MB2_OC_STATUS_SFT
1614
1615 /* GPIO and Internal Status (0xbf) */
1616 #define RT5640_GPIO1_STATUS
1617 #define RT5640_GPIO2_STATUS
1618 #define RT5640_JD_STATUS
1619 #define RT5640_OVT_STATUS
1620 #define RT5640_CLS_D_OVCD_STATUS
1621
1622 /* GPIO Control 1 (0xc0) */
1623 #define RT5640_GP1_PIN_MASK
1624 #define RT5640_GP1_PIN_SFT
1625 #define RT5640_GP1_PIN_GPIO1
1626 #define RT5640_GP1_PIN_IRQ
1627 #define RT5640_GP2_PIN_MASK
1628 #define RT5640_GP2_PIN_SFT
1629 #define RT5640_GP2_PIN_GPIO2
1630 #define RT5640_GP2_PIN_DMIC1_SCL
1631 #define RT5640_GP3_PIN_MASK
1632 #define RT5640_GP3_PIN_SFT
1633 #define RT5640_GP3_PIN_GPIO3
1634 #define RT5640_GP3_PIN_DMIC1_SDA
1635 #define RT5640_GP3_PIN_IRQ
1636 #define RT5640_GP4_PIN_MASK
1637 #define RT5640_GP4_PIN_SFT
1638 #define RT5640_GP4_PIN_GPIO4
1639 #define RT5640_GP4_PIN_DMIC2_SDA
1640 #define RT5640_DP_SIG_MASK
1641 #define RT5640_DP_SIG_SFT
1642 #define RT5640_DP_SIG_TEST
1643 #define RT5640_DP_SIG_AP
1644 #define RT5640_GPIO_M_MASK
1645 #define RT5640_GPIO_M_SFT
1646 #define RT5640_GPIO_M_FLT
1647 #define RT5640_GPIO_M_PH
1648
1649 /* GPIO Control 3 (0xc2) */
1650 #define RT5640_GP4_PF_MASK
1651 #define RT5640_GP4_PF_SFT
1652 #define RT5640_GP4_PF_IN
1653 #define RT5640_GP4_PF_OUT
1654 #define RT5640_GP4_OUT_MASK
1655 #define RT5640_GP4_OUT_SFT
1656 #define RT5640_GP4_OUT_LO
1657 #define RT5640_GP4_OUT_HI
1658 #define RT5640_GP4_P_MASK
1659 #define RT5640_GP4_P_SFT
1660 #define RT5640_GP4_P_NOR
1661 #define RT5640_GP4_P_INV
1662 #define RT5640_GP3_PF_MASK
1663 #define RT5640_GP3_PF_SFT
1664 #define RT5640_GP3_PF_IN
1665 #define RT5640_GP3_PF_OUT
1666 #define RT5640_GP3_OUT_MASK
1667 #define RT5640_GP3_OUT_SFT
1668 #define RT5640_GP3_OUT_LO
1669 #define RT5640_GP3_OUT_HI
1670 #define RT5640_GP3_P_MASK
1671 #define RT5640_GP3_P_SFT
1672 #define RT5640_GP3_P_NOR
1673 #define RT5640_GP3_P_INV
1674 #define RT5640_GP2_PF_MASK
1675 #define RT5640_GP2_PF_SFT
1676 #define RT5640_GP2_PF_IN
1677 #define RT5640_GP2_PF_OUT
1678 #define RT5640_GP2_OUT_MASK
1679 #define RT5640_GP2_OUT_SFT
1680 #define RT5640_GP2_OUT_LO
1681 #define RT5640_GP2_OUT_HI
1682 #define RT5640_GP2_P_MASK
1683 #define RT5640_GP2_P_SFT
1684 #define RT5640_GP2_P_NOR
1685 #define RT5640_GP2_P_INV
1686 #define RT5640_GP1_PF_MASK
1687 #define RT5640_GP1_PF_SFT
1688 #define RT5640_GP1_PF_IN
1689 #define RT5640_GP1_PF_OUT
1690 #define RT5640_GP1_OUT_MASK
1691 #define RT5640_GP1_OUT_SFT
1692 #define RT5640_GP1_OUT_LO
1693 #define RT5640_GP1_OUT_HI
1694 #define RT5640_GP1_P_MASK
1695 #define RT5640_GP1_P_SFT
1696 #define RT5640_GP1_P_NOR
1697 #define RT5640_GP1_P_INV
1698
1699 /* FM34-500 Register Control 1 (0xc4) */
1700 #define RT5640_DSP_ADD_SFT
1701
1702 /* FM34-500 Register Control 2 (0xc5) */
1703 #define RT5640_DSP_DAT_SFT
1704
1705 /* FM34-500 Register Control 3 (0xc6) */
1706 #define RT5640_DSP_BUSY_MASK
1707 #define RT5640_DSP_BUSY_BIT
1708 #define RT5640_DSP_DS_MASK
1709 #define RT5640_DSP_DS_SFT
1710 #define RT5640_DSP_DS_FM3010
1711 #define RT5640_DSP_DS_TEMP
1712 #define RT5640_DSP_CLK_MASK
1713 #define RT5640_DSP_CLK_SFT
1714 #define RT5640_DSP_CLK_384K
1715 #define RT5640_DSP_CLK_192K
1716 #define RT5640_DSP_CLK_96K
1717 #define RT5640_DSP_CLK_64K
1718 #define RT5640_DSP_PD_PIN_MASK
1719 #define RT5640_DSP_PD_PIN_SFT
1720 #define RT5640_DSP_PD_PIN_LO
1721 #define RT5640_DSP_PD_PIN_HI
1722 #define RT5640_DSP_RST_PIN_MASK
1723 #define RT5640_DSP_RST_PIN_SFT
1724 #define RT5640_DSP_RST_PIN_LO
1725 #define RT5640_DSP_RST_PIN_HI
1726 #define RT5640_DSP_R_EN
1727 #define RT5640_DSP_R_EN_BIT
1728 #define RT5640_DSP_W_EN
1729 #define RT5640_DSP_W_EN_BIT
1730 #define RT5640_DSP_CMD_MASK
1731 #define RT5640_DSP_CMD_SFT
1732 #define RT5640_DSP_CMD_MW
1733 #define RT5640_DSP_CMD_MR
1734 #define RT5640_DSP_CMD_RR
1735 #define RT5640_DSP_CMD_RW
1736
1737 /* Programmable Register Array Control 1 (0xc
1738 #define RT5640_REG_SEQ_MASK
1739 #define RT5640_REG_SEQ_SFT
1740 #define RT5640_SEQ1_ST_MASK
1741 #define RT5640_SEQ1_ST_SFT
1742 #define RT5640_SEQ1_ST_RUN
1743 #define RT5640_SEQ1_ST_FIN
1744 #define RT5640_SEQ2_ST_MASK
1745 #define RT5640_SEQ2_ST_SFT
1746 #define RT5640_SEQ2_ST_RUN
1747 #define RT5640_SEQ2_ST_FIN
1748 #define RT5640_REG_LV_MASK
1749 #define RT5640_REG_LV_SFT
1750 #define RT5640_REG_LV_MX
1751 #define RT5640_REG_LV_PR
1752 #define RT5640_SEQ_2_PT_MASK
1753 #define RT5640_SEQ_2_PT_BIT
1754 #define RT5640_REG_IDX_MASK
1755 #define RT5640_REG_IDX_SFT
1756
1757 /* Programmable Register Array Control 2 (0xc
1758 #define RT5640_REG_DAT_MASK
1759 #define RT5640_REG_DAT_SFT
1760
1761 /* Programmable Register Array Control 3 (0xc
1762 #define RT5640_SEQ_DLY_MASK
1763 #define RT5640_SEQ_DLY_SFT
1764 #define RT5640_PROG_MASK
1765 #define RT5640_PROG_SFT
1766 #define RT5640_PROG_DIS
1767 #define RT5640_PROG_EN
1768 #define RT5640_SEQ1_PT_RUN
1769 #define RT5640_SEQ1_PT_RUN_BIT
1770 #define RT5640_SEQ2_PT_RUN
1771 #define RT5640_SEQ2_PT_RUN_BIT
1772
1773 /* Programmable Register Array Control 4 (0xc
1774 #define RT5640_SEQ1_START_MASK
1775 #define RT5640_SEQ1_START_SFT
1776 #define RT5640_SEQ1_END_MASK
1777 #define RT5640_SEQ1_END_SFT
1778
1779 /* Programmable Register Array Control 5 (0xc
1780 #define RT5640_SEQ2_START_MASK
1781 #define RT5640_SEQ2_START_SFT
1782 #define RT5640_SEQ2_END_MASK
1783 #define RT5640_SEQ2_END_SFT
1784
1785 /* Scramble Function (0xcd) */
1786 #define RT5640_SCB_KEY_MASK
1787 #define RT5640_SCB_KEY_SFT
1788
1789 /* Scramble Control (0xce) */
1790 #define RT5640_SCB_SWAP_MASK
1791 #define RT5640_SCB_SWAP_SFT
1792 #define RT5640_SCB_SWAP_DIS
1793 #define RT5640_SCB_SWAP_EN
1794 #define RT5640_SCB_MASK
1795 #define RT5640_SCB_SFT
1796 #define RT5640_SCB_DIS
1797 #define RT5640_SCB_EN
1798
1799 /* Baseback Control (0xcf) */
1800 #define RT5640_BB_MASK
1801 #define RT5640_BB_SFT
1802 #define RT5640_BB_DIS
1803 #define RT5640_BB_EN
1804 #define RT5640_BB_CT_MASK
1805 #define RT5640_BB_CT_SFT
1806 #define RT5640_BB_CT_A
1807 #define RT5640_BB_CT_B
1808 #define RT5640_BB_CT_C
1809 #define RT5640_BB_CT_D
1810 #define RT5640_M_BB_L_MASK
1811 #define RT5640_M_BB_L_SFT
1812 #define RT5640_M_BB_R_MASK
1813 #define RT5640_M_BB_R_SFT
1814 #define RT5640_M_BB_HPF_L_MASK
1815 #define RT5640_M_BB_HPF_L_SFT
1816 #define RT5640_M_BB_HPF_R_MASK
1817 #define RT5640_M_BB_HPF_R_SFT
1818 #define RT5640_G_BB_BST_MASK
1819 #define RT5640_G_BB_BST_SFT
1820
1821 /* MP3 Plus Control 1 (0xd0) */
1822 #define RT5640_M_MP3_L_MASK
1823 #define RT5640_M_MP3_L_SFT
1824 #define RT5640_M_MP3_R_MASK
1825 #define RT5640_M_MP3_R_SFT
1826 #define RT5640_M_MP3_MASK
1827 #define RT5640_M_MP3_SFT
1828 #define RT5640_M_MP3_DIS
1829 #define RT5640_M_MP3_EN
1830 #define RT5640_EG_MP3_MASK
1831 #define RT5640_EG_MP3_SFT
1832 #define RT5640_MP3_HLP_MASK
1833 #define RT5640_MP3_HLP_SFT
1834 #define RT5640_MP3_HLP_DIS
1835 #define RT5640_MP3_HLP_EN
1836 #define RT5640_M_MP3_ORG_L_MASK
1837 #define RT5640_M_MP3_ORG_L_SFT
1838 #define RT5640_M_MP3_ORG_R_MASK
1839 #define RT5640_M_MP3_ORG_R_SFT
1840
1841 /* MP3 Plus Control 2 (0xd1) */
1842 #define RT5640_MP3_WT_MASK
1843 #define RT5640_MP3_WT_SFT
1844 #define RT5640_MP3_WT_1_4
1845 #define RT5640_MP3_WT_1_2
1846 #define RT5640_OG_MP3_MASK
1847 #define RT5640_OG_MP3_SFT
1848 #define RT5640_HG_MP3_MASK
1849 #define RT5640_HG_MP3_SFT
1850
1851 /* 3D HP Control 1 (0xd2) */
1852 #define RT5640_3D_CF_MASK
1853 #define RT5640_3D_CF_SFT
1854 #define RT5640_3D_CF_DIS
1855 #define RT5640_3D_CF_EN
1856 #define RT5640_3D_HP_MASK
1857 #define RT5640_3D_HP_SFT
1858 #define RT5640_3D_HP_DIS
1859 #define RT5640_3D_HP_EN
1860 #define RT5640_3D_BT_MASK
1861 #define RT5640_3D_BT_SFT
1862 #define RT5640_3D_BT_DIS
1863 #define RT5640_3D_BT_EN
1864 #define RT5640_3D_1F_MIX_MASK
1865 #define RT5640_3D_1F_MIX_SFT
1866 #define RT5640_3D_HP_M_MASK
1867 #define RT5640_3D_HP_M_SFT
1868 #define RT5640_3D_HP_M_SUR
1869 #define RT5640_3D_HP_M_FRO
1870 #define RT5640_M_3D_HRTF_MASK
1871 #define RT5640_M_3D_HRTF_SFT
1872 #define RT5640_M_3D_D2H_MASK
1873 #define RT5640_M_3D_D2H_SFT
1874 #define RT5640_M_3D_D2R_MASK
1875 #define RT5640_M_3D_D2R_SFT
1876 #define RT5640_M_3D_REVB_MASK
1877 #define RT5640_M_3D_REVB_SFT
1878
1879 /* Adjustable high pass filter control 1 (0xd
1880 #define RT5640_2ND_HPF_MASK
1881 #define RT5640_2ND_HPF_SFT
1882 #define RT5640_2ND_HPF_DIS
1883 #define RT5640_2ND_HPF_EN
1884 #define RT5640_HPF_CF_L_MASK
1885 #define RT5640_HPF_CF_L_SFT
1886 #define RT5640_1ST_HPF_MASK
1887 #define RT5640_1ST_HPF_SFT
1888 #define RT5640_1ST_HPF_DIS
1889 #define RT5640_1ST_HPF_EN
1890 #define RT5640_HPF_CF_R_MASK
1891 #define RT5640_HPF_CF_R_SFT
1892 #define RT5640_ZD_T_MASK
1893 #define RT5640_ZD_T_SFT
1894 #define RT5640_ZD_F_MASK
1895 #define RT5640_ZD_F_SFT
1896 #define RT5640_ZD_F_IM
1897 #define RT5640_ZD_F_ZC_IM
1898 #define RT5640_ZD_F_ZC_IOD
1899 #define RT5640_ZD_F_UN
1900
1901 /* HP calibration control and Amp detection (
1902 #define RT5640_SI_DAC_MASK
1903 #define RT5640_SI_DAC_SFT
1904 #define RT5640_SI_DAC_AUTO
1905 #define RT5640_SI_DAC_TEST
1906 #define RT5640_DC_CAL_M_MASK
1907 #define RT5640_DC_CAL_M_SFT
1908 #define RT5640_DC_CAL_M_CAL
1909 #define RT5640_DC_CAL_M_NOR
1910 #define RT5640_DC_CAL_MASK
1911 #define RT5640_DC_CAL_SFT
1912 #define RT5640_DC_CAL_DIS
1913 #define RT5640_DC_CAL_EN
1914 #define RT5640_HPD_RCV_MASK
1915 #define RT5640_HPD_RCV_SFT
1916 #define RT5640_HPD_PS_MASK
1917 #define RT5640_HPD_PS_SFT
1918 #define RT5640_HPD_PS_DIS
1919 #define RT5640_HPD_PS_EN
1920 #define RT5640_CAL_M_MASK
1921 #define RT5640_CAL_M_SFT
1922 #define RT5640_CAL_M_DEP
1923 #define RT5640_CAL_M_CAL
1924 #define RT5640_CAL_MASK
1925 #define RT5640_CAL_SFT
1926 #define RT5640_CAL_DIS
1927 #define RT5640_CAL_EN
1928 #define RT5640_CAL_TEST_MASK
1929 #define RT5640_CAL_TEST_SFT
1930 #define RT5640_CAL_TEST_DIS
1931 #define RT5640_CAL_TEST_EN
1932 #define RT5640_CAL_P_MASK
1933 #define RT5640_CAL_P_SFT
1934 #define RT5640_CAL_P_NONE
1935 #define RT5640_CAL_P_CAL
1936 #define RT5640_CAL_P_DAC_CAL
1937
1938 /* Soft volume and zero cross control 1 (0xd9
1939 #define RT5640_SV_MASK
1940 #define RT5640_SV_SFT
1941 #define RT5640_SV_DIS
1942 #define RT5640_SV_EN
1943 #define RT5640_SPO_SV_MASK
1944 #define RT5640_SPO_SV_SFT
1945 #define RT5640_SPO_SV_DIS
1946 #define RT5640_SPO_SV_EN
1947 #define RT5640_OUT_SV_MASK
1948 #define RT5640_OUT_SV_SFT
1949 #define RT5640_OUT_SV_DIS
1950 #define RT5640_OUT_SV_EN
1951 #define RT5640_HP_SV_MASK
1952 #define RT5640_HP_SV_SFT
1953 #define RT5640_HP_SV_DIS
1954 #define RT5640_HP_SV_EN
1955 #define RT5640_ZCD_DIG_MASK
1956 #define RT5640_ZCD_DIG_SFT
1957 #define RT5640_ZCD_DIG_DIS
1958 #define RT5640_ZCD_DIG_EN
1959 #define RT5640_ZCD_MASK
1960 #define RT5640_ZCD_SFT
1961 #define RT5640_ZCD_PD
1962 #define RT5640_ZCD_PU
1963 #define RT5640_M_ZCD_MASK
1964 #define RT5640_M_ZCD_SFT
1965 #define RT5640_M_ZCD_RM_L
1966 #define RT5640_M_ZCD_RM_R
1967 #define RT5640_M_ZCD_SM_L
1968 #define RT5640_M_ZCD_SM_R
1969 #define RT5640_M_ZCD_OM_L
1970 #define RT5640_M_ZCD_OM_R
1971 #define RT5640_SV_DLY_MASK
1972 #define RT5640_SV_DLY_SFT
1973
1974 /* Soft volume and zero cross control 2 (0xda
1975 #define RT5640_ZCD_HP_MASK
1976 #define RT5640_ZCD_HP_SFT
1977 #define RT5640_ZCD_HP_DIS
1978 #define RT5640_ZCD_HP_EN
1979
1980 /* General Control 1 (0xfa) */
1981 #define RT5640_EN_LOUT_DF
1982 #define RT5640_EN_LOUT_DF_SFT
1983 #define RT5640_M_MONO_ADC_L
1984 #define RT5640_M_MONO_ADC_L_SFT
1985 #define RT5640_M_MONO_ADC_R
1986 #define RT5640_M_MONO_ADC_R_SFT
1987 #define RT5640_MCLK_DET
1988
1989 /* General Control 1 (0xfb) */
1990 #define RT5640_IRQ_JD2_MASK
1991 #define RT5640_IRQ_JD2_SFT
1992 #define RT5640_IRQ_JD2_BP
1993 #define RT5640_IRQ_JD2_NOR
1994 #define RT5640_JD2_P_MASK
1995 #define RT5640_JD2_P_SFT
1996 #define RT5640_JD2_P_NOR
1997 #define RT5640_JD2_P_INV
1998 #define RT5640_JD2_MASK
1999 #define RT5640_JD2_SFT
2000 #define RT5640_JD2_DIS
2001 #define RT5640_JD2_EN
2002
2003 /* Codec Private Register definition */
2004
2005 /* MIC Over current threshold scale factor (0
2006 #define RT5640_MIC_OVCD_SF_MASK
2007 #define RT5640_MIC_OVCD_SF_SFT
2008 #define RT5640_MIC_OVCD_SF_0P5
2009 #define RT5640_MIC_OVCD_SF_0P75
2010 #define RT5640_MIC_OVCD_SF_1P0
2011 #define RT5640_MIC_OVCD_SF_1P5
2012
2013 /* 3D Speaker Control (0x63) */
2014 #define RT5640_3D_SPK_MASK
2015 #define RT5640_3D_SPK_SFT
2016 #define RT5640_3D_SPK_DIS
2017 #define RT5640_3D_SPK_EN
2018 #define RT5640_3D_SPK_M_MASK
2019 #define RT5640_3D_SPK_M_SFT
2020 #define RT5640_3D_SPK_CG_MASK
2021 #define RT5640_3D_SPK_CG_SFT
2022 #define RT5640_3D_SPK_SG_MASK
2023 #define RT5640_3D_SPK_SG_SFT
2024
2025 /* Wind Noise Detection Control 1 (0x6c) */
2026 #define RT5640_WND_MASK
2027 #define RT5640_WND_SFT
2028 #define RT5640_WND_DIS
2029 #define RT5640_WND_EN
2030
2031 /* Wind Noise Detection Control 2 (0x6d) */
2032 #define RT5640_WND_FC_NW_MASK
2033 #define RT5640_WND_FC_NW_SFT
2034 #define RT5640_WND_FC_WK_MASK
2035 #define RT5640_WND_FC_WK_SFT
2036
2037 /* Wind Noise Detection Control 3 (0x6e) */
2038 #define RT5640_HPF_FC_MASK
2039 #define RT5640_HPF_FC_SFT
2040 #define RT5640_WND_FC_ST_MASK
2041 #define RT5640_WND_FC_ST_SFT
2042
2043 /* Wind Noise Detection Control 4 (0x6f) */
2044 #define RT5640_WND_TH_LO_MASK
2045 #define RT5640_WND_TH_LO_SFT
2046
2047 /* Wind Noise Detection Control 5 (0x70) */
2048 #define RT5640_WND_TH_HI_MASK
2049 #define RT5640_WND_TH_HI_SFT
2050
2051 /* Wind Noise Detection Control 8 (0x73) */
2052 #define RT5640_WND_WIND_MASK
2053 #define RT5640_WND_WIND_SFT
2054 #define RT5640_WND_STRONG_MASK
2055 #define RT5640_WND_STRONG_SFT
2056 enum {
2057 RT5640_NO_WIND,
2058 RT5640_BREEZE,
2059 RT5640_STORM,
2060 };
2061
2062 /* Dipole Speaker Interface (0x75) */
2063 #define RT5640_DP_ATT_MASK
2064 #define RT5640_DP_ATT_SFT
2065 #define RT5640_DP_SPK_MASK
2066 #define RT5640_DP_SPK_SFT
2067 #define RT5640_DP_SPK_DIS
2068 #define RT5640_DP_SPK_EN
2069
2070 /* EQ Pre Volume Control (0xb3) */
2071 #define RT5640_EQ_PRE_VOL_MASK
2072 #define RT5640_EQ_PRE_VOL_SFT
2073
2074 /* EQ Post Volume Control (0xb4) */
2075 #define RT5640_EQ_PST_VOL_MASK
2076 #define RT5640_EQ_PST_VOL_SFT
2077
2078 #define RT5640_NO_JACK BIT(0)
2079 #define RT5640_HEADSET_DET BIT(1)
2080 #define RT5640_HEADPHO_DET BIT(2)
2081
2082 /* System Clock Source */
2083 #define RT5640_SCLK_S_MCLK 0
2084 #define RT5640_SCLK_S_PLL1 1
2085 #define RT5640_SCLK_S_PLL1_TK 2
2086 #define RT5640_SCLK_S_RCCLK 3
2087
2088 /* PLL1 Source */
2089 #define RT5640_PLL1_S_MCLK 0
2090 #define RT5640_PLL1_S_BCLK1 1
2091 #define RT5640_PLL1_S_BCLK2 2
2092 #define RT5640_PLL1_S_BCLK3 3
2093
2094
2095 enum {
2096 RT5640_AIF1,
2097 RT5640_AIF2,
2098 RT5640_AIF3,
2099 RT5640_AIFS,
2100 };
2101
2102 enum {
2103 RT5640_U_IF1 = 0x1,
2104 RT5640_U_IF2 = 0x2,
2105 RT5640_U_IF3 = 0x4,
2106 };
2107
2108 enum {
2109 RT5640_IF_123,
2110 RT5640_IF_132,
2111 RT5640_IF_312,
2112 RT5640_IF_321,
2113 RT5640_IF_231,
2114 RT5640_IF_213,
2115 RT5640_IF_113,
2116 RT5640_IF_223,
2117 RT5640_IF_ALL,
2118 };
2119
2120 enum {
2121 RT5640_DMIC_DIS,
2122 RT5640_DMIC1,
2123 RT5640_DMIC2,
2124 };
2125
2126 /* filter mask */
2127 enum {
2128 RT5640_DA_STEREO_FILTER = 0x1,
2129 RT5640_DA_MONO_L_FILTER = (0x1 << 1),
2130 RT5640_DA_MONO_R_FILTER = (0x1 << 2),
2131 RT5640_AD_STEREO_FILTER = (0x1 << 3),
2132 RT5640_AD_MONO_L_FILTER = (0x1 << 4),
2133 RT5640_AD_MONO_R_FILTER = (0x1 << 5),
2134 };
2135
2136 struct rt5640_priv {
2137 struct snd_soc_component *component;
2138 struct regmap *regmap;
2139 struct clk *mclk;
2140
2141 struct gpio_desc *ldo1_en; /* GPIO fo
2142 int irq;
2143 int jd_gpio_irq;
2144 int sysclk;
2145 int sysclk_src;
2146 int lrck[RT5640_AIFS];
2147 int bclk[RT5640_AIFS];
2148 int master[RT5640_AIFS];
2149
2150 int pll_src;
2151 int pll_in;
2152 int pll_out;
2153
2154 bool hp_mute;
2155 bool asrc_en;
2156 bool irq_requested;
2157 bool jd_gpio_irq_requested;
2158
2159 /* Jack and button detect data */
2160 bool ovcd_irq_enabled;
2161 bool pressed;
2162 bool press_reported;
2163 int press_count;
2164 int release_count;
2165 int poll_count;
2166 struct delayed_work bp_work;
2167 struct delayed_work jack_work;
2168 struct snd_soc_jack *jack;
2169 struct gpio_desc *jd_gpio;
2170 unsigned int jd_src;
2171 bool jd_inverted;
2172 unsigned int ovcd_th;
2173 unsigned int ovcd_sf;
2174 bool use_platform_clock;
2175 };
2176
2177 struct rt5640_set_jack_data {
2178 int codec_irq_override;
2179 struct gpio_desc *jd_gpio;
2180 bool use_platform_clock;
2181 };
2182
2183 int rt5640_dmic_enable(struct snd_soc_compone
2184 bool dmic1_data_pin, b
2185 int rt5640_sel_asrc_clk_src(struct snd_soc_co
2186 unsigned int filter_mask, uns
2187
2188 void rt5640_set_ovcd_params(struct snd_soc_co
2189 void rt5640_enable_micbias1_for_ovcd(struct s
2190 void rt5640_disable_micbias1_for_ovcd(struct
2191 int rt5640_detect_headset(struct snd_soc_comp
2192
2193 #endif
2194
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