1 /* SPDX-License-Identifier: GPL-2.0-only */ 1
2 /*
3 * rt5659.h -- RT5659/RT5658 ALSA SoC audio
4 *
5 * Copyright 2015 Realtek Microelectronics
6 * Author: Bard Liao <bardliao@realtek.com>
7 */
8
9 #ifndef __RT5659_H__
10 #define __RT5659_H__
11
12 #include <sound/rt5659.h>
13
14 #define DEVICE_ID 0x6311
15
16 /* Info */
17 #define RT5659_RESET
18 #define RT5659_VENDOR_ID
19 #define RT5659_VENDOR_ID_1
20 #define RT5659_DEVICE_ID
21 /* I/O - Output */
22 #define RT5659_SPO_VOL
23 #define RT5659_HP_VOL
24 #define RT5659_LOUT
25 #define RT5659_MONO_OUT
26 #define RT5659_HPL_GAIN
27 #define RT5659_HPR_GAIN
28 #define RT5659_MONO_GAIN
29 #define RT5659_SPDIF_CTRL_1
30 #define RT5659_SPDIF_CTRL_2
31 /* I/O - Input */
32 #define RT5659_CAL_BST_CTRL
33 #define RT5659_IN1_IN2
34 #define RT5659_IN3_IN4
35 #define RT5659_INL1_INR1_VOL
36 /* I/O - Speaker */
37 #define RT5659_EJD_CTRL_1
38 #define RT5659_EJD_CTRL_2
39 #define RT5659_EJD_CTRL_3
40 #define RT5659_SILENCE_CTRL
41 #define RT5659_PSV_CTRL
42 /* I/O - Sidetone */
43 #define RT5659_SIDETONE_CTRL
44 /* I/O - ADC/DAC/DMIC */
45 #define RT5659_DAC1_DIG_VOL
46 #define RT5659_DAC2_DIG_VOL
47 #define RT5659_DAC_CTRL
48 #define RT5659_STO1_ADC_DIG_VOL
49 #define RT5659_MONO_ADC_DIG_VOL
50 #define RT5659_STO2_ADC_DIG_VOL
51 #define RT5659_STO1_BOOST
52 #define RT5659_MONO_BOOST
53 #define RT5659_STO2_BOOST
54 #define RT5659_HP_IMP_GAIN_1
55 #define RT5659_HP_IMP_GAIN_2
56 /* Mixer - D-D */
57 #define RT5659_STO1_ADC_MIXER
58 #define RT5659_MONO_ADC_MIXER
59 #define RT5659_AD_DA_MIXER
60 #define RT5659_STO_DAC_MIXER
61 #define RT5659_MONO_DAC_MIXER
62 #define RT5659_DIG_MIXER
63 #define RT5659_A_DAC_MUX
64 #define RT5659_DIG_INF23_DATA
65 /* Mixer - PDM */
66 #define RT5659_PDM_OUT_CTRL
67 #define RT5659_PDM_DATA_CTRL_1
68 #define RT5659_PDM_DATA_CTRL_2
69 #define RT5659_PDM_DATA_CTRL_3
70 #define RT5659_PDM_DATA_CTRL_4
71 #define RT5659_SPDIF_CTRL
72
73 /* Mixer - ADC */
74 #define RT5659_REC1_GAIN
75 #define RT5659_REC1_L1_MIXER
76 #define RT5659_REC1_L2_MIXER
77 #define RT5659_REC1_R1_MIXER
78 #define RT5659_REC1_R2_MIXER
79 #define RT5659_CAL_REC
80 #define RT5659_REC2_L1_MIXER
81 #define RT5659_REC2_L2_MIXER
82 #define RT5659_REC2_R1_MIXER
83 #define RT5659_REC2_R2_MIXER
84 #define RT5659_RC_CLK_CTRL
85 /* Mixer - DAC */
86 #define RT5659_SPK_L_MIXER
87 #define RT5659_SPK_R_MIXER
88 #define RT5659_SPO_AMP_GAIN
89 #define RT5659_ALC_BACK_GAIN
90 #define RT5659_MONOMIX_GAIN
91 #define RT5659_MONOMIX_IN_GAIN
92 #define RT5659_OUT_L_GAIN
93 #define RT5659_OUT_L_MIXER
94 #define RT5659_OUT_R_GAIN
95 #define RT5659_OUT_R_MIXER
96 #define RT5659_LOUT_MIXER
97
98 #define RT5659_HAPTIC_GEN_CTRL_1
99 #define RT5659_HAPTIC_GEN_CTRL_2
100 #define RT5659_HAPTIC_GEN_CTRL_3
101 #define RT5659_HAPTIC_GEN_CTRL_4
102 #define RT5659_HAPTIC_GEN_CTRL_5
103 #define RT5659_HAPTIC_GEN_CTRL_6
104 #define RT5659_HAPTIC_GEN_CTRL_7
105 #define RT5659_HAPTIC_GEN_CTRL_8
106 #define RT5659_HAPTIC_GEN_CTRL_9
107 #define RT5659_HAPTIC_GEN_CTRL_10
108 #define RT5659_HAPTIC_GEN_CTRL_11
109 #define RT5659_HAPTIC_LPF_CTRL_1
110 #define RT5659_HAPTIC_LPF_CTRL_2
111 #define RT5659_HAPTIC_LPF_CTRL_3
112 /* Power */
113 #define RT5659_PWR_DIG_1
114 #define RT5659_PWR_DIG_2
115 #define RT5659_PWR_ANLG_1
116 #define RT5659_PWR_ANLG_2
117 #define RT5659_PWR_ANLG_3
118 #define RT5659_PWR_MIXER
119 #define RT5659_PWR_VOL
120 /* Private Register Control */
121 #define RT5659_PRIV_INDEX
122 #define RT5659_CLK_DET
123 #define RT5659_PRIV_DATA
124 /* System Clock Pre Divider Gating Control */
125 #define RT5659_PRE_DIV_1
126 #define RT5659_PRE_DIV_2
127 /* Format - ADC/DAC */
128 #define RT5659_I2S1_SDP
129 #define RT5659_I2S2_SDP
130 #define RT5659_I2S3_SDP
131 #define RT5659_ADDA_CLK_1
132 #define RT5659_ADDA_CLK_2
133 #define RT5659_DMIC_CTRL_1
134 #define RT5659_DMIC_CTRL_2
135 /* Format - TDM Control */
136 #define RT5659_TDM_CTRL_1
137 #define RT5659_TDM_CTRL_2
138 #define RT5659_TDM_CTRL_3
139 #define RT5659_TDM_CTRL_4
140 #define RT5659_TDM_CTRL_5
141
142 /* Function - Analog */
143 #define RT5659_GLB_CLK
144 #define RT5659_PLL_CTRL_1
145 #define RT5659_PLL_CTRL_2
146 #define RT5659_ASRC_1
147 #define RT5659_ASRC_2
148 #define RT5659_ASRC_3
149 #define RT5659_ASRC_4
150 #define RT5659_ASRC_5
151 #define RT5659_ASRC_6
152 #define RT5659_ASRC_7
153 #define RT5659_ASRC_8
154 #define RT5659_ASRC_9
155 #define RT5659_ASRC_10
156 #define RT5659_DEPOP_1
157 #define RT5659_DEPOP_2
158 #define RT5659_DEPOP_3
159 #define RT5659_HP_CHARGE_PUMP_1
160 #define RT5659_HP_CHARGE_PUMP_2
161 #define RT5659_MICBIAS_1
162 #define RT5659_MICBIAS_2
163 #define RT5659_ASRC_11
164 #define RT5659_ASRC_12
165 #define RT5659_ASRC_13
166 #define RT5659_REC_M1_M2_GAIN_CTRL
167 #define RT5659_CLASSD_CTRL_1
168 #define RT5659_CLASSD_CTRL_2
169
170 /* Function - Digital */
171 #define RT5659_ADC_EQ_CTRL_1
172 #define RT5659_ADC_EQ_CTRL_2
173 #define RT5659_DAC_EQ_CTRL_1
174 #define RT5659_DAC_EQ_CTRL_2
175 #define RT5659_DAC_EQ_CTRL_3
176
177 #define RT5659_IRQ_CTRL_1
178 #define RT5659_IRQ_CTRL_2
179 #define RT5659_IRQ_CTRL_3
180 #define RT5659_IRQ_CTRL_4
181 #define RT5659_IRQ_CTRL_5
182 #define RT5659_IRQ_CTRL_6
183 #define RT5659_INT_ST_1
184 #define RT5659_INT_ST_2
185 #define RT5659_GPIO_CTRL_1
186 #define RT5659_GPIO_CTRL_2
187 #define RT5659_GPIO_CTRL_3
188 #define RT5659_GPIO_CTRL_4
189 #define RT5659_GPIO_CTRL_5
190 #define RT5659_GPIO_STA
191 #define RT5659_SINE_GEN_CTRL_1
192 #define RT5659_SINE_GEN_CTRL_2
193 #define RT5659_SINE_GEN_CTRL_3
194 #define RT5659_HP_AMP_DET_CTRL_1
195 #define RT5659_HP_AMP_DET_CTRL_2
196 #define RT5659_SV_ZCD_1
197 #define RT5659_SV_ZCD_2
198 #define RT5659_IL_CMD_1
199 #define RT5659_IL_CMD_2
200 #define RT5659_IL_CMD_3
201 #define RT5659_IL_CMD_4
202 #define RT5659_4BTN_IL_CMD_1
203 #define RT5659_4BTN_IL_CMD_2
204 #define RT5659_4BTN_IL_CMD_3
205 #define RT5659_PSV_IL_CMD_1
206 #define RT5659_PSV_IL_CMD_2
207
208 #define RT5659_ADC_STO1_HP_CTRL_1
209 #define RT5659_ADC_STO1_HP_CTRL_2
210 #define RT5659_ADC_MONO_HP_CTRL_1
211 #define RT5659_ADC_MONO_HP_CTRL_2
212 #define RT5659_AJD1_CTRL
213 #define RT5659_AJD2_AJD3_CTRL
214 #define RT5659_JD1_THD
215 #define RT5659_JD2_THD
216 #define RT5659_JD3_THD
217 #define RT5659_JD_CTRL_1
218 #define RT5659_JD_CTRL_2
219 #define RT5659_JD_CTRL_3
220 #define RT5659_JD_CTRL_4
221 /* General Control */
222 #define RT5659_DIG_MISC
223 #define RT5659_DUMMY_2
224 #define RT5659_DUMMY_3
225
226 #define RT5659_DAC_ADC_DIG_VOL
227 #define RT5659_BIAS_CUR_CTRL_1
228 #define RT5659_BIAS_CUR_CTRL_2
229 #define RT5659_BIAS_CUR_CTRL_3
230 #define RT5659_BIAS_CUR_CTRL_4
231 #define RT5659_BIAS_CUR_CTRL_5
232 #define RT5659_BIAS_CUR_CTRL_6
233 #define RT5659_BIAS_CUR_CTRL_7
234 #define RT5659_BIAS_CUR_CTRL_8
235 #define RT5659_BIAS_CUR_CTRL_9
236 #define RT5659_BIAS_CUR_CTRL_10
237 #define RT5659_MEMORY_TEST
238 #define RT5659_VREF_REC_OP_FB_CAP_CTRL
239 #define RT5659_CLASSD_0
240 #define RT5659_CLASSD_1
241 #define RT5659_CLASSD_2
242 #define RT5659_CLASSD_3
243 #define RT5659_CLASSD_4
244 #define RT5659_CLASSD_5
245 #define RT5659_CLASSD_6
246 #define RT5659_CLASSD_7
247 #define RT5659_CLASSD_8
248 #define RT5659_CLASSD_9
249 #define RT5659_CLASSD_10
250 #define RT5659_CHARGE_PUMP_1
251 #define RT5659_CHARGE_PUMP_2
252 #define RT5659_DIG_IN_CTRL_1
253 #define RT5659_DIG_IN_CTRL_2
254 #define RT5659_PAD_DRIVING_CTRL
255 #define RT5659_SOFT_RAMP_DEPOP
256 #define RT5659_PLL
257 #define RT5659_CHOP_DAC
258 #define RT5659_CHOP_ADC
259 #define RT5659_CALIB_ADC_CTRL
260 #define RT5659_SOFT_RAMP_DEPOP_DAC_CLK_CTRL
261 #define RT5659_VOL_TEST
262 #define RT5659_TEST_MODE_CTRL_1
263 #define RT5659_TEST_MODE_CTRL_2
264 #define RT5659_TEST_MODE_CTRL_3
265 #define RT5659_TEST_MODE_CTRL_4
266 #define RT5659_BASSBACK_CTRL
267 #define RT5659_MP3_PLUS_CTRL_1
268 #define RT5659_MP3_PLUS_CTRL_2
269 #define RT5659_MP3_HPF_A1
270 #define RT5659_MP3_HPF_A2
271 #define RT5659_MP3_HPF_H0
272 #define RT5659_MP3_LPF_H0
273 #define RT5659_3D_SPK_CTRL
274 #define RT5659_3D_SPK_COEF_1
275 #define RT5659_3D_SPK_COEF_2
276 #define RT5659_3D_SPK_COEF_3
277 #define RT5659_3D_SPK_COEF_4
278 #define RT5659_3D_SPK_COEF_5
279 #define RT5659_3D_SPK_COEF_6
280 #define RT5659_3D_SPK_COEF_7
281 #define RT5659_STO_NG2_CTRL_1
282 #define RT5659_STO_NG2_CTRL_2
283 #define RT5659_STO_NG2_CTRL_3
284 #define RT5659_STO_NG2_CTRL_4
285 #define RT5659_STO_NG2_CTRL_5
286 #define RT5659_STO_NG2_CTRL_6
287 #define RT5659_STO_NG2_CTRL_7
288 #define RT5659_STO_NG2_CTRL_8
289 #define RT5659_MONO_NG2_CTRL_1
290 #define RT5659_MONO_NG2_CTRL_2
291 #define RT5659_MONO_NG2_CTRL_3
292 #define RT5659_MONO_NG2_CTRL_4
293 #define RT5659_MONO_NG2_CTRL_5
294 #define RT5659_MONO_NG2_CTRL_6
295 #define RT5659_MID_HP_AMP_DET
296 #define RT5659_LOW_HP_AMP_DET
297 #define RT5659_LDO_CTRL
298 #define RT5659_HP_DECROSS_CTRL_1
299 #define RT5659_HP_DECROSS_CTRL_2
300 #define RT5659_HP_DECROSS_CTRL_3
301 #define RT5659_HP_DECROSS_CTRL_4
302 #define RT5659_HP_IMP_SENS_CTRL_1
303 #define RT5659_HP_IMP_SENS_CTRL_2
304 #define RT5659_HP_IMP_SENS_CTRL_3
305 #define RT5659_HP_IMP_SENS_CTRL_4
306 #define RT5659_HP_IMP_SENS_MAP_1
307 #define RT5659_HP_IMP_SENS_MAP_2
308 #define RT5659_HP_IMP_SENS_MAP_3
309 #define RT5659_HP_IMP_SENS_MAP_4
310 #define RT5659_HP_IMP_SENS_MAP_5
311 #define RT5659_HP_IMP_SENS_MAP_6
312 #define RT5659_HP_IMP_SENS_MAP_7
313 #define RT5659_HP_IMP_SENS_MAP_8
314 #define RT5659_HP_LOGIC_CTRL_1
315 #define RT5659_HP_LOGIC_CTRL_2
316 #define RT5659_HP_CALIB_CTRL_1
317 #define RT5659_HP_CALIB_CTRL_2
318 #define RT5659_HP_CALIB_CTRL_3
319 #define RT5659_HP_CALIB_CTRL_4
320 #define RT5659_HP_CALIB_CTRL_5
321 #define RT5659_HP_CALIB_CTRL_6
322 #define RT5659_HP_CALIB_CTRL_7
323 #define RT5659_HP_CALIB_CTRL_9
324 #define RT5659_HP_CALIB_CTRL_10
325 #define RT5659_HP_CALIB_CTRL_11
326 #define RT5659_HP_CALIB_STA_1
327 #define RT5659_HP_CALIB_STA_2
328 #define RT5659_HP_CALIB_STA_3
329 #define RT5659_HP_CALIB_STA_4
330 #define RT5659_HP_CALIB_STA_5
331 #define RT5659_HP_CALIB_STA_6
332 #define RT5659_HP_CALIB_STA_7
333 #define RT5659_HP_CALIB_STA_8
334 #define RT5659_HP_CALIB_STA_9
335 #define RT5659_MONO_AMP_CALIB_CTRL_1
336 #define RT5659_MONO_AMP_CALIB_CTRL_2
337 #define RT5659_MONO_AMP_CALIB_CTRL_3
338 #define RT5659_MONO_AMP_CALIB_CTRL_4
339 #define RT5659_MONO_AMP_CALIB_CTRL_5
340 #define RT5659_MONO_AMP_CALIB_STA_1
341 #define RT5659_MONO_AMP_CALIB_STA_2
342 #define RT5659_MONO_AMP_CALIB_STA_3
343 #define RT5659_MONO_AMP_CALIB_STA_4
344 #define RT5659_SPK_PWR_LMT_CTRL_1
345 #define RT5659_SPK_PWR_LMT_CTRL_2
346 #define RT5659_SPK_PWR_LMT_CTRL_3
347 #define RT5659_SPK_PWR_LMT_STA_1
348 #define RT5659_SPK_PWR_LMT_STA_2
349 #define RT5659_SPK_PWR_LMT_STA_3
350 #define RT5659_SPK_PWR_LMT_STA_4
351 #define RT5659_SPK_PWR_LMT_STA_5
352 #define RT5659_SPK_PWR_LMT_STA_6
353 #define RT5659_FLEX_SPK_BST_CTRL_1
354 #define RT5659_FLEX_SPK_BST_CTRL_2
355 #define RT5659_FLEX_SPK_BST_CTRL_3
356 #define RT5659_FLEX_SPK_BST_CTRL_4
357 #define RT5659_SPK_EX_LMT_CTRL_1
358 #define RT5659_SPK_EX_LMT_CTRL_2
359 #define RT5659_SPK_EX_LMT_CTRL_3
360 #define RT5659_SPK_EX_LMT_CTRL_4
361 #define RT5659_SPK_EX_LMT_CTRL_5
362 #define RT5659_SPK_EX_LMT_CTRL_6
363 #define RT5659_SPK_EX_LMT_CTRL_7
364 #define RT5659_ADJ_HPF_CTRL_1
365 #define RT5659_ADJ_HPF_CTRL_2
366 #define RT5659_SPK_DC_CAILB_CTRL_1
367 #define RT5659_SPK_DC_CAILB_CTRL_2
368 #define RT5659_SPK_DC_CAILB_CTRL_3
369 #define RT5659_SPK_DC_CAILB_CTRL_4
370 #define RT5659_SPK_DC_CAILB_CTRL_5
371 #define RT5659_SPK_DC_CAILB_STA_1
372 #define RT5659_SPK_DC_CAILB_STA_2
373 #define RT5659_SPK_DC_CAILB_STA_3
374 #define RT5659_SPK_DC_CAILB_STA_4
375 #define RT5659_SPK_DC_CAILB_STA_5
376 #define RT5659_SPK_DC_CAILB_STA_6
377 #define RT5659_SPK_DC_CAILB_STA_7
378 #define RT5659_SPK_DC_CAILB_STA_8
379 #define RT5659_SPK_DC_CAILB_STA_9
380 #define RT5659_SPK_DC_CAILB_STA_10
381 #define RT5659_SPK_VDD_STA_1
382 #define RT5659_SPK_VDD_STA_2
383 #define RT5659_SPK_DC_DET_CTRL_1
384 #define RT5659_SPK_DC_DET_CTRL_2
385 #define RT5659_SPK_DC_DET_CTRL_3
386 #define RT5659_PURE_DC_DET_CTRL_1
387 #define RT5659_PURE_DC_DET_CTRL_2
388 #define RT5659_DUMMY_4
389 #define RT5659_DUMMY_5
390 #define RT5659_DUMMY_6
391 #define RT5659_DRC1_CTRL_1
392 #define RT5659_DRC1_CTRL_2
393 #define RT5659_DRC1_CTRL_3
394 #define RT5659_DRC1_CTRL_4
395 #define RT5659_DRC1_CTRL_5
396 #define RT5659_DRC1_CTRL_6
397 #define RT5659_DRC1_HARD_LMT_CTRL_1
398 #define RT5659_DRC1_HARD_LMT_CTRL_2
399 #define RT5659_DRC2_CTRL_1
400 #define RT5659_DRC2_CTRL_2
401 #define RT5659_DRC2_CTRL_3
402 #define RT5659_DRC2_CTRL_4
403 #define RT5659_DRC2_CTRL_5
404 #define RT5659_DRC2_CTRL_6
405 #define RT5659_DRC2_HARD_LMT_CTRL_1
406 #define RT5659_DRC2_HARD_LMT_CTRL_2
407 #define RT5659_DRC1_PRIV_1
408 #define RT5659_DRC1_PRIV_2
409 #define RT5659_DRC1_PRIV_3
410 #define RT5659_DRC1_PRIV_4
411 #define RT5659_DRC1_PRIV_5
412 #define RT5659_DRC1_PRIV_6
413 #define RT5659_DRC1_PRIV_7
414 #define RT5659_DRC2_PRIV_1
415 #define RT5659_DRC2_PRIV_2
416 #define RT5659_DRC2_PRIV_3
417 #define RT5659_DRC2_PRIV_4
418 #define RT5659_DRC2_PRIV_5
419 #define RT5659_DRC2_PRIV_6
420 #define RT5659_DRC2_PRIV_7
421 #define RT5659_MULTI_DRC_CTRL
422 #define RT5659_CROSS_OVER_1
423 #define RT5659_CROSS_OVER_2
424 #define RT5659_CROSS_OVER_3
425 #define RT5659_CROSS_OVER_4
426 #define RT5659_CROSS_OVER_5
427 #define RT5659_CROSS_OVER_6
428 #define RT5659_CROSS_OVER_7
429 #define RT5659_CROSS_OVER_8
430 #define RT5659_CROSS_OVER_9
431 #define RT5659_CROSS_OVER_10
432 #define RT5659_ALC_PGA_CTRL_1
433 #define RT5659_ALC_PGA_CTRL_2
434 #define RT5659_ALC_PGA_CTRL_3
435 #define RT5659_ALC_PGA_CTRL_4
436 #define RT5659_ALC_PGA_CTRL_5
437 #define RT5659_ALC_PGA_CTRL_6
438 #define RT5659_ALC_PGA_CTRL_7
439 #define RT5659_ALC_PGA_CTRL_8
440 #define RT5659_ALC_PGA_STA_1
441 #define RT5659_ALC_PGA_STA_2
442 #define RT5659_ALC_PGA_STA_3
443 #define RT5659_DAC_L_EQ_PRE_VOL
444 #define RT5659_DAC_R_EQ_PRE_VOL
445 #define RT5659_DAC_L_EQ_POST_VOL
446 #define RT5659_DAC_R_EQ_POST_VOL
447 #define RT5659_DAC_L_EQ_LPF1_A1
448 #define RT5659_DAC_L_EQ_LPF1_H0
449 #define RT5659_DAC_R_EQ_LPF1_A1
450 #define RT5659_DAC_R_EQ_LPF1_H0
451 #define RT5659_DAC_L_EQ_BPF2_A1
452 #define RT5659_DAC_L_EQ_BPF2_A2
453 #define RT5659_DAC_L_EQ_BPF2_H0
454 #define RT5659_DAC_R_EQ_BPF2_A1
455 #define RT5659_DAC_R_EQ_BPF2_A2
456 #define RT5659_DAC_R_EQ_BPF2_H0
457 #define RT5659_DAC_L_EQ_BPF3_A1
458 #define RT5659_DAC_L_EQ_BPF3_A2
459 #define RT5659_DAC_L_EQ_BPF3_H0
460 #define RT5659_DAC_R_EQ_BPF3_A1
461 #define RT5659_DAC_R_EQ_BPF3_A2
462 #define RT5659_DAC_R_EQ_BPF3_H0
463 #define RT5659_DAC_L_EQ_BPF4_A1
464 #define RT5659_DAC_L_EQ_BPF4_A2
465 #define RT5659_DAC_L_EQ_BPF4_H0
466 #define RT5659_DAC_R_EQ_BPF4_A1
467 #define RT5659_DAC_R_EQ_BPF4_A2
468 #define RT5659_DAC_R_EQ_BPF4_H0
469 #define RT5659_DAC_L_EQ_HPF1_A1
470 #define RT5659_DAC_L_EQ_HPF1_H0
471 #define RT5659_DAC_R_EQ_HPF1_A1
472 #define RT5659_DAC_R_EQ_HPF1_H0
473 #define RT5659_DAC_L_EQ_HPF2_A1
474 #define RT5659_DAC_L_EQ_HPF2_A2
475 #define RT5659_DAC_L_EQ_HPF2_H0
476 #define RT5659_DAC_R_EQ_HPF2_A1
477 #define RT5659_DAC_R_EQ_HPF2_A2
478 #define RT5659_DAC_R_EQ_HPF2_H0
479 #define RT5659_DAC_L_BI_EQ_BPF1_H0_1
480 #define RT5659_DAC_L_BI_EQ_BPF1_H0_2
481 #define RT5659_DAC_L_BI_EQ_BPF1_B1_1
482 #define RT5659_DAC_L_BI_EQ_BPF1_B1_2
483 #define RT5659_DAC_L_BI_EQ_BPF1_B2_1
484 #define RT5659_DAC_L_BI_EQ_BPF1_B2_2
485 #define RT5659_DAC_L_BI_EQ_BPF1_A1_1
486 #define RT5659_DAC_L_BI_EQ_BPF1_A1_2
487 #define RT5659_DAC_L_BI_EQ_BPF1_A2_1
488 #define RT5659_DAC_L_BI_EQ_BPF1_A2_2
489 #define RT5659_DAC_R_BI_EQ_BPF1_H0_1
490 #define RT5659_DAC_R_BI_EQ_BPF1_H0_2
491 #define RT5659_DAC_R_BI_EQ_BPF1_B1_1
492 #define RT5659_DAC_R_BI_EQ_BPF1_B1_2
493 #define RT5659_DAC_R_BI_EQ_BPF1_B2_1
494 #define RT5659_DAC_R_BI_EQ_BPF1_B2_2
495 #define RT5659_DAC_R_BI_EQ_BPF1_A1_1
496 #define RT5659_DAC_R_BI_EQ_BPF1_A1_2
497 #define RT5659_DAC_R_BI_EQ_BPF1_A2_1
498 #define RT5659_DAC_R_BI_EQ_BPF1_A2_2
499 #define RT5659_ADC_L_EQ_LPF1_A1
500 #define RT5659_ADC_R_EQ_LPF1_A1
501 #define RT5659_ADC_L_EQ_LPF1_H0
502 #define RT5659_ADC_R_EQ_LPF1_H0
503 #define RT5659_ADC_L_EQ_BPF1_A1
504 #define RT5659_ADC_R_EQ_BPF1_A1
505 #define RT5659_ADC_L_EQ_BPF1_A2
506 #define RT5659_ADC_R_EQ_BPF1_A2
507 #define RT5659_ADC_L_EQ_BPF1_H0
508 #define RT5659_ADC_R_EQ_BPF1_H0
509 #define RT5659_ADC_L_EQ_BPF2_A1
510 #define RT5659_ADC_R_EQ_BPF2_A1
511 #define RT5659_ADC_L_EQ_BPF2_A2
512 #define RT5659_ADC_R_EQ_BPF2_A2
513 #define RT5659_ADC_L_EQ_BPF2_H0
514 #define RT5659_ADC_R_EQ_BPF2_H0
515 #define RT5659_ADC_L_EQ_BPF3_A1
516 #define RT5659_ADC_R_EQ_BPF3_A1
517 #define RT5659_ADC_L_EQ_BPF3_A2
518 #define RT5659_ADC_R_EQ_BPF3_A2
519 #define RT5659_ADC_L_EQ_BPF3_H0
520 #define RT5659_ADC_R_EQ_BPF3_H0
521 #define RT5659_ADC_L_EQ_BPF4_A1
522 #define RT5659_ADC_R_EQ_BPF4_A1
523 #define RT5659_ADC_L_EQ_BPF4_A2
524 #define RT5659_ADC_R_EQ_BPF4_A2
525 #define RT5659_ADC_L_EQ_BPF4_H0
526 #define RT5659_ADC_R_EQ_BPF4_H0
527 #define RT5659_ADC_L_EQ_HPF1_A1
528 #define RT5659_ADC_R_EQ_HPF1_A1
529 #define RT5659_ADC_L_EQ_HPF1_H0
530 #define RT5659_ADC_R_EQ_HPF1_H0
531 #define RT5659_ADC_L_EQ_PRE_VOL
532 #define RT5659_ADC_R_EQ_PRE_VOL
533 #define RT5659_ADC_L_EQ_POST_VOL
534 #define RT5659_ADC_R_EQ_POST_VOL
535
536
537
538 /* global definition */
539 #define RT5659_L_MUTE
540 #define RT5659_L_MUTE_SFT
541 #define RT5659_VOL_L_MUTE
542 #define RT5659_VOL_L_SFT
543 #define RT5659_R_MUTE
544 #define RT5659_R_MUTE_SFT
545 #define RT5659_VOL_R_MUTE
546 #define RT5659_VOL_R_SFT
547 #define RT5659_L_VOL_MASK
548 #define RT5659_L_VOL_SFT
549 #define RT5659_R_VOL_MASK
550 #define RT5659_R_VOL_SFT
551
552 /*Headphone Amp L/R Analog Gain and Digital NG
553 #define RT5659_G_HP
554 #define RT5659_G_HP_SFT
555 #define RT5659_G_STO_DA_DMIX
556 #define RT5659_G_STO_DA_SFT
557
558 /* IN1/IN2 Control (0x000c) */
559 #define RT5659_IN1_DF_MASK
560 #define RT5659_IN1_DF
561 #define RT5659_BST1_MASK
562 #define RT5659_BST1_SFT
563 #define RT5659_BST2_MASK
564 #define RT5659_BST2_SFT
565
566 /* IN3/IN4 Control (0x000d) */
567 #define RT5659_IN3_DF_MASK
568 #define RT5659_IN3_DF
569 #define RT5659_BST3_MASK
570 #define RT5659_BST3_SFT
571 #define RT5659_IN4_DF_MASK
572 #define RT5659_IN4_DF
573 #define RT5659_BST4_MASK
574 #define RT5659_BST4_SFT
575
576 /* INL and INR Volume Control (0x000f) */
577 #define RT5659_INL_VOL_MASK
578 #define RT5659_INL_VOL_SFT
579 #define RT5659_INR_VOL_MASK
580 #define RT5659_INR_VOL_SFT
581
582 /* Embeeded Jack and Type Detection Control 1
583 #define RT5659_EMB_JD_EN
584 #define RT5659_EMB_JD_EN_SFT
585 #define RT5659_JD_MODE
586 #define RT5659_JD_MODE_SFT
587 #define RT5659_EXT_JD_EN
588 #define RT5659_EXT_JD_EN_SFT
589 #define RT5659_EXT_JD_DIG
590
591 /* Embeeded Jack and Type Detection Control 2
592 #define RT5659_EXT_JD_SRC
593 #define RT5659_EXT_JD_SRC_SFT
594 #define RT5659_EXT_JD_SRC_GPIO_JD1
595 #define RT5659_EXT_JD_SRC_GPIO_JD2
596 #define RT5659_EXT_JD_SRC_JD1_1
597 #define RT5659_EXT_JD_SRC_JD1_2
598 #define RT5659_EXT_JD_SRC_JD2
599 #define RT5659_EXT_JD_SRC_JD3
600 #define RT5659_EXT_JD_SRC_MANUAL
601
602 /* Slience Detection Control (0x0015) */
603 #define RT5659_SIL_DET_MASK
604 #define RT5659_SIL_DET_DIS
605 #define RT5659_SIL_DET_EN
606
607 /* Sidetone Control (0x0018) */
608 #define RT5659_ST_SEL_MASK
609 #define RT5659_ST_SEL_SFT
610 #define RT5659_ST_EN
611 #define RT5659_ST_EN_SFT
612
613 /* DAC1 Digital Volume (0x0019) */
614 #define RT5659_DAC_L1_VOL_MASK
615 #define RT5659_DAC_L1_VOL_SFT
616 #define RT5659_DAC_R1_VOL_MASK
617 #define RT5659_DAC_R1_VOL_SFT
618
619 /* DAC2 Digital Volume (0x001a) */
620 #define RT5659_DAC_L2_VOL_MASK
621 #define RT5659_DAC_L2_VOL_SFT
622 #define RT5659_DAC_R2_VOL_MASK
623 #define RT5659_DAC_R2_VOL_SFT
624
625 /* DAC2 Control (0x001b) */
626 #define RT5659_M_DAC2_L_VOL
627 #define RT5659_M_DAC2_L_VOL_SFT
628 #define RT5659_M_DAC2_R_VOL
629 #define RT5659_M_DAC2_R_VOL_SFT
630 #define RT5659_DAC_L2_SEL_MASK
631 #define RT5659_DAC_L2_SEL_SFT
632 #define RT5659_DAC_R2_SEL_MASK
633 #define RT5659_DAC_R2_SEL_SFT
634
635 /* ADC Digital Volume Control (0x001c) */
636 #define RT5659_ADC_L_VOL_MASK
637 #define RT5659_ADC_L_VOL_SFT
638 #define RT5659_ADC_R_VOL_MASK
639 #define RT5659_ADC_R_VOL_SFT
640
641 /* Mono ADC Digital Volume Control (0x001d) */
642 #define RT5659_MONO_ADC_L_VOL_MASK
643 #define RT5659_MONO_ADC_L_VOL_SFT
644 #define RT5659_MONO_ADC_R_VOL_MASK
645 #define RT5659_MONO_ADC_R_VOL_SFT
646
647 /* Stereo1 ADC Boost Gain Control (0x001f) */
648 #define RT5659_STO1_ADC_L_BST_MASK
649 #define RT5659_STO1_ADC_L_BST_SFT
650 #define RT5659_STO1_ADC_R_BST_MASK
651 #define RT5659_STO1_ADC_R_BST_SFT
652
653 /* Mono ADC Boost Gain Control (0x0020) */
654 #define RT5659_MONO_ADC_L_BST_MASK
655 #define RT5659_MONO_ADC_L_BST_SFT
656 #define RT5659_MONO_ADC_R_BST_MASK
657 #define RT5659_MONO_ADC_R_BST_SFT
658
659 /* Stereo1 ADC Boost Gain Control (0x001f) */
660 #define RT5659_STO2_ADC_L_BST_MASK
661 #define RT5659_STO2_ADC_L_BST_SFT
662 #define RT5659_STO2_ADC_R_BST_MASK
663 #define RT5659_STO2_ADC_R_BST_SFT
664
665 /* Stereo ADC Mixer Control (0x0026) */
666 #define RT5659_M_STO1_ADC_L1
667 #define RT5659_M_STO1_ADC_L1_SFT
668 #define RT5659_M_STO1_ADC_L2
669 #define RT5659_M_STO1_ADC_L2_SFT
670 #define RT5659_STO1_ADC1_SRC_MASK
671 #define RT5659_STO1_ADC1_SRC_SFT
672 #define RT5659_STO1_ADC1_SRC_ADC
673 #define RT5659_STO1_ADC1_SRC_DACMIX
674 #define RT5659_STO1_ADC_SRC_MASK
675 #define RT5659_STO1_ADC_SRC_SFT
676 #define RT5659_STO1_ADC_SRC_ADC1
677 #define RT5659_STO1_ADC_SRC_ADC2
678 #define RT5659_STO1_ADC2_SRC_MASK
679 #define RT5659_STO1_ADC2_SRC_SFT
680 #define RT5659_STO1_DMIC_SRC_MASK
681 #define RT5659_STO1_DMIC_SRC_SFT
682 #define RT5659_STO1_DMIC_SRC_DMIC2
683 #define RT5659_STO1_DMIC_SRC_DMIC1
684 #define RT5659_M_STO1_ADC_R1
685 #define RT5659_M_STO1_ADC_R1_SFT
686 #define RT5659_M_STO1_ADC_R2
687 #define RT5659_M_STO1_ADC_R2_SFT
688
689 /* Mono1 ADC Mixer control (0x0027) */
690 #define RT5659_M_MONO_ADC_L1
691 #define RT5659_M_MONO_ADC_L1_SFT
692 #define RT5659_M_MONO_ADC_L2
693 #define RT5659_M_MONO_ADC_L2_SFT
694 #define RT5659_MONO_ADC_L2_SRC_MASK
695 #define RT5659_MONO_ADC_L2_SRC_SFT
696 #define RT5659_MONO_ADC_L1_SRC_MASK
697 #define RT5659_MONO_ADC_L1_SRC_SFT
698 #define RT5659_MONO_ADC_L_SRC_MASK
699 #define RT5659_MONO_ADC_L_SRC_SFT
700 #define RT5659_MONO_DMIC_L_SRC_MASK
701 #define RT5659_MONO_DMIC_L_SRC_SFT
702 #define RT5659_M_MONO_ADC_R1
703 #define RT5659_M_MONO_ADC_R1_SFT
704 #define RT5659_M_MONO_ADC_R2
705 #define RT5659_M_MONO_ADC_R2_SFT
706 #define RT5659_STO2_ADC_SRC_MASK
707 #define RT5659_STO2_ADC_SRC_SFT
708 #define RT5659_MONO_ADC_R2_SRC_MASK
709 #define RT5659_MONO_ADC_R2_SRC_SFT
710 #define RT5659_MONO_ADC_R1_SRC_MASK
711 #define RT5659_MONO_ADC_R1_SRC_SFT
712 #define RT5659_MONO_ADC_R_SRC_MASK
713 #define RT5659_MONO_ADC_R_SRC_SFT
714 #define RT5659_MONO_DMIC_R_SRC_MASK
715 #define RT5659_MONO_DMIC_R_SRC_SFT
716
717 /* ADC Mixer to DAC Mixer Control (0x0029) */
718 #define RT5659_M_ADCMIX_L
719 #define RT5659_M_ADCMIX_L_SFT
720 #define RT5659_M_DAC1_L
721 #define RT5659_M_DAC1_L_SFT
722 #define RT5659_DAC1_R_SEL_MASK
723 #define RT5659_DAC1_R_SEL_SFT
724 #define RT5659_DAC1_R_SEL_IF1
725 #define RT5659_DAC1_R_SEL_IF2
726 #define RT5659_DAC1_R_SEL_IF3
727 #define RT5659_DAC1_L_SEL_MASK
728 #define RT5659_DAC1_L_SEL_SFT
729 #define RT5659_DAC1_L_SEL_IF1
730 #define RT5659_DAC1_L_SEL_IF2
731 #define RT5659_DAC1_L_SEL_IF3
732 #define RT5659_M_ADCMIX_R
733 #define RT5659_M_ADCMIX_R_SFT
734 #define RT5659_M_DAC1_R
735 #define RT5659_M_DAC1_R_SFT
736
737 /* Stereo DAC Mixer Control (0x002a) */
738 #define RT5659_M_DAC_L1_STO_L
739 #define RT5659_M_DAC_L1_STO_L_SFT
740 #define RT5659_G_DAC_L1_STO_L_MASK
741 #define RT5659_G_DAC_L1_STO_L_SFT
742 #define RT5659_M_DAC_R1_STO_L
743 #define RT5659_M_DAC_R1_STO_L_SFT
744 #define RT5659_G_DAC_R1_STO_L_MASK
745 #define RT5659_G_DAC_R1_STO_L_SFT
746 #define RT5659_M_DAC_L2_STO_L
747 #define RT5659_M_DAC_L2_STO_L_SFT
748 #define RT5659_G_DAC_L2_STO_L_MASK
749 #define RT5659_G_DAC_L2_STO_L_SFT
750 #define RT5659_M_DAC_R2_STO_L
751 #define RT5659_M_DAC_R2_STO_L_SFT
752 #define RT5659_G_DAC_R2_STO_L_MASK
753 #define RT5659_G_DAC_R2_STO_L_SFT
754 #define RT5659_M_DAC_L1_STO_R
755 #define RT5659_M_DAC_L1_STO_R_SFT
756 #define RT5659_G_DAC_L1_STO_R_MASK
757 #define RT5659_G_DAC_L1_STO_R_SFT
758 #define RT5659_M_DAC_R1_STO_R
759 #define RT5659_M_DAC_R1_STO_R_SFT
760 #define RT5659_G_DAC_R1_STO_R_MASK
761 #define RT5659_G_DAC_R1_STO_R_SFT
762 #define RT5659_M_DAC_L2_STO_R
763 #define RT5659_M_DAC_L2_STO_R_SFT
764 #define RT5659_G_DAC_L2_STO_R_MASK
765 #define RT5659_G_DAC_L2_STO_R_SFT
766 #define RT5659_M_DAC_R2_STO_R
767 #define RT5659_M_DAC_R2_STO_R_SFT
768 #define RT5659_G_DAC_R2_STO_R_MASK
769 #define RT5659_G_DAC_R2_STO_R_SFT
770
771 /* Mono DAC Mixer Control (0x002b) */
772 #define RT5659_M_DAC_L1_MONO_L
773 #define RT5659_M_DAC_L1_MONO_L_SFT
774 #define RT5659_G_DAC_L1_MONO_L_MASK
775 #define RT5659_G_DAC_L1_MONO_L_SFT
776 #define RT5659_M_DAC_R1_MONO_L
777 #define RT5659_M_DAC_R1_MONO_L_SFT
778 #define RT5659_G_DAC_R1_MONO_L_MASK
779 #define RT5659_G_DAC_R1_MONO_L_SFT
780 #define RT5659_M_DAC_L2_MONO_L
781 #define RT5659_M_DAC_L2_MONO_L_SFT
782 #define RT5659_G_DAC_L2_MONO_L_MASK
783 #define RT5659_G_DAC_L2_MONO_L_SFT
784 #define RT5659_M_DAC_R2_MONO_L
785 #define RT5659_M_DAC_R2_MONO_L_SFT
786 #define RT5659_G_DAC_R2_MONO_L_MASK
787 #define RT5659_G_DAC_R2_MONO_L_SFT
788 #define RT5659_M_DAC_L1_MONO_R
789 #define RT5659_M_DAC_L1_MONO_R_SFT
790 #define RT5659_G_DAC_L1_MONO_R_MASK
791 #define RT5659_G_DAC_L1_MONO_R_SFT
792 #define RT5659_M_DAC_R1_MONO_R
793 #define RT5659_M_DAC_R1_MONO_R_SFT
794 #define RT5659_G_DAC_R1_MONO_R_MASK
795 #define RT5659_G_DAC_R1_MONO_R_SFT
796 #define RT5659_M_DAC_L2_MONO_R
797 #define RT5659_M_DAC_L2_MONO_R_SFT
798 #define RT5659_G_DAC_L2_MONO_R_MASK
799 #define RT5659_G_DAC_L2_MONO_R_SFT
800 #define RT5659_M_DAC_R2_MONO_R
801 #define RT5659_M_DAC_R2_MONO_R_SFT
802 #define RT5659_G_DAC_R2_MONO_R_MASK
803 #define RT5659_G_DAC_R2_MONO_R_SFT
804
805 /* Digital Mixer Control (0x002c) */
806 #define RT5659_M_DAC_MIX_L
807 #define RT5659_M_DAC_MIX_L_SFT
808 #define RT5659_DAC_MIX_L_MASK
809 #define RT5659_DAC_MIX_L_SFT
810 #define RT5659_M_DAC_MIX_R
811 #define RT5659_M_DAC_MIX_R_SFT
812 #define RT5659_DAC_MIX_R_MASK
813 #define RT5659_DAC_MIX_R_SFT
814
815 /* Analog DAC Input Source Control (0x002d) */
816 #define RT5659_A_DACL1_SEL
817 #define RT5659_A_DACL1_SFT
818 #define RT5659_A_DACR1_SEL
819 #define RT5659_A_DACR1_SFT
820 #define RT5659_A_DACL2_SEL
821 #define RT5659_A_DACL2_SFT
822 #define RT5659_A_DACR2_SEL
823 #define RT5659_A_DACR2_SFT
824
825 /* Digital Interface Data Control (0x002f) */
826 #define RT5659_IF2_ADC3_IN_MASK
827 #define RT5659_IF2_ADC3_IN_SFT
828 #define RT5659_IF2_ADC_IN_MASK
829 #define RT5659_IF2_ADC_IN_SFT
830 #define RT5659_IF2_DAC_SEL_MASK
831 #define RT5659_IF2_DAC_SEL_SFT
832 #define RT5659_IF2_ADC_SEL_MASK
833 #define RT5659_IF2_ADC_SEL_SFT
834 #define RT5659_IF3_DAC_SEL_MASK
835 #define RT5659_IF3_DAC_SEL_SFT
836 #define RT5659_IF3_ADC_SEL_MASK
837 #define RT5659_IF3_ADC_SEL_SFT
838 #define RT5659_IF3_ADC_IN_MASK
839 #define RT5659_IF3_ADC_IN_SFT
840
841 /* PDM Output Control (0x0031) */
842 #define RT5659_PDM1_L_MASK
843 #define RT5659_PDM1_L_SFT
844 #define RT5659_M_PDM1_L
845 #define RT5659_M_PDM1_L_SFT
846 #define RT5659_PDM1_R_MASK
847 #define RT5659_PDM1_R_SFT
848 #define RT5659_M_PDM1_R
849 #define RT5659_M_PDM1_R_SFT
850 #define RT5659_PDM2_BUSY
851 #define RT5659_PDM1_BUSY
852 #define RT5659_PDM_PATTERN
853 #define RT5659_PDM_GAIN
854 #define RT5659_PDM_DIV_MASK
855
856 /*S/PDIF Output Control (0x0036) */
857 #define RT5659_SPDIF_SEL_MASK
858 #define RT5659_SPDIF_SEL_SFT
859
860 /* REC Left Mixer Control 2 (0x003c) */
861 #define RT5659_M_BST1_RM1_L
862 #define RT5659_M_BST1_RM1_L_SFT
863 #define RT5659_M_BST2_RM1_L
864 #define RT5659_M_BST2_RM1_L_SFT
865 #define RT5659_M_BST3_RM1_L
866 #define RT5659_M_BST3_RM1_L_SFT
867 #define RT5659_M_BST4_RM1_L
868 #define RT5659_M_BST4_RM1_L_SFT
869 #define RT5659_M_INL_RM1_L
870 #define RT5659_M_INL_RM1_L_SFT
871 #define RT5659_M_SPKVOLL_RM1_L
872 #define RT5659_M_SPKVOLL_RM1_L_SFT
873
874 /* REC Right Mixer Control 2 (0x003e) */
875 #define RT5659_M_BST1_RM1_R
876 #define RT5659_M_BST1_RM1_R_SFT
877 #define RT5659_M_BST2_RM1_R
878 #define RT5659_M_BST2_RM1_R_SFT
879 #define RT5659_M_BST3_RM1_R
880 #define RT5659_M_BST3_RM1_R_SFT
881 #define RT5659_M_BST4_RM1_R
882 #define RT5659_M_BST4_RM1_R_SFT
883 #define RT5659_M_INR_RM1_R
884 #define RT5659_M_INR_RM1_R_SFT
885 #define RT5659_M_HPOVOLR_RM1_R
886 #define RT5659_M_HPOVOLR_RM1_R_SFT
887
888 /* SPK Left Mixer Control (0x0046) */
889 #define RT5659_M_BST3_SM_L
890 #define RT5659_M_BST3_SM_L_SFT
891 #define RT5659_M_IN_R_SM_L
892 #define RT5659_M_IN_R_SM_L_SFT
893 #define RT5659_M_IN_L_SM_L
894 #define RT5659_M_IN_L_SM_L_SFT
895 #define RT5659_M_BST1_SM_L
896 #define RT5659_M_BST1_SM_L_SFT
897 #define RT5659_M_DAC_L2_SM_L
898 #define RT5659_M_DAC_L2_SM_L_SFT
899
900 /* SPK Right Mixer Control (0x0047) */
901 #define RT5659_M_BST3_SM_R
902 #define RT5659_M_BST3_SM_R_SFT
903 #define RT5659_M_IN_R_SM_R
904 #define RT5659_M_IN_R_SM_R_SFT
905 #define RT5659_M_IN_L_SM_R
906 #define RT5659_M_IN_L_SM_R_SFT
907 #define RT5659_M_BST4_SM_R
908 #define RT5659_M_BST4_SM_R_SFT
909 #define RT5659_M_DAC_R2_SM_R
910 #define RT5659_M_DAC_R2_SM_R_SFT
911
912 /* SPO Amp Input and Gain Control (0x0048) */
913 #define RT5659_M_DAC_L2_SPKOMIX
914 #define RT5659_M_DAC_L2_SPKOMIX_SFT
915 #define RT5659_M_SPKVOLL_SPKOMIX
916 #define RT5659_M_SPKVOLL_SPKOMIX_SFT
917 #define RT5659_M_DAC_R2_SPKOMIX
918 #define RT5659_M_DAC_R2_SPKOMIX_SFT
919 #define RT5659_M_SPKVOLR_SPKOMIX
920 #define RT5659_M_SPKVOLR_SPKOMIX_SFT
921
922 /* MONOMIX Input and Gain Control (0x004b) */
923 #define RT5659_M_MONOVOL_MA
924 #define RT5659_M_MONOVOL_MA_SFT
925 #define RT5659_M_DAC_L2_MA
926 #define RT5659_M_DAC_L2_MA_SFT
927 #define RT5659_M_BST3_MM
928 #define RT5659_M_BST3_MM_SFT
929 #define RT5659_M_BST2_MM
930 #define RT5659_M_BST2_MM_SFT
931 #define RT5659_M_BST1_MM
932 #define RT5659_M_BST1_MM_SFT
933 #define RT5659_M_DAC_R2_MM
934 #define RT5659_M_DAC_R2_MM_SFT
935 #define RT5659_M_DAC_L2_MM
936 #define RT5659_M_DAC_L2_MM_SFT
937
938 /* Output Left Mixer Control 1 (0x004d) */
939 #define RT5659_G_BST3_OM_L_MASK
940 #define RT5659_G_BST3_OM_L_SFT
941 #define RT5659_G_BST2_OM_L_MASK
942 #define RT5659_G_BST2_OM_L_SFT
943 #define RT5659_G_BST1_OM_L_MASK
944 #define RT5659_G_BST1_OM_L_SFT
945 #define RT5659_G_IN_L_OM_L_MASK
946 #define RT5659_G_IN_L_OM_L_SFT
947 #define RT5659_G_DAC_L2_OM_L_MASK
948 #define RT5659_G_DAC_L2_OM_L_SFT
949
950 /* Output Left Mixer Input Control (0x004e) */
951 #define RT5659_M_BST3_OM_L
952 #define RT5659_M_BST3_OM_L_SFT
953 #define RT5659_M_BST2_OM_L
954 #define RT5659_M_BST2_OM_L_SFT
955 #define RT5659_M_BST1_OM_L
956 #define RT5659_M_BST1_OM_L_SFT
957 #define RT5659_M_IN_L_OM_L
958 #define RT5659_M_IN_L_OM_L_SFT
959 #define RT5659_M_DAC_L2_OM_L
960 #define RT5659_M_DAC_L2_OM_L_SFT
961
962 /* Output Right Mixer Input Control (0x0050) *
963 #define RT5659_M_BST4_OM_R
964 #define RT5659_M_BST4_OM_R_SFT
965 #define RT5659_M_BST3_OM_R
966 #define RT5659_M_BST3_OM_R_SFT
967 #define RT5659_M_BST2_OM_R
968 #define RT5659_M_BST2_OM_R_SFT
969 #define RT5659_M_IN_R_OM_R
970 #define RT5659_M_IN_R_OM_R_SFT
971 #define RT5659_M_DAC_R2_OM_R
972 #define RT5659_M_DAC_R2_OM_R_SFT
973
974 /* LOUT Mixer Control (0x0052) */
975 #define RT5659_M_DAC_L2_LM
976 #define RT5659_M_DAC_L2_LM_SFT
977 #define RT5659_M_DAC_R2_LM
978 #define RT5659_M_DAC_R2_LM_SFT
979 #define RT5659_M_OV_L_LM
980 #define RT5659_M_OV_L_LM_SFT
981 #define RT5659_M_OV_R_LM
982 #define RT5659_M_OV_R_LM_SFT
983
984 /* Power Management for Digital 1 (0x0061) */
985 #define RT5659_PWR_I2S1
986 #define RT5659_PWR_I2S1_BIT
987 #define RT5659_PWR_I2S2
988 #define RT5659_PWR_I2S2_BIT
989 #define RT5659_PWR_I2S3
990 #define RT5659_PWR_I2S3_BIT
991 #define RT5659_PWR_SPDIF
992 #define RT5659_PWR_SPDIF_BIT
993 #define RT5659_PWR_DAC_L1
994 #define RT5659_PWR_DAC_L1_BIT
995 #define RT5659_PWR_DAC_R1
996 #define RT5659_PWR_DAC_R1_BIT
997 #define RT5659_PWR_DAC_L2
998 #define RT5659_PWR_DAC_L2_BIT
999 #define RT5659_PWR_DAC_R2
1000 #define RT5659_PWR_DAC_R2_BIT
1001 #define RT5659_PWR_LDO
1002 #define RT5659_PWR_LDO_BIT
1003 #define RT5659_PWR_ADC_L1
1004 #define RT5659_PWR_ADC_L1_BIT
1005 #define RT5659_PWR_ADC_R1
1006 #define RT5659_PWR_ADC_R1_BIT
1007 #define RT5659_PWR_ADC_L2
1008 #define RT5659_PWR_ADC_L2_BIT
1009 #define RT5659_PWR_ADC_R2
1010 #define RT5659_PWR_ADC_R2_BIT
1011 #define RT5659_PWR_CLS_D
1012 #define RT5659_PWR_CLS_D_BIT
1013
1014 /* Power Management for Digital 2 (0x0062) */
1015 #define RT5659_PWR_ADC_S1F
1016 #define RT5659_PWR_ADC_S1F_BIT
1017 #define RT5659_PWR_ADC_S2F
1018 #define RT5659_PWR_ADC_S2F_BIT
1019 #define RT5659_PWR_ADC_MF_L
1020 #define RT5659_PWR_ADC_MF_L_BIT
1021 #define RT5659_PWR_ADC_MF_R
1022 #define RT5659_PWR_ADC_MF_R_BIT
1023 #define RT5659_PWR_DAC_S1F
1024 #define RT5659_PWR_DAC_S1F_BIT
1025 #define RT5659_PWR_DAC_MF_L
1026 #define RT5659_PWR_DAC_MF_L_BIT
1027 #define RT5659_PWR_DAC_MF_R
1028 #define RT5659_PWR_DAC_MF_R_BIT
1029 #define RT5659_PWR_PDM1
1030 #define RT5659_PWR_PDM1_BIT
1031
1032 /* Power Management for Analog 1 (0x0063) */
1033 #define RT5659_PWR_VREF1
1034 #define RT5659_PWR_VREF1_BIT
1035 #define RT5659_PWR_FV1
1036 #define RT5659_PWR_FV1_BIT
1037 #define RT5659_PWR_VREF2
1038 #define RT5659_PWR_VREF2_BIT
1039 #define RT5659_PWR_FV2
1040 #define RT5659_PWR_FV2_BIT
1041 #define RT5659_PWR_VREF3
1042 #define RT5659_PWR_VREF3_BIT
1043 #define RT5659_PWR_FV3
1044 #define RT5659_PWR_FV3_BIT
1045 #define RT5659_PWR_MB
1046 #define RT5659_PWR_MB_BIT
1047 #define RT5659_PWR_LM
1048 #define RT5659_PWR_LM_BIT
1049 #define RT5659_PWR_BG
1050 #define RT5659_PWR_BG_BIT
1051 #define RT5659_PWR_MA
1052 #define RT5659_PWR_MA_BIT
1053 #define RT5659_PWR_HA_L
1054 #define RT5659_PWR_HA_L_BIT
1055 #define RT5659_PWR_HA_R
1056 #define RT5659_PWR_HA_R_BIT
1057
1058 /* Power Management for Analog 2 (0x0064) */
1059 #define RT5659_PWR_BST1
1060 #define RT5659_PWR_BST1_BIT
1061 #define RT5659_PWR_BST2
1062 #define RT5659_PWR_BST2_BIT
1063 #define RT5659_PWR_BST3
1064 #define RT5659_PWR_BST3_BIT
1065 #define RT5659_PWR_BST4
1066 #define RT5659_PWR_BST4_BIT
1067 #define RT5659_PWR_MB1
1068 #define RT5659_PWR_MB1_BIT
1069 #define RT5659_PWR_MB2
1070 #define RT5659_PWR_MB2_BIT
1071 #define RT5659_PWR_MB3
1072 #define RT5659_PWR_MB3_BIT
1073 #define RT5659_PWR_BST1_P
1074 #define RT5659_PWR_BST1_P_BIT
1075 #define RT5659_PWR_BST2_P
1076 #define RT5659_PWR_BST2_P_BIT
1077 #define RT5659_PWR_BST3_P
1078 #define RT5659_PWR_BST3_P_BIT
1079 #define RT5659_PWR_BST4_P
1080 #define RT5659_PWR_BST4_P_BIT
1081 #define RT5659_PWR_JD1
1082 #define RT5659_PWR_JD1_BIT
1083 #define RT5659_PWR_JD2
1084 #define RT5659_PWR_JD2_BIT
1085 #define RT5659_PWR_JD3
1086 #define RT5659_PWR_JD3_BIT
1087
1088 /* Power Management for Analog 3 (0x0065) */
1089 #define RT5659_PWR_BST_L
1090 #define RT5659_PWR_BST_L_BIT
1091 #define RT5659_PWR_BST_R
1092 #define RT5659_PWR_BST_R_BIT
1093 #define RT5659_PWR_PLL
1094 #define RT5659_PWR_PLL_BIT
1095 #define RT5659_PWR_LDO5
1096 #define RT5659_PWR_LDO5_BIT
1097 #define RT5659_PWR_LDO4
1098 #define RT5659_PWR_LDO4_BIT
1099 #define RT5659_PWR_LDO3
1100 #define RT5659_PWR_LDO3_BIT
1101 #define RT5659_PWR_LDO2
1102 #define RT5659_PWR_LDO2_BIT
1103 #define RT5659_PWR_SVD
1104 #define RT5659_PWR_SVD_BIT
1105
1106 /* Power Management for Mixer (0x0066) */
1107 #define RT5659_PWR_OM_L
1108 #define RT5659_PWR_OM_L_BIT
1109 #define RT5659_PWR_OM_R
1110 #define RT5659_PWR_OM_R_BIT
1111 #define RT5659_PWR_SM_L
1112 #define RT5659_PWR_SM_L_BIT
1113 #define RT5659_PWR_SM_R
1114 #define RT5659_PWR_SM_R_BIT
1115 #define RT5659_PWR_RM1_L
1116 #define RT5659_PWR_RM1_L_BIT
1117 #define RT5659_PWR_RM1_R
1118 #define RT5659_PWR_RM1_R_BIT
1119 #define RT5659_PWR_MM
1120 #define RT5659_PWR_MM_BIT
1121 #define RT5659_PWR_RM2_L
1122 #define RT5659_PWR_RM2_L_BIT
1123 #define RT5659_PWR_RM2_R
1124 #define RT5659_PWR_RM2_R_BIT
1125
1126 /* Power Management for Volume (0x0067) */
1127 #define RT5659_PWR_SV_L
1128 #define RT5659_PWR_SV_L_BIT
1129 #define RT5659_PWR_SV_R
1130 #define RT5659_PWR_SV_R_BIT
1131 #define RT5659_PWR_OV_L
1132 #define RT5659_PWR_OV_L_BIT
1133 #define RT5659_PWR_OV_R
1134 #define RT5659_PWR_OV_R_BIT
1135 #define RT5659_PWR_IN_L
1136 #define RT5659_PWR_IN_L_BIT
1137 #define RT5659_PWR_IN_R
1138 #define RT5659_PWR_IN_R_BIT
1139 #define RT5659_PWR_MV
1140 #define RT5659_PWR_MV_BIT
1141 #define RT5659_PWR_MIC_DET
1142 #define RT5659_PWR_MIC_DET_BIT
1143
1144 /* I2S1/2/3 Audio Serial Data Port Control (0
1145 #define RT5659_I2S_MS_MASK
1146 #define RT5659_I2S_MS_SFT
1147 #define RT5659_I2S_MS_M
1148 #define RT5659_I2S_MS_S
1149 #define RT5659_I2S_O_CP_MASK
1150 #define RT5659_I2S_O_CP_SFT
1151 #define RT5659_I2S_O_CP_OFF
1152 #define RT5659_I2S_O_CP_U_LAW
1153 #define RT5659_I2S_O_CP_A_LAW
1154 #define RT5659_I2S_I_CP_MASK
1155 #define RT5659_I2S_I_CP_SFT
1156 #define RT5659_I2S_I_CP_OFF
1157 #define RT5659_I2S_I_CP_U_LAW
1158 #define RT5659_I2S_I_CP_A_LAW
1159 #define RT5659_I2S_BP_MASK
1160 #define RT5659_I2S_BP_SFT
1161 #define RT5659_I2S_BP_NOR
1162 #define RT5659_I2S_BP_INV
1163 #define RT5659_I2S_DL_MASK
1164 #define RT5659_I2S_DL_SFT
1165 #define RT5659_I2S_DL_16
1166 #define RT5659_I2S_DL_20
1167 #define RT5659_I2S_DL_24
1168 #define RT5659_I2S_DL_8
1169 #define RT5659_I2S_DF_MASK
1170 #define RT5659_I2S_DF_SFT
1171 #define RT5659_I2S_DF_I2S
1172 #define RT5659_I2S_DF_LEFT
1173 #define RT5659_I2S_DF_PCM_A
1174 #define RT5659_I2S_DF_PCM_B
1175 #define RT5659_I2S_DF_PCM_A_N
1176 #define RT5659_I2S_DF_PCM_B_N
1177
1178 /* ADC/DAC Clock Control 1 (0x0073) */
1179 #define RT5659_I2S_PD1_MASK
1180 #define RT5659_I2S_PD1_SFT
1181 #define RT5659_I2S_PD1_1
1182 #define RT5659_I2S_PD1_2
1183 #define RT5659_I2S_PD1_3
1184 #define RT5659_I2S_PD1_4
1185 #define RT5659_I2S_PD1_6
1186 #define RT5659_I2S_PD1_8
1187 #define RT5659_I2S_PD1_12
1188 #define RT5659_I2S_PD1_16
1189 #define RT5659_I2S_BCLK_MS2_MASK
1190 #define RT5659_I2S_BCLK_MS2_SFT
1191 #define RT5659_I2S_BCLK_MS2_32
1192 #define RT5659_I2S_BCLK_MS2_64
1193 #define RT5659_I2S_PD2_MASK
1194 #define RT5659_I2S_PD2_SFT
1195 #define RT5659_I2S_PD2_1
1196 #define RT5659_I2S_PD2_2
1197 #define RT5659_I2S_PD2_3
1198 #define RT5659_I2S_PD2_4
1199 #define RT5659_I2S_PD2_6
1200 #define RT5659_I2S_PD2_8
1201 #define RT5659_I2S_PD2_12
1202 #define RT5659_I2S_PD2_16
1203 #define RT5659_I2S_BCLK_MS3_MASK
1204 #define RT5659_I2S_BCLK_MS3_SFT
1205 #define RT5659_I2S_BCLK_MS3_32
1206 #define RT5659_I2S_BCLK_MS3_64
1207 #define RT5659_I2S_PD3_MASK
1208 #define RT5659_I2S_PD3_SFT
1209 #define RT5659_I2S_PD3_1
1210 #define RT5659_I2S_PD3_2
1211 #define RT5659_I2S_PD3_3
1212 #define RT5659_I2S_PD3_4
1213 #define RT5659_I2S_PD3_6
1214 #define RT5659_I2S_PD3_8
1215 #define RT5659_I2S_PD3_12
1216 #define RT5659_I2S_PD3_16
1217 #define RT5659_DAC_OSR_MASK
1218 #define RT5659_DAC_OSR_SFT
1219 #define RT5659_DAC_OSR_128
1220 #define RT5659_DAC_OSR_64
1221 #define RT5659_DAC_OSR_32
1222 #define RT5659_DAC_OSR_16
1223 #define RT5659_ADC_OSR_MASK
1224 #define RT5659_ADC_OSR_SFT
1225 #define RT5659_ADC_OSR_128
1226 #define RT5659_ADC_OSR_64
1227 #define RT5659_ADC_OSR_32
1228 #define RT5659_ADC_OSR_16
1229
1230 /* Digital Microphone Control (0x0075) */
1231 #define RT5659_DMIC_1_EN_MASK
1232 #define RT5659_DMIC_1_EN_SFT
1233 #define RT5659_DMIC_1_DIS
1234 #define RT5659_DMIC_1_EN
1235 #define RT5659_DMIC_2_EN_MASK
1236 #define RT5659_DMIC_2_EN_SFT
1237 #define RT5659_DMIC_2_DIS
1238 #define RT5659_DMIC_2_EN
1239 #define RT5659_DMIC_1L_LH_MASK
1240 #define RT5659_DMIC_1L_LH_SFT
1241 #define RT5659_DMIC_1L_LH_RISING
1242 #define RT5659_DMIC_1L_LH_FALLING
1243 #define RT5659_DMIC_1R_LH_MASK
1244 #define RT5659_DMIC_1R_LH_SFT
1245 #define RT5659_DMIC_1R_LH_RISING
1246 #define RT5659_DMIC_1R_LH_FALLING
1247 #define RT5659_DMIC_2_DP_MASK
1248 #define RT5659_DMIC_2_DP_SFT
1249 #define RT5659_DMIC_2_DP_GPIO6
1250 #define RT5659_DMIC_2_DP_GPIO10
1251 #define RT5659_DMIC_2_DP_GPIO12
1252 #define RT5659_DMIC_2_DP_IN2P
1253 #define RT5659_DMIC_CLK_MASK
1254 #define RT5659_DMIC_CLK_SFT
1255 #define RT5659_DMIC_1_DP_MASK
1256 #define RT5659_DMIC_1_DP_SFT
1257 #define RT5659_DMIC_1_DP_GPIO5
1258 #define RT5659_DMIC_1_DP_GPIO9
1259 #define RT5659_DMIC_1_DP_GPIO11
1260 #define RT5659_DMIC_1_DP_IN2N
1261
1262 /* TDM control 1 (0x0078)*/
1263 #define RT5659_DS_ADC_SLOT01_SFT
1264 #define RT5659_DS_ADC_SLOT23_SFT
1265 #define RT5659_DS_ADC_SLOT45_SFT
1266 #define RT5659_DS_ADC_SLOT67_SFT
1267 #define RT5659_ADCDAT_SRC_MASK
1268 #define RT5659_ADCDAT_SRC_SFT
1269
1270 /* Global Clock Control (0x0080) */
1271 #define RT5659_SCLK_SRC_MASK
1272 #define RT5659_SCLK_SRC_SFT
1273 #define RT5659_SCLK_SRC_MCLK
1274 #define RT5659_SCLK_SRC_PLL1
1275 #define RT5659_SCLK_SRC_RCCLK
1276 #define RT5659_PLL1_SRC_MASK
1277 #define RT5659_PLL1_SRC_SFT
1278 #define RT5659_PLL1_SRC_MCLK
1279 #define RT5659_PLL1_SRC_BCLK1
1280 #define RT5659_PLL1_SRC_BCLK2
1281 #define RT5659_PLL1_SRC_BCLK3
1282 #define RT5659_PLL1_PD_MASK
1283 #define RT5659_PLL1_PD_SFT
1284 #define RT5659_PLL1_PD_1
1285 #define RT5659_PLL1_PD_2
1286
1287 #define RT5659_PLL_INP_MAX
1288 #define RT5659_PLL_INP_MIN
1289 /* PLL M/N/K Code Control 1 (0x0081) */
1290 #define RT5659_PLL_N_MAX
1291 #define RT5659_PLL_N_MASK
1292 #define RT5659_PLL_N_SFT
1293 #define RT5659_PLL_K_MAX
1294 #define RT5659_PLL_K_MASK
1295 #define RT5659_PLL_K_SFT
1296
1297 /* PLL M/N/K Code Control 2 (0x0082) */
1298 #define RT5659_PLL_M_MAX
1299 #define RT5659_PLL_M_MASK
1300 #define RT5659_PLL_M_SFT
1301 #define RT5659_PLL_M_BP
1302 #define RT5659_PLL_M_BP_SFT
1303
1304 /* PLL tracking mode 1 (0x0083) */
1305 #define RT5659_I2S3_ASRC_MASK
1306 #define RT5659_I2S3_ASRC_SFT
1307 #define RT5659_I2S2_ASRC_MASK
1308 #define RT5659_I2S2_ASRC_SFT
1309 #define RT5659_I2S1_ASRC_MASK
1310 #define RT5659_I2S1_ASRC_SFT
1311 #define RT5659_DAC_STO_ASRC_MASK
1312 #define RT5659_DAC_STO_ASRC_SFT
1313 #define RT5659_DAC_MONO_L_ASRC_MASK
1314 #define RT5659_DAC_MONO_L_ASRC_SFT
1315 #define RT5659_DAC_MONO_R_ASRC_MASK
1316 #define RT5659_DAC_MONO_R_ASRC_SFT
1317 #define RT5659_DMIC_STO1_ASRC_MASK
1318 #define RT5659_DMIC_STO1_ASRC_SFT
1319 #define RT5659_DMIC_MONO_L_ASRC_MASK
1320 #define RT5659_DMIC_MONO_L_ASRC_SFT
1321 #define RT5659_DMIC_MONO_R_ASRC_MASK
1322 #define RT5659_DMIC_MONO_R_ASRC_SFT
1323 #define RT5659_ADC_STO1_ASRC_MASK
1324 #define RT5659_ADC_STO1_ASRC_SFT
1325 #define RT5659_ADC_MONO_L_ASRC_MASK
1326 #define RT5659_ADC_MONO_L_ASRC_SFT
1327 #define RT5659_ADC_MONO_R_ASRC_MASK
1328 #define RT5659_ADC_MONO_R_ASRC_SFT
1329
1330 /* PLL tracking mode 2 (0x0084)*/
1331 #define RT5659_DA_STO_T_MASK
1332 #define RT5659_DA_STO_T_SFT
1333 #define RT5659_DA_MONO_L_T_MASK
1334 #define RT5659_DA_MONO_L_T_SFT
1335 #define RT5659_DA_MONO_R_T_MASK
1336 #define RT5659_DA_MONO_R_T_SFT
1337 #define RT5659_AD_STO1_T_MASK
1338 #define RT5659_AD_STO1_T_SFT
1339
1340 /* PLL tracking mode 3 (0x0085)*/
1341 #define RT5659_AD_STO2_T_MASK
1342 #define RT5659_AD_STO2_T_SFT
1343 #define RT5659_AD_MONO_L_T_MASK
1344 #define RT5659_AD_MONO_L_T_SFT
1345 #define RT5659_AD_MONO_R_T_MASK
1346 #define RT5659_AD_MONO_R_T_SFT
1347
1348 /* ASRC Control 4 (0x0086) */
1349 #define RT5659_I2S1_RATE_MASK
1350 #define RT5659_I2S1_RATE_SFT
1351 #define RT5659_I2S2_RATE_MASK
1352 #define RT5659_I2S2_RATE_SFT
1353 #define RT5659_I2S3_RATE_MASK
1354 #define RT5659_I2S3_RATE_SFT
1355
1356 /* Depop Mode Control 1 (0x8e) */
1357 #define RT5659_SMT_TRIG_MASK
1358 #define RT5659_SMT_TRIG_SFT
1359 #define RT5659_SMT_TRIG_DIS
1360 #define RT5659_SMT_TRIG_EN
1361 #define RT5659_HP_L_SMT_MASK
1362 #define RT5659_HP_L_SMT_SFT
1363 #define RT5659_HP_L_SMT_DIS
1364 #define RT5659_HP_L_SMT_EN
1365 #define RT5659_HP_R_SMT_MASK
1366 #define RT5659_HP_R_SMT_SFT
1367 #define RT5659_HP_R_SMT_DIS
1368 #define RT5659_HP_R_SMT_EN
1369 #define RT5659_HP_CD_PD_MASK
1370 #define RT5659_HP_CD_PD_SFT
1371 #define RT5659_HP_CD_PD_DIS
1372 #define RT5659_HP_CD_PD_EN
1373 #define RT5659_RSTN_MASK
1374 #define RT5659_RSTN_SFT
1375 #define RT5659_RSTN_DIS
1376 #define RT5659_RSTN_EN
1377 #define RT5659_RSTP_MASK
1378 #define RT5659_RSTP_SFT
1379 #define RT5659_RSTP_DIS
1380 #define RT5659_RSTP_EN
1381 #define RT5659_HP_CO_MASK
1382 #define RT5659_HP_CO_SFT
1383 #define RT5659_HP_CO_DIS
1384 #define RT5659_HP_CO_EN
1385 #define RT5659_HP_CP_MASK
1386 #define RT5659_HP_CP_SFT
1387 #define RT5659_HP_CP_PD
1388 #define RT5659_HP_CP_PU
1389 #define RT5659_HP_SG_MASK
1390 #define RT5659_HP_SG_SFT
1391 #define RT5659_HP_SG_DIS
1392 #define RT5659_HP_SG_EN
1393 #define RT5659_HP_DP_MASK
1394 #define RT5659_HP_DP_SFT
1395 #define RT5659_HP_DP_PD
1396 #define RT5659_HP_DP_PU
1397 #define RT5659_HP_CB_MASK
1398 #define RT5659_HP_CB_SFT
1399 #define RT5659_HP_CB_PD
1400 #define RT5659_HP_CB_PU
1401
1402 /* Depop Mode Control 2 (0x8f) */
1403 #define RT5659_DEPOP_MASK
1404 #define RT5659_DEPOP_SFT
1405 #define RT5659_DEPOP_AUTO
1406 #define RT5659_DEPOP_MAN
1407 #define RT5659_RAMP_MASK
1408 #define RT5659_RAMP_SFT
1409 #define RT5659_RAMP_DIS
1410 #define RT5659_RAMP_EN
1411 #define RT5659_BPS_MASK
1412 #define RT5659_BPS_SFT
1413 #define RT5659_BPS_DIS
1414 #define RT5659_BPS_EN
1415 #define RT5659_FAST_UPDN_MASK
1416 #define RT5659_FAST_UPDN_SFT
1417 #define RT5659_FAST_UPDN_DIS
1418 #define RT5659_FAST_UPDN_EN
1419 #define RT5659_MRES_MASK
1420 #define RT5659_MRES_SFT
1421 #define RT5659_MRES_15MO
1422 #define RT5659_MRES_25MO
1423 #define RT5659_MRES_35MO
1424 #define RT5659_MRES_45MO
1425 #define RT5659_VLO_MASK
1426 #define RT5659_VLO_SFT
1427 #define RT5659_VLO_3V
1428 #define RT5659_VLO_32V
1429 #define RT5659_DIG_DP_MASK
1430 #define RT5659_DIG_DP_SFT
1431 #define RT5659_DIG_DP_DIS
1432 #define RT5659_DIG_DP_EN
1433 #define RT5659_DP_TH_MASK
1434 #define RT5659_DP_TH_SFT
1435
1436 /* Depop Mode Control 3 (0x90) */
1437 #define RT5659_CP_SYS_MASK
1438 #define RT5659_CP_SYS_SFT
1439 #define RT5659_CP_FQ1_MASK
1440 #define RT5659_CP_FQ1_SFT
1441 #define RT5659_CP_FQ2_MASK
1442 #define RT5659_CP_FQ2_SFT
1443 #define RT5659_CP_FQ3_MASK
1444 #define RT5659_CP_FQ3_SFT
1445 #define RT5659_CP_FQ_1_5_KHZ
1446 #define RT5659_CP_FQ_3_KHZ
1447 #define RT5659_CP_FQ_6_KHZ
1448 #define RT5659_CP_FQ_12_KHZ
1449 #define RT5659_CP_FQ_24_KHZ
1450 #define RT5659_CP_FQ_48_KHZ
1451 #define RT5659_CP_FQ_96_KHZ
1452 #define RT5659_CP_FQ_192_KHZ
1453
1454 /* HPOUT charge pump 1 (0x0091) */
1455 #define RT5659_OSW_L_MASK
1456 #define RT5659_OSW_L_SFT
1457 #define RT5659_OSW_L_DIS
1458 #define RT5659_OSW_L_EN
1459 #define RT5659_OSW_R_MASK
1460 #define RT5659_OSW_R_SFT
1461 #define RT5659_OSW_R_DIS
1462 #define RT5659_OSW_R_EN
1463 #define RT5659_PM_HP_MASK
1464 #define RT5659_PM_HP_SFT
1465 #define RT5659_PM_HP_LV
1466 #define RT5659_PM_HP_MV
1467 #define RT5659_PM_HP_HV
1468 #define RT5659_IB_HP_MASK
1469 #define RT5659_IB_HP_SFT
1470 #define RT5659_IB_HP_125IL
1471 #define RT5659_IB_HP_25IL
1472 #define RT5659_IB_HP_5IL
1473 #define RT5659_IB_HP_1IL
1474
1475 /* PV detection and SPK gain control (0x92) *
1476 #define RT5659_PVDD_DET_MASK
1477 #define RT5659_PVDD_DET_SFT
1478 #define RT5659_PVDD_DET_DIS
1479 #define RT5659_PVDD_DET_EN
1480 #define RT5659_SPK_AG_MASK
1481 #define RT5659_SPK_AG_SFT
1482 #define RT5659_SPK_AG_DIS
1483 #define RT5659_SPK_AG_EN
1484
1485 /* Micbias Control (0x93) */
1486 #define RT5659_MIC1_BS_MASK
1487 #define RT5659_MIC1_BS_SFT
1488 #define RT5659_MIC1_BS_9AV
1489 #define RT5659_MIC1_BS_75AV
1490 #define RT5659_MIC2_BS_MASK
1491 #define RT5659_MIC2_BS_SFT
1492 #define RT5659_MIC2_BS_9AV
1493 #define RT5659_MIC2_BS_75AV
1494 #define RT5659_MIC1_CLK_MASK
1495 #define RT5659_MIC1_CLK_SFT
1496 #define RT5659_MIC1_CLK_DIS
1497 #define RT5659_MIC1_CLK_EN
1498 #define RT5659_MIC2_CLK_MASK
1499 #define RT5659_MIC2_CLK_SFT
1500 #define RT5659_MIC2_CLK_DIS
1501 #define RT5659_MIC2_CLK_EN
1502 #define RT5659_MIC1_OVCD_MASK
1503 #define RT5659_MIC1_OVCD_SFT
1504 #define RT5659_MIC1_OVCD_DIS
1505 #define RT5659_MIC1_OVCD_EN
1506 #define RT5659_MIC1_OVTH_MASK
1507 #define RT5659_MIC1_OVTH_SFT
1508 #define RT5659_MIC1_OVTH_600UA
1509 #define RT5659_MIC1_OVTH_1500UA
1510 #define RT5659_MIC1_OVTH_2000UA
1511 #define RT5659_MIC2_OVCD_MASK
1512 #define RT5659_MIC2_OVCD_SFT
1513 #define RT5659_MIC2_OVCD_DIS
1514 #define RT5659_MIC2_OVCD_EN
1515 #define RT5659_MIC2_OVTH_MASK
1516 #define RT5659_MIC2_OVTH_SFT
1517 #define RT5659_MIC2_OVTH_600UA
1518 #define RT5659_MIC2_OVTH_1500UA
1519 #define RT5659_MIC2_OVTH_2000UA
1520 #define RT5659_PWR_MB_MASK
1521 #define RT5659_PWR_MB_SFT
1522 #define RT5659_PWR_MB_PD
1523 #define RT5659_PWR_MB_PU
1524 #define RT5659_PWR_CLK25M_MASK
1525 #define RT5659_PWR_CLK25M_SFT
1526 #define RT5659_PWR_CLK25M_PD
1527 #define RT5659_PWR_CLK25M_PU
1528
1529 /* REC Mixer 2 Left Control 2 (0x009c) */
1530 #define RT5659_M_BST1_RM2_L
1531 #define RT5659_M_BST1_RM2_L_SFT
1532 #define RT5659_M_BST2_RM2_L
1533 #define RT5659_M_BST2_RM2_L_SFT
1534 #define RT5659_M_BST3_RM2_L
1535 #define RT5659_M_BST3_RM2_L_SFT
1536 #define RT5659_M_BST4_RM2_L
1537 #define RT5659_M_BST4_RM2_L_SFT
1538 #define RT5659_M_OUTVOLL_RM2_L
1539 #define RT5659_M_OUTVOLL_RM2_L_SFT
1540 #define RT5659_M_SPKVOL_RM2_L
1541 #define RT5659_M_SPKVOL_RM2_L_SFT
1542
1543 /* REC Mixer 2 Right Control 2 (0x009e) */
1544 #define RT5659_M_BST1_RM2_R
1545 #define RT5659_M_BST1_RM2_R_SFT
1546 #define RT5659_M_BST2_RM2_R
1547 #define RT5659_M_BST2_RM2_R_SFT
1548 #define RT5659_M_BST3_RM2_R
1549 #define RT5659_M_BST3_RM2_R_SFT
1550 #define RT5659_M_BST4_RM2_R
1551 #define RT5659_M_BST4_RM2_R_SFT
1552 #define RT5659_M_OUTVOLR_RM2_R
1553 #define RT5659_M_OUTVOLR_RM2_R_SFT
1554 #define RT5659_M_MONOVOL_RM2_R
1555 #define RT5659_M_MONOVOL_RM2_R_SFT
1556
1557 /* Class D Output Control (0x00a0) */
1558 #define RT5659_POW_CLSD_DB_MASK
1559 #define RT5659_POW_CLSD_DB_EN
1560 #define RT5659_POW_CLSD_DB_DIS
1561
1562 /* EQ Control 1 (0x00b0) */
1563 #define RT5659_EQ_SRC_DAC
1564 #define RT5659_EQ_SRC_ADC
1565 #define RT5659_EQ_UPD
1566 #define RT5659_EQ_UPD_BIT
1567 #define RT5659_EQ_CD_MASK
1568 #define RT5659_EQ_CD_SFT
1569 #define RT5659_EQ_CD_DIS
1570 #define RT5659_EQ_CD_EN
1571 #define RT5659_EQ_DITH_MASK
1572 #define RT5659_EQ_DITH_SFT
1573 #define RT5659_EQ_DITH_NOR
1574 #define RT5659_EQ_DITH_LSB
1575 #define RT5659_EQ_DITH_LSB_1
1576 #define RT5659_EQ_DITH_LSB_2
1577
1578 /* IRQ Control 1 (0x00b7) */
1579 #define RT5659_JD1_1_EN_MASK
1580 #define RT5659_JD1_1_EN_SFT
1581 #define RT5659_JD1_1_DIS
1582 #define RT5659_JD1_1_EN
1583 #define RT5659_JD1_2_EN_MASK
1584 #define RT5659_JD1_2_EN_SFT
1585 #define RT5659_JD1_2_DIS
1586 #define RT5659_JD1_2_EN
1587 #define RT5659_IL_IRQ_MASK
1588 #define RT5659_IL_IRQ_DIS
1589 #define RT5659_IL_IRQ_EN
1590
1591 /* IRQ Control 5 (0x00ba) */
1592 #define RT5659_IRQ_JD_EN
1593 #define RT5659_IRQ_JD_EN_SFT
1594
1595 /* GPIO Control 1 (0x00c0) */
1596 #define RT5659_GP1_PIN_MASK
1597 #define RT5659_GP1_PIN_SFT
1598 #define RT5659_GP1_PIN_GPIO1
1599 #define RT5659_GP1_PIN_IRQ
1600 #define RT5659_GP2_PIN_MASK
1601 #define RT5659_GP2_PIN_SFT
1602 #define RT5659_GP2_PIN_GPIO2
1603 #define RT5659_GP2_PIN_DMIC1_SCL
1604 #define RT5659_GP3_PIN_MASK
1605 #define RT5659_GP3_PIN_SFT
1606 #define RT5659_GP3_PIN_GPIO3
1607 #define RT5659_GP3_PIN_PDM_SCL
1608 #define RT5659_GP4_PIN_MASK
1609 #define RT5659_GP4_PIN_SFT
1610 #define RT5659_GP4_PIN_GPIO4
1611 #define RT5659_GP4_PIN_PDM_SDA
1612 #define RT5659_GP5_PIN_MASK
1613 #define RT5659_GP5_PIN_SFT
1614 #define RT5659_GP5_PIN_GPIO5
1615 #define RT5659_GP5_PIN_DMIC1_SDA
1616 #define RT5659_GP6_PIN_MASK
1617 #define RT5659_GP6_PIN_SFT
1618 #define RT5659_GP6_PIN_GPIO6
1619 #define RT5659_GP6_PIN_DMIC2_SDA
1620 #define RT5659_GP7_PIN_MASK
1621 #define RT5659_GP7_PIN_SFT
1622 #define RT5659_GP7_PIN_GPIO7
1623 #define RT5659_GP7_PIN_PDM_SCL
1624 #define RT5659_GP8_PIN_MASK
1625 #define RT5659_GP8_PIN_SFT
1626 #define RT5659_GP8_PIN_GPIO8
1627 #define RT5659_GP8_PIN_PDM_SDA
1628 #define RT5659_GP9_PIN_MASK
1629 #define RT5659_GP9_PIN_SFT
1630 #define RT5659_GP9_PIN_GPIO9
1631 #define RT5659_GP9_PIN_DMIC1_SDA
1632 #define RT5659_GP10_PIN_MASK
1633 #define RT5659_GP10_PIN_SFT
1634 #define RT5659_GP10_PIN_GPIO10
1635 #define RT5659_GP10_PIN_DMIC2_SDA
1636 #define RT5659_GP11_PIN_MASK
1637 #define RT5659_GP11_PIN_SFT
1638 #define RT5659_GP11_PIN_GPIO11
1639 #define RT5659_GP11_PIN_DMIC1_SDA
1640 #define RT5659_GP12_PIN_MASK
1641 #define RT5659_GP12_PIN_SFT
1642 #define RT5659_GP12_PIN_GPIO12
1643 #define RT5659_GP12_PIN_DMIC2_SDA
1644 #define RT5659_GP13_PIN_MASK
1645 #define RT5659_GP13_PIN_SFT
1646 #define RT5659_GP13_PIN_GPIO13
1647 #define RT5659_GP13_PIN_SPDIF_SDA
1648 #define RT5659_GP13_PIN_DMIC2_SCL
1649 #define RT5659_GP13_PIN_PDM_SCL
1650 #define RT5659_GP15_PIN_MASK
1651 #define RT5659_GP15_PIN_SFT
1652 #define RT5659_GP15_PIN_GPIO15
1653 #define RT5659_GP15_PIN_DMIC3_SCL
1654 #define RT5659_GP15_PIN_PDM_SDA
1655
1656 /* GPIO Control 2 (0x00c1)*/
1657 #define RT5659_GP1_PF_IN
1658 #define RT5659_GP1_PF_OUT
1659 #define RT5659_GP1_PF_MASK
1660 #define RT5659_GP1_PF_SFT
1661
1662 /* GPIO Control 3 (0x00c2) */
1663 #define RT5659_I2S2_PIN_MASK
1664 #define RT5659_I2S2_PIN_SFT
1665 #define RT5659_I2S2_PIN_I2S
1666 #define RT5659_I2S2_PIN_GPIO
1667
1668 /* Soft volume and zero cross control 1 (0x00
1669 #define RT5659_SV_MASK
1670 #define RT5659_SV_SFT
1671 #define RT5659_SV_DIS
1672 #define RT5659_SV_EN
1673 #define RT5659_OUT_SV_MASK
1674 #define RT5659_OUT_SV_SFT
1675 #define RT5659_OUT_SV_DIS
1676 #define RT5659_OUT_SV_EN
1677 #define RT5659_HP_SV_MASK
1678 #define RT5659_HP_SV_SFT
1679 #define RT5659_HP_SV_DIS
1680 #define RT5659_HP_SV_EN
1681 #define RT5659_ZCD_DIG_MASK
1682 #define RT5659_ZCD_DIG_SFT
1683 #define RT5659_ZCD_DIG_DIS
1684 #define RT5659_ZCD_DIG_EN
1685 #define RT5659_ZCD_MASK
1686 #define RT5659_ZCD_SFT
1687 #define RT5659_ZCD_PD
1688 #define RT5659_ZCD_PU
1689 #define RT5659_SV_DLY_MASK
1690 #define RT5659_SV_DLY_SFT
1691
1692 /* Soft volume and zero cross control 2 (0x00
1693 #define RT5659_ZCD_HP_MASK
1694 #define RT5659_ZCD_HP_SFT
1695 #define RT5659_ZCD_HP_DIS
1696 #define RT5659_ZCD_HP_EN
1697
1698 /* 4 Button Inline Command Control 2 (0x00e0)
1699 #define RT5659_4BTN_IL_MASK
1700 #define RT5659_4BTN_IL_EN
1701 #define RT5659_4BTN_IL_DIS
1702
1703 /* Analog JD Control 1 (0x00f0) */
1704 #define RT5659_JD1_MODE_MASK
1705 #define RT5659_JD1_MODE_0
1706 #define RT5659_JD1_MODE_1
1707 #define RT5659_JD1_MODE_2
1708
1709 /* Jack Detect Control 3 (0x00f8) */
1710 #define RT5659_JD_TRI_HPO_SEL_MASK
1711 #define RT5659_JD_TRI_HPO_SEL_SFT
1712 #define RT5659_JD_HPO_GPIO_JD1
1713 #define RT5659_JD_HPO_JD1_1
1714 #define RT5659_JD_HPO_JD1_2
1715 #define RT5659_JD_HPO_JD2
1716 #define RT5659_JD_HPO_GPIO_JD2
1717 #define RT5659_JD_HPO_JD3
1718 #define RT5659_JD_HPO_JD_D
1719
1720 /* Digital Misc Control (0x00fa) */
1721 #define RT5659_AM_MASK
1722 #define RT5659_AM_EN
1723 #define RT5659_AM_DIS
1724 #define RT5659_DIG_GATE_CTRL
1725 #define RT5659_DIG_GATE_CTRL_SFT
1726
1727 /* Chopper and Clock control for ADC (0x011c)
1728 #define RT5659_M_RF_DIG_MASK
1729 #define RT5659_M_RF_DIG_SFT
1730 #define RT5659_M_RI_DIG
1731
1732 /* Chopper and Clock control for DAC (0x013a)
1733 #define RT5659_CKXEN_DAC1_MASK
1734 #define RT5659_CKXEN_DAC1_SFT
1735 #define RT5659_CKGEN_DAC1_MASK
1736 #define RT5659_CKGEN_DAC1_SFT
1737 #define RT5659_CKXEN_DAC2_MASK
1738 #define RT5659_CKXEN_DAC2_SFT
1739 #define RT5659_CKGEN_DAC2_MASK
1740 #define RT5659_CKGEN_DAC2_SFT
1741
1742 /* Chopper and Clock control for ADC (0x013b)
1743 #define RT5659_CKXEN_ADC1_MASK
1744 #define RT5659_CKXEN_ADC1_SFT
1745 #define RT5659_CKGEN_ADC1_MASK
1746 #define RT5659_CKGEN_ADC1_SFT
1747 #define RT5659_CKXEN_ADC2_MASK
1748 #define RT5659_CKXEN_ADC2_SFT
1749 #define RT5659_CKGEN_ADC2_MASK
1750 #define RT5659_CKGEN_ADC2_SFT
1751
1752 /* Test Mode Control 1 (0x0145) */
1753 #define RT5659_AD2DA_LB_MASK
1754 #define RT5659_AD2DA_LB_SFT
1755
1756 /* Stereo Noise Gate Control 1 (0x0160) */
1757 #define RT5659_NG2_EN_MASK
1758 #define RT5659_NG2_EN
1759 #define RT5659_NG2_DIS
1760
1761 /* System Clock Source */
1762 enum {
1763 RT5659_SCLK_S_MCLK,
1764 RT5659_SCLK_S_PLL1,
1765 RT5659_SCLK_S_RCCLK,
1766 };
1767
1768 /* PLL1 Source */
1769 enum {
1770 RT5659_PLL1_S_MCLK,
1771 RT5659_PLL1_S_BCLK1,
1772 RT5659_PLL1_S_BCLK2,
1773 RT5659_PLL1_S_BCLK3,
1774 RT5659_PLL1_S_BCLK4,
1775 };
1776
1777 enum {
1778 RT5659_AIF1,
1779 RT5659_AIF2,
1780 RT5659_AIF3,
1781 RT5659_AIF4,
1782 RT5659_AIFS,
1783 };
1784
1785 struct rt5659_pll_code {
1786 bool m_bp;
1787 int m_code;
1788 int n_code;
1789 int k_code;
1790 };
1791
1792 struct rt5659_priv {
1793 struct snd_soc_component *component;
1794 struct rt5659_platform_data pdata;
1795 struct regmap *regmap;
1796 struct gpio_desc *gpiod_ldo1_en;
1797 struct gpio_desc *gpiod_reset;
1798 struct snd_soc_jack *hs_jack;
1799 struct delayed_work jack_detect_work;
1800 struct clk *mclk;
1801
1802 int sysclk;
1803 int sysclk_src;
1804 int lrck[RT5659_AIFS];
1805 int bclk[RT5659_AIFS];
1806 int master[RT5659_AIFS];
1807 int v_id;
1808
1809 int pll_src;
1810 int pll_in;
1811 int pll_out;
1812
1813 int jack_type;
1814 bool hda_hp_plugged;
1815 bool hda_mic_plugged;
1816 };
1817
1818 int rt5659_set_jack_detect(struct snd_soc_com
1819 struct snd_soc_jack *hs_jack);
1820
1821 #endif /* __RT5659_H__ */
1822
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