1 /* SPDX-License-Identifier: GPL-2.0-only */ 1
2 /*
3 * rt5665.h -- RT5665/RT5658 ALSA SoC audio
4 *
5 * Copyright 2016 Realtek Microelectronics
6 * Author: Bard Liao <bardliao@realtek.com>
7 */
8
9 #ifndef __RT5665_H__
10 #define __RT5665_H__
11
12 #include <sound/rt5665.h>
13
14 #define DEVICE_ID 0x6451
15
16 /* Info */
17 #define RT5665_RESET
18 #define RT5665_VENDOR_ID
19 #define RT5665_VENDOR_ID_1
20 #define RT5665_DEVICE_ID
21 /* I/O - Output */
22 #define RT5665_LOUT
23 #define RT5665_HP_CTRL_1
24 #define RT5665_HP_CTRL_2
25 #define RT5665_MONO_OUT
26 #define RT5665_HPL_GAIN
27 #define RT5665_HPR_GAIN
28 #define RT5665_MONO_GAIN
29
30 /* I/O - Input */
31 #define RT5665_CAL_BST_CTRL
32 #define RT5665_CBJ_BST_CTRL
33 #define RT5665_IN1_IN2
34 #define RT5665_IN3_IN4
35 #define RT5665_INL1_INR1_VOL
36 /* I/O - Speaker */
37 #define RT5665_EJD_CTRL_1
38 #define RT5665_EJD_CTRL_2
39 #define RT5665_EJD_CTRL_3
40 #define RT5665_EJD_CTRL_4
41 #define RT5665_EJD_CTRL_5
42 #define RT5665_EJD_CTRL_6
43 #define RT5665_EJD_CTRL_7
44 /* I/O - ADC/DAC/DMIC */
45 #define RT5665_DAC2_CTRL
46 #define RT5665_DAC2_DIG_VOL
47 #define RT5665_DAC1_DIG_VOL
48 #define RT5665_DAC3_DIG_VOL
49 #define RT5665_DAC3_CTRL
50 #define RT5665_STO1_ADC_DIG_VOL
51 #define RT5665_MONO_ADC_DIG_VOL
52 #define RT5665_STO2_ADC_DIG_VOL
53 #define RT5665_STO1_ADC_BOOST
54 #define RT5665_MONO_ADC_BOOST
55 #define RT5665_STO2_ADC_BOOST
56 #define RT5665_HP_IMP_GAIN_1
57 #define RT5665_HP_IMP_GAIN_2
58 /* Mixer - D-D */
59 #define RT5665_STO1_ADC_MIXER
60 #define RT5665_MONO_ADC_MIXER
61 #define RT5665_STO2_ADC_MIXER
62 #define RT5665_AD_DA_MIXER
63 #define RT5665_STO1_DAC_MIXER
64 #define RT5665_MONO_DAC_MIXER
65 #define RT5665_STO2_DAC_MIXER
66 #define RT5665_A_DAC1_MUX
67 #define RT5665_A_DAC2_MUX
68 #define RT5665_DIG_INF2_DATA
69 #define RT5665_DIG_INF3_DATA
70 /* Mixer - PDM */
71 #define RT5665_PDM_OUT_CTRL
72 #define RT5665_PDM_DATA_CTRL_1
73 #define RT5665_PDM_DATA_CTRL_2
74 #define RT5665_PDM_DATA_CTRL_3
75 #define RT5665_PDM_DATA_CTRL_4
76 /* Mixer - ADC */
77 #define RT5665_REC1_GAIN
78 #define RT5665_REC1_L1_MIXER
79 #define RT5665_REC1_L2_MIXER
80 #define RT5665_REC1_R1_MIXER
81 #define RT5665_REC1_R2_MIXER
82 #define RT5665_REC2_GAIN
83 #define RT5665_REC2_L1_MIXER
84 #define RT5665_REC2_L2_MIXER
85 #define RT5665_REC2_R1_MIXER
86 #define RT5665_REC2_R2_MIXER
87 #define RT5665_CAL_REC
88 /* Mixer - DAC */
89 #define RT5665_ALC_BACK_GAIN
90 #define RT5665_MONOMIX_GAIN
91 #define RT5665_MONOMIX_IN_GAIN
92 #define RT5665_OUT_L_GAIN
93 #define RT5665_OUT_L_MIXER
94 #define RT5665_OUT_R_GAIN
95 #define RT5665_OUT_R_MIXER
96 #define RT5665_LOUT_MIXER
97 /* Power */
98 #define RT5665_PWR_DIG_1
99 #define RT5665_PWR_DIG_2
100 #define RT5665_PWR_ANLG_1
101 #define RT5665_PWR_ANLG_2
102 #define RT5665_PWR_ANLG_3
103 #define RT5665_PWR_MIXER
104 #define RT5665_PWR_VOL
105 /* Clock Detect */
106 #define RT5665_CLK_DET
107 /* Filter */
108 #define RT5665_HPF_CTRL1
109 /* DMIC */
110 #define RT5665_DMIC_CTRL_1
111 #define RT5665_DMIC_CTRL_2
112 /* Format - ADC/DAC */
113 #define RT5665_I2S1_SDP
114 #define RT5665_I2S2_SDP
115 #define RT5665_I2S3_SDP
116 #define RT5665_ADDA_CLK_1
117 #define RT5665_ADDA_CLK_2
118 #define RT5665_I2S1_F_DIV_CTRL_1
119 #define RT5665_I2S1_F_DIV_CTRL_2
120 /* Format - TDM Control */
121 #define RT5665_TDM_CTRL_1
122 #define RT5665_TDM_CTRL_2
123 #define RT5665_TDM_CTRL_3
124 #define RT5665_TDM_CTRL_4
125 #define RT5665_TDM_CTRL_5
126 #define RT5665_TDM_CTRL_6
127 #define RT5665_TDM_CTRL_7
128 #define RT5665_TDM_CTRL_8
129 /* Function - Analog */
130 #define RT5665_GLB_CLK
131 #define RT5665_PLL_CTRL_1
132 #define RT5665_PLL_CTRL_2
133 #define RT5665_ASRC_1
134 #define RT5665_ASRC_2
135 #define RT5665_ASRC_3
136 #define RT5665_ASRC_4
137 #define RT5665_ASRC_5
138 #define RT5665_ASRC_6
139 #define RT5665_ASRC_7
140 #define RT5665_ASRC_8
141 #define RT5665_ASRC_9
142 #define RT5665_ASRC_10
143 #define RT5665_DEPOP_1
144 #define RT5665_DEPOP_2
145 #define RT5665_HP_CHARGE_PUMP_1
146 #define RT5665_HP_CHARGE_PUMP_2
147 #define RT5665_MICBIAS_1
148 #define RT5665_MICBIAS_2
149 #define RT5665_ASRC_12
150 #define RT5665_ASRC_13
151 #define RT5665_ASRC_14
152 #define RT5665_RC_CLK_CTRL
153 #define RT5665_I2S_M_CLK_CTRL_1
154 #define RT5665_I2S2_F_DIV_CTRL_1
155 #define RT5665_I2S2_F_DIV_CTRL_2
156 #define RT5665_I2S3_F_DIV_CTRL_1
157 #define RT5665_I2S3_F_DIV_CTRL_2
158 /* Function - Digital */
159 #define RT5665_EQ_CTRL_1
160 #define RT5665_EQ_CTRL_2
161 #define RT5665_IRQ_CTRL_1
162 #define RT5665_IRQ_CTRL_2
163 #define RT5665_IRQ_CTRL_3
164 #define RT5665_IRQ_CTRL_4
165 #define RT5665_IRQ_CTRL_5
166 #define RT5665_IRQ_CTRL_6
167 #define RT5665_INT_ST_1
168 #define RT5665_GPIO_CTRL_1
169 #define RT5665_GPIO_CTRL_2
170 #define RT5665_GPIO_CTRL_3
171 #define RT5665_GPIO_CTRL_4
172 #define RT5665_GPIO_STA
173 #define RT5665_HP_AMP_DET_CTRL_1
174 #define RT5665_HP_AMP_DET_CTRL_2
175 #define RT5665_MID_HP_AMP_DET
176 #define RT5665_LOW_HP_AMP_DET
177 #define RT5665_SV_ZCD_1
178 #define RT5665_SV_ZCD_2
179 #define RT5665_IL_CMD_1
180 #define RT5665_IL_CMD_2
181 #define RT5665_IL_CMD_3
182 #define RT5665_IL_CMD_4
183 #define RT5665_4BTN_IL_CMD_1
184 #define RT5665_4BTN_IL_CMD_2
185 #define RT5665_4BTN_IL_CMD_3
186 #define RT5665_PSV_IL_CMD_1
187
188 #define RT5665_ADC_STO1_HP_CTRL_1
189 #define RT5665_ADC_STO1_HP_CTRL_2
190 #define RT5665_ADC_MONO_HP_CTRL_1
191 #define RT5665_ADC_MONO_HP_CTRL_2
192 #define RT5665_ADC_STO2_HP_CTRL_1
193 #define RT5665_ADC_STO2_HP_CTRL_2
194 #define RT5665_AJD1_CTRL
195 #define RT5665_JD1_THD
196 #define RT5665_JD2_THD
197 #define RT5665_JD_CTRL_1
198 #define RT5665_JD_CTRL_2
199 #define RT5665_JD_CTRL_3
200 /* General Control */
201 #define RT5665_DIG_MISC
202 #define RT5665_DUMMY_2
203 #define RT5665_DUMMY_3
204
205 #define RT5665_DAC_ADC_DIG_VOL1
206 #define RT5665_DAC_ADC_DIG_VOL2
207 #define RT5665_BIAS_CUR_CTRL_1
208 #define RT5665_BIAS_CUR_CTRL_2
209 #define RT5665_BIAS_CUR_CTRL_3
210 #define RT5665_BIAS_CUR_CTRL_4
211 #define RT5665_BIAS_CUR_CTRL_5
212 #define RT5665_BIAS_CUR_CTRL_6
213 #define RT5665_BIAS_CUR_CTRL_7
214 #define RT5665_BIAS_CUR_CTRL_8
215 #define RT5665_BIAS_CUR_CTRL_9
216 #define RT5665_BIAS_CUR_CTRL_10
217 #define RT5665_VREF_REC_OP_FB_CAP_CTRL
218 #define RT5665_CHARGE_PUMP_1
219 #define RT5665_DIG_IN_CTRL_1
220 #define RT5665_DIG_IN_CTRL_2
221 #define RT5665_PAD_DRIVING_CTRL
222 #define RT5665_SOFT_RAMP_DEPOP
223 #define RT5665_PLL
224 #define RT5665_CHOP_DAC
225 #define RT5665_CHOP_ADC
226 #define RT5665_CALIB_ADC_CTRL
227 #define RT5665_VOL_TEST
228 #define RT5665_TEST_MODE_CTRL_1
229 #define RT5665_TEST_MODE_CTRL_2
230 #define RT5665_TEST_MODE_CTRL_3
231 #define RT5665_TEST_MODE_CTRL_4
232 #define RT5665_BASSBACK_CTRL
233 #define RT5665_STO_NG2_CTRL_1
234 #define RT5665_STO_NG2_CTRL_2
235 #define RT5665_STO_NG2_CTRL_3
236 #define RT5665_STO_NG2_CTRL_4
237 #define RT5665_STO_NG2_CTRL_5
238 #define RT5665_STO_NG2_CTRL_6
239 #define RT5665_STO_NG2_CTRL_7
240 #define RT5665_STO_NG2_CTRL_8
241 #define RT5665_MONO_NG2_CTRL_1
242 #define RT5665_MONO_NG2_CTRL_2
243 #define RT5665_MONO_NG2_CTRL_3
244 #define RT5665_MONO_NG2_CTRL_4
245 #define RT5665_MONO_NG2_CTRL_5
246 #define RT5665_MONO_NG2_CTRL_6
247 #define RT5665_STO1_DAC_SIL_DET
248 #define RT5665_MONOL_DAC_SIL_DET
249 #define RT5665_MONOR_DAC_SIL_DET
250 #define RT5665_STO2_DAC_SIL_DET
251 #define RT5665_SIL_PSV_CTRL1
252 #define RT5665_SIL_PSV_CTRL2
253 #define RT5665_SIL_PSV_CTRL3
254 #define RT5665_SIL_PSV_CTRL4
255 #define RT5665_SIL_PSV_CTRL5
256 #define RT5665_SIL_PSV_CTRL6
257 #define RT5665_MONO_AMP_CALIB_CTRL_1
258 #define RT5665_MONO_AMP_CALIB_CTRL_2
259 #define RT5665_MONO_AMP_CALIB_CTRL_3
260 #define RT5665_MONO_AMP_CALIB_CTRL_4
261 #define RT5665_MONO_AMP_CALIB_CTRL_5
262 #define RT5665_MONO_AMP_CALIB_CTRL_6
263 #define RT5665_MONO_AMP_CALIB_CTRL_7
264 #define RT5665_MONO_AMP_CALIB_STA1
265 #define RT5665_MONO_AMP_CALIB_STA2
266 #define RT5665_MONO_AMP_CALIB_STA3
267 #define RT5665_MONO_AMP_CALIB_STA4
268 #define RT5665_MONO_AMP_CALIB_STA6
269 #define RT5665_HP_IMP_SENS_CTRL_01
270 #define RT5665_HP_IMP_SENS_CTRL_02
271 #define RT5665_HP_IMP_SENS_CTRL_03
272 #define RT5665_HP_IMP_SENS_CTRL_04
273 #define RT5665_HP_IMP_SENS_CTRL_05
274 #define RT5665_HP_IMP_SENS_CTRL_06
275 #define RT5665_HP_IMP_SENS_CTRL_07
276 #define RT5665_HP_IMP_SENS_CTRL_08
277 #define RT5665_HP_IMP_SENS_CTRL_09
278 #define RT5665_HP_IMP_SENS_CTRL_10
279 #define RT5665_HP_IMP_SENS_CTRL_11
280 #define RT5665_HP_IMP_SENS_CTRL_12
281 #define RT5665_HP_IMP_SENS_CTRL_13
282 #define RT5665_HP_IMP_SENS_CTRL_14
283 #define RT5665_HP_IMP_SENS_CTRL_15
284 #define RT5665_HP_IMP_SENS_CTRL_16
285 #define RT5665_HP_IMP_SENS_CTRL_17
286 #define RT5665_HP_IMP_SENS_CTRL_18
287 #define RT5665_HP_IMP_SENS_CTRL_19
288 #define RT5665_HP_IMP_SENS_CTRL_20
289 #define RT5665_HP_IMP_SENS_CTRL_21
290 #define RT5665_HP_IMP_SENS_CTRL_22
291 #define RT5665_HP_IMP_SENS_CTRL_23
292 #define RT5665_HP_IMP_SENS_CTRL_24
293 #define RT5665_HP_IMP_SENS_CTRL_25
294 #define RT5665_HP_IMP_SENS_CTRL_26
295 #define RT5665_HP_IMP_SENS_CTRL_27
296 #define RT5665_HP_IMP_SENS_CTRL_28
297 #define RT5665_HP_IMP_SENS_CTRL_29
298 #define RT5665_HP_IMP_SENS_CTRL_30
299 #define RT5665_HP_IMP_SENS_CTRL_31
300 #define RT5665_HP_IMP_SENS_CTRL_32
301 #define RT5665_HP_IMP_SENS_CTRL_33
302 #define RT5665_HP_IMP_SENS_CTRL_34
303 #define RT5665_HP_LOGIC_CTRL_1
304 #define RT5665_HP_LOGIC_CTRL_2
305 #define RT5665_HP_LOGIC_CTRL_3
306 #define RT5665_HP_CALIB_CTRL_1
307 #define RT5665_HP_CALIB_CTRL_2
308 #define RT5665_HP_CALIB_CTRL_3
309 #define RT5665_HP_CALIB_CTRL_4
310 #define RT5665_HP_CALIB_CTRL_5
311 #define RT5665_HP_CALIB_CTRL_6
312 #define RT5665_HP_CALIB_CTRL_7
313 #define RT5665_HP_CALIB_CTRL_9
314 #define RT5665_HP_CALIB_CTRL_10
315 #define RT5665_HP_CALIB_CTRL_11
316 #define RT5665_HP_CALIB_STA_1
317 #define RT5665_HP_CALIB_STA_2
318 #define RT5665_HP_CALIB_STA_3
319 #define RT5665_HP_CALIB_STA_4
320 #define RT5665_HP_CALIB_STA_5
321 #define RT5665_HP_CALIB_STA_6
322 #define RT5665_HP_CALIB_STA_7
323 #define RT5665_HP_CALIB_STA_8
324 #define RT5665_HP_CALIB_STA_9
325 #define RT5665_HP_CALIB_STA_10
326 #define RT5665_HP_CALIB_STA_11
327 #define RT5665_PGM_TAB_CTRL1
328 #define RT5665_PGM_TAB_CTRL2
329 #define RT5665_PGM_TAB_CTRL3
330 #define RT5665_PGM_TAB_CTRL4
331 #define RT5665_PGM_TAB_CTRL5
332 #define RT5665_PGM_TAB_CTRL6
333 #define RT5665_PGM_TAB_CTRL7
334 #define RT5665_PGM_TAB_CTRL8
335 #define RT5665_PGM_TAB_CTRL9
336 #define RT5665_SAR_IL_CMD_1
337 #define RT5665_SAR_IL_CMD_2
338 #define RT5665_SAR_IL_CMD_3
339 #define RT5665_SAR_IL_CMD_4
340 #define RT5665_SAR_IL_CMD_5
341 #define RT5665_SAR_IL_CMD_6
342 #define RT5665_SAR_IL_CMD_7
343 #define RT5665_SAR_IL_CMD_8
344 #define RT5665_SAR_IL_CMD_9
345 #define RT5665_SAR_IL_CMD_10
346 #define RT5665_SAR_IL_CMD_11
347 #define RT5665_SAR_IL_CMD_12
348 #define RT5665_DRC1_CTRL_0
349 #define RT5665_DRC1_CTRL_1
350 #define RT5665_DRC1_CTRL_2
351 #define RT5665_DRC1_CTRL_3
352 #define RT5665_DRC1_CTRL_4
353 #define RT5665_DRC1_CTRL_5
354 #define RT5665_DRC1_CTRL_6
355 #define RT5665_DRC1_HARD_LMT_CTRL_1
356 #define RT5665_DRC1_HARD_LMT_CTRL_2
357 #define RT5665_DRC1_PRIV_1
358 #define RT5665_DRC1_PRIV_2
359 #define RT5665_DRC1_PRIV_3
360 #define RT5665_DRC1_PRIV_4
361 #define RT5665_DRC1_PRIV_5
362 #define RT5665_DRC1_PRIV_6
363 #define RT5665_DRC1_PRIV_7
364 #define RT5665_DRC1_PRIV_8
365 #define RT5665_ALC_PGA_CTRL_1
366 #define RT5665_ALC_PGA_CTRL_2
367 #define RT5665_ALC_PGA_CTRL_3
368 #define RT5665_ALC_PGA_CTRL_4
369 #define RT5665_ALC_PGA_CTRL_5
370 #define RT5665_ALC_PGA_CTRL_6
371 #define RT5665_ALC_PGA_CTRL_7
372 #define RT5665_ALC_PGA_CTRL_8
373 #define RT5665_ALC_PGA_STA_1
374 #define RT5665_ALC_PGA_STA_2
375 #define RT5665_ALC_PGA_STA_3
376 #define RT5665_EQ_AUTO_RCV_CTRL1
377 #define RT5665_EQ_AUTO_RCV_CTRL2
378 #define RT5665_EQ_AUTO_RCV_CTRL3
379 #define RT5665_EQ_AUTO_RCV_CTRL4
380 #define RT5665_EQ_AUTO_RCV_CTRL5
381 #define RT5665_EQ_AUTO_RCV_CTRL6
382 #define RT5665_EQ_AUTO_RCV_CTRL7
383 #define RT5665_EQ_AUTO_RCV_CTRL8
384 #define RT5665_EQ_AUTO_RCV_CTRL9
385 #define RT5665_EQ_AUTO_RCV_CTRL10
386 #define RT5665_EQ_AUTO_RCV_CTRL11
387 #define RT5665_EQ_AUTO_RCV_CTRL12
388 #define RT5665_EQ_AUTO_RCV_CTRL13
389 #define RT5665_ADC_L_EQ_LPF1_A1
390 #define RT5665_R_EQ_LPF1_A1
391 #define RT5665_L_EQ_LPF1_H0
392 #define RT5665_R_EQ_LPF1_H0
393 #define RT5665_L_EQ_BPF1_A1
394 #define RT5665_R_EQ_BPF1_A1
395 #define RT5665_L_EQ_BPF1_A2
396 #define RT5665_R_EQ_BPF1_A2
397 #define RT5665_L_EQ_BPF1_H0
398 #define RT5665_R_EQ_BPF1_H0
399 #define RT5665_L_EQ_BPF2_A1
400 #define RT5665_R_EQ_BPF2_A1
401 #define RT5665_L_EQ_BPF2_A2
402 #define RT5665_R_EQ_BPF2_A2
403 #define RT5665_L_EQ_BPF2_H0
404 #define RT5665_R_EQ_BPF2_H0
405 #define RT5665_L_EQ_BPF3_A1
406 #define RT5665_R_EQ_BPF3_A1
407 #define RT5665_L_EQ_BPF3_A2
408 #define RT5665_R_EQ_BPF3_A2
409 #define RT5665_L_EQ_BPF3_H0
410 #define RT5665_R_EQ_BPF3_H0
411 #define RT5665_L_EQ_BPF4_A1
412 #define RT5665_R_EQ_BPF4_A1
413 #define RT5665_L_EQ_BPF4_A2
414 #define RT5665_R_EQ_BPF4_A2
415 #define RT5665_L_EQ_BPF4_H0
416 #define RT5665_R_EQ_BPF4_H0
417 #define RT5665_L_EQ_HPF1_A1
418 #define RT5665_R_EQ_HPF1_A1
419 #define RT5665_L_EQ_HPF1_H0
420 #define RT5665_R_EQ_HPF1_H0
421 #define RT5665_L_EQ_PRE_VOL
422 #define RT5665_R_EQ_PRE_VOL
423 #define RT5665_L_EQ_POST_VOL
424 #define RT5665_R_EQ_POST_VOL
425 #define RT5665_SCAN_MODE_CTRL
426 #define RT5665_I2C_MODE
427
428
429
430 /* global definition */
431 #define RT5665_L_MUTE
432 #define RT5665_L_MUTE_SFT
433 #define RT5665_VOL_L_MUTE
434 #define RT5665_VOL_L_SFT
435 #define RT5665_R_MUTE
436 #define RT5665_R_MUTE_SFT
437 #define RT5665_VOL_R_MUTE
438 #define RT5665_VOL_R_SFT
439 #define RT5665_L_VOL_MASK
440 #define RT5665_L_VOL_SFT
441 #define RT5665_R_VOL_MASK
442 #define RT5665_R_VOL_SFT
443
444 /*Headphone Amp L/R Analog Gain and Digital NG
445 #define RT5665_G_HP
446 #define RT5665_G_HP_SFT
447 #define RT5665_G_STO_DA_DMIX
448 #define RT5665_G_STO_DA_SFT
449
450 /* CBJ Control (0x000b) */
451 #define RT5665_BST_CBJ_MASK
452 #define RT5665_BST_CBJ_SFT
453
454 /* IN1/IN2 Control (0x000c) */
455 #define RT5665_IN1_DF_MASK
456 #define RT5665_IN1_DF
457 #define RT5665_BST1_MASK
458 #define RT5665_BST1_SFT
459 #define RT5665_IN2_DF_MASK
460 #define RT5665_IN2_DF
461 #define RT5665_BST2_MASK
462 #define RT5665_BST2_SFT
463
464 /* IN3/IN4 Control (0x000d) */
465 #define RT5665_IN3_DF_MASK
466 #define RT5665_IN3_DF
467 #define RT5665_BST3_MASK
468 #define RT5665_BST3_SFT
469 #define RT5665_IN4_DF_MASK
470 #define RT5665_IN4_DF
471 #define RT5665_BST4_MASK
472 #define RT5665_BST4_SFT
473
474 /* INL and INR Volume Control (0x000f) */
475 #define RT5665_INL_VOL_MASK
476 #define RT5665_INL_VOL_SFT
477 #define RT5665_INR_VOL_MASK
478 #define RT5665_INR_VOL_SFT
479
480 /* Embeeded Jack and Type Detection Control 1
481 #define RT5665_EMB_JD_EN
482 #define RT5665_EMB_JD_EN_SFT
483 #define RT5665_JD_MODE
484 #define RT5665_JD_MODE_SFT
485 #define RT5665_POLA_EXT_JD_MASK
486 #define RT5665_POLA_EXT_JD_LOW
487 #define RT5665_POLA_EXT_JD_HIGH
488 #define RT5665_EXT_JD_DIG
489 #define RT5665_POL_FAST_OFF_MASK
490 #define RT5665_POL_FAST_OFF_HIGH
491 #define RT5665_POL_FAST_OFF_LOW
492 #define RT5665_VREF_POW_MASK
493 #define RT5665_VREF_POW_FSM
494 #define RT5665_VREF_POW_REG
495 #define RT5665_MB1_PATH_MASK
496 #define RT5665_CTRL_MB1_REG
497 #define RT5665_CTRL_MB1_FSM
498 #define RT5665_MB2_PATH_MASK
499 #define RT5665_CTRL_MB2_REG
500 #define RT5665_CTRL_MB2_FSM
501 #define RT5665_TRIG_JD_MASK
502 #define RT5665_TRIG_JD_HIGH
503 #define RT5665_TRIG_JD_LOW
504
505 /* Embeeded Jack and Type Detection Control 2
506 #define RT5665_EXT_JD_SRC
507 #define RT5665_EXT_JD_SRC_SFT
508 #define RT5665_EXT_JD_SRC_GPIO_JD1
509 #define RT5665_EXT_JD_SRC_GPIO_JD2
510 #define RT5665_EXT_JD_SRC_JD1_1
511 #define RT5665_EXT_JD_SRC_JD1_2
512 #define RT5665_EXT_JD_SRC_JD2
513 #define RT5665_EXT_JD_SRC_JD3
514 #define RT5665_EXT_JD_SRC_MANUAL
515
516 /* Combo Jack and Type Detection Control 4 (0x
517 #define RT5665_SEL_SHT_MID_TON_MASK
518 #define RT5665_SEL_SHT_MID_TON_2
519 #define RT5665_SEL_SHT_MID_TON_3
520 #define RT5665_CBJ_JD_TEST_MASK
521 #define RT5665_CBJ_JD_TEST_NORM
522 #define RT5665_CBJ_JD_TEST_MODE
523
524 /* Slience Detection Control (0x0015) */
525 #define RT5665_SIL_DET_MASK
526 #define RT5665_SIL_DET_DIS
527 #define RT5665_SIL_DET_EN
528
529 /* DAC2 Control (0x0017) */
530 #define RT5665_M_DAC2_L_VOL
531 #define RT5665_M_DAC2_L_VOL_SFT
532 #define RT5665_M_DAC2_R_VOL
533 #define RT5665_M_DAC2_R_VOL_SFT
534 #define RT5665_DAC_L2_SEL_MASK
535 #define RT5665_DAC_L2_SEL_SFT
536 #define RT5665_DAC_R2_SEL_MASK
537 #define RT5665_DAC_R2_SEL_SFT
538
539 /* Sidetone Control (0x0018) */
540 #define RT5665_ST_SEL_MASK
541 #define RT5665_ST_SEL_SFT
542 #define RT5665_ST_EN
543 #define RT5665_ST_EN_SFT
544
545 /* DAC1 Digital Volume (0x0019) */
546 #define RT5665_DAC_L1_VOL_MASK
547 #define RT5665_DAC_L1_VOL_SFT
548 #define RT5665_DAC_R1_VOL_MASK
549 #define RT5665_DAC_R1_VOL_SFT
550
551 /* DAC2 Digital Volume (0x001a) */
552 #define RT5665_DAC_L2_VOL_MASK
553 #define RT5665_DAC_L2_VOL_SFT
554 #define RT5665_DAC_R2_VOL_MASK
555 #define RT5665_DAC_R2_VOL_SFT
556
557 /* DAC3 Control (0x001b) */
558 #define RT5665_M_DAC3_L_VOL
559 #define RT5665_M_DAC3_L_VOL_SFT
560 #define RT5665_M_DAC3_R_VOL
561 #define RT5665_M_DAC3_R_VOL_SFT
562 #define RT5665_DAC_L3_SEL_MASK
563 #define RT5665_DAC_L3_SEL_SFT
564 #define RT5665_DAC_R3_SEL_MASK
565 #define RT5665_DAC_R3_SEL_SFT
566
567 /* ADC Digital Volume Control (0x001c) */
568 #define RT5665_ADC_L_VOL_MASK
569 #define RT5665_ADC_L_VOL_SFT
570 #define RT5665_ADC_R_VOL_MASK
571 #define RT5665_ADC_R_VOL_SFT
572
573 /* Mono ADC Digital Volume Control (0x001d) */
574 #define RT5665_MONO_ADC_L_VOL_MASK
575 #define RT5665_MONO_ADC_L_VOL_SFT
576 #define RT5665_MONO_ADC_R_VOL_MASK
577 #define RT5665_MONO_ADC_R_VOL_SFT
578
579 /* Stereo1 ADC Boost Gain Control (0x001f) */
580 #define RT5665_STO1_ADC_L_BST_MASK
581 #define RT5665_STO1_ADC_L_BST_SFT
582 #define RT5665_STO1_ADC_R_BST_MASK
583 #define RT5665_STO1_ADC_R_BST_SFT
584
585 /* Mono ADC Boost Gain Control (0x0020) */
586 #define RT5665_MONO_ADC_L_BST_MASK
587 #define RT5665_MONO_ADC_L_BST_SFT
588 #define RT5665_MONO_ADC_R_BST_MASK
589 #define RT5665_MONO_ADC_R_BST_SFT
590
591 /* Stereo1 ADC Boost Gain Control (0x001f) */
592 #define RT5665_STO2_ADC_L_BST_MASK
593 #define RT5665_STO2_ADC_L_BST_SFT
594 #define RT5665_STO2_ADC_R_BST_MASK
595 #define RT5665_STO2_ADC_R_BST_SFT
596
597 /* Stereo1 ADC Mixer Control (0x0026) */
598 #define RT5665_M_STO1_ADC_L1
599 #define RT5665_M_STO1_ADC_L1_SFT
600 #define RT5665_M_STO1_ADC_L2
601 #define RT5665_M_STO1_ADC_L2_SFT
602 #define RT5665_STO1_ADC1L_SRC_MASK
603 #define RT5665_STO1_ADC1L_SRC_SFT
604 #define RT5665_STO1_ADC1_SRC_ADC
605 #define RT5665_STO1_ADC1_SRC_DACMIX
606 #define RT5665_STO1_ADC2L_SRC_MASK
607 #define RT5665_STO1_ADC2L_SRC_SFT
608 #define RT5665_STO1_ADCL_SRC_MASK
609 #define RT5665_STO1_ADCL_SRC_SFT
610 #define RT5665_STO1_DD_L_SRC_MASK
611 #define RT5665_STO1_DD_L_SRC_SFT
612 #define RT5665_STO1_DMIC_SRC_MASK
613 #define RT5665_STO1_DMIC_SRC_SFT
614 #define RT5665_STO1_DMIC_SRC_DMIC2
615 #define RT5665_STO1_DMIC_SRC_DMIC1
616 #define RT5665_M_STO1_ADC_R1
617 #define RT5665_M_STO1_ADC_R1_SFT
618 #define RT5665_M_STO1_ADC_R2
619 #define RT5665_M_STO1_ADC_R2_SFT
620 #define RT5665_STO1_ADC1R_SRC_MASK
621 #define RT5665_STO1_ADC1R_SRC_SFT
622 #define RT5665_STO1_ADC2R_SRC_MASK
623 #define RT5665_STO1_ADC2R_SRC_SFT
624 #define RT5665_STO1_ADCR_SRC_MASK
625 #define RT5665_STO1_ADCR_SRC_SFT
626 #define RT5665_STO1_DD_R_SRC_MASK
627 #define RT5665_STO1_DD_R_SRC_SFT
628
629
630 /* Mono1 ADC Mixer control (0x0027) */
631 #define RT5665_M_MONO_ADC_L1
632 #define RT5665_M_MONO_ADC_L1_SFT
633 #define RT5665_M_MONO_ADC_L2
634 #define RT5665_M_MONO_ADC_L2_SFT
635 #define RT5665_MONO_ADC_L1_SRC_MASK
636 #define RT5665_MONO_ADC_L1_SRC_SFT
637 #define RT5665_MONO_ADC_L2_SRC_MASK
638 #define RT5665_MONO_ADC_L2_SRC_SFT
639 #define RT5665_MONO_ADC_L_SRC_MASK
640 #define RT5665_MONO_ADC_L_SRC_SFT
641 #define RT5665_MONO_DD_L_SRC_MASK
642 #define RT5665_MONO_DD_L_SRC_SFT
643 #define RT5665_MONO_DMIC_L_SRC_MASK
644 #define RT5665_MONO_DMIC_L_SRC_SFT
645 #define RT5665_M_MONO_ADC_R1
646 #define RT5665_M_MONO_ADC_R1_SFT
647 #define RT5665_M_MONO_ADC_R2
648 #define RT5665_M_MONO_ADC_R2_SFT
649 #define RT5665_MONO_ADC_R1_SRC_MASK
650 #define RT5665_MONO_ADC_R1_SRC_SFT
651 #define RT5665_MONO_ADC_R2_SRC_MASK
652 #define RT5665_MONO_ADC_R2_SRC_SFT
653 #define RT5665_MONO_ADC_R_SRC_MASK
654 #define RT5665_MONO_ADC_R_SRC_SFT
655 #define RT5665_MONO_DD_R_SRC_MASK
656 #define RT5665_MONO_DD_R_SRC_SFT
657 #define RT5665_MONO_DMIC_R_SRC_MASK
658 #define RT5665_MONO_DMIC_R_SRC_SFT
659
660 /* Stereo2 ADC Mixer Control (0x0028) */
661 #define RT5665_M_STO2_ADC_L1
662 #define RT5665_M_STO2_ADC_L1_UN
663 #define RT5665_M_STO2_ADC_L1_SFT
664 #define RT5665_M_STO2_ADC_L2
665 #define RT5665_M_STO2_ADC_L2_SFT
666 #define RT5665_STO2_ADC1L_SRC_MASK
667 #define RT5665_STO2_ADC1L_SRC_SFT
668 #define RT5665_STO2_ADC1_SRC_ADC
669 #define RT5665_STO2_ADC1_SRC_DACMIX
670 #define RT5665_STO2_ADC2L_SRC_MASK
671 #define RT5665_STO2_ADC2L_SRC_SFT
672 #define RT5665_STO2_ADCL_SRC_MASK
673 #define RT5665_STO2_ADCL_SRC_SFT
674 #define RT5665_STO2_DD_L_SRC_MASK
675 #define RT5665_STO2_DD_L_SRC_SFT
676 #define RT5665_STO2_DMIC_SRC_MASK
677 #define RT5665_STO2_DMIC_SRC_SFT
678 #define RT5665_STO2_DMIC_SRC_DMIC2
679 #define RT5665_STO2_DMIC_SRC_DMIC1
680 #define RT5665_M_STO2_ADC_R1
681 #define RT5665_M_STO2_ADC_R1_UN
682 #define RT5665_M_STO2_ADC_R1_SFT
683 #define RT5665_M_STO2_ADC_R2
684 #define RT5665_M_STO2_ADC_R2_SFT
685 #define RT5665_STO2_ADC1R_SRC_MASK
686 #define RT5665_STO2_ADC1R_SRC_SFT
687 #define RT5665_STO2_ADC2R_SRC_MASK
688 #define RT5665_STO2_ADC2R_SRC_SFT
689 #define RT5665_STO2_ADCR_SRC_MASK
690 #define RT5665_STO2_ADCR_SRC_SFT
691 #define RT5665_STO2_DD_R_SRC_MASK
692 #define RT5665_STO2_DD_R_SRC_SFT
693
694 /* ADC Mixer to DAC Mixer Control (0x0029) */
695 #define RT5665_M_ADCMIX_L
696 #define RT5665_M_ADCMIX_L_SFT
697 #define RT5665_M_DAC1_L
698 #define RT5665_M_DAC1_L_SFT
699 #define RT5665_DAC1_R_SEL_MASK
700 #define RT5665_DAC1_R_SEL_SFT
701 #define RT5665_DAC1_L_SEL_MASK
702 #define RT5665_DAC1_L_SEL_SFT
703 #define RT5665_M_ADCMIX_R
704 #define RT5665_M_ADCMIX_R_SFT
705 #define RT5665_M_DAC1_R
706 #define RT5665_M_DAC1_R_SFT
707
708 /* Stereo1 DAC Mixer Control (0x002a) */
709 #define RT5665_M_DAC_L1_STO_L
710 #define RT5665_M_DAC_L1_STO_L_SFT
711 #define RT5665_G_DAC_L1_STO_L_MASK
712 #define RT5665_G_DAC_L1_STO_L_SFT
713 #define RT5665_M_DAC_R1_STO_L
714 #define RT5665_M_DAC_R1_STO_L_SFT
715 #define RT5665_G_DAC_R1_STO_L_MASK
716 #define RT5665_G_DAC_R1_STO_L_SFT
717 #define RT5665_M_DAC_L2_STO_L
718 #define RT5665_M_DAC_L2_STO_L_SFT
719 #define RT5665_G_DAC_L2_STO_L_MASK
720 #define RT5665_G_DAC_L2_STO_L_SFT
721 #define RT5665_M_DAC_R2_STO_L
722 #define RT5665_M_DAC_R2_STO_L_SFT
723 #define RT5665_G_DAC_R2_STO_L_MASK
724 #define RT5665_G_DAC_R2_STO_L_SFT
725 #define RT5665_M_DAC_L1_STO_R
726 #define RT5665_M_DAC_L1_STO_R_SFT
727 #define RT5665_G_DAC_L1_STO_R_MASK
728 #define RT5665_G_DAC_L1_STO_R_SFT
729 #define RT5665_M_DAC_R1_STO_R
730 #define RT5665_M_DAC_R1_STO_R_SFT
731 #define RT5665_G_DAC_R1_STO_R_MASK
732 #define RT5665_G_DAC_R1_STO_R_SFT
733 #define RT5665_M_DAC_L2_STO_R
734 #define RT5665_M_DAC_L2_STO_R_SFT
735 #define RT5665_G_DAC_L2_STO_R_MASK
736 #define RT5665_G_DAC_L2_STO_R_SFT
737 #define RT5665_M_DAC_R2_STO_R
738 #define RT5665_M_DAC_R2_STO_R_SFT
739 #define RT5665_G_DAC_R2_STO_R_MASK
740 #define RT5665_G_DAC_R2_STO_R_SFT
741
742 /* Mono DAC Mixer Control (0x002b) */
743 #define RT5665_M_DAC_L1_MONO_L
744 #define RT5665_M_DAC_L1_MONO_L_SFT
745 #define RT5665_G_DAC_L1_MONO_L_MASK
746 #define RT5665_G_DAC_L1_MONO_L_SFT
747 #define RT5665_M_DAC_R1_MONO_L
748 #define RT5665_M_DAC_R1_MONO_L_SFT
749 #define RT5665_G_DAC_R1_MONO_L_MASK
750 #define RT5665_G_DAC_R1_MONO_L_SFT
751 #define RT5665_M_DAC_L2_MONO_L
752 #define RT5665_M_DAC_L2_MONO_L_SFT
753 #define RT5665_G_DAC_L2_MONO_L_MASK
754 #define RT5665_G_DAC_L2_MONO_L_SFT
755 #define RT5665_M_DAC_R2_MONO_L
756 #define RT5665_M_DAC_R2_MONO_L_SFT
757 #define RT5665_G_DAC_R2_MONO_L_MASK
758 #define RT5665_G_DAC_R2_MONO_L_SFT
759 #define RT5665_M_DAC_L1_MONO_R
760 #define RT5665_M_DAC_L1_MONO_R_SFT
761 #define RT5665_G_DAC_L1_MONO_R_MASK
762 #define RT5665_G_DAC_L1_MONO_R_SFT
763 #define RT5665_M_DAC_R1_MONO_R
764 #define RT5665_M_DAC_R1_MONO_R_SFT
765 #define RT5665_G_DAC_R1_MONO_R_MASK
766 #define RT5665_G_DAC_R1_MONO_R_SFT
767 #define RT5665_M_DAC_L2_MONO_R
768 #define RT5665_M_DAC_L2_MONO_R_SFT
769 #define RT5665_G_DAC_L2_MONO_R_MASK
770 #define RT5665_G_DAC_L2_MONO_R_SFT
771 #define RT5665_M_DAC_R2_MONO_R
772 #define RT5665_M_DAC_R2_MONO_R_SFT
773 #define RT5665_G_DAC_R2_MONO_R_MASK
774 #define RT5665_G_DAC_R2_MONO_R_SFT
775
776 /* Stereo2 DAC Mixer Control (0x002c) */
777 #define RT5665_M_DAC_L1_STO2_L
778 #define RT5665_M_DAC_L1_STO2_L_SFT
779 #define RT5665_G_DAC_L1_STO2_L_MASK
780 #define RT5665_G_DAC_L1_STO2_L_SFT
781 #define RT5665_M_DAC_L2_STO2_L
782 #define RT5665_M_DAC_L2_STO2_L_SFT
783 #define RT5665_G_DAC_L2_STO2_L_MASK
784 #define RT5665_G_DAC_L2_STO2_L_SFT
785 #define RT5665_M_DAC_L3_STO2_L
786 #define RT5665_M_DAC_L3_STO2_L_SFT
787 #define RT5665_G_DAC_L3_STO2_L_MASK
788 #define RT5665_G_DAC_L3_STO2_L_SFT
789 #define RT5665_M_ST_DAC_L1
790 #define RT5665_M_ST_DAC_L1_SFT
791 #define RT5665_M_ST_DAC_R1
792 #define RT5665_M_ST_DAC_R1_SFT
793 #define RT5665_M_DAC_R1_STO2_R
794 #define RT5665_M_DAC_R1_STO2_R_SFT
795 #define RT5665_G_DAC_R1_STO2_R_MASK
796 #define RT5665_G_DAC_R1_STO2_R_SFT
797 #define RT5665_M_DAC_R2_STO2_R
798 #define RT5665_M_DAC_R2_STO2_R_SFT
799 #define RT5665_G_DAC_R2_STO2_R_MASK
800 #define RT5665_G_DAC_R2_STO2_R_SFT
801 #define RT5665_M_DAC_R3_STO2_R
802 #define RT5665_M_DAC_R3_STO2_R_SFT
803 #define RT5665_G_DAC_R3_STO2_R_MASK
804 #define RT5665_G_DAC_R3_STO2_R_SFT
805
806 /* Analog DAC1 Input Source Control (0x002d) *
807 #define RT5665_DAC_MIX_L_MASK
808 #define RT5665_DAC_MIX_L_SFT
809 #define RT5665_DAC_MIX_R_MASK
810 #define RT5665_DAC_MIX_R_SFT
811 #define RT5665_DAC_L1_SRC_MASK
812 #define RT5665_A_DACL1_SFT
813 #define RT5665_DAC_R1_SRC_MASK
814 #define RT5665_A_DACR1_SFT
815
816 /* Analog DAC Input Source Control (0x002e) */
817 #define RT5665_A_DACL2_SEL
818 #define RT5665_A_DACL2_SFT
819 #define RT5665_A_DACR2_SEL
820 #define RT5665_A_DACR2_SFT
821
822 /* Digital Interface Data Control (0x002f) */
823 #define RT5665_IF2_1_ADC_IN_MASK
824 #define RT5665_IF2_1_ADC_IN_SFT
825 #define RT5665_IF2_1_DAC_SEL_MASK
826 #define RT5665_IF2_1_DAC_SEL_SFT
827 #define RT5665_IF2_1_ADC_SEL_MASK
828 #define RT5665_IF2_1_ADC_SEL_SFT
829 #define RT5665_IF2_2_ADC_IN_MASK
830 #define RT5665_IF2_2_ADC_IN_SFT
831 #define RT5665_IF2_2_DAC_SEL_MASK
832 #define RT5665_IF2_2_DAC_SEL_SFT
833 #define RT5665_IF2_2_ADC_SEL_MASK
834 #define RT5665_IF2_2_ADC_SEL_SFT
835
836 /* Digital Interface Data Control (0x0030) */
837 #define RT5665_IF3_ADC_IN_MASK
838 #define RT5665_IF3_ADC_IN_SFT
839 #define RT5665_IF3_DAC_SEL_MASK
840 #define RT5665_IF3_DAC_SEL_SFT
841 #define RT5665_IF3_ADC_SEL_MASK
842 #define RT5665_IF3_ADC_SEL_SFT
843
844 /* PDM Output Control (0x0031) */
845 #define RT5665_M_PDM1_L
846 #define RT5665_M_PDM1_L_SFT
847 #define RT5665_M_PDM1_R
848 #define RT5665_M_PDM1_R_SFT
849 #define RT5665_PDM1_L_MASK
850 #define RT5665_PDM1_L_SFT
851 #define RT5665_PDM1_R_MASK
852 #define RT5665_PDM1_R_SFT
853 #define RT5665_PDM1_BUSY
854 #define RT5665_PDM_PATTERN
855 #define RT5665_PDM_GAIN
856 #define RT5665_LRCK_PDM_PI2C
857 #define RT5665_PDM_DIV_MASK
858
859 /*S/PDIF Output Control (0x0036) */
860 #define RT5665_SPDIF_SEL_MASK
861 #define RT5665_SPDIF_SEL_SFT
862
863 /* REC Left Mixer Control 2 (0x003c) */
864 #define RT5665_M_CBJ_RM1_L
865 #define RT5665_M_CBJ_RM1_L_SFT
866 #define RT5665_M_BST1_RM1_L
867 #define RT5665_M_BST1_RM1_L_SFT
868 #define RT5665_M_BST2_RM1_L
869 #define RT5665_M_BST2_RM1_L_SFT
870 #define RT5665_M_BST3_RM1_L
871 #define RT5665_M_BST3_RM1_L_SFT
872 #define RT5665_M_BST4_RM1_L
873 #define RT5665_M_BST4_RM1_L_SFT
874 #define RT5665_M_INL_RM1_L
875 #define RT5665_M_INL_RM1_L_SFT
876 #define RT5665_M_INR_RM1_L
877 #define RT5665_M_INR_RM1_L_SFT
878
879 /* REC Right Mixer Control 2 (0x003e) */
880 #define RT5665_M_AEC_REF_RM1_R
881 #define RT5665_M_AEC_REF_RM1_R_SFT
882 #define RT5665_M_BST1_RM1_R
883 #define RT5665_M_BST1_RM1_R_SFT
884 #define RT5665_M_BST2_RM1_R
885 #define RT5665_M_BST2_RM1_R_SFT
886 #define RT5665_M_BST3_RM1_R
887 #define RT5665_M_BST3_RM1_R_SFT
888 #define RT5665_M_BST4_RM1_R
889 #define RT5665_M_BST4_RM1_R_SFT
890 #define RT5665_M_INR_RM1_R
891 #define RT5665_M_INR_RM1_R_SFT
892 #define RT5665_M_MONOVOL_RM1_R
893 #define RT5665_M_MONOVOL_RM1_R_SFT
894
895 /* REC Mixer 2 Left Control 2 (0x0041) */
896 #define RT5665_M_CBJ_RM2_L
897 #define RT5665_M_CBJ_RM2_L_SFT
898 #define RT5665_M_BST1_RM2_L
899 #define RT5665_M_BST1_RM2_L_SFT
900 #define RT5665_M_BST2_RM2_L
901 #define RT5665_M_BST2_RM2_L_SFT
902 #define RT5665_M_BST3_RM2_L
903 #define RT5665_M_BST3_RM2_L_SFT
904 #define RT5665_M_BST4_RM2_L
905 #define RT5665_M_BST4_RM2_L_SFT
906 #define RT5665_M_INL_RM2_L
907 #define RT5665_M_INL_RM2_L_SFT
908 #define RT5665_M_INR_RM2_L
909 #define RT5665_M_INR_RM2_L_SFT
910
911 /* REC Mixer 2 Right Control 2 (0x0043) */
912 #define RT5665_M_MONOVOL_RM2_R
913 #define RT5665_M_MONOVOL_RM2_R_SFT
914 #define RT5665_M_BST1_RM2_R
915 #define RT5665_M_BST1_RM2_R_SFT
916 #define RT5665_M_BST2_RM2_R
917 #define RT5665_M_BST2_RM2_R_SFT
918 #define RT5665_M_BST3_RM2_R
919 #define RT5665_M_BST3_RM2_R_SFT
920 #define RT5665_M_BST4_RM2_R
921 #define RT5665_M_BST4_RM2_R_SFT
922 #define RT5665_M_INL_RM2_R
923 #define RT5665_M_INL_RM2_R_SFT
924 #define RT5665_M_INR_RM2_R
925 #define RT5665_M_INR_RM2_R_SFT
926
927 /* SPK Left Mixer Control (0x0046) */
928 #define RT5665_M_BST3_SM_L
929 #define RT5665_M_BST3_SM_L_SFT
930 #define RT5665_M_IN_R_SM_L
931 #define RT5665_M_IN_R_SM_L_SFT
932 #define RT5665_M_IN_L_SM_L
933 #define RT5665_M_IN_L_SM_L_SFT
934 #define RT5665_M_BST1_SM_L
935 #define RT5665_M_BST1_SM_L_SFT
936 #define RT5665_M_DAC_L2_SM_L
937 #define RT5665_M_DAC_L2_SM_L_SFT
938
939 /* SPK Right Mixer Control (0x0047) */
940 #define RT5665_M_BST3_SM_R
941 #define RT5665_M_BST3_SM_R_SFT
942 #define RT5665_M_IN_R_SM_R
943 #define RT5665_M_IN_R_SM_R_SFT
944 #define RT5665_M_IN_L_SM_R
945 #define RT5665_M_IN_L_SM_R_SFT
946 #define RT5665_M_BST4_SM_R
947 #define RT5665_M_BST4_SM_R_SFT
948 #define RT5665_M_DAC_R2_SM_R
949 #define RT5665_M_DAC_R2_SM_R_SFT
950
951 /* SPO Amp Input and Gain Control (0x0048) */
952 #define RT5665_M_DAC_L2_SPKOMIX
953 #define RT5665_M_DAC_L2_SPKOMIX_SFT
954 #define RT5665_M_SPKVOLL_SPKOMIX
955 #define RT5665_M_SPKVOLL_SPKOMIX_SFT
956 #define RT5665_M_DAC_R2_SPKOMIX
957 #define RT5665_M_DAC_R2_SPKOMIX_SFT
958 #define RT5665_M_SPKVOLR_SPKOMIX
959 #define RT5665_M_SPKVOLR_SPKOMIX_SFT
960
961 /* MONOMIX Input and Gain Control (0x004b) */
962 #define RT5665_G_MONOVOL_MA
963 #define RT5665_G_MONOVOL_MA_SFT
964 #define RT5665_M_MONOVOL_MA
965 #define RT5665_M_MONOVOL_MA_SFT
966 #define RT5665_M_DAC_L2_MA
967 #define RT5665_M_DAC_L2_MA_SFT
968 #define RT5665_M_BST3_MM
969 #define RT5665_M_BST3_MM_SFT
970 #define RT5665_M_BST2_MM
971 #define RT5665_M_BST2_MM_SFT
972 #define RT5665_M_BST1_MM
973 #define RT5665_M_BST1_MM_SFT
974 #define RT5665_M_RECMIC2L_MM
975 #define RT5665_M_RECMIC2L_MM_SFT
976 #define RT5665_M_DAC_L2_MM
977 #define RT5665_M_DAC_L2_MM_SFT
978
979 /* Output Left Mixer Control 1 (0x004d) */
980 #define RT5665_G_BST3_OM_L_MASK
981 #define RT5665_G_BST3_OM_L_SFT
982 #define RT5665_G_BST2_OM_L_MASK
983 #define RT5665_G_BST2_OM_L_SFT
984 #define RT5665_G_BST1_OM_L_MASK
985 #define RT5665_G_BST1_OM_L_SFT
986 #define RT5665_G_IN_L_OM_L_MASK
987 #define RT5665_G_IN_L_OM_L_SFT
988 #define RT5665_G_DAC_L2_OM_L_MASK
989 #define RT5665_G_DAC_L2_OM_L_SFT
990
991 /* Output Left Mixer Input Control (0x004e) */
992 #define RT5665_M_BST3_OM_L
993 #define RT5665_M_BST3_OM_L_SFT
994 #define RT5665_M_BST2_OM_L
995 #define RT5665_M_BST2_OM_L_SFT
996 #define RT5665_M_BST1_OM_L
997 #define RT5665_M_BST1_OM_L_SFT
998 #define RT5665_M_IN_L_OM_L
999 #define RT5665_M_IN_L_OM_L_SFT
1000 #define RT5665_M_DAC_L2_OM_L
1001 #define RT5665_M_DAC_L2_OM_L_SFT
1002
1003 /* Output Right Mixer Input Control (0x0050)
1004 #define RT5665_M_BST4_OM_R
1005 #define RT5665_M_BST4_OM_R_SFT
1006 #define RT5665_M_BST3_OM_R
1007 #define RT5665_M_BST3_OM_R_SFT
1008 #define RT5665_M_BST2_OM_R
1009 #define RT5665_M_BST2_OM_R_SFT
1010 #define RT5665_M_IN_R_OM_R
1011 #define RT5665_M_IN_R_OM_R_SFT
1012 #define RT5665_M_DAC_R2_OM_R
1013 #define RT5665_M_DAC_R2_OM_R_SFT
1014
1015 /* LOUT Mixer Control (0x0052) */
1016 #define RT5665_M_DAC_L2_LM
1017 #define RT5665_M_DAC_L2_LM_SFT
1018 #define RT5665_M_DAC_R2_LM
1019 #define RT5665_M_DAC_R2_LM_SFT
1020 #define RT5665_M_OV_L_LM
1021 #define RT5665_M_OV_L_LM_SFT
1022 #define RT5665_M_OV_R_LM
1023 #define RT5665_M_OV_R_LM_SFT
1024 #define RT5665_LOUT_BST_SFT
1025 #define RT5665_LOUT_DF
1026 #define RT5665_LOUT_DF_SFT
1027
1028 /* Power Management for Digital 1 (0x0061) */
1029 #define RT5665_PWR_I2S1_1
1030 #define RT5665_PWR_I2S1_1_BIT
1031 #define RT5665_PWR_I2S1_2
1032 #define RT5665_PWR_I2S1_2_BIT
1033 #define RT5665_PWR_I2S2_1
1034 #define RT5665_PWR_I2S2_1_BIT
1035 #define RT5665_PWR_I2S2_2
1036 #define RT5665_PWR_I2S2_2_BIT
1037 #define RT5665_PWR_DAC_L1
1038 #define RT5665_PWR_DAC_L1_BIT
1039 #define RT5665_PWR_DAC_R1
1040 #define RT5665_PWR_DAC_R1_BIT
1041 #define RT5665_PWR_I2S3
1042 #define RT5665_PWR_I2S3_BIT
1043 #define RT5665_PWR_LDO
1044 #define RT5665_PWR_LDO_BIT
1045 #define RT5665_PWR_DAC_L2
1046 #define RT5665_PWR_DAC_L2_BIT
1047 #define RT5665_PWR_DAC_R2
1048 #define RT5665_PWR_DAC_R2_BIT
1049 #define RT5665_PWR_ADC_L1
1050 #define RT5665_PWR_ADC_L1_BIT
1051 #define RT5665_PWR_ADC_R1
1052 #define RT5665_PWR_ADC_R1_BIT
1053 #define RT5665_PWR_ADC_L2
1054 #define RT5665_PWR_ADC_L2_BIT
1055 #define RT5665_PWR_ADC_R2
1056 #define RT5665_PWR_ADC_R2_BIT
1057
1058 /* Power Management for Digital 2 (0x0062) */
1059 #define RT5665_PWR_ADC_S1F
1060 #define RT5665_PWR_ADC_S1F_BIT
1061 #define RT5665_PWR_ADC_S2F
1062 #define RT5665_PWR_ADC_S2F_BIT
1063 #define RT5665_PWR_ADC_MF_L
1064 #define RT5665_PWR_ADC_MF_L_BIT
1065 #define RT5665_PWR_ADC_MF_R
1066 #define RT5665_PWR_ADC_MF_R_BIT
1067 #define RT5665_PWR_DAC_S2F
1068 #define RT5665_PWR_DAC_S2F_BIT
1069 #define RT5665_PWR_DAC_S1F
1070 #define RT5665_PWR_DAC_S1F_BIT
1071 #define RT5665_PWR_DAC_MF_L
1072 #define RT5665_PWR_DAC_MF_L_BIT
1073 #define RT5665_PWR_DAC_MF_R
1074 #define RT5665_PWR_DAC_MF_R_BIT
1075 #define RT5665_PWR_PDM1
1076 #define RT5665_PWR_PDM1_BIT
1077
1078 /* Power Management for Analog 1 (0x0063) */
1079 #define RT5665_PWR_VREF1
1080 #define RT5665_PWR_VREF1_BIT
1081 #define RT5665_PWR_FV1
1082 #define RT5665_PWR_FV1_BIT
1083 #define RT5665_PWR_VREF2
1084 #define RT5665_PWR_VREF2_BIT
1085 #define RT5665_PWR_FV2
1086 #define RT5665_PWR_FV2_BIT
1087 #define RT5665_PWR_VREF3
1088 #define RT5665_PWR_VREF3_BIT
1089 #define RT5665_PWR_FV3
1090 #define RT5665_PWR_FV3_BIT
1091 #define RT5665_PWR_MB
1092 #define RT5665_PWR_MB_BIT
1093 #define RT5665_PWR_LM
1094 #define RT5665_PWR_LM_BIT
1095 #define RT5665_PWR_BG
1096 #define RT5665_PWR_BG_BIT
1097 #define RT5665_PWR_MA
1098 #define RT5665_PWR_MA_BIT
1099 #define RT5665_PWR_HA_L
1100 #define RT5665_PWR_HA_L_BIT
1101 #define RT5665_PWR_HA_R
1102 #define RT5665_PWR_HA_R_BIT
1103 #define RT5665_HP_DRIVER_MASK
1104 #define RT5665_HP_DRIVER_1X
1105 #define RT5665_HP_DRIVER_3X
1106 #define RT5665_HP_DRIVER_5X
1107 #define RT5665_LDO1_DVO_MASK
1108 #define RT5665_LDO1_DVO_09
1109 #define RT5665_LDO1_DVO_10
1110 #define RT5665_LDO1_DVO_12
1111 #define RT5665_LDO1_DVO_14
1112
1113 /* Power Management for Analog 2 (0x0064) */
1114 #define RT5665_PWR_BST1
1115 #define RT5665_PWR_BST1_BIT
1116 #define RT5665_PWR_BST2
1117 #define RT5665_PWR_BST2_BIT
1118 #define RT5665_PWR_BST3
1119 #define RT5665_PWR_BST3_BIT
1120 #define RT5665_PWR_BST4
1121 #define RT5665_PWR_BST4_BIT
1122 #define RT5665_PWR_MB1
1123 #define RT5665_PWR_MB1_PWR_DOWN
1124 #define RT5665_PWR_MB1_BIT
1125 #define RT5665_PWR_MB2
1126 #define RT5665_PWR_MB2_PWR_DOWN
1127 #define RT5665_PWR_MB2_BIT
1128 #define RT5665_PWR_MB3
1129 #define RT5665_PWR_MB3_BIT
1130 #define RT5665_PWR_BST1_P
1131 #define RT5665_PWR_BST1_P_BIT
1132 #define RT5665_PWR_BST2_P
1133 #define RT5665_PWR_BST2_P_BIT
1134 #define RT5665_PWR_BST3_P
1135 #define RT5665_PWR_BST3_P_BIT
1136 #define RT5665_PWR_BST4_P
1137 #define RT5665_PWR_BST4_P_BIT
1138 #define RT5665_PWR_JD1
1139 #define RT5665_PWR_JD1_BIT
1140 #define RT5665_PWR_JD2
1141 #define RT5665_PWR_JD2_BIT
1142 #define RT5665_PWR_RM1_L
1143 #define RT5665_PWR_RM1_L_BIT
1144 #define RT5665_PWR_RM1_R
1145 #define RT5665_PWR_RM1_R_BIT
1146
1147 /* Power Management for Analog 3 (0x0065) */
1148 #define RT5665_PWR_CBJ
1149 #define RT5665_PWR_CBJ_BIT
1150 #define RT5665_PWR_BST_L
1151 #define RT5665_PWR_BST_L_BIT
1152 #define RT5665_PWR_BST_R
1153 #define RT5665_PWR_BST_R_BIT
1154 #define RT5665_PWR_PLL
1155 #define RT5665_PWR_PLL_BIT
1156 #define RT5665_PWR_LDO2
1157 #define RT5665_PWR_LDO2_BIT
1158 #define RT5665_PWR_SVD
1159 #define RT5665_PWR_SVD_BIT
1160
1161 /* Power Management for Mixer (0x0066) */
1162 #define RT5665_PWR_RM2_L
1163 #define RT5665_PWR_RM2_L_BIT
1164 #define RT5665_PWR_RM2_R
1165 #define RT5665_PWR_RM2_R_BIT
1166 #define RT5665_PWR_OM_L
1167 #define RT5665_PWR_OM_L_BIT
1168 #define RT5665_PWR_OM_R
1169 #define RT5665_PWR_OM_R_BIT
1170 #define RT5665_PWR_MM
1171 #define RT5665_PWR_MM_BIT
1172 #define RT5665_PWR_AEC_REF
1173 #define RT5665_PWR_AEC_REF_BIT
1174 #define RT5665_PWR_STO1_DAC_L
1175 #define RT5665_PWR_STO1_DAC_L_BIT
1176 #define RT5665_PWR_STO1_DAC_R
1177 #define RT5665_PWR_STO1_DAC_R_BIT
1178 #define RT5665_PWR_MONO_DAC_L
1179 #define RT5665_PWR_MONO_DAC_L_BIT
1180 #define RT5665_PWR_MONO_DAC_R
1181 #define RT5665_PWR_MONO_DAC_R_BIT
1182 #define RT5665_PWR_STO2_DAC_L
1183 #define RT5665_PWR_STO2_DAC_L_BIT
1184 #define RT5665_PWR_STO2_DAC_R
1185 #define RT5665_PWR_STO2_DAC_R_BIT
1186
1187 /* Power Management for Volume (0x0067) */
1188 #define RT5665_PWR_OV_L
1189 #define RT5665_PWR_OV_L_BIT
1190 #define RT5665_PWR_OV_R
1191 #define RT5665_PWR_OV_R_BIT
1192 #define RT5665_PWR_IN_L
1193 #define RT5665_PWR_IN_L_BIT
1194 #define RT5665_PWR_IN_R
1195 #define RT5665_PWR_IN_R_BIT
1196 #define RT5665_PWR_MV
1197 #define RT5665_PWR_MV_BIT
1198 #define RT5665_PWR_MIC_DET
1199 #define RT5665_PWR_MIC_DET_BIT
1200
1201 /* (0x006b) */
1202 #define RT5665_SYS_CLK_DET
1203 #define RT5665_HP_CLK_DET
1204 #define RT5665_MONO_CLK_DET
1205 #define RT5665_LOUT_CLK_DET
1206 #define RT5665_POW_CLK_DET
1207
1208 /* Digital Microphone Control 1 (0x006e) */
1209 #define RT5665_DMIC_1_EN_MASK
1210 #define RT5665_DMIC_1_EN_SFT
1211 #define RT5665_DMIC_1_DIS
1212 #define RT5665_DMIC_1_EN
1213 #define RT5665_DMIC_2_EN_MASK
1214 #define RT5665_DMIC_2_EN_SFT
1215 #define RT5665_DMIC_2_DIS
1216 #define RT5665_DMIC_2_EN
1217 #define RT5665_DMIC_2_DP_MASK
1218 #define RT5665_DMIC_2_DP_SFT
1219 #define RT5665_DMIC_2_DP_GPIO5
1220 #define RT5665_DMIC_2_DP_IN2P
1221 #define RT5665_DMIC_CLK_MASK
1222 #define RT5665_DMIC_CLK_SFT
1223 #define RT5665_DMIC_1_DP_MASK
1224 #define RT5665_DMIC_1_DP_SFT
1225 #define RT5665_DMIC_1_DP_GPIO4
1226 #define RT5665_DMIC_1_DP_IN2N
1227
1228
1229 /* Digital Microphone Control 1 (0x006f) */
1230 #define RT5665_DMIC_2L_LH_MASK
1231 #define RT5665_DMIC_2L_LH_SFT
1232 #define RT5665_DMIC_2L_LH_RISING
1233 #define RT5665_DMIC_2L_LH_FALLING
1234 #define RT5665_DMIC_2R_LH_MASK
1235 #define RT5665_DMIC_2R_LH_SFT
1236 #define RT5665_DMIC_2R_LH_RISING
1237 #define RT5665_DMIC_2R_LH_FALLING
1238 #define RT5665_DMIC_1L_LH_MASK
1239 #define RT5665_DMIC_1L_LH_SFT
1240 #define RT5665_DMIC_1L_LH_RISING
1241 #define RT5665_DMIC_1L_LH_FALLING
1242 #define RT5665_DMIC_1R_LH_MASK
1243 #define RT5665_DMIC_1R_LH_SFT
1244 #define RT5665_DMIC_1R_LH_RISING
1245 #define RT5665_DMIC_1R_LH_FALLING
1246
1247 /* I2S1/2/3 Audio Serial Data Port Control (0
1248 #define RT5665_I2S_MS_MASK
1249 #define RT5665_I2S_MS_SFT
1250 #define RT5665_I2S_MS_M
1251 #define RT5665_I2S_MS_S
1252 #define RT5665_I2S_PIN_CFG_MASK
1253 #define RT5665_I2S_PIN_CFG_SFT
1254 #define RT5665_I2S_CLK_SEL_MASK
1255 #define RT5665_I2S_CLK_SEL_SFT
1256 #define RT5665_I2S_BP_MASK
1257 #define RT5665_I2S_BP_SFT
1258 #define RT5665_I2S_BP_NOR
1259 #define RT5665_I2S_BP_INV
1260 #define RT5665_I2S_DL_MASK
1261 #define RT5665_I2S_DL_SFT
1262 #define RT5665_I2S_DL_16
1263 #define RT5665_I2S_DL_20
1264 #define RT5665_I2S_DL_24
1265 #define RT5665_I2S_DL_8
1266 #define RT5665_I2S_DF_MASK
1267 #define RT5665_I2S_DF_SFT
1268 #define RT5665_I2S_DF_I2S
1269 #define RT5665_I2S_DF_LEFT
1270 #define RT5665_I2S_DF_PCM_A
1271 #define RT5665_I2S_DF_PCM_B
1272 #define RT5665_I2S_DF_PCM_A_N
1273 #define RT5665_I2S_DF_PCM_B_N
1274
1275 /* ADC/DAC Clock Control 1 (0x0073) */
1276 #define RT5665_I2S_PD1_MASK
1277 #define RT5665_I2S_PD1_SFT
1278 #define RT5665_I2S_PD1_1
1279 #define RT5665_I2S_PD1_2
1280 #define RT5665_I2S_PD1_3
1281 #define RT5665_I2S_PD1_4
1282 #define RT5665_I2S_PD1_6
1283 #define RT5665_I2S_PD1_8
1284 #define RT5665_I2S_PD1_12
1285 #define RT5665_I2S_PD1_16
1286 #define RT5665_I2S_M_PD2_MASK
1287 #define RT5665_I2S_M_PD2_SFT
1288 #define RT5665_I2S_M_PD2_1
1289 #define RT5665_I2S_M_PD2_2
1290 #define RT5665_I2S_M_PD2_3
1291 #define RT5665_I2S_M_PD2_4
1292 #define RT5665_I2S_M_PD2_6
1293 #define RT5665_I2S_M_PD2_8
1294 #define RT5665_I2S_M_PD2_12
1295 #define RT5665_I2S_M_PD2_16
1296 #define RT5665_I2S_CLK_SRC_MASK
1297 #define RT5665_I2S_CLK_SRC_SFT
1298 #define RT5665_I2S_CLK_SRC_MCLK
1299 #define RT5665_I2S_CLK_SRC_PLL1
1300 #define RT5665_I2S_CLK_SRC_RCCLK
1301 #define RT5665_DAC_OSR_MASK
1302 #define RT5665_DAC_OSR_SFT
1303 #define RT5665_DAC_OSR_128
1304 #define RT5665_DAC_OSR_64
1305 #define RT5665_DAC_OSR_32
1306 #define RT5665_ADC_OSR_MASK
1307 #define RT5665_ADC_OSR_SFT
1308 #define RT5665_ADC_OSR_128
1309 #define RT5665_ADC_OSR_64
1310 #define RT5665_ADC_OSR_32
1311
1312 /* ADC/DAC Clock Control 2 (0x0074) */
1313 #define RT5665_I2S_BCLK_MS2_MASK
1314 #define RT5665_I2S_BCLK_MS2_SFT
1315 #define RT5665_I2S_BCLK_MS2_32
1316 #define RT5665_I2S_BCLK_MS2_64
1317 #define RT5665_I2S_PD2_MASK
1318 #define RT5665_I2S_PD2_SFT
1319 #define RT5665_I2S_PD2_1
1320 #define RT5665_I2S_PD2_2
1321 #define RT5665_I2S_PD2_3
1322 #define RT5665_I2S_PD2_4
1323 #define RT5665_I2S_PD2_6
1324 #define RT5665_I2S_PD2_8
1325 #define RT5665_I2S_PD2_12
1326 #define RT5665_I2S_PD2_16
1327 #define RT5665_I2S_BCLK_MS3_MASK
1328 #define RT5665_I2S_BCLK_MS3_SFT
1329 #define RT5665_I2S_BCLK_MS3_32
1330 #define RT5665_I2S_BCLK_MS3_64
1331 #define RT5665_I2S_PD3_MASK
1332 #define RT5665_I2S_PD3_SFT
1333 #define RT5665_I2S_PD3_1
1334 #define RT5665_I2S_PD3_2
1335 #define RT5665_I2S_PD3_3
1336 #define RT5665_I2S_PD3_4
1337 #define RT5665_I2S_PD3_6
1338 #define RT5665_I2S_PD3_8
1339 #define RT5665_I2S_PD3_12
1340 #define RT5665_I2S_PD3_16
1341 #define RT5665_I2S_PD4_MASK
1342 #define RT5665_I2S_PD4_SFT
1343 #define RT5665_I2S_PD4_1
1344 #define RT5665_I2S_PD4_2
1345 #define RT5665_I2S_PD4_3
1346 #define RT5665_I2S_PD4_4
1347 #define RT5665_I2S_PD4_6
1348 #define RT5665_I2S_PD4_8
1349 #define RT5665_I2S_PD4_12
1350 #define RT5665_I2S_PD4_16
1351
1352 /* TDM control 1 (0x0078) */
1353 #define RT5665_I2S1_MODE_MASK
1354 #define RT5665_I2S1_MODE_I2S
1355 #define RT5665_I2S1_MODE_TDM
1356 #define RT5665_TDM_IN_CH_MASK
1357 #define RT5665_TDM_IN_CH_2
1358 #define RT5665_TDM_IN_CH_4
1359 #define RT5665_TDM_IN_CH_6
1360 #define RT5665_TDM_IN_CH_8
1361 #define RT5665_TDM_OUT_CH_MASK
1362 #define RT5665_TDM_OUT_CH_2
1363 #define RT5665_TDM_OUT_CH_4
1364 #define RT5665_TDM_OUT_CH_6
1365 #define RT5665_TDM_OUT_CH_8
1366 #define RT5665_TDM_IN_LEN_MASK
1367 #define RT5665_TDM_IN_LEN_16
1368 #define RT5665_TDM_IN_LEN_20
1369 #define RT5665_TDM_IN_LEN_24
1370 #define RT5665_TDM_IN_LEN_32
1371 #define RT5665_TDM_OUT_LEN_MASK
1372 #define RT5665_TDM_OUT_LEN_16
1373 #define RT5665_TDM_OUT_LEN_20
1374 #define RT5665_TDM_OUT_LEN_24
1375 #define RT5665_TDM_OUT_LEN_32
1376
1377
1378 /* TDM control 2 (0x0079) */
1379 #define RT5665_I2S1_1_DS_ADC_SLOT01_SFT
1380 #define RT5665_I2S1_1_DS_ADC_SLOT23_SFT
1381 #define RT5665_I2S1_1_DS_ADC_SLOT45_SFT
1382 #define RT5665_I2S1_1_DS_ADC_SLOT67_SFT
1383 #define RT5665_I2S1_2_DS_ADC_SLOT01_SFT
1384 #define RT5665_I2S1_2_DS_ADC_SLOT23_SFT
1385 #define RT5665_I2S1_2_DS_ADC_SLOT45_SFT
1386 #define RT5665_I2S1_2_DS_ADC_SLOT67_SFT
1387
1388 /* TDM control 3/4 (0x007a) (0x007b) */
1389 #define RT5665_IF1_ADC1_SEL_SFT
1390 #define RT5665_IF1_ADC2_SEL_SFT
1391 #define RT5665_IF1_ADC3_SEL_SFT
1392 #define RT5665_IF1_ADC4_SEL_SFT
1393 #define RT5665_TDM_ADC_SEL_SFT
1394 #define RT5665_TDM_ADC_CTRL_MASK
1395 #define RT5665_TDM_ADC_DATA_06
1396
1397 /* Global Clock Control (0x0080) */
1398 #define RT5665_SCLK_SRC_MASK
1399 #define RT5665_SCLK_SRC_SFT
1400 #define RT5665_SCLK_SRC_MCLK
1401 #define RT5665_SCLK_SRC_PLL1
1402 #define RT5665_SCLK_SRC_RCCLK
1403 #define RT5665_PLL1_SRC_MASK
1404 #define RT5665_PLL1_SRC_SFT
1405 #define RT5665_PLL1_SRC_MCLK
1406 #define RT5665_PLL1_SRC_BCLK1
1407 #define RT5665_PLL1_SRC_BCLK2
1408 #define RT5665_PLL1_SRC_BCLK3
1409 #define RT5665_PLL1_PD_MASK
1410 #define RT5665_PLL1_PD_SFT
1411
1412
1413 #define RT5665_PLL_INP_MAX
1414 #define RT5665_PLL_INP_MIN
1415 /* PLL M/N/K Code Control 1 (0x0081) */
1416 #define RT5665_PLL_N_MAX
1417 #define RT5665_PLL_N_MASK
1418 #define RT5665_PLL_N_SFT
1419 #define RT5665_PLL_K_MAX
1420 #define RT5665_PLL_K_MASK
1421 #define RT5665_PLL_K_SFT
1422
1423 /* PLL M/N/K Code Control 2 (0x0082) */
1424 #define RT5665_PLL_M_MAX
1425 #define RT5665_PLL_M_MASK
1426 #define RT5665_PLL_M_SFT
1427 #define RT5665_PLL_M_BP
1428 #define RT5665_PLL_M_BP_SFT
1429 #define RT5665_PLL_K_BP
1430 #define RT5665_PLL_K_BP_SFT
1431
1432 /* PLL tracking mode 1 (0x0083) */
1433 #define RT5665_I2S3_ASRC_MASK
1434 #define RT5665_I2S3_ASRC_SFT
1435 #define RT5665_I2S2_ASRC_MASK
1436 #define RT5665_I2S2_ASRC_SFT
1437 #define RT5665_I2S1_ASRC_MASK
1438 #define RT5665_I2S1_ASRC_SFT
1439 #define RT5665_DAC_STO1_ASRC_MASK
1440 #define RT5665_DAC_STO1_ASRC_SFT
1441 #define RT5665_DAC_STO2_ASRC_MASK
1442 #define RT5665_DAC_STO2_ASRC_SFT
1443 #define RT5665_DAC_MONO_L_ASRC_MASK
1444 #define RT5665_DAC_MONO_L_ASRC_SFT
1445 #define RT5665_DAC_MONO_R_ASRC_MASK
1446 #define RT5665_DAC_MONO_R_ASRC_SFT
1447 #define RT5665_DMIC_STO1_ASRC_MASK
1448 #define RT5665_DMIC_STO1_ASRC_SFT
1449 #define RT5665_DMIC_STO2_ASRC_MASK
1450 #define RT5665_DMIC_STO2_ASRC_SFT
1451 #define RT5665_DMIC_MONO_L_ASRC_MASK
1452 #define RT5665_DMIC_MONO_L_ASRC_SFT
1453 #define RT5665_DMIC_MONO_R_ASRC_MASK
1454 #define RT5665_DMIC_MONO_R_ASRC_SFT
1455 #define RT5665_ADC_STO1_ASRC_MASK
1456 #define RT5665_ADC_STO1_ASRC_SFT
1457 #define RT5665_ADC_STO2_ASRC_MASK
1458 #define RT5665_ADC_STO2_ASRC_SFT
1459 #define RT5665_ADC_MONO_L_ASRC_MASK
1460 #define RT5665_ADC_MONO_L_ASRC_SFT
1461 #define RT5665_ADC_MONO_R_ASRC_MASK
1462 #define RT5665_ADC_MONO_R_ASRC_SFT
1463
1464 /* PLL tracking mode 2 (0x0084)*/
1465 #define RT5665_DA_STO1_CLK_SEL_MASK
1466 #define RT5665_DA_STO1_CLK_SEL_SFT
1467 #define RT5665_DA_STO2_CLK_SEL_MASK
1468 #define RT5665_DA_STO2_CLK_SEL_SFT
1469 #define RT5665_DA_MONOL_CLK_SEL_MASK
1470 #define RT5665_DA_MONOL_CLK_SEL_SFT
1471 #define RT5665_DA_MONOR_CLK_SEL_MASK
1472 #define RT5665_DA_MONOR_CLK_SEL_SFT
1473
1474 /* PLL tracking mode 3 (0x0085)*/
1475 #define RT5665_AD_STO1_CLK_SEL_MASK
1476 #define RT5665_AD_STO1_CLK_SEL_SFT
1477 #define RT5665_AD_STO2_CLK_SEL_MASK
1478 #define RT5665_AD_STO2_CLK_SEL_SFT
1479 #define RT5665_AD_MONOL_CLK_SEL_MASK
1480 #define RT5665_AD_MONOL_CLK_SEL_SFT
1481 #define RT5665_AD_MONOR_CLK_SEL_MASK
1482 #define RT5665_AD_MONOR_CLK_SEL_SFT
1483
1484 /* ASRC Control 4 (0x0086) */
1485 #define RT5665_I2S1_RATE_MASK
1486 #define RT5665_I2S1_RATE_SFT
1487 #define RT5665_I2S2_RATE_MASK
1488 #define RT5665_I2S2_RATE_SFT
1489 #define RT5665_I2S3_RATE_MASK
1490 #define RT5665_I2S3_RATE_SFT
1491
1492 /* Depop Mode Control 1 (0x008e) */
1493 #define RT5665_PUMP_EN
1494
1495 /* Depop Mode Control 2 (0x8f) */
1496 #define RT5665_DEPOP_MASK
1497 #define RT5665_DEPOP_SFT
1498 #define RT5665_DEPOP_AUTO
1499 #define RT5665_DEPOP_MAN
1500 #define RT5665_RAMP_MASK
1501 #define RT5665_RAMP_SFT
1502 #define RT5665_RAMP_DIS
1503 #define RT5665_RAMP_EN
1504 #define RT5665_BPS_MASK
1505 #define RT5665_BPS_SFT
1506 #define RT5665_BPS_DIS
1507 #define RT5665_BPS_EN
1508 #define RT5665_FAST_UPDN_MASK
1509 #define RT5665_FAST_UPDN_SFT
1510 #define RT5665_FAST_UPDN_DIS
1511 #define RT5665_FAST_UPDN_EN
1512 #define RT5665_MRES_MASK
1513 #define RT5665_MRES_SFT
1514 #define RT5665_MRES_15MO
1515 #define RT5665_MRES_25MO
1516 #define RT5665_MRES_35MO
1517 #define RT5665_MRES_45MO
1518 #define RT5665_VLO_MASK
1519 #define RT5665_VLO_SFT
1520 #define RT5665_VLO_3V
1521 #define RT5665_VLO_32V
1522 #define RT5665_DIG_DP_MASK
1523 #define RT5665_DIG_DP_SFT
1524 #define RT5665_DIG_DP_DIS
1525 #define RT5665_DIG_DP_EN
1526 #define RT5665_DP_TH_MASK
1527 #define RT5665_DP_TH_SFT
1528
1529 /* Depop Mode Control 3 (0x90) */
1530 #define RT5665_CP_SYS_MASK
1531 #define RT5665_CP_SYS_SFT
1532 #define RT5665_CP_FQ1_MASK
1533 #define RT5665_CP_FQ1_SFT
1534 #define RT5665_CP_FQ2_MASK
1535 #define RT5665_CP_FQ2_SFT
1536 #define RT5665_CP_FQ3_MASK
1537 #define RT5665_CP_FQ3_SFT
1538 #define RT5665_CP_FQ_1_5_KHZ
1539 #define RT5665_CP_FQ_3_KHZ
1540 #define RT5665_CP_FQ_6_KHZ
1541 #define RT5665_CP_FQ_12_KHZ
1542 #define RT5665_CP_FQ_24_KHZ
1543 #define RT5665_CP_FQ_48_KHZ
1544 #define RT5665_CP_FQ_96_KHZ
1545 #define RT5665_CP_FQ_192_KHZ
1546
1547 /* HPOUT charge pump 1 (0x0091) */
1548 #define RT5665_OSW_L_MASK
1549 #define RT5665_OSW_L_SFT
1550 #define RT5665_OSW_L_DIS
1551 #define RT5665_OSW_L_EN
1552 #define RT5665_OSW_R_MASK
1553 #define RT5665_OSW_R_SFT
1554 #define RT5665_OSW_R_DIS
1555 #define RT5665_OSW_R_EN
1556 #define RT5665_PM_HP_MASK
1557 #define RT5665_PM_HP_SFT
1558 #define RT5665_PM_HP_LV
1559 #define RT5665_PM_HP_MV
1560 #define RT5665_PM_HP_HV
1561 #define RT5665_IB_HP_MASK
1562 #define RT5665_IB_HP_SFT
1563 #define RT5665_IB_HP_125IL
1564 #define RT5665_IB_HP_25IL
1565 #define RT5665_IB_HP_5IL
1566 #define RT5665_IB_HP_1IL
1567
1568 /* PV detection and SPK gain control (0x92) *
1569 #define RT5665_PVDD_DET_MASK
1570 #define RT5665_PVDD_DET_SFT
1571 #define RT5665_PVDD_DET_DIS
1572 #define RT5665_PVDD_DET_EN
1573 #define RT5665_SPK_AG_MASK
1574 #define RT5665_SPK_AG_SFT
1575 #define RT5665_SPK_AG_DIS
1576 #define RT5665_SPK_AG_EN
1577
1578 /* Micbias Control1 (0x93) */
1579 #define RT5665_MIC1_BS_MASK
1580 #define RT5665_MIC1_BS_SFT
1581 #define RT5665_MIC1_BS_9AV
1582 #define RT5665_MIC1_BS_75AV
1583 #define RT5665_MIC2_BS_MASK
1584 #define RT5665_MIC2_BS_SFT
1585 #define RT5665_MIC2_BS_9AV
1586 #define RT5665_MIC2_BS_75AV
1587 #define RT5665_MIC1_CLK_MASK
1588 #define RT5665_MIC1_CLK_SFT
1589 #define RT5665_MIC1_CLK_DIS
1590 #define RT5665_MIC1_CLK_EN
1591 #define RT5665_MIC2_CLK_MASK
1592 #define RT5665_MIC2_CLK_SFT
1593 #define RT5665_MIC2_CLK_DIS
1594 #define RT5665_MIC2_CLK_EN
1595 #define RT5665_MIC1_OVCD_MASK
1596 #define RT5665_MIC1_OVCD_SFT
1597 #define RT5665_MIC1_OVCD_DIS
1598 #define RT5665_MIC1_OVCD_EN
1599 #define RT5665_MIC1_OVTH_MASK
1600 #define RT5665_MIC1_OVTH_SFT
1601 #define RT5665_MIC1_OVTH_600UA
1602 #define RT5665_MIC1_OVTH_1500UA
1603 #define RT5665_MIC1_OVTH_2000UA
1604 #define RT5665_MIC2_OVCD_MASK
1605 #define RT5665_MIC2_OVCD_SFT
1606 #define RT5665_MIC2_OVCD_DIS
1607 #define RT5665_MIC2_OVCD_EN
1608 #define RT5665_MIC2_OVTH_MASK
1609 #define RT5665_MIC2_OVTH_SFT
1610 #define RT5665_MIC2_OVTH_600UA
1611 #define RT5665_MIC2_OVTH_1500UA
1612 #define RT5665_MIC2_OVTH_2000UA
1613 #define RT5665_PWR_MB_MASK
1614 #define RT5665_PWR_MB_SFT
1615 #define RT5665_PWR_MB_PD
1616 #define RT5665_PWR_MB_PU
1617
1618 /* Micbias Control2 (0x94) */
1619 #define RT5665_PWR_CLK25M_MASK
1620 #define RT5665_PWR_CLK25M_SFT
1621 #define RT5665_PWR_CLK25M_PD
1622 #define RT5665_PWR_CLK25M_PU
1623 #define RT5665_PWR_CLK1M_MASK
1624 #define RT5665_PWR_CLK1M_SFT
1625 #define RT5665_PWR_CLK1M_PD
1626 #define RT5665_PWR_CLK1M_PU
1627
1628 /* I2S Master Mode Clock Control 1 (0x00a0) *
1629 #define RT5665_CLK_SRC_MCLK
1630 #define RT5665_CLK_SRC_PLL1
1631 #define RT5665_CLK_SRC_RCCLK
1632 #define RT5665_I2S_PD_1
1633 #define RT5665_I2S_PD_2
1634 #define RT5665_I2S_PD_3
1635 #define RT5665_I2S_PD_4
1636 #define RT5665_I2S_PD_6
1637 #define RT5665_I2S_PD_8
1638 #define RT5665_I2S_PD_12
1639 #define RT5665_I2S_PD_16
1640 #define RT5665_I2S2_SRC_MASK
1641 #define RT5665_I2S2_SRC_SFT
1642 #define RT5665_I2S2_M_PD_MASK
1643 #define RT5665_I2S2_M_PD_SFT
1644 #define RT5665_I2S3_SRC_MASK
1645 #define RT5665_I2S3_SRC_SFT
1646 #define RT5665_I2S3_M_PD_MASK
1647 #define RT5665_I2S3_M_PD_SFT
1648
1649
1650 /* EQ Control 1 (0x00b0) */
1651 #define RT5665_EQ_SRC_DAC
1652 #define RT5665_EQ_SRC_ADC
1653 #define RT5665_EQ_UPD
1654 #define RT5665_EQ_UPD_BIT
1655 #define RT5665_EQ_CD_MASK
1656 #define RT5665_EQ_CD_SFT
1657 #define RT5665_EQ_CD_DIS
1658 #define RT5665_EQ_CD_EN
1659 #define RT5665_EQ_DITH_MASK
1660 #define RT5665_EQ_DITH_SFT
1661 #define RT5665_EQ_DITH_NOR
1662 #define RT5665_EQ_DITH_LSB
1663 #define RT5665_EQ_DITH_LSB_1
1664 #define RT5665_EQ_DITH_LSB_2
1665
1666 /* IRQ Control 1 (0x00b7) */
1667 #define RT5665_JD1_1_EN_MASK
1668 #define RT5665_JD1_1_EN_SFT
1669 #define RT5665_JD1_1_DIS
1670 #define RT5665_JD1_1_EN
1671 #define RT5665_JD1_2_EN_MASK
1672 #define RT5665_JD1_2_EN_SFT
1673 #define RT5665_JD1_2_DIS
1674 #define RT5665_JD1_2_EN
1675
1676 /* IRQ Control 2 (0x00b8) */
1677 #define RT5665_IL_IRQ_MASK
1678 #define RT5665_IL_IRQ_DIS
1679 #define RT5665_IL_IRQ_EN
1680
1681 /* IRQ Control 5 (0x00ba) */
1682 #define RT5665_IRQ_JD_EN
1683 #define RT5665_IRQ_JD_EN_SFT
1684
1685 /* GPIO Control 1 (0x00c0) */
1686 #define RT5665_GP1_PIN_MASK
1687 #define RT5665_GP1_PIN_SFT
1688 #define RT5665_GP1_PIN_GPIO1
1689 #define RT5665_GP1_PIN_IRQ
1690 #define RT5665_GP2_PIN_MASK
1691 #define RT5665_GP2_PIN_SFT
1692 #define RT5665_GP2_PIN_GPIO2
1693 #define RT5665_GP2_PIN_BCLK2
1694 #define RT5665_GP2_PIN_PDM_SCL
1695 #define RT5665_GP3_PIN_MASK
1696 #define RT5665_GP3_PIN_SFT
1697 #define RT5665_GP3_PIN_GPIO3
1698 #define RT5665_GP3_PIN_LRCK2
1699 #define RT5665_GP3_PIN_PDM_SDA
1700 #define RT5665_GP4_PIN_MASK
1701 #define RT5665_GP4_PIN_SFT
1702 #define RT5665_GP4_PIN_GPIO4
1703 #define RT5665_GP4_PIN_DACDAT2_1
1704 #define RT5665_GP4_PIN_DMIC1_SDA
1705 #define RT5665_GP5_PIN_MASK
1706 #define RT5665_GP5_PIN_SFT
1707 #define RT5665_GP5_PIN_GPIO5
1708 #define RT5665_GP5_PIN_ADCDAT2_1
1709 #define RT5665_GP5_PIN_DMIC2_SDA
1710 #define RT5665_GP6_PIN_MASK
1711 #define RT5665_GP6_PIN_SFT
1712 #define RT5665_GP6_PIN_GPIO6
1713 #define RT5665_GP6_PIN_BCLK3
1714 #define RT5665_GP6_PIN_PDM_SCL
1715 #define RT5665_GP7_PIN_MASK
1716 #define RT5665_GP7_PIN_SFT
1717 #define RT5665_GP7_PIN_GPIO7
1718 #define RT5665_GP7_PIN_LRCK3
1719 #define RT5665_GP7_PIN_PDM_SDA
1720 #define RT5665_GP8_PIN_MASK
1721 #define RT5665_GP8_PIN_SFT
1722 #define RT5665_GP8_PIN_GPIO8
1723 #define RT5665_GP8_PIN_DACDAT3
1724 #define RT5665_GP8_PIN_DMIC2_SCL
1725 #define RT5665_GP8_PIN_DACDAT2_2
1726
1727
1728 /* GPIO Control 2 (0x00c1)*/
1729 #define RT5665_GP9_PIN_MASK
1730 #define RT5665_GP9_PIN_SFT
1731 #define RT5665_GP9_PIN_GPIO9
1732 #define RT5665_GP9_PIN_ADCDAT3
1733 #define RT5665_GP9_PIN_DMIC1_SCL
1734 #define RT5665_GP9_PIN_ADCDAT2_2
1735 #define RT5665_GP10_PIN_MASK
1736 #define RT5665_GP10_PIN_SFT
1737 #define RT5665_GP10_PIN_GPIO10
1738 #define RT5665_GP10_PIN_ADCDAT1_2
1739 #define RT5665_GP10_PIN_LPD
1740 #define RT5665_GP1_PF_MASK
1741 #define RT5665_GP1_PF_IN
1742 #define RT5665_GP1_PF_OUT
1743 #define RT5665_GP1_OUT_MASK
1744 #define RT5665_GP1_OUT_H
1745 #define RT5665_GP1_OUT_L
1746 #define RT5665_GP2_PF_MASK
1747 #define RT5665_GP2_PF_IN
1748 #define RT5665_GP2_PF_OUT
1749 #define RT5665_GP2_OUT_MASK
1750 #define RT5665_GP2_OUT_H
1751 #define RT5665_GP2_OUT_L
1752 #define RT5665_GP3_PF_MASK
1753 #define RT5665_GP3_PF_IN
1754 #define RT5665_GP3_PF_OUT
1755 #define RT5665_GP3_OUT_MASK
1756 #define RT5665_GP3_OUT_H
1757 #define RT5665_GP3_OUT_L
1758 #define RT5665_GP4_PF_MASK
1759 #define RT5665_GP4_PF_IN
1760 #define RT5665_GP4_PF_OUT
1761 #define RT5665_GP4_OUT_MASK
1762 #define RT5665_GP4_OUT_H
1763 #define RT5665_GP4_OUT_L
1764 #define RT5665_GP5_PF_MASK
1765 #define RT5665_GP5_PF_IN
1766 #define RT5665_GP5_PF_OUT
1767 #define RT5665_GP5_OUT_MASK
1768 #define RT5665_GP5_OUT_H
1769 #define RT5665_GP5_OUT_L
1770 #define RT5665_GP6_PF_MASK
1771 #define RT5665_GP6_PF_IN
1772 #define RT5665_GP6_PF_OUT
1773 #define RT5665_GP6_OUT_MASK
1774 #define RT5665_GP6_OUT_H
1775 #define RT5665_GP6_OUT_L
1776
1777
1778 /* GPIO Control 3 (0x00c2) */
1779 #define RT5665_GP7_PF_MASK
1780 #define RT5665_GP7_PF_IN
1781 #define RT5665_GP7_PF_OUT
1782 #define RT5665_GP7_OUT_MASK
1783 #define RT5665_GP7_OUT_H
1784 #define RT5665_GP7_OUT_L
1785 #define RT5665_GP8_PF_MASK
1786 #define RT5665_GP8_PF_IN
1787 #define RT5665_GP8_PF_OUT
1788 #define RT5665_GP8_OUT_MASK
1789 #define RT5665_GP8_OUT_H
1790 #define RT5665_GP8_OUT_L
1791 #define RT5665_GP9_PF_MASK
1792 #define RT5665_GP9_PF_IN
1793 #define RT5665_GP9_PF_OUT
1794 #define RT5665_GP9_OUT_MASK
1795 #define RT5665_GP9_OUT_H
1796 #define RT5665_GP9_OUT_L
1797 #define RT5665_GP10_PF_MASK
1798 #define RT5665_GP10_PF_IN
1799 #define RT5665_GP10_PF_OUT
1800 #define RT5665_GP10_OUT_MASK
1801 #define RT5665_GP10_OUT_H
1802 #define RT5665_GP10_OUT_L
1803 #define RT5665_GP11_PF_MASK
1804 #define RT5665_GP11_PF_IN
1805 #define RT5665_GP11_PF_OUT
1806 #define RT5665_GP11_OUT_MASK
1807 #define RT5665_GP11_OUT_H
1808 #define RT5665_GP11_OUT_L
1809
1810 /* Soft volume and zero cross control 1 (0x00
1811 #define RT5665_SV_MASK
1812 #define RT5665_SV_SFT
1813 #define RT5665_SV_DIS
1814 #define RT5665_SV_EN
1815 #define RT5665_OUT_SV_MASK
1816 #define RT5665_OUT_SV_SFT
1817 #define RT5665_OUT_SV_DIS
1818 #define RT5665_OUT_SV_EN
1819 #define RT5665_HP_SV_MASK
1820 #define RT5665_HP_SV_SFT
1821 #define RT5665_HP_SV_DIS
1822 #define RT5665_HP_SV_EN
1823 #define RT5665_ZCD_DIG_MASK
1824 #define RT5665_ZCD_DIG_SFT
1825 #define RT5665_ZCD_DIG_DIS
1826 #define RT5665_ZCD_DIG_EN
1827 #define RT5665_ZCD_MASK
1828 #define RT5665_ZCD_SFT
1829 #define RT5665_ZCD_PD
1830 #define RT5665_ZCD_PU
1831 #define RT5665_SV_DLY_MASK
1832 #define RT5665_SV_DLY_SFT
1833
1834 /* Soft volume and zero cross control 2 (0x00
1835 #define RT5665_ZCD_HP_MASK
1836 #define RT5665_ZCD_HP_SFT
1837 #define RT5665_ZCD_HP_DIS
1838 #define RT5665_ZCD_HP_EN
1839
1840 /* 4 Button Inline Command Control 2 (0x00e0)
1841 #define RT5665_4BTN_IL_MASK
1842 #define RT5665_4BTN_IL_EN
1843 #define RT5665_4BTN_IL_DIS
1844 #define RT5665_4BTN_IL_RST_MASK
1845 #define RT5665_4BTN_IL_NOR
1846 #define RT5665_4BTN_IL_RST
1847
1848 /* Analog JD Control 1 (0x00f0) */
1849 #define RT5665_JD1_MODE_MASK
1850 #define RT5665_JD1_MODE_0
1851 #define RT5665_JD1_MODE_1
1852 #define RT5665_JD1_MODE_2
1853
1854 /* Jack Detect Control 3 (0x00f8) */
1855 #define RT5665_JD_TRI_HPO_SEL_MASK
1856 #define RT5665_JD_TRI_HPO_SEL_SFT
1857 #define RT5665_JD_HPO_GPIO_JD1
1858 #define RT5665_JD_HPO_JD1_1
1859 #define RT5665_JD_HPO_JD1_2
1860 #define RT5665_JD_HPO_JD2
1861 #define RT5665_JD_HPO_GPIO_JD2
1862 #define RT5665_JD_HPO_JD3
1863 #define RT5665_JD_HPO_JD_D
1864
1865 /* Digital Misc Control (0x00fa) */
1866 #define RT5665_AM_MASK
1867 #define RT5665_AM_EN
1868 #define RT5665_AM_DIS
1869 #define RT5665_DIG_GATE_CTRL
1870 #define RT5665_DIG_GATE_CTRL_SFT
1871
1872 /* Chopper and Clock control for ADC (0x011c)
1873 #define RT5665_M_RF_DIG_MASK
1874 #define RT5665_M_RF_DIG_SFT
1875 #define RT5665_M_RI_DIG
1876
1877 /* Chopper and Clock control for DAC (0x013a)
1878 #define RT5665_CKXEN_DAC1_MASK
1879 #define RT5665_CKXEN_DAC1_SFT
1880 #define RT5665_CKGEN_DAC1_MASK
1881 #define RT5665_CKGEN_DAC1_SFT
1882 #define RT5665_CKXEN_DAC2_MASK
1883 #define RT5665_CKXEN_DAC2_SFT
1884 #define RT5665_CKGEN_DAC2_MASK
1885 #define RT5665_CKGEN_DAC2_SFT
1886
1887 /* Chopper and Clock control for ADC (0x013b)
1888 #define RT5665_CKXEN_ADC1_MASK
1889 #define RT5665_CKXEN_ADC1_SFT
1890 #define RT5665_CKGEN_ADC1_MASK
1891 #define RT5665_CKGEN_ADC1_SFT
1892 #define RT5665_CKXEN_ADC2_MASK
1893 #define RT5665_CKXEN_ADC2_SFT
1894 #define RT5665_CKGEN_ADC2_MASK
1895 #define RT5665_CKGEN_ADC2_SFT
1896
1897 /* Volume test (0x013f)*/
1898 #define RT5665_SEL_CLK_VOL_MASK
1899 #define RT5665_SEL_CLK_VOL_EN
1900 #define RT5665_SEL_CLK_VOL_DIS
1901
1902 /* Test Mode Control 1 (0x0145) */
1903 #define RT5665_AD2DA_LB_MASK
1904 #define RT5665_AD2DA_LB_SFT
1905
1906 /* Stereo Noise Gate Control 1 (0x0160) */
1907 #define RT5665_NG2_EN_MASK
1908 #define RT5665_NG2_EN
1909 #define RT5665_NG2_DIS
1910
1911 /* Stereo1 DAC Silence Detection Control (0x0
1912 #define RT5665_DEB_STO_DAC_MASK
1913 #define RT5665_DEB_80_MS
1914
1915 /* SAR ADC Inline Command Control 1 (0x0210)
1916 #define RT5665_SAR_BUTT_DET_MASK
1917 #define RT5665_SAR_BUTT_DET_EN
1918 #define RT5665_SAR_BUTT_DET_DIS
1919 #define RT5665_SAR_BUTDET_MODE_MASK
1920 #define RT5665_SAR_BUTDET_POW_SAV
1921 #define RT5665_SAR_BUTDET_POW_NORM
1922 #define RT5665_SAR_BUTDET_RST_MASK
1923 #define RT5665_SAR_BUTDET_RST_NORMAL
1924 #define RT5665_SAR_BUTDET_RST
1925 #define RT5665_SAR_POW_MASK
1926 #define RT5665_SAR_POW_EN
1927 #define RT5665_SAR_POW_DIS
1928 #define RT5665_SAR_RST_MASK
1929 #define RT5665_SAR_RST_NORMAL
1930 #define RT5665_SAR_RST
1931 #define RT5665_SAR_BYPASS_MASK
1932 #define RT5665_SAR_BYPASS_EN
1933 #define RT5665_SAR_BYPASS_DIS
1934 #define RT5665_SAR_SEL_MB1_MASK
1935 #define RT5665_SAR_SEL_MB1_SEL
1936 #define RT5665_SAR_SEL_MB1_NOSEL
1937 #define RT5665_SAR_SEL_MB2_MASK
1938 #define RT5665_SAR_SEL_MB2_SEL
1939 #define RT5665_SAR_SEL_MB2_NOSEL
1940 #define RT5665_SAR_SEL_MODE_MASK
1941 #define RT5665_SAR_SEL_MODE_CMP
1942 #define RT5665_SAR_SEL_MODE_ADC
1943 #define RT5665_SAR_SEL_MB1_MB2_MASK
1944 #define RT5665_SAR_SEL_MB1_MB2_AUTO
1945 #define RT5665_SAR_SEL_MB1_MB2_MANU
1946 #define RT5665_SAR_SEL_SIGNAL_MASK
1947 #define RT5665_SAR_SEL_SIGNAL_AUTO
1948 #define RT5665_SAR_SEL_SIGNAL_MANU
1949
1950 /* System Clock Source */
1951 enum {
1952 RT5665_SCLK_S_MCLK,
1953 RT5665_SCLK_S_PLL1,
1954 RT5665_SCLK_S_RCCLK,
1955 };
1956
1957 /* PLL1 Source */
1958 enum {
1959 RT5665_PLL1_S_MCLK,
1960 RT5665_PLL1_S_BCLK1,
1961 RT5665_PLL1_S_BCLK2,
1962 RT5665_PLL1_S_BCLK3,
1963 RT5665_PLL1_S_BCLK4,
1964 };
1965
1966 enum {
1967 RT5665_AIF1_1,
1968 RT5665_AIF1_2,
1969 RT5665_AIF2_1,
1970 RT5665_AIF2_2,
1971 RT5665_AIF3,
1972 RT5665_AIFS
1973 };
1974
1975 enum {
1976 CODEC_5665,
1977 CODEC_5666,
1978 };
1979
1980 /* filter mask */
1981 enum {
1982 RT5665_DA_STEREO1_FILTER = 0x1,
1983 RT5665_DA_STEREO2_FILTER = (0x1 << 1)
1984 RT5665_DA_MONO_L_FILTER = (0x1 << 2),
1985 RT5665_DA_MONO_R_FILTER = (0x1 << 3),
1986 RT5665_AD_STEREO1_FILTER = (0x1 << 4)
1987 RT5665_AD_STEREO2_FILTER = (0x1 << 5)
1988 RT5665_AD_MONO_L_FILTER = (0x1 << 6),
1989 RT5665_AD_MONO_R_FILTER = (0x1 << 7),
1990 };
1991
1992 enum {
1993 RT5665_CLK_SEL_SYS,
1994 RT5665_CLK_SEL_I2S1_ASRC,
1995 RT5665_CLK_SEL_I2S2_ASRC,
1996 RT5665_CLK_SEL_I2S3_ASRC,
1997 RT5665_CLK_SEL_SYS2,
1998 RT5665_CLK_SEL_SYS3,
1999 RT5665_CLK_SEL_SYS4,
2000 };
2001
2002 int rt5665_sel_asrc_clk_src(struct snd_soc_co
2003 unsigned int filter_mask, uns
2004
2005 #endif /* __RT5665_H__ */
2006
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