1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 /* 3 * sgtl5000.h - SGTL5000 audio codec interface 4 * 5 * Copyright 2010-2011 Freescale Semiconductor 6 */ 7 8 #ifndef _SGTL5000_H 9 #define _SGTL5000_H 10 11 /* 12 * Registers addresses 13 */ 14 #define SGTL5000_CHIP_ID 15 #define SGTL5000_CHIP_DIG_POWER 16 #define SGTL5000_CHIP_CLK_CTRL 17 #define SGTL5000_CHIP_I2S_CTRL 18 #define SGTL5000_CHIP_SSS_CTRL 19 #define SGTL5000_CHIP_ADCDAC_CTRL 20 #define SGTL5000_CHIP_DAC_VOL 21 #define SGTL5000_CHIP_PAD_STRENGTH 22 #define SGTL5000_CHIP_ANA_ADC_CTRL 23 #define SGTL5000_CHIP_ANA_HP_CTRL 24 #define SGTL5000_CHIP_ANA_CTRL 25 #define SGTL5000_CHIP_LINREG_CTRL 26 #define SGTL5000_CHIP_REF_CTRL 27 #define SGTL5000_CHIP_MIC_CTRL 28 #define SGTL5000_CHIP_LINE_OUT_CTRL 29 #define SGTL5000_CHIP_LINE_OUT_VOL 30 #define SGTL5000_CHIP_ANA_POWER 31 #define SGTL5000_CHIP_PLL_CTRL 32 #define SGTL5000_CHIP_CLK_TOP_CTRL 33 #define SGTL5000_CHIP_ANA_STATUS 34 #define SGTL5000_CHIP_SHORT_CTRL 35 #define SGTL5000_CHIP_ANA_TEST2 36 #define SGTL5000_DAP_CTRL 37 #define SGTL5000_DAP_PEQ 38 #define SGTL5000_DAP_BASS_ENHANCE 39 #define SGTL5000_DAP_BASS_ENHANCE_CTRL 40 #define SGTL5000_DAP_AUDIO_EQ 41 #define SGTL5000_DAP_SURROUND 42 #define SGTL5000_DAP_FLT_COEF_ACCESS 43 #define SGTL5000_DAP_COEF_WR_B0_MSB 44 #define SGTL5000_DAP_COEF_WR_B0_LSB 45 #define SGTL5000_DAP_EQ_BASS_BAND0 46 #define SGTL5000_DAP_EQ_BASS_BAND1 47 #define SGTL5000_DAP_EQ_BASS_BAND2 48 #define SGTL5000_DAP_EQ_BASS_BAND3 49 #define SGTL5000_DAP_EQ_BASS_BAND4 50 #define SGTL5000_DAP_MAIN_CHAN 51 #define SGTL5000_DAP_MIX_CHAN 52 #define SGTL5000_DAP_AVC_CTRL 53 #define SGTL5000_DAP_AVC_THRESHOLD 54 #define SGTL5000_DAP_AVC_ATTACK 55 #define SGTL5000_DAP_AVC_DECAY 56 #define SGTL5000_DAP_COEF_WR_B1_MSB 57 #define SGTL5000_DAP_COEF_WR_B1_LSB 58 #define SGTL5000_DAP_COEF_WR_B2_MSB 59 #define SGTL5000_DAP_COEF_WR_B2_LSB 60 #define SGTL5000_DAP_COEF_WR_A1_MSB 61 #define SGTL5000_DAP_COEF_WR_A1_LSB 62 #define SGTL5000_DAP_COEF_WR_A2_MSB 63 #define SGTL5000_DAP_COEF_WR_A2_LSB 64 65 /* 66 * Field Definitions. 67 */ 68 69 /* 70 * SGTL5000_CHIP_ID 71 */ 72 #define SGTL5000_PARTID_MASK 73 #define SGTL5000_PARTID_SHIFT 74 #define SGTL5000_PARTID_WIDTH 75 #define SGTL5000_PARTID_PART_ID 76 #define SGTL5000_REVID_MASK 77 #define SGTL5000_REVID_SHIFT 78 #define SGTL5000_REVID_WIDTH 79 80 /* 81 * SGTL5000_CHIP_DIG_POWER 82 */ 83 #define SGTL5000_DIG_POWER_DEFAULT 84 #define SGTL5000_ADC_EN 85 #define SGTL5000_DAC_EN 86 #define SGTL5000_DAP_POWERUP 87 #define SGTL5000_I2S_OUT_POWERUP 88 #define SGTL5000_I2S_IN_POWERUP 89 90 /* 91 * SGTL5000_CHIP_CLK_CTRL 92 */ 93 #define SGTL5000_CHIP_CLK_CTRL_DEFAULT 94 #define SGTL5000_RATE_MODE_MASK 95 #define SGTL5000_RATE_MODE_SHIFT 96 #define SGTL5000_RATE_MODE_WIDTH 97 #define SGTL5000_RATE_MODE_DIV_1 98 #define SGTL5000_RATE_MODE_DIV_2 99 #define SGTL5000_RATE_MODE_DIV_4 100 #define SGTL5000_RATE_MODE_DIV_6 101 #define SGTL5000_SYS_FS_MASK 102 #define SGTL5000_SYS_FS_SHIFT 103 #define SGTL5000_SYS_FS_WIDTH 104 #define SGTL5000_SYS_FS_32k 105 #define SGTL5000_SYS_FS_44_1k 106 #define SGTL5000_SYS_FS_48k 107 #define SGTL5000_SYS_FS_96k 108 #define SGTL5000_MCLK_FREQ_MASK 109 #define SGTL5000_MCLK_FREQ_SHIFT 110 #define SGTL5000_MCLK_FREQ_WIDTH 111 #define SGTL5000_MCLK_FREQ_256FS 112 #define SGTL5000_MCLK_FREQ_384FS 113 #define SGTL5000_MCLK_FREQ_512FS 114 #define SGTL5000_MCLK_FREQ_PLL 115 116 /* 117 * SGTL5000_CHIP_I2S_CTRL 118 */ 119 #define SGTL5000_I2S_SCLKFREQ_MASK 120 #define SGTL5000_I2S_SCLKFREQ_SHIFT 121 #define SGTL5000_I2S_SCLKFREQ_WIDTH 122 #define SGTL5000_I2S_SCLKFREQ_64FS 123 #define SGTL5000_I2S_SCLKFREQ_32FS 124 #define SGTL5000_I2S_MASTER 125 #define SGTL5000_I2S_SCLK_INV 126 #define SGTL5000_I2S_DLEN_MASK 127 #define SGTL5000_I2S_DLEN_SHIFT 128 #define SGTL5000_I2S_DLEN_WIDTH 129 #define SGTL5000_I2S_DLEN_32 130 #define SGTL5000_I2S_DLEN_24 131 #define SGTL5000_I2S_DLEN_20 132 #define SGTL5000_I2S_DLEN_16 133 #define SGTL5000_I2S_MODE_MASK 134 #define SGTL5000_I2S_MODE_SHIFT 135 #define SGTL5000_I2S_MODE_WIDTH 136 #define SGTL5000_I2S_MODE_I2S_LJ 137 #define SGTL5000_I2S_MODE_RJ 138 #define SGTL5000_I2S_MODE_PCM 139 #define SGTL5000_I2S_LRALIGN 140 #define SGTL5000_I2S_LRPOL 141 142 /* 143 * SGTL5000_CHIP_SSS_CTRL 144 */ 145 #define SGTL5000_DAP_MIX_LRSWAP 146 #define SGTL5000_DAP_LRSWAP 147 #define SGTL5000_DAC_LRSWAP 148 #define SGTL5000_I2S_OUT_LRSWAP 149 #define SGTL5000_DAP_MIX_SEL_MASK 150 #define SGTL5000_DAP_MIX_SEL_SHIFT 151 #define SGTL5000_DAP_MIX_SEL_WIDTH 152 #define SGTL5000_DAP_MIX_SEL_ADC 153 #define SGTL5000_DAP_MIX_SEL_I2S_IN 154 #define SGTL5000_DAP_SEL_MASK 155 #define SGTL5000_DAP_SEL_SHIFT 156 #define SGTL5000_DAP_SEL_WIDTH 157 #define SGTL5000_DAP_SEL_ADC 158 #define SGTL5000_DAP_SEL_I2S_IN 159 #define SGTL5000_DAC_SEL_MASK 160 #define SGTL5000_DAC_SEL_SHIFT 161 #define SGTL5000_DAC_SEL_WIDTH 162 #define SGTL5000_DAC_SEL_ADC 163 #define SGTL5000_DAC_SEL_I2S_IN 164 #define SGTL5000_DAC_SEL_DAP 165 #define SGTL5000_I2S_OUT_SEL_MASK 166 #define SGTL5000_I2S_OUT_SEL_SHIFT 167 #define SGTL5000_I2S_OUT_SEL_WIDTH 168 #define SGTL5000_I2S_OUT_SEL_ADC 169 #define SGTL5000_I2S_OUT_SEL_I2S_IN 170 #define SGTL5000_I2S_OUT_SEL_DAP 171 172 /* 173 * SGTL5000_CHIP_ADCDAC_CTRL 174 */ 175 #define SGTL5000_VOL_BUSY_DAC_RIGHT 176 #define SGTL5000_VOL_BUSY_DAC_LEFT 177 #define SGTL5000_DAC_VOL_RAMP_EN 178 #define SGTL5000_DAC_VOL_RAMP_EXPO 179 #define SGTL5000_DAC_MUTE_RIGHT 180 #define SGTL5000_DAC_MUTE_LEFT 181 #define SGTL5000_ADC_HPF_FREEZE 182 #define SGTL5000_ADC_HPF_BYPASS 183 184 /* 185 * SGTL5000_CHIP_DAC_VOL 186 */ 187 #define SGTL5000_DAC_VOL_RIGHT_MASK 188 #define SGTL5000_DAC_VOL_RIGHT_SHIFT 189 #define SGTL5000_DAC_VOL_RIGHT_WIDTH 190 #define SGTL5000_DAC_VOL_LEFT_MASK 191 #define SGTL5000_DAC_VOL_LEFT_SHIFT 192 #define SGTL5000_DAC_VOL_LEFT_WIDTH 193 194 /* 195 * SGTL5000_CHIP_PAD_STRENGTH 196 */ 197 #define SGTL5000_PAD_I2S_LRCLK_MASK 198 #define SGTL5000_PAD_I2S_LRCLK_SHIFT 199 #define SGTL5000_PAD_I2S_LRCLK_WIDTH 200 #define SGTL5000_PAD_I2S_SCLK_MASK 201 #define SGTL5000_PAD_I2S_SCLK_SHIFT 202 #define SGTL5000_PAD_I2S_SCLK_WIDTH 203 #define SGTL5000_PAD_I2S_DOUT_MASK 204 #define SGTL5000_PAD_I2S_DOUT_SHIFT 205 #define SGTL5000_PAD_I2S_DOUT_WIDTH 206 #define SGTL5000_PAD_I2C_SDA_MASK 207 #define SGTL5000_PAD_I2C_SDA_SHIFT 208 #define SGTL5000_PAD_I2C_SDA_WIDTH 209 #define SGTL5000_PAD_I2C_SCL_MASK 210 #define SGTL5000_PAD_I2C_SCL_SHIFT 211 #define SGTL5000_PAD_I2C_SCL_WIDTH 212 213 /* 214 * SGTL5000_CHIP_ANA_ADC_CTRL 215 */ 216 #define SGTL5000_ADC_VOL_M6DB 217 #define SGTL5000_ADC_VOL_RIGHT_MASK 218 #define SGTL5000_ADC_VOL_RIGHT_SHIFT 219 #define SGTL5000_ADC_VOL_RIGHT_WIDTH 220 #define SGTL5000_ADC_VOL_LEFT_MASK 221 #define SGTL5000_ADC_VOL_LEFT_SHIFT 222 #define SGTL5000_ADC_VOL_LEFT_WIDTH 223 224 /* 225 * SGTL5000_CHIP_ANA_HP_CTRL 226 */ 227 #define SGTL5000_HP_VOL_RIGHT_MASK 228 #define SGTL5000_HP_VOL_RIGHT_SHIFT 229 #define SGTL5000_HP_VOL_RIGHT_WIDTH 230 #define SGTL5000_HP_VOL_LEFT_MASK 231 #define SGTL5000_HP_VOL_LEFT_SHIFT 232 #define SGTL5000_HP_VOL_LEFT_WIDTH 233 234 /* 235 * SGTL5000_CHIP_ANA_CTRL 236 */ 237 #define SGTL5000_CHIP_ANA_CTRL_DEFAULT 238 #define SGTL5000_LINE_OUT_MUTE 239 #define SGTL5000_HP_SEL_MASK 240 #define SGTL5000_HP_SEL_SHIFT 241 #define SGTL5000_HP_SEL_WIDTH 242 #define SGTL5000_HP_SEL_DAC 243 #define SGTL5000_HP_SEL_LINE_IN 244 #define SGTL5000_HP_ZCD_EN 245 #define SGTL5000_HP_MUTE 246 #define SGTL5000_ADC_SEL_MASK 247 #define SGTL5000_ADC_SEL_SHIFT 248 #define SGTL5000_ADC_SEL_WIDTH 249 #define SGTL5000_ADC_SEL_MIC 250 #define SGTL5000_ADC_SEL_LINE_IN 251 #define SGTL5000_ADC_ZCD_EN 252 #define SGTL5000_ADC_MUTE 253 254 /* 255 * SGTL5000_CHIP_LINREG_CTRL 256 */ 257 #define SGTL5000_VDDC_MAN_ASSN_MASK 258 #define SGTL5000_VDDC_MAN_ASSN_SHIFT 259 #define SGTL5000_VDDC_MAN_ASSN_WIDTH 260 #define SGTL5000_VDDC_MAN_ASSN_VDDA 261 #define SGTL5000_VDDC_MAN_ASSN_VDDIO 262 #define SGTL5000_VDDC_ASSN_OVRD 263 #define SGTL5000_LINREG_VDDD_MASK 264 #define SGTL5000_LINREG_VDDD_SHIFT 265 #define SGTL5000_LINREG_VDDD_WIDTH 266 267 /* 268 * SGTL5000_CHIP_REF_CTRL 269 */ 270 #define SGTL5000_ANA_GND_MASK 271 #define SGTL5000_ANA_GND_SHIFT 272 #define SGTL5000_ANA_GND_WIDTH 273 #define SGTL5000_ANA_GND_BASE 274 #define SGTL5000_ANA_GND_STP 275 #define SGTL5000_BIAS_CTRL_MASK 276 #define SGTL5000_BIAS_CTRL_SHIFT 277 #define SGTL5000_BIAS_CTRL_WIDTH 278 #define SGTL5000_SMALL_POP 279 280 /* 281 * SGTL5000_CHIP_MIC_CTRL 282 */ 283 #define SGTL5000_BIAS_R_MASK 284 #define SGTL5000_BIAS_R_SHIFT 285 #define SGTL5000_BIAS_R_WIDTH 286 #define SGTL5000_BIAS_R_off 287 #define SGTL5000_BIAS_R_2K 288 #define SGTL5000_BIAS_R_4k 289 #define SGTL5000_BIAS_R_8k 290 #define SGTL5000_BIAS_VOLT_MASK 291 #define SGTL5000_BIAS_VOLT_SHIFT 292 #define SGTL5000_BIAS_VOLT_WIDTH 293 #define SGTL5000_MIC_GAIN_MASK 294 #define SGTL5000_MIC_GAIN_SHIFT 295 #define SGTL5000_MIC_GAIN_WIDTH 296 297 /* 298 * SGTL5000_CHIP_LINE_OUT_CTRL 299 */ 300 #define SGTL5000_LINE_OUT_CURRENT_MASK 301 #define SGTL5000_LINE_OUT_CURRENT_SHIFT 302 #define SGTL5000_LINE_OUT_CURRENT_WIDTH 303 #define SGTL5000_LINE_OUT_CURRENT_180u 304 #define SGTL5000_LINE_OUT_CURRENT_270u 305 #define SGTL5000_LINE_OUT_CURRENT_360u 306 #define SGTL5000_LINE_OUT_CURRENT_450u 307 #define SGTL5000_LINE_OUT_CURRENT_540u 308 #define SGTL5000_LINE_OUT_GND_MASK 309 #define SGTL5000_LINE_OUT_GND_SHIFT 310 #define SGTL5000_LINE_OUT_GND_WIDTH 311 #define SGTL5000_LINE_OUT_GND_BASE 312 #define SGTL5000_LINE_OUT_GND_STP 313 #define SGTL5000_LINE_OUT_GND_MAX 314 315 /* 316 * SGTL5000_CHIP_LINE_OUT_VOL 317 */ 318 #define SGTL5000_LINE_OUT_VOL_RIGHT_MASK 319 #define SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT 320 #define SGTL5000_LINE_OUT_VOL_RIGHT_WIDTH 321 #define SGTL5000_LINE_OUT_VOL_LEFT_MASK 322 #define SGTL5000_LINE_OUT_VOL_LEFT_SHIFT 323 #define SGTL5000_LINE_OUT_VOL_LEFT_WIDTH 324 325 /* 326 * SGTL5000_CHIP_ANA_POWER 327 */ 328 #define SGTL5000_ANA_POWER_DEFAULT 329 #define SGTL5000_DAC_STEREO 330 #define SGTL5000_LINREG_SIMPLE_POWERUP 331 #define SGTL5000_STARTUP_POWERUP 332 #define SGTL5000_VDDC_CHRGPMP_POWERUP 333 #define SGTL5000_PLL_POWERUP 334 #define SGTL5000_LINEREG_D_POWERUP 335 #define SGTL5000_VCOAMP_POWERUP 336 #define SGTL5000_VAG_POWERUP 337 #define SGTL5000_ADC_STEREO 338 #define SGTL5000_REFTOP_POWERUP 339 #define SGTL5000_HP_POWERUP 340 #define SGTL5000_DAC_POWERUP 341 #define SGTL5000_CAPLESS_HP_POWERUP 342 #define SGTL5000_ADC_POWERUP 343 #define SGTL5000_LINE_OUT_POWERUP 344 345 /* 346 * SGTL5000_CHIP_PLL_CTRL 347 */ 348 #define SGTL5000_PLL_INT_DIV_MASK 349 #define SGTL5000_PLL_INT_DIV_SHIFT 350 #define SGTL5000_PLL_INT_DIV_WIDTH 351 #define SGTL5000_PLL_FRAC_DIV_MASK 352 #define SGTL5000_PLL_FRAC_DIV_SHIFT 353 #define SGTL5000_PLL_FRAC_DIV_WIDTH 354 355 /* 356 * SGTL5000_CHIP_CLK_TOP_CTRL 357 */ 358 #define SGTL5000_INT_OSC_EN 359 #define SGTL5000_INPUT_FREQ_DIV2 360 361 /* 362 * SGTL5000_CHIP_ANA_STATUS 363 */ 364 #define SGTL5000_HP_LRSHORT 365 #define SGTL5000_CAPLESS_SHORT 366 #define SGTL5000_PLL_LOCKED 367 368 /* 369 * SGTL5000_CHIP_SHORT_CTRL 370 */ 371 #define SGTL5000_LVLADJR_MASK 372 #define SGTL5000_LVLADJR_SHIFT 373 #define SGTL5000_LVLADJR_WIDTH 374 #define SGTL5000_LVLADJL_MASK 375 #define SGTL5000_LVLADJL_SHIFT 376 #define SGTL5000_LVLADJL_WIDTH 377 #define SGTL5000_LVLADJC_MASK 378 #define SGTL5000_LVLADJC_SHIFT 379 #define SGTL5000_LVLADJC_WIDTH 380 #define SGTL5000_LR_SHORT_MOD_MASK 381 #define SGTL5000_LR_SHORT_MOD_SHIFT 382 #define SGTL5000_LR_SHORT_MOD_WIDTH 383 #define SGTL5000_CM_SHORT_MOD_MASK 384 #define SGTL5000_CM_SHORT_MOD_SHIFT 385 #define SGTL5000_CM_SHORT_MOD_WIDTH 386 387 /* 388 *SGTL5000_CHIP_ANA_TEST2 389 */ 390 #define SGTL5000_MONO_DAC 391 392 /* 393 * SGTL5000_DAP_CTRL 394 */ 395 #define SGTL5000_DAP_MIX_EN 396 #define SGTL5000_DAP_EN 397 398 #define SGTL5000_SYSCLK 399 #define SGTL5000_LRCLK 400 401 /* 402 * SGTL5000_DAP_AUDIO_EQ 403 */ 404 #define SGTL5000_DAP_SEL_PEQ 405 #define SGTL5000_DAP_SEL_TONE_CTRL 406 #define SGTL5000_DAP_SEL_GEQ 407 408 #endif 409
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