1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* 2 /*
3 * tlv320aic32x4.h 3 * tlv320aic32x4.h
4 */ 4 */
5 5
6 6
7 #ifndef _TLV320AIC32X4_H 7 #ifndef _TLV320AIC32X4_H
8 #define _TLV320AIC32X4_H 8 #define _TLV320AIC32X4_H
9 9
10 struct device; 10 struct device;
11 struct regmap_config; 11 struct regmap_config;
12 12
13 enum aic32x4_type { 13 enum aic32x4_type {
14 AIC32X4_TYPE_AIC32X4 = 0, 14 AIC32X4_TYPE_AIC32X4 = 0,
15 AIC32X4_TYPE_AIC32X6, 15 AIC32X4_TYPE_AIC32X6,
16 AIC32X4_TYPE_TAS2505, 16 AIC32X4_TYPE_TAS2505,
17 }; 17 };
18 18
19 extern const struct regmap_config aic32x4_regm 19 extern const struct regmap_config aic32x4_regmap_config;
20 int aic32x4_probe(struct device *dev, struct r !! 20 int aic32x4_probe(struct device *dev, struct regmap *regmap);
21 enum aic32x4_type type); <<
22 void aic32x4_remove(struct device *dev); 21 void aic32x4_remove(struct device *dev);
23 int aic32x4_register_clocks(struct device *dev 22 int aic32x4_register_clocks(struct device *dev, const char *mclk_name);
24 23
25 /* tlv320aic32x4 register space (in decimal to 24 /* tlv320aic32x4 register space (in decimal to match datasheet) */
26 25
27 #define AIC32X4_REG(page, reg) ((page * 128) 26 #define AIC32X4_REG(page, reg) ((page * 128) + reg)
28 27
29 #define AIC32X4_PSEL AIC32X4_REG(0, 28 #define AIC32X4_PSEL AIC32X4_REG(0, 0)
30 29
31 #define AIC32X4_RESET AIC32X4_REG(0, 30 #define AIC32X4_RESET AIC32X4_REG(0, 1)
32 #define AIC32X4_CLKMUX AIC32X4_REG(0, 31 #define AIC32X4_CLKMUX AIC32X4_REG(0, 4)
33 #define AIC32X4_PLLPR AIC32X4_REG(0, 32 #define AIC32X4_PLLPR AIC32X4_REG(0, 5)
34 #define AIC32X4_PLLJ AIC32X4_REG(0, 33 #define AIC32X4_PLLJ AIC32X4_REG(0, 6)
35 #define AIC32X4_PLLDMSB AIC32X4_REG(0, 34 #define AIC32X4_PLLDMSB AIC32X4_REG(0, 7)
36 #define AIC32X4_PLLDLSB AIC32X4_REG(0, 35 #define AIC32X4_PLLDLSB AIC32X4_REG(0, 8)
37 #define AIC32X4_NDAC AIC32X4_REG(0, 36 #define AIC32X4_NDAC AIC32X4_REG(0, 11)
38 #define AIC32X4_MDAC AIC32X4_REG(0, 37 #define AIC32X4_MDAC AIC32X4_REG(0, 12)
39 #define AIC32X4_DOSRMSB AIC32X4_REG(0, 38 #define AIC32X4_DOSRMSB AIC32X4_REG(0, 13)
40 #define AIC32X4_DOSRLSB AIC32X4_REG(0, 39 #define AIC32X4_DOSRLSB AIC32X4_REG(0, 14)
41 #define AIC32X4_NADC AIC32X4_REG(0, 40 #define AIC32X4_NADC AIC32X4_REG(0, 18)
42 #define AIC32X4_MADC AIC32X4_REG(0, 41 #define AIC32X4_MADC AIC32X4_REG(0, 19)
43 #define AIC32X4_AOSR AIC32X4_REG(0, 42 #define AIC32X4_AOSR AIC32X4_REG(0, 20)
44 #define AIC32X4_CLKMUX2 AIC32X4_REG(0, 43 #define AIC32X4_CLKMUX2 AIC32X4_REG(0, 25)
45 #define AIC32X4_CLKOUTM AIC32X4_REG(0, 44 #define AIC32X4_CLKOUTM AIC32X4_REG(0, 26)
46 #define AIC32X4_IFACE1 AIC32X4_REG(0, 45 #define AIC32X4_IFACE1 AIC32X4_REG(0, 27)
47 #define AIC32X4_IFACE2 AIC32X4_REG(0, 46 #define AIC32X4_IFACE2 AIC32X4_REG(0, 28)
48 #define AIC32X4_IFACE3 AIC32X4_REG(0, 47 #define AIC32X4_IFACE3 AIC32X4_REG(0, 29)
49 #define AIC32X4_BCLKN AIC32X4_REG(0, 48 #define AIC32X4_BCLKN AIC32X4_REG(0, 30)
50 #define AIC32X4_IFACE4 AIC32X4_REG(0, 49 #define AIC32X4_IFACE4 AIC32X4_REG(0, 31)
51 #define AIC32X4_IFACE5 AIC32X4_REG(0, 50 #define AIC32X4_IFACE5 AIC32X4_REG(0, 32)
52 #define AIC32X4_IFACE6 AIC32X4_REG(0, 51 #define AIC32X4_IFACE6 AIC32X4_REG(0, 33)
53 #define AIC32X4_GPIOCTL AIC32X4_REG(0, 52 #define AIC32X4_GPIOCTL AIC32X4_REG(0, 52)
54 #define AIC32X4_DOUTCTL AIC32X4_REG(0, 53 #define AIC32X4_DOUTCTL AIC32X4_REG(0, 53)
55 #define AIC32X4_DINCTL AIC32X4_REG(0, 54 #define AIC32X4_DINCTL AIC32X4_REG(0, 54)
56 #define AIC32X4_MISOCTL AIC32X4_REG(0, 55 #define AIC32X4_MISOCTL AIC32X4_REG(0, 55)
57 #define AIC32X4_SCLKCTL AIC32X4_REG(0, 56 #define AIC32X4_SCLKCTL AIC32X4_REG(0, 56)
58 #define AIC32X4_DACSPB AIC32X4_REG(0, 57 #define AIC32X4_DACSPB AIC32X4_REG(0, 60)
59 #define AIC32X4_ADCSPB AIC32X4_REG(0, 58 #define AIC32X4_ADCSPB AIC32X4_REG(0, 61)
60 #define AIC32X4_DACSETUP AIC32X4_REG(0, 59 #define AIC32X4_DACSETUP AIC32X4_REG(0, 63)
61 #define AIC32X4_DACMUTE AIC32X4_REG(0, 60 #define AIC32X4_DACMUTE AIC32X4_REG(0, 64)
62 #define AIC32X4_LDACVOL AIC32X4_REG(0, 61 #define AIC32X4_LDACVOL AIC32X4_REG(0, 65)
63 #define AIC32X4_RDACVOL AIC32X4_REG(0, 62 #define AIC32X4_RDACVOL AIC32X4_REG(0, 66)
64 #define AIC32X4_ADCSETUP AIC32X4_REG(0, 63 #define AIC32X4_ADCSETUP AIC32X4_REG(0, 81)
65 #define AIC32X4_ADCFGA AIC32X4_REG(0, 64 #define AIC32X4_ADCFGA AIC32X4_REG(0, 82)
66 #define AIC32X4_LADCVOL AIC32X4_REG(0, 65 #define AIC32X4_LADCVOL AIC32X4_REG(0, 83)
67 #define AIC32X4_RADCVOL AIC32X4_REG(0, 66 #define AIC32X4_RADCVOL AIC32X4_REG(0, 84)
68 #define AIC32X4_LAGC1 AIC32X4_REG(0, 67 #define AIC32X4_LAGC1 AIC32X4_REG(0, 86)
69 #define AIC32X4_LAGC2 AIC32X4_REG(0, 68 #define AIC32X4_LAGC2 AIC32X4_REG(0, 87)
70 #define AIC32X4_LAGC3 AIC32X4_REG(0, 69 #define AIC32X4_LAGC3 AIC32X4_REG(0, 88)
71 #define AIC32X4_LAGC4 AIC32X4_REG(0, 70 #define AIC32X4_LAGC4 AIC32X4_REG(0, 89)
72 #define AIC32X4_LAGC5 AIC32X4_REG(0, 71 #define AIC32X4_LAGC5 AIC32X4_REG(0, 90)
73 #define AIC32X4_LAGC6 AIC32X4_REG(0, 72 #define AIC32X4_LAGC6 AIC32X4_REG(0, 91)
74 #define AIC32X4_LAGC7 AIC32X4_REG(0, 73 #define AIC32X4_LAGC7 AIC32X4_REG(0, 92)
75 #define AIC32X4_RAGC1 AIC32X4_REG(0, 74 #define AIC32X4_RAGC1 AIC32X4_REG(0, 94)
76 #define AIC32X4_RAGC2 AIC32X4_REG(0, 75 #define AIC32X4_RAGC2 AIC32X4_REG(0, 95)
77 #define AIC32X4_RAGC3 AIC32X4_REG(0, 76 #define AIC32X4_RAGC3 AIC32X4_REG(0, 96)
78 #define AIC32X4_RAGC4 AIC32X4_REG(0, 77 #define AIC32X4_RAGC4 AIC32X4_REG(0, 97)
79 #define AIC32X4_RAGC5 AIC32X4_REG(0, 78 #define AIC32X4_RAGC5 AIC32X4_REG(0, 98)
80 #define AIC32X4_RAGC6 AIC32X4_REG(0, 79 #define AIC32X4_RAGC6 AIC32X4_REG(0, 99)
81 #define AIC32X4_RAGC7 AIC32X4_REG(0, 80 #define AIC32X4_RAGC7 AIC32X4_REG(0, 100)
82 81
83 #define AIC32X4_PWRCFG AIC32X4_REG(1, 82 #define AIC32X4_PWRCFG AIC32X4_REG(1, 1)
84 #define AIC32X4_LDOCTL AIC32X4_REG(1, 83 #define AIC32X4_LDOCTL AIC32X4_REG(1, 2)
85 #define AIC32X4_LPLAYBACK AIC32X4_REG(1, 84 #define AIC32X4_LPLAYBACK AIC32X4_REG(1, 3)
86 #define AIC32X4_RPLAYBACK AIC32X4_REG(1, 85 #define AIC32X4_RPLAYBACK AIC32X4_REG(1, 4)
87 #define AIC32X4_OUTPWRCTL AIC32X4_REG(1, 86 #define AIC32X4_OUTPWRCTL AIC32X4_REG(1, 9)
88 #define AIC32X4_CMMODE AIC32X4_REG(1, 87 #define AIC32X4_CMMODE AIC32X4_REG(1, 10)
89 #define AIC32X4_HPLROUTE AIC32X4_REG(1, 88 #define AIC32X4_HPLROUTE AIC32X4_REG(1, 12)
90 #define AIC32X4_HPRROUTE AIC32X4_REG(1, 89 #define AIC32X4_HPRROUTE AIC32X4_REG(1, 13)
91 #define AIC32X4_LOLROUTE AIC32X4_REG(1, 90 #define AIC32X4_LOLROUTE AIC32X4_REG(1, 14)
92 #define AIC32X4_LORROUTE AIC32X4_REG(1, 91 #define AIC32X4_LORROUTE AIC32X4_REG(1, 15)
93 #define AIC32X4_HPLGAIN AIC32X4_REG(1, 92 #define AIC32X4_HPLGAIN AIC32X4_REG(1, 16)
94 #define AIC32X4_HPRGAIN AIC32X4_REG(1, 93 #define AIC32X4_HPRGAIN AIC32X4_REG(1, 17)
95 #define AIC32X4_LOLGAIN AIC32X4_REG(1, 94 #define AIC32X4_LOLGAIN AIC32X4_REG(1, 18)
96 #define AIC32X4_LORGAIN AIC32X4_REG(1, 95 #define AIC32X4_LORGAIN AIC32X4_REG(1, 19)
97 #define AIC32X4_HEADSTART AIC32X4_REG(1, 96 #define AIC32X4_HEADSTART AIC32X4_REG(1, 20)
98 #define TAS2505_SPK AIC32X4_REG(1, 97 #define TAS2505_SPK AIC32X4_REG(1, 45)
99 #define TAS2505_SPKVOL1 AIC32X4_REG(1, 98 #define TAS2505_SPKVOL1 AIC32X4_REG(1, 46)
100 #define TAS2505_SPKVOL2 AIC32X4_REG(1, 99 #define TAS2505_SPKVOL2 AIC32X4_REG(1, 48)
101 #define AIC32X4_MICBIAS AIC32X4_REG(1, 100 #define AIC32X4_MICBIAS AIC32X4_REG(1, 51)
102 #define AIC32X4_LMICPGAPIN AIC32X4_REG(1, 101 #define AIC32X4_LMICPGAPIN AIC32X4_REG(1, 52)
103 #define AIC32X4_LMICPGANIN AIC32X4_REG(1, 102 #define AIC32X4_LMICPGANIN AIC32X4_REG(1, 54)
104 #define AIC32X4_RMICPGAPIN AIC32X4_REG(1, 103 #define AIC32X4_RMICPGAPIN AIC32X4_REG(1, 55)
105 #define AIC32X4_RMICPGANIN AIC32X4_REG(1, 104 #define AIC32X4_RMICPGANIN AIC32X4_REG(1, 57)
106 #define AIC32X4_FLOATINGINPUT AIC32X4_REG(1, 105 #define AIC32X4_FLOATINGINPUT AIC32X4_REG(1, 58)
107 #define AIC32X4_LMICPGAVOL AIC32X4_REG(1, 106 #define AIC32X4_LMICPGAVOL AIC32X4_REG(1, 59)
108 #define AIC32X4_RMICPGAVOL AIC32X4_REG(1, 107 #define AIC32X4_RMICPGAVOL AIC32X4_REG(1, 60)
109 #define TAS2505_REFPOWERUP AIC32X4_REG(1, 108 #define TAS2505_REFPOWERUP AIC32X4_REG(1, 122)
110 #define AIC32X4_REFPOWERUP AIC32X4_REG(1, 109 #define AIC32X4_REFPOWERUP AIC32X4_REG(1, 123)
111 110
112 /* Bits, masks, and shifts */ 111 /* Bits, masks, and shifts */
113 112
114 /* AIC32X4_CLKMUX */ 113 /* AIC32X4_CLKMUX */
115 #define AIC32X4_PLL_CLKIN_MASK GENMAS 114 #define AIC32X4_PLL_CLKIN_MASK GENMASK(3, 2)
116 #define AIC32X4_PLL_CLKIN_SHIFT (2) 115 #define AIC32X4_PLL_CLKIN_SHIFT (2)
117 #define AIC32X4_PLL_CLKIN_MCLK (0x00) 116 #define AIC32X4_PLL_CLKIN_MCLK (0x00)
118 #define AIC32X4_PLL_CLKIN_BCKL (0x01) 117 #define AIC32X4_PLL_CLKIN_BCKL (0x01)
119 #define AIC32X4_PLL_CLKIN_GPIO1 (0x02) 118 #define AIC32X4_PLL_CLKIN_GPIO1 (0x02)
120 #define AIC32X4_PLL_CLKIN_DIN (0x03) 119 #define AIC32X4_PLL_CLKIN_DIN (0x03)
121 #define AIC32X4_CODEC_CLKIN_MASK GENMAS 120 #define AIC32X4_CODEC_CLKIN_MASK GENMASK(1, 0)
122 #define AIC32X4_CODEC_CLKIN_SHIFT (0) 121 #define AIC32X4_CODEC_CLKIN_SHIFT (0)
123 #define AIC32X4_CODEC_CLKIN_MCLK (0x00) 122 #define AIC32X4_CODEC_CLKIN_MCLK (0x00)
124 #define AIC32X4_CODEC_CLKIN_BCLK (0x01) 123 #define AIC32X4_CODEC_CLKIN_BCLK (0x01)
125 #define AIC32X4_CODEC_CLKIN_GPIO1 (0x02) 124 #define AIC32X4_CODEC_CLKIN_GPIO1 (0x02)
126 #define AIC32X4_CODEC_CLKIN_PLL (0x03) 125 #define AIC32X4_CODEC_CLKIN_PLL (0x03)
127 126
128 /* AIC32X4_PLLPR */ 127 /* AIC32X4_PLLPR */
129 #define AIC32X4_PLLEN BIT(7) 128 #define AIC32X4_PLLEN BIT(7)
130 #define AIC32X4_PLL_P_MASK GENMAS 129 #define AIC32X4_PLL_P_MASK GENMASK(6, 4)
131 #define AIC32X4_PLL_P_SHIFT (4) 130 #define AIC32X4_PLL_P_SHIFT (4)
132 #define AIC32X4_PLL_R_MASK GENMAS 131 #define AIC32X4_PLL_R_MASK GENMASK(3, 0)
133 132
134 /* AIC32X4_NDAC */ 133 /* AIC32X4_NDAC */
135 #define AIC32X4_NDACEN BIT(7) 134 #define AIC32X4_NDACEN BIT(7)
136 #define AIC32X4_NDAC_MASK GENMAS 135 #define AIC32X4_NDAC_MASK GENMASK(6, 0)
137 136
138 /* AIC32X4_MDAC */ 137 /* AIC32X4_MDAC */
139 #define AIC32X4_MDACEN BIT(7) 138 #define AIC32X4_MDACEN BIT(7)
140 #define AIC32X4_MDAC_MASK GENMAS 139 #define AIC32X4_MDAC_MASK GENMASK(6, 0)
141 140
142 /* AIC32X4_NADC */ 141 /* AIC32X4_NADC */
143 #define AIC32X4_NADCEN BIT(7) 142 #define AIC32X4_NADCEN BIT(7)
144 #define AIC32X4_NADC_MASK GENMAS 143 #define AIC32X4_NADC_MASK GENMASK(6, 0)
145 144
146 /* AIC32X4_MADC */ 145 /* AIC32X4_MADC */
147 #define AIC32X4_MADCEN BIT(7) 146 #define AIC32X4_MADCEN BIT(7)
148 #define AIC32X4_MADC_MASK GENMAS 147 #define AIC32X4_MADC_MASK GENMASK(6, 0)
149 148
150 /* AIC32X4_BCLKN */ 149 /* AIC32X4_BCLKN */
151 #define AIC32X4_BCLKEN BIT(7) 150 #define AIC32X4_BCLKEN BIT(7)
152 #define AIC32X4_BCLK_MASK GENMAS 151 #define AIC32X4_BCLK_MASK GENMASK(6, 0)
153 152
154 /* AIC32X4_IFACE1 */ 153 /* AIC32X4_IFACE1 */
155 #define AIC32X4_IFACE1_DATATYPE_MASK GENMAS 154 #define AIC32X4_IFACE1_DATATYPE_MASK GENMASK(7, 6)
156 #define AIC32X4_IFACE1_DATATYPE_SHIFT (6) 155 #define AIC32X4_IFACE1_DATATYPE_SHIFT (6)
157 #define AIC32X4_I2S_MODE (0x00) 156 #define AIC32X4_I2S_MODE (0x00)
158 #define AIC32X4_DSP_MODE (0x01) 157 #define AIC32X4_DSP_MODE (0x01)
159 #define AIC32X4_RIGHT_JUSTIFIED_MODE (0x02) 158 #define AIC32X4_RIGHT_JUSTIFIED_MODE (0x02)
160 #define AIC32X4_LEFT_JUSTIFIED_MODE (0x03) 159 #define AIC32X4_LEFT_JUSTIFIED_MODE (0x03)
161 #define AIC32X4_IFACE1_DATALEN_MASK GENMAS 160 #define AIC32X4_IFACE1_DATALEN_MASK GENMASK(5, 4)
162 #define AIC32X4_IFACE1_DATALEN_SHIFT (4) 161 #define AIC32X4_IFACE1_DATALEN_SHIFT (4)
163 #define AIC32X4_WORD_LEN_16BITS (0x00) 162 #define AIC32X4_WORD_LEN_16BITS (0x00)
164 #define AIC32X4_WORD_LEN_20BITS (0x01) 163 #define AIC32X4_WORD_LEN_20BITS (0x01)
165 #define AIC32X4_WORD_LEN_24BITS (0x02) 164 #define AIC32X4_WORD_LEN_24BITS (0x02)
166 #define AIC32X4_WORD_LEN_32BITS (0x03) 165 #define AIC32X4_WORD_LEN_32BITS (0x03)
167 #define AIC32X4_IFACE1_MASTER_MASK GENMAS 166 #define AIC32X4_IFACE1_MASTER_MASK GENMASK(3, 2)
168 #define AIC32X4_BCLKMASTER BIT(2) 167 #define AIC32X4_BCLKMASTER BIT(2)
169 #define AIC32X4_WCLKMASTER BIT(3) 168 #define AIC32X4_WCLKMASTER BIT(3)
170 169
171 /* AIC32X4_IFACE2 */ 170 /* AIC32X4_IFACE2 */
172 #define AIC32X4_DATA_OFFSET_MASK GENMAS 171 #define AIC32X4_DATA_OFFSET_MASK GENMASK(7, 0)
173 172
174 /* AIC32X4_IFACE3 */ 173 /* AIC32X4_IFACE3 */
175 #define AIC32X4_BCLKINV_MASK BIT(3) 174 #define AIC32X4_BCLKINV_MASK BIT(3)
176 #define AIC32X4_BDIVCLK_MASK GENMAS 175 #define AIC32X4_BDIVCLK_MASK GENMASK(1, 0)
177 #define AIC32X4_BDIVCLK_SHIFT (0) 176 #define AIC32X4_BDIVCLK_SHIFT (0)
178 #define AIC32X4_DAC2BCLK (0x00) 177 #define AIC32X4_DAC2BCLK (0x00)
179 #define AIC32X4_DACMOD2BCLK (0x01) 178 #define AIC32X4_DACMOD2BCLK (0x01)
180 #define AIC32X4_ADC2BCLK (0x02) 179 #define AIC32X4_ADC2BCLK (0x02)
181 #define AIC32X4_ADCMOD2BCLK (0x03) 180 #define AIC32X4_ADCMOD2BCLK (0x03)
182 181
183 /* AIC32X4_DACSETUP */ 182 /* AIC32X4_DACSETUP */
184 #define AIC32X4_DAC_CHAN_MASK GENMAS 183 #define AIC32X4_DAC_CHAN_MASK GENMASK(5, 2)
185 #define AIC32X4_LDAC2RCHN BIT(5) 184 #define AIC32X4_LDAC2RCHN BIT(5)
186 #define AIC32X4_LDAC2LCHN BIT(4) 185 #define AIC32X4_LDAC2LCHN BIT(4)
187 #define AIC32X4_RDAC2LCHN BIT(3) 186 #define AIC32X4_RDAC2LCHN BIT(3)
188 #define AIC32X4_RDAC2RCHN BIT(2) 187 #define AIC32X4_RDAC2RCHN BIT(2)
189 188
190 /* AIC32X4_DACMUTE */ 189 /* AIC32X4_DACMUTE */
191 #define AIC32X4_MUTEON 0x0C 190 #define AIC32X4_MUTEON 0x0C
192 191
193 /* AIC32X4_ADCSETUP */ 192 /* AIC32X4_ADCSETUP */
194 #define AIC32X4_LADC_EN BIT(7) 193 #define AIC32X4_LADC_EN BIT(7)
195 #define AIC32X4_RADC_EN BIT(6) 194 #define AIC32X4_RADC_EN BIT(6)
196 195
197 /* AIC32X4_PWRCFG */ 196 /* AIC32X4_PWRCFG */
198 #define AIC32X4_AVDDWEAKDISABLE BIT(3) 197 #define AIC32X4_AVDDWEAKDISABLE BIT(3)
199 198
200 /* AIC32X4_LDOCTL */ 199 /* AIC32X4_LDOCTL */
201 #define AIC32X4_LDOCTLEN BIT(0) 200 #define AIC32X4_LDOCTLEN BIT(0)
202 201
203 /* AIC32X4_CMMODE */ 202 /* AIC32X4_CMMODE */
204 #define AIC32X4_LDOIN_18_36 BIT(0) 203 #define AIC32X4_LDOIN_18_36 BIT(0)
205 #define AIC32X4_LDOIN2HP BIT(1) 204 #define AIC32X4_LDOIN2HP BIT(1)
206 205
207 /* AIC32X4_MICBIAS */ 206 /* AIC32X4_MICBIAS */
208 #define AIC32X4_MICBIAS_LDOIN BIT(3) 207 #define AIC32X4_MICBIAS_LDOIN BIT(3)
209 #define AIC32X4_MICBIAS_2075V 0x60 208 #define AIC32X4_MICBIAS_2075V 0x60
210 #define AIC32x4_MICBIAS_MASK GENMAS 209 #define AIC32x4_MICBIAS_MASK GENMASK(6, 3)
211 210
212 /* AIC32X4_LMICPGANIN */ 211 /* AIC32X4_LMICPGANIN */
213 #define AIC32X4_LMICPGANIN_IN2R_10K 0x10 212 #define AIC32X4_LMICPGANIN_IN2R_10K 0x10
214 #define AIC32X4_LMICPGANIN_CM1L_10K 0x40 213 #define AIC32X4_LMICPGANIN_CM1L_10K 0x40
215 214
216 /* AIC32X4_RMICPGANIN */ 215 /* AIC32X4_RMICPGANIN */
217 #define AIC32X4_RMICPGANIN_IN1L_10K 0x10 216 #define AIC32X4_RMICPGANIN_IN1L_10K 0x10
218 #define AIC32X4_RMICPGANIN_CM1R_10K 0x40 217 #define AIC32X4_RMICPGANIN_CM1R_10K 0x40
219 218
220 /* AIC32X4_REFPOWERUP */ 219 /* AIC32X4_REFPOWERUP */
221 #define AIC32X4_REFPOWERUP_SLOW 0x04 220 #define AIC32X4_REFPOWERUP_SLOW 0x04
222 #define AIC32X4_REFPOWERUP_40MS 0x05 221 #define AIC32X4_REFPOWERUP_40MS 0x05
223 #define AIC32X4_REFPOWERUP_80MS 0x06 222 #define AIC32X4_REFPOWERUP_80MS 0x06
224 #define AIC32X4_REFPOWERUP_120MS 0x07 223 #define AIC32X4_REFPOWERUP_120MS 0x07
225 224
226 /* Common mask and enable for all of the divid 225 /* Common mask and enable for all of the dividers */
227 #define AIC32X4_DIVEN BIT(7) !! 226 #define AIC32X4_DIVEN BIT(7)
228 #define AIC32X4_DIV_MASK GENMAS !! 227 #define AIC32X4_DIV_MASK GENMASK(6, 0)
229 #define AIC32X4_DIV_MAX 128 <<
230 228
231 /* Clock Limits */ 229 /* Clock Limits */
232 #define AIC32X4_MAX_DOSR_FREQ 620000 230 #define AIC32X4_MAX_DOSR_FREQ 6200000
233 #define AIC32X4_MIN_DOSR_FREQ 280000 231 #define AIC32X4_MIN_DOSR_FREQ 2800000
234 #define AIC32X4_MAX_CODEC_CLKIN_FREQ 110000 232 #define AIC32X4_MAX_CODEC_CLKIN_FREQ 110000000
235 #define AIC32X4_MAX_PLL_CLKIN 200000 233 #define AIC32X4_MAX_PLL_CLKIN 20000000
236 234
237 #endif /* _TLV320AIC3 235 #endif /* _TLV320AIC32X4_H */
238 236
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