1 /* SPDX-License-Identifier: GPL-2.0-only */ <<
2 /* 1 /*
3 * tlv320aic32x4.h 2 * tlv320aic32x4.h
>> 3 *
>> 4 * This program is free software; you can redistribute it and/or modify
>> 5 * it under the terms of the GNU General Public License version 2 as
>> 6 * published by the Free Software Foundation.
4 */ 7 */
5 8
6 9
7 #ifndef _TLV320AIC32X4_H 10 #ifndef _TLV320AIC32X4_H
8 #define _TLV320AIC32X4_H 11 #define _TLV320AIC32X4_H
9 12
10 struct device; <<
11 struct regmap_config; <<
12 <<
13 enum aic32x4_type { <<
14 AIC32X4_TYPE_AIC32X4 = 0, <<
15 AIC32X4_TYPE_AIC32X6, <<
16 AIC32X4_TYPE_TAS2505, <<
17 }; <<
18 <<
19 extern const struct regmap_config aic32x4_regm <<
20 int aic32x4_probe(struct device *dev, struct r <<
21 enum aic32x4_type type); <<
22 void aic32x4_remove(struct device *dev); <<
23 int aic32x4_register_clocks(struct device *dev <<
24 <<
25 /* tlv320aic32x4 register space (in decimal to 13 /* tlv320aic32x4 register space (in decimal to match datasheet) */
26 14
27 #define AIC32X4_REG(page, reg) ((page * 128) !! 15 #define AIC32X4_PAGE1 128
28 16
29 #define AIC32X4_PSEL AIC32X4_REG(0, !! 17 #define AIC32X4_PSEL 0
>> 18 #define AIC32X4_RESET 1
>> 19 #define AIC32X4_CLKMUX 4
>> 20 #define AIC32X4_PLLPR 5
>> 21 #define AIC32X4_PLLJ 6
>> 22 #define AIC32X4_PLLDMSB 7
>> 23 #define AIC32X4_PLLDLSB 8
>> 24 #define AIC32X4_NDAC 11
>> 25 #define AIC32X4_MDAC 12
>> 26 #define AIC32X4_DOSRMSB 13
>> 27 #define AIC32X4_DOSRLSB 14
>> 28 #define AIC32X4_NADC 18
>> 29 #define AIC32X4_MADC 19
>> 30 #define AIC32X4_AOSR 20
>> 31 #define AIC32X4_CLKMUX2 25
>> 32 #define AIC32X4_CLKOUTM 26
>> 33 #define AIC32X4_IFACE1 27
>> 34 #define AIC32X4_IFACE2 28
>> 35 #define AIC32X4_IFACE3 29
>> 36 #define AIC32X4_BCLKN 30
>> 37 #define AIC32X4_IFACE4 31
>> 38 #define AIC32X4_IFACE5 32
>> 39 #define AIC32X4_IFACE6 33
>> 40 #define AIC32X4_DOUTCTL 53
>> 41 #define AIC32X4_DINCTL 54
>> 42 #define AIC32X4_DACSPB 60
>> 43 #define AIC32X4_ADCSPB 61
>> 44 #define AIC32X4_DACSETUP 63
>> 45 #define AIC32X4_DACMUTE 64
>> 46 #define AIC32X4_LDACVOL 65
>> 47 #define AIC32X4_RDACVOL 66
>> 48 #define AIC32X4_ADCSETUP 81
>> 49 #define AIC32X4_ADCFGA 82
>> 50 #define AIC32X4_LADCVOL 83
>> 51 #define AIC32X4_RADCVOL 84
>> 52 #define AIC32X4_LAGC1 86
>> 53 #define AIC32X4_LAGC2 87
>> 54 #define AIC32X4_LAGC3 88
>> 55 #define AIC32X4_LAGC4 89
>> 56 #define AIC32X4_LAGC5 90
>> 57 #define AIC32X4_LAGC6 91
>> 58 #define AIC32X4_LAGC7 92
>> 59 #define AIC32X4_RAGC1 94
>> 60 #define AIC32X4_RAGC2 95
>> 61 #define AIC32X4_RAGC3 96
>> 62 #define AIC32X4_RAGC4 97
>> 63 #define AIC32X4_RAGC5 98
>> 64 #define AIC32X4_RAGC6 99
>> 65 #define AIC32X4_RAGC7 100
>> 66 #define AIC32X4_PWRCFG (AIC32X4_PAGE1 + 1)
>> 67 #define AIC32X4_LDOCTL (AIC32X4_PAGE1 + 2)
>> 68 #define AIC32X4_OUTPWRCTL (AIC32X4_PAGE1 + 9)
>> 69 #define AIC32X4_CMMODE (AIC32X4_PAGE1 + 10)
>> 70 #define AIC32X4_HPLROUTE (AIC32X4_PAGE1 + 12)
>> 71 #define AIC32X4_HPRROUTE (AIC32X4_PAGE1 + 13)
>> 72 #define AIC32X4_LOLROUTE (AIC32X4_PAGE1 + 14)
>> 73 #define AIC32X4_LORROUTE (AIC32X4_PAGE1 + 15)
>> 74 #define AIC32X4_HPLGAIN (AIC32X4_PAGE1 + 16)
>> 75 #define AIC32X4_HPRGAIN (AIC32X4_PAGE1 + 17)
>> 76 #define AIC32X4_LOLGAIN (AIC32X4_PAGE1 + 18)
>> 77 #define AIC32X4_LORGAIN (AIC32X4_PAGE1 + 19)
>> 78 #define AIC32X4_HEADSTART (AIC32X4_PAGE1 + 20)
>> 79 #define AIC32X4_MICBIAS (AIC32X4_PAGE1 + 51)
>> 80 #define AIC32X4_LMICPGAPIN (AIC32X4_PAGE1 + 52)
>> 81 #define AIC32X4_LMICPGANIN (AIC32X4_PAGE1 + 54)
>> 82 #define AIC32X4_RMICPGAPIN (AIC32X4_PAGE1 + 55)
>> 83 #define AIC32X4_RMICPGANIN (AIC32X4_PAGE1 + 57)
>> 84 #define AIC32X4_FLOATINGINPUT (AIC32X4_PAGE1 + 58)
>> 85 #define AIC32X4_LMICPGAVOL (AIC32X4_PAGE1 + 59)
>> 86 #define AIC32X4_RMICPGAVOL (AIC32X4_PAGE1 + 60)
>> 87
>> 88 #define AIC32X4_FREQ_12000000 12000000
>> 89 #define AIC32X4_FREQ_24000000 24000000
>> 90 #define AIC32X4_FREQ_25000000 25000000
>> 91
>> 92 #define AIC32X4_WORD_LEN_16BITS 0x00
>> 93 #define AIC32X4_WORD_LEN_20BITS 0x01
>> 94 #define AIC32X4_WORD_LEN_24BITS 0x02
>> 95 #define AIC32X4_WORD_LEN_32BITS 0x03
>> 96
>> 97 #define AIC32X4_LADC_EN (1 << 7)
>> 98 #define AIC32X4_RADC_EN (1 << 6)
>> 99
>> 100 #define AIC32X4_I2S_MODE 0x00
>> 101 #define AIC32X4_DSP_MODE 0x01
>> 102 #define AIC32X4_RIGHT_JUSTIFIED_MODE 0x02
>> 103 #define AIC32X4_LEFT_JUSTIFIED_MODE 0x03
>> 104
>> 105 #define AIC32X4_AVDDWEAKDISABLE 0x08
>> 106 #define AIC32X4_LDOCTLEN 0x01
>> 107
>> 108 #define AIC32X4_LDOIN_18_36 0x01
>> 109 #define AIC32X4_LDOIN2HP 0x02
>> 110
>> 111 #define AIC32X4_DACSPBLOCK_MASK 0x1f
>> 112 #define AIC32X4_ADCSPBLOCK_MASK 0x1f
30 113
31 #define AIC32X4_RESET AIC32X4_REG(0, !! 114 #define AIC32X4_PLLJ_SHIFT 6
32 #define AIC32X4_CLKMUX AIC32X4_REG(0, !! 115 #define AIC32X4_DOSRMSB_SHIFT 4
33 #define AIC32X4_PLLPR AIC32X4_REG(0, <<
34 #define AIC32X4_PLLJ AIC32X4_REG(0, <<
35 #define AIC32X4_PLLDMSB AIC32X4_REG(0, <<
36 #define AIC32X4_PLLDLSB AIC32X4_REG(0, <<
37 #define AIC32X4_NDAC AIC32X4_REG(0, <<
38 #define AIC32X4_MDAC AIC32X4_REG(0, <<
39 #define AIC32X4_DOSRMSB AIC32X4_REG(0, <<
40 #define AIC32X4_DOSRLSB AIC32X4_REG(0, <<
41 #define AIC32X4_NADC AIC32X4_REG(0, <<
42 #define AIC32X4_MADC AIC32X4_REG(0, <<
43 #define AIC32X4_AOSR AIC32X4_REG(0, <<
44 #define AIC32X4_CLKMUX2 AIC32X4_REG(0, <<
45 #define AIC32X4_CLKOUTM AIC32X4_REG(0, <<
46 #define AIC32X4_IFACE1 AIC32X4_REG(0, <<
47 #define AIC32X4_IFACE2 AIC32X4_REG(0, <<
48 #define AIC32X4_IFACE3 AIC32X4_REG(0, <<
49 #define AIC32X4_BCLKN AIC32X4_REG(0, <<
50 #define AIC32X4_IFACE4 AIC32X4_REG(0, <<
51 #define AIC32X4_IFACE5 AIC32X4_REG(0, <<
52 #define AIC32X4_IFACE6 AIC32X4_REG(0, <<
53 #define AIC32X4_GPIOCTL AIC32X4_REG(0, <<
54 #define AIC32X4_DOUTCTL AIC32X4_REG(0, <<
55 #define AIC32X4_DINCTL AIC32X4_REG(0, <<
56 #define AIC32X4_MISOCTL AIC32X4_REG(0, <<
57 #define AIC32X4_SCLKCTL AIC32X4_REG(0, <<
58 #define AIC32X4_DACSPB AIC32X4_REG(0, <<
59 #define AIC32X4_ADCSPB AIC32X4_REG(0, <<
60 #define AIC32X4_DACSETUP AIC32X4_REG(0, <<
61 #define AIC32X4_DACMUTE AIC32X4_REG(0, <<
62 #define AIC32X4_LDACVOL AIC32X4_REG(0, <<
63 #define AIC32X4_RDACVOL AIC32X4_REG(0, <<
64 #define AIC32X4_ADCSETUP AIC32X4_REG(0, <<
65 #define AIC32X4_ADCFGA AIC32X4_REG(0, <<
66 #define AIC32X4_LADCVOL AIC32X4_REG(0, <<
67 #define AIC32X4_RADCVOL AIC32X4_REG(0, <<
68 #define AIC32X4_LAGC1 AIC32X4_REG(0, <<
69 #define AIC32X4_LAGC2 AIC32X4_REG(0, <<
70 #define AIC32X4_LAGC3 AIC32X4_REG(0, <<
71 #define AIC32X4_LAGC4 AIC32X4_REG(0, <<
72 #define AIC32X4_LAGC5 AIC32X4_REG(0, <<
73 #define AIC32X4_LAGC6 AIC32X4_REG(0, <<
74 #define AIC32X4_LAGC7 AIC32X4_REG(0, <<
75 #define AIC32X4_RAGC1 AIC32X4_REG(0, <<
76 #define AIC32X4_RAGC2 AIC32X4_REG(0, <<
77 #define AIC32X4_RAGC3 AIC32X4_REG(0, <<
78 #define AIC32X4_RAGC4 AIC32X4_REG(0, <<
79 #define AIC32X4_RAGC5 AIC32X4_REG(0, <<
80 #define AIC32X4_RAGC6 AIC32X4_REG(0, <<
81 #define AIC32X4_RAGC7 AIC32X4_REG(0, <<
82 <<
83 #define AIC32X4_PWRCFG AIC32X4_REG(1, <<
84 #define AIC32X4_LDOCTL AIC32X4_REG(1, <<
85 #define AIC32X4_LPLAYBACK AIC32X4_REG(1, <<
86 #define AIC32X4_RPLAYBACK AIC32X4_REG(1, <<
87 #define AIC32X4_OUTPWRCTL AIC32X4_REG(1, <<
88 #define AIC32X4_CMMODE AIC32X4_REG(1, <<
89 #define AIC32X4_HPLROUTE AIC32X4_REG(1, <<
90 #define AIC32X4_HPRROUTE AIC32X4_REG(1, <<
91 #define AIC32X4_LOLROUTE AIC32X4_REG(1, <<
92 #define AIC32X4_LORROUTE AIC32X4_REG(1, <<
93 #define AIC32X4_HPLGAIN AIC32X4_REG(1, <<
94 #define AIC32X4_HPRGAIN AIC32X4_REG(1, <<
95 #define AIC32X4_LOLGAIN AIC32X4_REG(1, <<
96 #define AIC32X4_LORGAIN AIC32X4_REG(1, <<
97 #define AIC32X4_HEADSTART AIC32X4_REG(1, <<
98 #define TAS2505_SPK AIC32X4_REG(1, <<
99 #define TAS2505_SPKVOL1 AIC32X4_REG(1, <<
100 #define TAS2505_SPKVOL2 AIC32X4_REG(1, <<
101 #define AIC32X4_MICBIAS AIC32X4_REG(1, <<
102 #define AIC32X4_LMICPGAPIN AIC32X4_REG(1, <<
103 #define AIC32X4_LMICPGANIN AIC32X4_REG(1, <<
104 #define AIC32X4_RMICPGAPIN AIC32X4_REG(1, <<
105 #define AIC32X4_RMICPGANIN AIC32X4_REG(1, <<
106 #define AIC32X4_FLOATINGINPUT AIC32X4_REG(1, <<
107 #define AIC32X4_LMICPGAVOL AIC32X4_REG(1, <<
108 #define AIC32X4_RMICPGAVOL AIC32X4_REG(1, <<
109 #define TAS2505_REFPOWERUP AIC32X4_REG(1, <<
110 #define AIC32X4_REFPOWERUP AIC32X4_REG(1, <<
111 <<
112 /* Bits, masks, and shifts */ <<
113 <<
114 /* AIC32X4_CLKMUX */ <<
115 #define AIC32X4_PLL_CLKIN_MASK GENMAS <<
116 #define AIC32X4_PLL_CLKIN_SHIFT (2) <<
117 #define AIC32X4_PLL_CLKIN_MCLK (0x00) <<
118 #define AIC32X4_PLL_CLKIN_BCKL (0x01) <<
119 #define AIC32X4_PLL_CLKIN_GPIO1 (0x02) <<
120 #define AIC32X4_PLL_CLKIN_DIN (0x03) <<
121 #define AIC32X4_CODEC_CLKIN_MASK GENMAS <<
122 #define AIC32X4_CODEC_CLKIN_SHIFT (0) <<
123 #define AIC32X4_CODEC_CLKIN_MCLK (0x00) <<
124 #define AIC32X4_CODEC_CLKIN_BCLK (0x01) <<
125 #define AIC32X4_CODEC_CLKIN_GPIO1 (0x02) <<
126 #define AIC32X4_CODEC_CLKIN_PLL (0x03) <<
127 <<
128 /* AIC32X4_PLLPR */ <<
129 #define AIC32X4_PLLEN BIT(7) <<
130 #define AIC32X4_PLL_P_MASK GENMAS <<
131 #define AIC32X4_PLL_P_SHIFT (4) <<
132 #define AIC32X4_PLL_R_MASK GENMAS <<
133 <<
134 /* AIC32X4_NDAC */ <<
135 #define AIC32X4_NDACEN BIT(7) <<
136 #define AIC32X4_NDAC_MASK GENMAS <<
137 <<
138 /* AIC32X4_MDAC */ <<
139 #define AIC32X4_MDACEN BIT(7) <<
140 #define AIC32X4_MDAC_MASK GENMAS <<
141 <<
142 /* AIC32X4_NADC */ <<
143 #define AIC32X4_NADCEN BIT(7) <<
144 #define AIC32X4_NADC_MASK GENMAS <<
145 <<
146 /* AIC32X4_MADC */ <<
147 #define AIC32X4_MADCEN BIT(7) <<
148 #define AIC32X4_MADC_MASK GENMAS <<
149 <<
150 /* AIC32X4_BCLKN */ <<
151 #define AIC32X4_BCLKEN BIT(7) <<
152 #define AIC32X4_BCLK_MASK GENMAS <<
153 <<
154 /* AIC32X4_IFACE1 */ <<
155 #define AIC32X4_IFACE1_DATATYPE_MASK GENMAS <<
156 #define AIC32X4_IFACE1_DATATYPE_SHIFT (6) <<
157 #define AIC32X4_I2S_MODE (0x00) <<
158 #define AIC32X4_DSP_MODE (0x01) <<
159 #define AIC32X4_RIGHT_JUSTIFIED_MODE (0x02) <<
160 #define AIC32X4_LEFT_JUSTIFIED_MODE (0x03) <<
161 #define AIC32X4_IFACE1_DATALEN_MASK GENMAS <<
162 #define AIC32X4_IFACE1_DATALEN_SHIFT (4) <<
163 #define AIC32X4_WORD_LEN_16BITS (0x00) <<
164 #define AIC32X4_WORD_LEN_20BITS (0x01) <<
165 #define AIC32X4_WORD_LEN_24BITS (0x02) <<
166 #define AIC32X4_WORD_LEN_32BITS (0x03) <<
167 #define AIC32X4_IFACE1_MASTER_MASK GENMAS <<
168 #define AIC32X4_BCLKMASTER BIT(2) <<
169 #define AIC32X4_WCLKMASTER BIT(3) <<
170 <<
171 /* AIC32X4_IFACE2 */ <<
172 #define AIC32X4_DATA_OFFSET_MASK GENMAS <<
173 <<
174 /* AIC32X4_IFACE3 */ <<
175 #define AIC32X4_BCLKINV_MASK BIT(3) <<
176 #define AIC32X4_BDIVCLK_MASK GENMAS <<
177 #define AIC32X4_BDIVCLK_SHIFT (0) <<
178 #define AIC32X4_DAC2BCLK (0x00) <<
179 #define AIC32X4_DACMOD2BCLK (0x01) <<
180 #define AIC32X4_ADC2BCLK (0x02) <<
181 #define AIC32X4_ADCMOD2BCLK (0x03) <<
182 <<
183 /* AIC32X4_DACSETUP */ <<
184 #define AIC32X4_DAC_CHAN_MASK GENMAS <<
185 #define AIC32X4_LDAC2RCHN BIT(5) <<
186 #define AIC32X4_LDAC2LCHN BIT(4) <<
187 #define AIC32X4_RDAC2LCHN BIT(3) <<
188 #define AIC32X4_RDAC2RCHN BIT(2) <<
189 <<
190 /* AIC32X4_DACMUTE */ <<
191 #define AIC32X4_MUTEON 0x0C <<
192 116
193 /* AIC32X4_ADCSETUP */ !! 117 #define AIC32X4_PLLCLKIN 0x03
194 #define AIC32X4_LADC_EN BIT(7) <<
195 #define AIC32X4_RADC_EN BIT(6) <<
196 <<
197 /* AIC32X4_PWRCFG */ <<
198 #define AIC32X4_AVDDWEAKDISABLE BIT(3) <<
199 <<
200 /* AIC32X4_LDOCTL */ <<
201 #define AIC32X4_LDOCTLEN BIT(0) <<
202 <<
203 /* AIC32X4_CMMODE */ <<
204 #define AIC32X4_LDOIN_18_36 BIT(0) <<
205 #define AIC32X4_LDOIN2HP BIT(1) <<
206 118
207 /* AIC32X4_MICBIAS */ !! 119 #define AIC32X4_MICBIAS_LDOIN 0x08
208 #define AIC32X4_MICBIAS_LDOIN BIT(3) <<
209 #define AIC32X4_MICBIAS_2075V 0x60 120 #define AIC32X4_MICBIAS_2075V 0x60
210 #define AIC32x4_MICBIAS_MASK GENMAS <<
211 121
212 /* AIC32X4_LMICPGANIN */ <<
213 #define AIC32X4_LMICPGANIN_IN2R_10K 0x10 122 #define AIC32X4_LMICPGANIN_IN2R_10K 0x10
214 #define AIC32X4_LMICPGANIN_CM1L_10K 0x40 <<
215 <<
216 /* AIC32X4_RMICPGANIN */ <<
217 #define AIC32X4_RMICPGANIN_IN1L_10K 0x10 123 #define AIC32X4_RMICPGANIN_IN1L_10K 0x10
218 #define AIC32X4_RMICPGANIN_CM1R_10K 0x40 <<
219 124
220 /* AIC32X4_REFPOWERUP */ !! 125 #define AIC32X4_LMICPGAVOL_NOGAIN 0x80
221 #define AIC32X4_REFPOWERUP_SLOW 0x04 !! 126 #define AIC32X4_RMICPGAVOL_NOGAIN 0x80
222 #define AIC32X4_REFPOWERUP_40MS 0x05 !! 127
223 #define AIC32X4_REFPOWERUP_80MS 0x06 !! 128 #define AIC32X4_BCLKMASTER 0x08
224 #define AIC32X4_REFPOWERUP_120MS 0x07 !! 129 #define AIC32X4_WCLKMASTER 0x04
225 !! 130 #define AIC32X4_PLLEN (0x01 << 7)
226 /* Common mask and enable for all of the divid !! 131 #define AIC32X4_NDACEN (0x01 << 7)
227 #define AIC32X4_DIVEN BIT(7) !! 132 #define AIC32X4_MDACEN (0x01 << 7)
228 #define AIC32X4_DIV_MASK GENMAS !! 133 #define AIC32X4_NADCEN (0x01 << 7)
229 #define AIC32X4_DIV_MAX 128 !! 134 #define AIC32X4_MADCEN (0x01 << 7)
230 !! 135 #define AIC32X4_BCLKEN (0x01 << 7)
231 /* Clock Limits */ !! 136 #define AIC32X4_DACEN (0x03 << 6)
232 #define AIC32X4_MAX_DOSR_FREQ 620000 !! 137 #define AIC32X4_RDAC2LCHN (0x02 << 2)
233 #define AIC32X4_MIN_DOSR_FREQ 280000 !! 138 #define AIC32X4_LDAC2RCHN (0x02 << 4)
234 #define AIC32X4_MAX_CODEC_CLKIN_FREQ 110000 !! 139 #define AIC32X4_LDAC2LCHN (0x01 << 4)
235 #define AIC32X4_MAX_PLL_CLKIN 200000 !! 140 #define AIC32X4_RDAC2RCHN (0x01 << 2)
>> 141
>> 142 #define AIC32X4_SSTEP2WCLK 0x01
>> 143 #define AIC32X4_MUTEON 0x0C
>> 144 #define AIC32X4_DACMOD2BCLK 0x01
236 145
237 #endif /* _TLV320AIC3 146 #endif /* _TLV320AIC32X4_H */
238 147
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