1 /* SPDX-License-Identifier: GPL-2.0-only */ <<
2 /* 1 /*
3 * ALSA SoC TLV320AIC3X codec driver 2 * ALSA SoC TLV320AIC3X codec driver
4 * 3 *
5 * Author: Vladimir Barinov, <vbarinov@em 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
6 * Copyright: (C) 2007 MontaVista Software, 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
>> 6 *
>> 7 * This program is free software; you can redistribute it and/or modify
>> 8 * it under the terms of the GNU General Public License version 2 as
>> 9 * published by the Free Software Foundation.
7 */ 10 */
8 11
9 #ifndef _AIC3X_H 12 #ifndef _AIC3X_H
10 #define _AIC3X_H 13 #define _AIC3X_H
11 14
12 struct device; <<
13 struct regmap_config; <<
14 <<
15 extern const struct regmap_config aic3x_regmap <<
16 int aic3x_probe(struct device *dev, struct reg <<
17 void aic3x_remove(struct device *dev); <<
18 <<
19 #define AIC3X_MODEL_3X 0 <<
20 #define AIC3X_MODEL_33 1 <<
21 #define AIC3X_MODEL_3007 2 <<
22 #define AIC3X_MODEL_3104 3 <<
23 #define AIC3X_MODEL_3106 4 <<
24 <<
25 /* AIC3X register space */ 15 /* AIC3X register space */
26 #define AIC3X_CACHEREGNUM 110 16 #define AIC3X_CACHEREGNUM 110
27 17
28 /* Page select register */ 18 /* Page select register */
29 #define AIC3X_PAGE_SELECT 0 19 #define AIC3X_PAGE_SELECT 0
30 /* Software reset register */ 20 /* Software reset register */
31 #define AIC3X_RESET 1 21 #define AIC3X_RESET 1
32 /* Codec Sample rate select register */ 22 /* Codec Sample rate select register */
33 #define AIC3X_SAMPLE_RATE_SEL_REG 2 23 #define AIC3X_SAMPLE_RATE_SEL_REG 2
34 /* PLL progrramming register A */ 24 /* PLL progrramming register A */
35 #define AIC3X_PLL_PROGA_REG 3 25 #define AIC3X_PLL_PROGA_REG 3
36 /* PLL progrramming register B */ 26 /* PLL progrramming register B */
37 #define AIC3X_PLL_PROGB_REG 4 27 #define AIC3X_PLL_PROGB_REG 4
38 /* PLL progrramming register C */ 28 /* PLL progrramming register C */
39 #define AIC3X_PLL_PROGC_REG 5 29 #define AIC3X_PLL_PROGC_REG 5
40 /* PLL progrramming register D */ 30 /* PLL progrramming register D */
41 #define AIC3X_PLL_PROGD_REG 6 31 #define AIC3X_PLL_PROGD_REG 6
42 /* Codec datapath setup register */ 32 /* Codec datapath setup register */
43 #define AIC3X_CODEC_DATAPATH_REG 7 33 #define AIC3X_CODEC_DATAPATH_REG 7
44 /* Audio serial data interface control registe 34 /* Audio serial data interface control register A */
45 #define AIC3X_ASD_INTF_CTRLA 8 35 #define AIC3X_ASD_INTF_CTRLA 8
46 /* Audio serial data interface control registe 36 /* Audio serial data interface control register B */
47 #define AIC3X_ASD_INTF_CTRLB 9 37 #define AIC3X_ASD_INTF_CTRLB 9
48 /* Audio serial data interface control registe 38 /* Audio serial data interface control register C */
49 #define AIC3X_ASD_INTF_CTRLC 10 39 #define AIC3X_ASD_INTF_CTRLC 10
50 /* Audio overflow status and PLL R value progr 40 /* Audio overflow status and PLL R value programming register */
51 #define AIC3X_OVRF_STATUS_AND_PLLR_REG 11 41 #define AIC3X_OVRF_STATUS_AND_PLLR_REG 11
52 /* Audio codec digital filter control register 42 /* Audio codec digital filter control register */
53 #define AIC3X_CODEC_DFILT_CTRL 12 43 #define AIC3X_CODEC_DFILT_CTRL 12
54 /* Headset/button press detection register */ 44 /* Headset/button press detection register */
55 #define AIC3X_HEADSET_DETECT_CTRL_A 13 45 #define AIC3X_HEADSET_DETECT_CTRL_A 13
56 #define AIC3X_HEADSET_DETECT_CTRL_B 14 46 #define AIC3X_HEADSET_DETECT_CTRL_B 14
57 /* ADC PGA Gain control registers */ 47 /* ADC PGA Gain control registers */
58 #define LADC_VOL 15 48 #define LADC_VOL 15
59 #define RADC_VOL 16 49 #define RADC_VOL 16
60 /* MIC3 control registers */ 50 /* MIC3 control registers */
61 #define MIC3LR_2_LADC_CTRL 17 51 #define MIC3LR_2_LADC_CTRL 17
62 #define MIC3LR_2_RADC_CTRL 18 52 #define MIC3LR_2_RADC_CTRL 18
63 /* Line1 Input control registers */ 53 /* Line1 Input control registers */
64 #define LINE1L_2_LADC_CTRL 19 54 #define LINE1L_2_LADC_CTRL 19
65 #define LINE1R_2_LADC_CTRL 21 55 #define LINE1R_2_LADC_CTRL 21
66 #define LINE1R_2_RADC_CTRL 22 56 #define LINE1R_2_RADC_CTRL 22
67 #define LINE1L_2_RADC_CTRL 24 57 #define LINE1L_2_RADC_CTRL 24
68 /* Line2 Input control registers */ 58 /* Line2 Input control registers */
69 #define LINE2L_2_LADC_CTRL 20 59 #define LINE2L_2_LADC_CTRL 20
70 #define LINE2R_2_RADC_CTRL 23 60 #define LINE2R_2_RADC_CTRL 23
71 /* MICBIAS Control Register */ 61 /* MICBIAS Control Register */
72 #define MICBIAS_CTRL 25 62 #define MICBIAS_CTRL 25
73 63
74 /* AGC Control Registers A, B, C */ 64 /* AGC Control Registers A, B, C */
75 #define LAGC_CTRL_A 26 65 #define LAGC_CTRL_A 26
76 #define LAGC_CTRL_B 27 66 #define LAGC_CTRL_B 27
77 #define LAGC_CTRL_C 28 67 #define LAGC_CTRL_C 28
78 #define RAGC_CTRL_A 29 68 #define RAGC_CTRL_A 29
79 #define RAGC_CTRL_B 30 69 #define RAGC_CTRL_B 30
80 #define RAGC_CTRL_C 31 70 #define RAGC_CTRL_C 31
81 71
82 /* DAC Power and Left High Power Output contro 72 /* DAC Power and Left High Power Output control registers */
83 #define DAC_PWR 37 73 #define DAC_PWR 37
84 #define HPLCOM_CFG 37 74 #define HPLCOM_CFG 37
85 /* Right High Power Output control registers * 75 /* Right High Power Output control registers */
86 #define HPRCOM_CFG 38 76 #define HPRCOM_CFG 38
87 /* High Power Output Stage Control Register */ 77 /* High Power Output Stage Control Register */
88 #define HPOUT_SC 40 78 #define HPOUT_SC 40
89 /* DAC Output Switching control registers */ 79 /* DAC Output Switching control registers */
90 #define DAC_LINE_MUX 41 80 #define DAC_LINE_MUX 41
91 /* High Power Output Driver Pop Reduction regi 81 /* High Power Output Driver Pop Reduction registers */
92 #define HPOUT_POP_REDUCTION 42 82 #define HPOUT_POP_REDUCTION 42
93 /* DAC Digital control registers */ 83 /* DAC Digital control registers */
94 #define LDAC_VOL 43 84 #define LDAC_VOL 43
95 #define RDAC_VOL 44 85 #define RDAC_VOL 44
96 /* Left High Power Output control registers */ 86 /* Left High Power Output control registers */
97 #define LINE2L_2_HPLOUT_VOL 45 87 #define LINE2L_2_HPLOUT_VOL 45
98 #define PGAL_2_HPLOUT_VOL 46 88 #define PGAL_2_HPLOUT_VOL 46
99 #define DACL1_2_HPLOUT_VOL 47 89 #define DACL1_2_HPLOUT_VOL 47
100 #define LINE2R_2_HPLOUT_VOL 48 90 #define LINE2R_2_HPLOUT_VOL 48
101 #define PGAR_2_HPLOUT_VOL 49 91 #define PGAR_2_HPLOUT_VOL 49
102 #define DACR1_2_HPLOUT_VOL 50 92 #define DACR1_2_HPLOUT_VOL 50
103 #define HPLOUT_CTRL 51 93 #define HPLOUT_CTRL 51
104 /* Left High Power COM control registers */ 94 /* Left High Power COM control registers */
105 #define LINE2L_2_HPLCOM_VOL 52 95 #define LINE2L_2_HPLCOM_VOL 52
106 #define PGAL_2_HPLCOM_VOL 53 96 #define PGAL_2_HPLCOM_VOL 53
107 #define DACL1_2_HPLCOM_VOL 54 97 #define DACL1_2_HPLCOM_VOL 54
108 #define LINE2R_2_HPLCOM_VOL 55 98 #define LINE2R_2_HPLCOM_VOL 55
109 #define PGAR_2_HPLCOM_VOL 56 99 #define PGAR_2_HPLCOM_VOL 56
110 #define DACR1_2_HPLCOM_VOL 57 100 #define DACR1_2_HPLCOM_VOL 57
111 #define HPLCOM_CTRL 58 101 #define HPLCOM_CTRL 58
112 /* Right High Power Output control registers * 102 /* Right High Power Output control registers */
113 #define LINE2L_2_HPROUT_VOL 59 103 #define LINE2L_2_HPROUT_VOL 59
114 #define PGAL_2_HPROUT_VOL 60 104 #define PGAL_2_HPROUT_VOL 60
115 #define DACL1_2_HPROUT_VOL 61 105 #define DACL1_2_HPROUT_VOL 61
116 #define LINE2R_2_HPROUT_VOL 62 106 #define LINE2R_2_HPROUT_VOL 62
117 #define PGAR_2_HPROUT_VOL 63 107 #define PGAR_2_HPROUT_VOL 63
118 #define DACR1_2_HPROUT_VOL 64 108 #define DACR1_2_HPROUT_VOL 64
119 #define HPROUT_CTRL 65 109 #define HPROUT_CTRL 65
120 /* Right High Power COM control registers */ 110 /* Right High Power COM control registers */
121 #define LINE2L_2_HPRCOM_VOL 66 111 #define LINE2L_2_HPRCOM_VOL 66
122 #define PGAL_2_HPRCOM_VOL 67 112 #define PGAL_2_HPRCOM_VOL 67
123 #define DACL1_2_HPRCOM_VOL 68 113 #define DACL1_2_HPRCOM_VOL 68
124 #define LINE2R_2_HPRCOM_VOL 69 114 #define LINE2R_2_HPRCOM_VOL 69
125 #define PGAR_2_HPRCOM_VOL 70 115 #define PGAR_2_HPRCOM_VOL 70
126 #define DACR1_2_HPRCOM_VOL 71 116 #define DACR1_2_HPRCOM_VOL 71
127 #define HPRCOM_CTRL 72 117 #define HPRCOM_CTRL 72
128 /* Mono Line Output Plus/Minus control registe 118 /* Mono Line Output Plus/Minus control registers */
129 #define LINE2L_2_MONOLOPM_VOL 73 119 #define LINE2L_2_MONOLOPM_VOL 73
130 #define PGAL_2_MONOLOPM_VOL 74 120 #define PGAL_2_MONOLOPM_VOL 74
131 #define DACL1_2_MONOLOPM_VOL 75 121 #define DACL1_2_MONOLOPM_VOL 75
132 #define LINE2R_2_MONOLOPM_VOL 76 122 #define LINE2R_2_MONOLOPM_VOL 76
133 #define PGAR_2_MONOLOPM_VOL 77 123 #define PGAR_2_MONOLOPM_VOL 77
134 #define DACR1_2_MONOLOPM_VOL 78 124 #define DACR1_2_MONOLOPM_VOL 78
135 #define MONOLOPM_CTRL 79 125 #define MONOLOPM_CTRL 79
136 /* Class-D speaker driver on tlv320aic3007 */ 126 /* Class-D speaker driver on tlv320aic3007 */
137 #define CLASSD_CTRL 73 127 #define CLASSD_CTRL 73
138 /* Left Line Output Plus/Minus control registe 128 /* Left Line Output Plus/Minus control registers */
139 #define LINE2L_2_LLOPM_VOL 80 129 #define LINE2L_2_LLOPM_VOL 80
140 #define PGAL_2_LLOPM_VOL 81 130 #define PGAL_2_LLOPM_VOL 81
141 #define DACL1_2_LLOPM_VOL 82 131 #define DACL1_2_LLOPM_VOL 82
142 #define LINE2R_2_LLOPM_VOL 83 132 #define LINE2R_2_LLOPM_VOL 83
143 #define PGAR_2_LLOPM_VOL 84 133 #define PGAR_2_LLOPM_VOL 84
144 #define DACR1_2_LLOPM_VOL 85 134 #define DACR1_2_LLOPM_VOL 85
145 #define LLOPM_CTRL 86 135 #define LLOPM_CTRL 86
146 /* Right Line Output Plus/Minus control regist 136 /* Right Line Output Plus/Minus control registers */
147 #define LINE2L_2_RLOPM_VOL 87 137 #define LINE2L_2_RLOPM_VOL 87
148 #define PGAL_2_RLOPM_VOL 88 138 #define PGAL_2_RLOPM_VOL 88
149 #define DACL1_2_RLOPM_VOL 89 139 #define DACL1_2_RLOPM_VOL 89
150 #define LINE2R_2_RLOPM_VOL 90 140 #define LINE2R_2_RLOPM_VOL 90
151 #define PGAR_2_RLOPM_VOL 91 141 #define PGAR_2_RLOPM_VOL 91
152 #define DACR1_2_RLOPM_VOL 92 142 #define DACR1_2_RLOPM_VOL 92
153 #define RLOPM_CTRL 93 143 #define RLOPM_CTRL 93
154 /* GPIO/IRQ registers */ 144 /* GPIO/IRQ registers */
155 #define AIC3X_STICKY_IRQ_FLAGS_REG 96 145 #define AIC3X_STICKY_IRQ_FLAGS_REG 96
156 #define AIC3X_RT_IRQ_FLAGS_REG 97 146 #define AIC3X_RT_IRQ_FLAGS_REG 97
157 #define AIC3X_GPIO1_REG 98 147 #define AIC3X_GPIO1_REG 98
158 #define AIC3X_GPIO2_REG 99 148 #define AIC3X_GPIO2_REG 99
159 #define AIC3X_GPIOA_REG 100 149 #define AIC3X_GPIOA_REG 100
160 #define AIC3X_GPIOB_REG 101 150 #define AIC3X_GPIOB_REG 101
161 /* Clock generation control register */ 151 /* Clock generation control register */
162 #define AIC3X_CLKGEN_CTRL_REG 102 152 #define AIC3X_CLKGEN_CTRL_REG 102
163 /* New AGC registers */ 153 /* New AGC registers */
164 #define LAGCN_ATTACK 103 154 #define LAGCN_ATTACK 103
165 #define LAGCN_DECAY 104 155 #define LAGCN_DECAY 104
166 #define RAGCN_ATTACK 105 156 #define RAGCN_ATTACK 105
167 #define RAGCN_DECAY 106 157 #define RAGCN_DECAY 106
168 /* New Programmable ADC Digital Path and I2C B 158 /* New Programmable ADC Digital Path and I2C Bus Condition Register */
169 #define NEW_ADC_DIGITALPATH 107 159 #define NEW_ADC_DIGITALPATH 107
170 /* Passive Analog Signal Bypass Selection Duri 160 /* Passive Analog Signal Bypass Selection During Powerdown Register */
171 #define PASSIVE_BYPASS 108 161 #define PASSIVE_BYPASS 108
172 /* DAC Quiescent Current Adjustment Register * 162 /* DAC Quiescent Current Adjustment Register */
173 #define DAC_ICC_ADJ 109 163 #define DAC_ICC_ADJ 109
174 164
175 /* Page select register bits */ 165 /* Page select register bits */
176 #define PAGE0_SELECT 0 166 #define PAGE0_SELECT 0
177 #define PAGE1_SELECT 1 167 #define PAGE1_SELECT 1
178 168
179 /* Audio serial data interface control registe 169 /* Audio serial data interface control register A bits */
180 #define BIT_CLK_MASTER 0x80 170 #define BIT_CLK_MASTER 0x80
181 #define WORD_CLK_MASTER 0x40 171 #define WORD_CLK_MASTER 0x40
182 #define DOUT_TRISTATE 0x20 <<
183 172
184 /* Codec Datapath setup register 7 */ 173 /* Codec Datapath setup register 7 */
185 #define FSREF_44100 (1 << 7) 174 #define FSREF_44100 (1 << 7)
186 #define FSREF_48000 (0 << 7) 175 #define FSREF_48000 (0 << 7)
187 #define DUAL_RATE_MODE ((1 << 5) | (1 176 #define DUAL_RATE_MODE ((1 << 5) | (1 << 6))
188 #define LDAC2LCH (0x1 << 3) 177 #define LDAC2LCH (0x1 << 3)
189 #define RDAC2RCH (0x1 << 1) 178 #define RDAC2RCH (0x1 << 1)
190 #define LDAC2RCH (0x2 << 3) 179 #define LDAC2RCH (0x2 << 3)
191 #define RDAC2LCH (0x2 << 1) 180 #define RDAC2LCH (0x2 << 1)
192 #define LDAC2MONOMIX (0x3 << 3) 181 #define LDAC2MONOMIX (0x3 << 3)
193 #define RDAC2MONOMIX (0x3 << 1) 182 #define RDAC2MONOMIX (0x3 << 1)
194 183
195 /* PLL registers bitfields */ 184 /* PLL registers bitfields */
196 #define PLLP_SHIFT 0 185 #define PLLP_SHIFT 0
197 #define PLLP_MASK 7 186 #define PLLP_MASK 7
198 #define PLLQ_SHIFT 3 187 #define PLLQ_SHIFT 3
199 #define PLLR_SHIFT 0 188 #define PLLR_SHIFT 0
200 #define PLLJ_SHIFT 2 189 #define PLLJ_SHIFT 2
201 #define PLLD_MSB_SHIFT 0 190 #define PLLD_MSB_SHIFT 0
202 #define PLLD_LSB_SHIFT 2 191 #define PLLD_LSB_SHIFT 2
203 192
204 /* Clock generation register bits */ 193 /* Clock generation register bits */
205 #define CODEC_CLKIN_PLLDIV 0 194 #define CODEC_CLKIN_PLLDIV 0
206 #define CODEC_CLKIN_CLKDIV 1 195 #define CODEC_CLKIN_CLKDIV 1
207 #define PLL_CLKIN_SHIFT 4 196 #define PLL_CLKIN_SHIFT 4
208 #define MCLK_SOURCE 0x0 197 #define MCLK_SOURCE 0x0
209 #define PLL_CLKDIV_SHIFT 0 198 #define PLL_CLKDIV_SHIFT 0
210 #define PLLCLK_IN_MASK 0x30 199 #define PLLCLK_IN_MASK 0x30
211 #define PLLCLK_IN_SHIFT 4 200 #define PLLCLK_IN_SHIFT 4
212 #define CLKDIV_IN_MASK 0xc0 201 #define CLKDIV_IN_MASK 0xc0
213 #define CLKDIV_IN_SHIFT 6 202 #define CLKDIV_IN_SHIFT 6
214 /* clock in source */ 203 /* clock in source */
215 #define CLKIN_MCLK 0 204 #define CLKIN_MCLK 0
216 #define CLKIN_GPIO2 1 205 #define CLKIN_GPIO2 1
217 #define CLKIN_BCLK 2 206 #define CLKIN_BCLK 2
218 207
219 /* Software reset register bits */ 208 /* Software reset register bits */
220 #define SOFT_RESET 0x80 209 #define SOFT_RESET 0x80
221 210
222 /* PLL progrramming register A bits */ 211 /* PLL progrramming register A bits */
223 #define PLL_ENABLE 0x80 212 #define PLL_ENABLE 0x80
224 213
225 /* Route bits */ 214 /* Route bits */
226 #define ROUTE_ON 0x80 215 #define ROUTE_ON 0x80
227 216
228 /* Mute bits */ 217 /* Mute bits */
229 #define UNMUTE 0x08 218 #define UNMUTE 0x08
230 #define MUTE_ON 0x80 219 #define MUTE_ON 0x80
231 220
232 /* Power bits */ 221 /* Power bits */
233 #define LADC_PWR_ON 0x04 222 #define LADC_PWR_ON 0x04
234 #define RADC_PWR_ON 0x04 223 #define RADC_PWR_ON 0x04
235 #define LDAC_PWR_ON 0x80 224 #define LDAC_PWR_ON 0x80
236 #define RDAC_PWR_ON 0x40 225 #define RDAC_PWR_ON 0x40
237 #define HPLOUT_PWR_ON 0x01 226 #define HPLOUT_PWR_ON 0x01
238 #define HPROUT_PWR_ON 0x01 227 #define HPROUT_PWR_ON 0x01
239 #define HPLCOM_PWR_ON 0x01 228 #define HPLCOM_PWR_ON 0x01
240 #define HPRCOM_PWR_ON 0x01 229 #define HPRCOM_PWR_ON 0x01
241 #define MONOLOPM_PWR_ON 0x01 230 #define MONOLOPM_PWR_ON 0x01
242 #define LLOPM_PWR_ON 0x01 231 #define LLOPM_PWR_ON 0x01
243 #define RLOPM_PWR_ON 0x01 232 #define RLOPM_PWR_ON 0x01
244 233
245 #define INVERT_VOL(val) (0x7f - val) 234 #define INVERT_VOL(val) (0x7f - val)
246 235
247 /* Default output volume (inverted) */ 236 /* Default output volume (inverted) */
248 #define DEFAULT_VOL INVERT_VOL(0x50) 237 #define DEFAULT_VOL INVERT_VOL(0x50)
249 /* Default input volume */ 238 /* Default input volume */
250 #define DEFAULT_GAIN 0x20 239 #define DEFAULT_GAIN 0x20
251 240
252 /* MICBIAS Control Register */ 241 /* MICBIAS Control Register */
253 #define MICBIAS_LEVEL_SHIFT (6) 242 #define MICBIAS_LEVEL_SHIFT (6)
254 #define MICBIAS_LEVEL_MASK (3 << 6) 243 #define MICBIAS_LEVEL_MASK (3 << 6)
255 244
256 /* HPOUT_SC */ <<
257 #define HPOUT_SC_OCMV_MASK (3 << 6) <<
258 #define HPOUT_SC_OCMV_SHIFT (6) <<
259 #define HPOUT_SC_OCMV_1_35V 0 <<
260 #define HPOUT_SC_OCMV_1_5V 1 <<
261 #define HPOUT_SC_OCMV_1_65V 2 <<
262 #define HPOUT_SC_OCMV_1_8V 3 <<
263 <<
264 /* headset detection / button API */ 245 /* headset detection / button API */
265 246
266 /* The AIC3x supports detection of stereo head 247 /* The AIC3x supports detection of stereo headsets (GND + left + right signal)
267 * and cellular headsets (GND + speaker output 248 * and cellular headsets (GND + speaker output + microphone input).
268 * It is recommended to enable MIC bias for th 249 * It is recommended to enable MIC bias for this function to work properly.
269 * For more information, please refer to the d 250 * For more information, please refer to the datasheet. */
270 enum { 251 enum {
271 AIC3X_HEADSET_DETECT_OFF = 0, 252 AIC3X_HEADSET_DETECT_OFF = 0,
272 AIC3X_HEADSET_DETECT_STEREO = 1, 253 AIC3X_HEADSET_DETECT_STEREO = 1,
273 AIC3X_HEADSET_DETECT_CELLULAR = 2, 254 AIC3X_HEADSET_DETECT_CELLULAR = 2,
274 AIC3X_HEADSET_DETECT_BOTH = 3 255 AIC3X_HEADSET_DETECT_BOTH = 3
275 }; 256 };
276 257
277 enum { 258 enum {
278 AIC3X_HEADSET_DEBOUNCE_16MS = 0, 259 AIC3X_HEADSET_DEBOUNCE_16MS = 0,
279 AIC3X_HEADSET_DEBOUNCE_32MS = 1, 260 AIC3X_HEADSET_DEBOUNCE_32MS = 1,
280 AIC3X_HEADSET_DEBOUNCE_64MS = 2, 261 AIC3X_HEADSET_DEBOUNCE_64MS = 2,
281 AIC3X_HEADSET_DEBOUNCE_128MS = 3, 262 AIC3X_HEADSET_DEBOUNCE_128MS = 3,
282 AIC3X_HEADSET_DEBOUNCE_256MS = 4, 263 AIC3X_HEADSET_DEBOUNCE_256MS = 4,
283 AIC3X_HEADSET_DEBOUNCE_512MS = 5 264 AIC3X_HEADSET_DEBOUNCE_512MS = 5
284 }; 265 };
285 266
286 enum { 267 enum {
287 AIC3X_BUTTON_DEBOUNCE_0MS = 0, 268 AIC3X_BUTTON_DEBOUNCE_0MS = 0,
288 AIC3X_BUTTON_DEBOUNCE_8MS = 1, 269 AIC3X_BUTTON_DEBOUNCE_8MS = 1,
289 AIC3X_BUTTON_DEBOUNCE_16MS = 2, 270 AIC3X_BUTTON_DEBOUNCE_16MS = 2,
290 AIC3X_BUTTON_DEBOUNCE_32MS = 3 271 AIC3X_BUTTON_DEBOUNCE_32MS = 3
291 }; 272 };
292 273
293 #define AIC3X_HEADSET_DETECT_ENABLED 0x80 274 #define AIC3X_HEADSET_DETECT_ENABLED 0x80
294 #define AIC3X_HEADSET_DETECT_SHIFT 5 275 #define AIC3X_HEADSET_DETECT_SHIFT 5
295 #define AIC3X_HEADSET_DETECT_MASK 3 276 #define AIC3X_HEADSET_DETECT_MASK 3
296 #define AIC3X_HEADSET_DEBOUNCE_SHIFT 2 277 #define AIC3X_HEADSET_DEBOUNCE_SHIFT 2
297 #define AIC3X_HEADSET_DEBOUNCE_MASK 7 278 #define AIC3X_HEADSET_DEBOUNCE_MASK 7
298 #define AIC3X_BUTTON_DEBOUNCE_SHIFT 0 279 #define AIC3X_BUTTON_DEBOUNCE_SHIFT 0
299 #define AIC3X_BUTTON_DEBOUNCE_MASK 3 280 #define AIC3X_BUTTON_DEBOUNCE_MASK 3
300 <<
301 /* GPIO API */ <<
302 enum { <<
303 AIC3X_GPIO1_FUNC_DISABLED <<
304 AIC3X_GPIO1_FUNC_AUDIO_WORDCLK_ADC <<
305 AIC3X_GPIO1_FUNC_CLOCK_MUX <<
306 AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV2 <<
307 AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV4 <<
308 AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV8 <<
309 AIC3X_GPIO1_FUNC_SHORT_CIRCUIT_IRQ <<
310 AIC3X_GPIO1_FUNC_AGC_NOISE_IRQ <<
311 AIC3X_GPIO1_FUNC_INPUT <<
312 AIC3X_GPIO1_FUNC_OUTPUT <<
313 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK <<
314 AIC3X_GPIO1_FUNC_AUDIO_WORDCLK <<
315 AIC3X_GPIO1_FUNC_BUTTON_IRQ <<
316 AIC3X_GPIO1_FUNC_HEADSET_DETECT_IRQ <<
317 AIC3X_GPIO1_FUNC_HEADSET_DETECT_OR_BUT <<
318 AIC3X_GPIO1_FUNC_ALL_IRQ <<
319 }; <<
320 <<
321 enum { <<
322 AIC3X_GPIO2_FUNC_DISABLED <<
323 AIC3X_GPIO2_FUNC_HEADSET_DETECT_IRQ <<
324 AIC3X_GPIO2_FUNC_INPUT <<
325 AIC3X_GPIO2_FUNC_OUTPUT <<
326 AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT <<
327 AIC3X_GPIO2_FUNC_AUDIO_BITCLK <<
328 AIC3X_GPIO2_FUNC_HEADSET_DETECT_OR_BUT <<
329 AIC3X_GPIO2_FUNC_ALL_IRQ <<
330 AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_OR_AGC_ <<
331 AIC3X_GPIO2_FUNC_HEADSET_OR_BUTTON_PRE <<
332 AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_IRQ <<
333 AIC3X_GPIO2_FUNC_AGC_NOISE_IRQ <<
334 AIC3X_GPIO2_FUNC_BUTTON_PRESS_IRQ <<
335 }; <<
336 <<
337 enum aic3x_micbias_voltage { <<
338 AIC3X_MICBIAS_OFF = 0, <<
339 AIC3X_MICBIAS_2_0V = 1, <<
340 AIC3X_MICBIAS_2_5V = 2, <<
341 AIC3X_MICBIAS_AVDDV = 3, <<
342 }; <<
343 281
344 #endif /* _AIC3X_H */ 282 #endif /* _AIC3X_H */
345 283
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