1 // SPDX-License-Identifier: GPL-2.0-only 1
2 // Copyright (c) 2023-2024 Qualcomm Innovation
3
4 #include <linux/component.h>
5 #include <linux/delay.h>
6 #include <linux/device.h>
7 #include <linux/gpio/consumer.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/of_gpio.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/regmap.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/slab.h>
17 #include <sound/jack.h>
18 #include <sound/pcm_params.h>
19 #include <sound/pcm.h>
20 #include <sound/soc-dapm.h>
21 #include <sound/soc.h>
22 #include <sound/tlv.h>
23
24 #include "wcd-clsh-v2.h"
25 #include "wcd-mbhc-v2.h"
26 #include "wcd937x.h"
27
28 enum {
29 CHIPID_WCD9370 = 0,
30 CHIPID_WCD9375 = 5,
31 };
32
33 /* Z value defined in milliohm */
34 #define WCD937X_ZDET_VAL_32 (32000
35 #define WCD937X_ZDET_VAL_400 (40000
36 #define WCD937X_ZDET_VAL_1200 (12000
37 #define WCD937X_ZDET_VAL_100K (10000
38 /* Z floating defined in ohms */
39 #define WCD937X_ZDET_FLOATING_IMPEDANCE (0x0FF
40 #define WCD937X_ZDET_NUM_MEASUREMENTS (900)
41 #define WCD937X_MBHC_GET_C1(c) (((c)
42 #define WCD937X_MBHC_GET_X1(x) ((x) &
43 /* Z value compared in milliOhm */
44 #define WCD937X_MBHC_IS_SECOND_RAMP_REQUIRED(z
45 #define WCD937X_MBHC_ZDET_CONST (86 *
46 #define WCD937X_MBHC_MOISTURE_RREF R_24_K
47 #define WCD_MBHC_HS_V_MAX 1600
48 #define EAR_RX_PATH_AUX 1
49 #define WCD937X_MBHC_MAX_BUTTONS 8
50
51 #define WCD937X_RATES (SNDRV_PCM_RATE_8000 | S
52 SNDRV_PCM_RATE_32000 |
53 SNDRV_PCM_RATE_96000 |
54 SNDRV_PCM_RATE_384000)
55
56 /* Fractional Rates */
57 #define WCD937X_FRAC_RATES (SNDRV_PCM_RATE_441
58 SNDRV_PCM_RATE_176
59
60 #define WCD937X_FORMATS (SNDRV_PCM_FMTBIT_S16_
61 SNDRV_PCM_FMTBIT_S24_
62
63 enum {
64 ALLOW_BUCK_DISABLE,
65 HPH_COMP_DELAY,
66 HPH_PA_DELAY,
67 AMIC2_BCS_ENABLE,
68 };
69
70 enum {
71 AIF1_PB = 0,
72 AIF1_CAP,
73 NUM_CODEC_DAIS,
74 };
75
76 struct wcd937x_priv {
77 struct sdw_slave *tx_sdw_dev;
78 struct wcd937x_sdw_priv *sdw_priv[NUM_
79 struct device *txdev;
80 struct device *rxdev;
81 struct device_node *rxnode;
82 struct device_node *txnode;
83 struct regmap *regmap;
84 /* micb setup lock */
85 struct mutex micb_lock;
86 /* mbhc module */
87 struct wcd_mbhc *wcd_mbhc;
88 struct wcd_mbhc_config mbhc_cfg;
89 struct wcd_mbhc_intr intr_ids;
90 struct wcd_clsh_ctrl *clsh_info;
91 struct irq_domain *virq;
92 struct regmap_irq_chip *wcd_regmap_irq
93 struct regmap_irq_chip_data *irq_chip;
94 struct regulator_bulk_data supplies[WC
95 struct regulator *buck_supply;
96 struct snd_soc_jack *jack;
97 unsigned long status_mask;
98 s32 micb_ref[WCD937X_MAX_MICBIAS];
99 s32 pullup_ref[WCD937X_MAX_MICBIAS];
100 u32 hph_mode;
101 int ear_rx_path;
102 u32 micb1_mv;
103 u32 micb2_mv;
104 u32 micb3_mv;
105 int hphr_pdm_wd_int;
106 int hphl_pdm_wd_int;
107 int aux_pdm_wd_int;
108 bool comp1_enable;
109 bool comp2_enable;
110
111 struct gpio_desc *us_euro_gpio;
112 struct gpio_desc *reset_gpio;
113
114 atomic_t rx_clk_cnt;
115 atomic_t ana_clk_count;
116 };
117
118 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(
119 static const DECLARE_TLV_DB_SCALE(line_gain, 0
120 static const DECLARE_TLV_DB_SCALE(analog_gain,
121
122 struct wcd937x_mbhc_zdet_param {
123 u16 ldo_ctl;
124 u16 noff;
125 u16 nshift;
126 u16 btn5;
127 u16 btn6;
128 u16 btn7;
129 };
130
131 static const struct wcd_mbhc_field wcd_mbhc_fi
132 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD9
133 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WC
134 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION
135 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL,
136 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTIO
137 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_
138 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_
139 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE
140 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE,
141 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K
142 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_IS
143 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD937
144 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, W
145 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD9
146 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD93
147 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT
148 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STA
149 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESU
150 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RES
151 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RES
152 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WC
153 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WC
154 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL,
155 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT,
156 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD
157 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIM
158 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WC
159 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WC
160 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD
161 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REM
162 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WC
163 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WC
164 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD93
165 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATU
166 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD9
167 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD9
168 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_E
169 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_E
170 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATU
171 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATU
172 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD937
173 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE,
174 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, W
175 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WC
176 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WC
177 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD9
178 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE
179 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN,
180 };
181
182 static const struct regmap_irq wcd937x_irqs[WC
183 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON
184 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON
185 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_
186 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_
187 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET
188 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_IN
189 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_IN
190 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_IN
191 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_IN
192 REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT
193 REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT
194 REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT
195 REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT
196 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD
197 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD
198 REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_
199 REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_I
200 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTU
201 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_
202 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_
203 };
204
205 static int wcd937x_handle_post_irq(void *data)
206 {
207 struct wcd937x_priv *wcd937x;
208
209 if (data)
210 wcd937x = (struct wcd937x_priv
211 else
212 return IRQ_HANDLED;
213
214 regmap_write(wcd937x->regmap, WCD937X_
215 regmap_write(wcd937x->regmap, WCD937X_
216 regmap_write(wcd937x->regmap, WCD937X_
217
218 return IRQ_HANDLED;
219 }
220
221 static const u32 wcd937x_config_regs[] = {
222 WCD937X_DIGITAL_INTR_LEVEL_0,
223 };
224
225 static const struct regmap_irq_chip wcd937x_re
226 .name = "wcd937x",
227 .irqs = wcd937x_irqs,
228 .num_irqs = ARRAY_SIZE(wcd937x_irqs),
229 .num_regs = 3,
230 .status_base = WCD937X_DIGITAL_INTR_ST
231 .mask_base = WCD937X_DIGITAL_INTR_MASK
232 .ack_base = WCD937X_DIGITAL_INTR_CLEAR
233 .use_ack = 1,
234 .clear_ack = 1,
235 .config_base = wcd937x_config_regs,
236 .num_config_bases = ARRAY_SIZE(wcd937x
237 .num_config_regs = 1,
238 .runtime_pm = true,
239 .handle_post_irq = wcd937x_handle_post
240 .irq_drv_data = NULL,
241 };
242
243 static void wcd937x_reset(struct wcd937x_priv
244 {
245 gpiod_set_value(wcd937x->reset_gpio, 1
246 usleep_range(20, 30);
247 gpiod_set_value(wcd937x->reset_gpio, 0
248 usleep_range(20, 30);
249 }
250
251 static void wcd937x_io_init(struct regmap *reg
252 {
253 u32 val = 0, temp = 0, temp1 = 0;
254
255 regmap_read(regmap, WCD937X_DIGITAL_EF
256
257 val = val & 0x0F;
258
259 regmap_read(regmap, WCD937X_DIGITAL_EF
260 regmap_read(regmap, WCD937X_DIGITAL_EF
261
262 if (temp == 0x02 || temp1 > 0x09)
263 regmap_update_bits(regmap, WCD
264 else
265 regmap_update_bits(regmap, WCD
266
267 regmap_update_bits(regmap, WCD937X_SLE
268 usleep_range(1000, 1010);
269
270 regmap_update_bits(regmap, WCD937X_SLE
271 usleep_range(1000, 1010);
272
273 regmap_update_bits(regmap, WCD937X_LDO
274 regmap_update_bits(regmap, WCD937X_BIA
275 regmap_update_bits(regmap, WCD937X_ANA
276 regmap_update_bits(regmap, WCD937X_ANA
277 usleep_range(10000, 10010);
278
279 regmap_update_bits(regmap, WCD937X_ANA
280 regmap_update_bits(regmap, WCD937X_HPH
281 regmap_update_bits(regmap, WCD937X_MIC
282 regmap_update_bits(regmap, WCD937X_MIC
283 regmap_update_bits(regmap, WCD937X_MIC
284
285 regmap_update_bits(regmap, WCD937X_MIC
286 regmap_update_bits(regmap, WCD937X_MIC
287 regmap_update_bits(regmap, WCD937X_MIC
288
289 /* Set Bandgap Fine Adjustment to +5mV
290 regmap_read(regmap, WCD937X_DIGITAL_EF
291 if (val == 0x01) {
292 regmap_update_bits(regmap, WCD
293 } else if (val == 0x02) {
294 regmap_update_bits(regmap, WCD
295 regmap_update_bits(regmap, WCD
296 regmap_update_bits(regmap, WCD
297 regmap_update_bits(regmap, WCD
298 }
299 }
300
301 static int wcd937x_rx_clk_enable(struct snd_so
302 {
303 struct wcd937x_priv *wcd937x = snd_soc
304
305 if (atomic_read(&wcd937x->rx_clk_cnt))
306 return 0;
307
308 snd_soc_component_update_bits(componen
309 snd_soc_component_update_bits(componen
310 snd_soc_component_update_bits(componen
311 snd_soc_component_update_bits(componen
312 snd_soc_component_update_bits(componen
313 snd_soc_component_update_bits(componen
314 snd_soc_component_update_bits(componen
315
316 atomic_inc(&wcd937x->rx_clk_cnt);
317
318 return 0;
319 }
320
321 static int wcd937x_rx_clk_disable(struct snd_s
322 {
323 struct wcd937x_priv *wcd937x = snd_soc
324
325 if (!atomic_read(&wcd937x->rx_clk_cnt)
326 dev_err(component->dev, "clk a
327 return 0;
328 }
329
330 atomic_dec(&wcd937x->rx_clk_cnt);
331
332 snd_soc_component_update_bits(componen
333 snd_soc_component_update_bits(componen
334 snd_soc_component_update_bits(componen
335
336 return 0;
337 }
338
339 static int wcd937x_codec_hphl_dac_event(struct
340 struct
341 int ev
342 {
343 struct snd_soc_component *component =
344 struct wcd937x_priv *wcd937x = snd_soc
345 int hph_mode = wcd937x->hph_mode;
346
347 switch (event) {
348 case SND_SOC_DAPM_PRE_PMU:
349 wcd937x_rx_clk_enable(componen
350 snd_soc_component_update_bits(
351
352
353 snd_soc_component_update_bits(
354
355
356 snd_soc_component_update_bits(
357
358
359 set_bit(HPH_COMP_DELAY, &wcd93
360 break;
361 case SND_SOC_DAPM_POST_PMU:
362 if (hph_mode == CLS_AB_HIFI ||
363 snd_soc_component_upda
364
365
366 else if (hph_mode == CLS_H_LOH
367 snd_soc_component_upda
368
369
370
371 if (wcd937x->comp1_enable) {
372 snd_soc_component_upda
373
374
375 snd_soc_component_upda
376
377
378
379 if (wcd937x->comp2_ena
380 snd_soc_compon
381
382
383 snd_soc_compon
384
385 }
386
387 if (test_bit(HPH_COMP_
388 usleep_range(5
389 clear_bit(HPH_
390 }
391 } else {
392 snd_soc_component_upda
393
394
395 snd_soc_component_upda
396
397
398 }
399
400 snd_soc_component_update_bits(
401
402
403 break;
404 case SND_SOC_DAPM_POST_PMD:
405 snd_soc_component_update_bits(
406
407
408 break;
409 }
410
411 return 0;
412 }
413
414 static int wcd937x_codec_hphr_dac_event(struct
415 struct
416 int ev
417 {
418 struct snd_soc_component *component =
419 struct wcd937x_priv *wcd937x = snd_soc
420 int hph_mode = wcd937x->hph_mode;
421
422 switch (event) {
423 case SND_SOC_DAPM_PRE_PMU:
424 wcd937x_rx_clk_enable(componen
425 snd_soc_component_update_bits(
426
427 snd_soc_component_update_bits(
428
429 snd_soc_component_update_bits(
430
431 set_bit(HPH_COMP_DELAY, &wcd93
432 break;
433 case SND_SOC_DAPM_POST_PMU:
434 if (hph_mode == CLS_AB_HIFI ||
435 snd_soc_component_upda
436
437
438 else if (hph_mode == CLS_H_LOH
439 snd_soc_component_upda
440
441
442 if (wcd937x->comp2_enable) {
443 snd_soc_component_upda
444
445
446 snd_soc_component_upda
447
448 if (wcd937x->comp1_ena
449 snd_soc_compon
450
451
452 snd_soc_compon
453
454
455 }
456
457 if (test_bit(HPH_COMP_
458 usleep_range(5
459 clear_bit(HPH_
460 }
461 } else {
462 snd_soc_component_upda
463
464
465 snd_soc_component_upda
466
467
468 }
469 snd_soc_component_update_bits(
470
471
472 break;
473 case SND_SOC_DAPM_POST_PMD:
474 snd_soc_component_update_bits(
475
476
477 break;
478 }
479
480 return 0;
481 }
482
483 static int wcd937x_codec_ear_dac_event(struct
484 struct
485 int eve
486 {
487 struct snd_soc_component *component =
488 struct wcd937x_priv *wcd937x = snd_soc
489 int hph_mode = wcd937x->hph_mode;
490
491 switch (event) {
492 case SND_SOC_DAPM_PRE_PMU:
493 wcd937x_rx_clk_enable(componen
494 snd_soc_component_update_bits(
495
496
497 snd_soc_component_update_bits(
498
499
500
501 if (hph_mode == CLS_AB_HIFI ||
502 snd_soc_component_upda
503
504
505 else if (hph_mode == CLS_H_LOH
506 snd_soc_component_upda
507
508
509 if (wcd937x->comp1_enable)
510 snd_soc_component_upda
511
512
513 usleep_range(5000, 5010);
514
515 snd_soc_component_update_bits(
516 wcd_clsh_ctrl_set_state(wcd937
517 WCD_CL
518 WCD_CL
519 hph_mo
520
521 break;
522 case SND_SOC_DAPM_POST_PMD:
523 if (hph_mode == CLS_AB_HIFI ||
524 hph_mode == CLS_H_HIFI)
525 snd_soc_component_upda
526
527
528 if (wcd937x->comp1_enable)
529 snd_soc_component_upda
530
531
532 break;
533 }
534
535 return 0;
536 }
537
538 static int wcd937x_codec_aux_dac_event(struct
539 struct
540 int eve
541 {
542 struct snd_soc_component *component =
543 struct wcd937x_priv *wcd937x = snd_soc
544 int hph_mode = wcd937x->hph_mode;
545
546 switch (event) {
547 case SND_SOC_DAPM_PRE_PMU:
548 wcd937x_rx_clk_enable(componen
549 snd_soc_component_update_bits(
550
551
552 snd_soc_component_update_bits(
553
554
555 snd_soc_component_update_bits(
556
557
558 wcd_clsh_ctrl_set_state(wcd937
559 WCD_CL
560 WCD_CL
561 hph_mo
562
563 break;
564 case SND_SOC_DAPM_POST_PMD:
565 snd_soc_component_update_bits(
566
567
568 break;
569 }
570
571 return 0;
572 }
573
574 static int wcd937x_codec_enable_hphr_pa(struct
575 struct
576 int ev
577 {
578 struct snd_soc_component *component =
579 struct wcd937x_priv *wcd937x = snd_soc
580 int hph_mode = wcd937x->hph_mode;
581
582 switch (event) {
583 case SND_SOC_DAPM_PRE_PMU:
584 wcd_clsh_ctrl_set_state(wcd937
585 WCD_CL
586 WCD_CL
587 hph_mo
588 snd_soc_component_update_bits(
589
590 usleep_range(100, 110);
591 set_bit(HPH_PA_DELAY, &wcd937x
592 snd_soc_component_update_bits(
593
594
595 break;
596 case SND_SOC_DAPM_POST_PMU:
597 if (test_bit(HPH_PA_DELAY, &wc
598 if (wcd937x->comp2_ena
599 usleep_range(7
600 else
601 usleep_range(2
602 clear_bit(HPH_PA_DELAY
603 }
604
605 snd_soc_component_update_bits(
606
607
608 if (hph_mode == CLS_AB || hph_
609 snd_soc_component_upda
610
611
612 enable_irq(wcd937x->hphr_pdm_w
613 break;
614 case SND_SOC_DAPM_PRE_PMD:
615 disable_irq_nosync(wcd937x->hp
616 set_bit(HPH_PA_DELAY, &wcd937x
617 wcd_mbhc_event_notify(wcd937x-
618 break;
619 case SND_SOC_DAPM_POST_PMD:
620 if (test_bit(HPH_PA_DELAY, &wc
621 if (wcd937x->comp2_ena
622 usleep_range(7
623 else
624 usleep_range(2
625 clear_bit(HPH_PA_DELAY
626 }
627
628 wcd_mbhc_event_notify(wcd937x-
629 snd_soc_component_update_bits(
630
631 snd_soc_component_update_bits(
632
633 wcd_clsh_ctrl_set_state(wcd937
634 WCD_CL
635 WCD_CL
636 hph_mo
637 break;
638 }
639
640 return 0;
641 }
642
643 static int wcd937x_codec_enable_hphl_pa(struct
644 struct
645 int ev
646 {
647 struct snd_soc_component *component =
648 struct wcd937x_priv *wcd937x = snd_soc
649 int hph_mode = wcd937x->hph_mode;
650
651 switch (event) {
652 case SND_SOC_DAPM_PRE_PMU:
653 wcd_clsh_ctrl_set_state(wcd937
654 WCD_CL
655 WCD_CL
656 hph_mo
657 snd_soc_component_update_bits(
658
659 usleep_range(100, 110);
660 set_bit(HPH_PA_DELAY, &wcd937x
661 snd_soc_component_update_bits(
662
663 break;
664 case SND_SOC_DAPM_POST_PMU:
665 if (test_bit(HPH_PA_DELAY, &wc
666 if (!wcd937x->comp1_en
667 usleep_range(2
668 else
669 usleep_range(7
670 clear_bit(HPH_PA_DELAY
671 }
672
673 snd_soc_component_update_bits(
674
675
676 if (hph_mode == CLS_AB || hph_
677 snd_soc_component_upda
678
679
680 enable_irq(wcd937x->hphl_pdm_w
681 break;
682 case SND_SOC_DAPM_PRE_PMD:
683 disable_irq_nosync(wcd937x->hp
684 set_bit(HPH_PA_DELAY, &wcd937x
685 wcd_mbhc_event_notify(wcd937x-
686 break;
687 case SND_SOC_DAPM_POST_PMD:
688 if (test_bit(HPH_PA_DELAY, &wc
689 if (!wcd937x->comp1_en
690 usleep_range(2
691 else
692 usleep_range(7
693 clear_bit(HPH_PA_DELAY
694 }
695
696 wcd_mbhc_event_notify(wcd937x-
697 snd_soc_component_update_bits(
698
699 snd_soc_component_update_bits(
700
701 wcd_clsh_ctrl_set_state(wcd937
702 WCD_CL
703 WCD_CL
704 hph_mo
705 break;
706 }
707
708 return 0;
709 }
710
711 static int wcd937x_codec_enable_aux_pa(struct
712 struct
713 int eve
714 {
715 struct snd_soc_component *component =
716 struct wcd937x_priv *wcd937x = snd_soc
717 int hph_mode = wcd937x->hph_mode;
718 u8 val;
719
720 switch (event) {
721 case SND_SOC_DAPM_PRE_PMU:
722 val = WCD937X_DIGITAL_PDM_WD_C
723 WCD937X_DIGITAL_PDM_WD_C
724 WCD937X_DIGITAL_PDM_WD_C
725 snd_soc_component_update_bits(
726
727
728
729 break;
730 case SND_SOC_DAPM_POST_PMU:
731 usleep_range(1000, 1010);
732 if (hph_mode == CLS_AB || hph_
733 snd_soc_component_upda
734
735
736 enable_irq(wcd937x->aux_pdm_wd
737 break;
738 case SND_SOC_DAPM_PRE_PMD:
739 disable_irq_nosync(wcd937x->au
740 break;
741 case SND_SOC_DAPM_POST_PMD:
742 usleep_range(2000, 2010);
743 wcd_clsh_ctrl_set_state(wcd937
744 WCD_CL
745 WCD_CL
746 hph_mo
747 snd_soc_component_update_bits(
748
749
750
751 break;
752 }
753
754 return 0;
755 }
756
757 static int wcd937x_codec_enable_ear_pa(struct
758 struct
759 int eve
760 {
761 struct snd_soc_component *component =
762 struct wcd937x_priv *wcd937x = snd_soc
763 int hph_mode = wcd937x->hph_mode;
764
765 switch (event) {
766 case SND_SOC_DAPM_PRE_PMU:
767 /* Enable watchdog interrupt f
768 wcd937x->ear_rx_path = snd_soc
769
770
771 if (wcd937x->ear_rx_path & EAR
772 snd_soc_component_upda
773
774
775 else
776 snd_soc_component_upda
777
778
779 if (!wcd937x->comp1_enable)
780 snd_soc_component_upda
781
782
783 break;
784 case SND_SOC_DAPM_POST_PMU:
785 usleep_range(6000, 6010);
786 if (hph_mode == CLS_AB || hph_
787 snd_soc_component_upda
788
789
790
791 if (wcd937x->ear_rx_path & EAR
792 enable_irq(wcd937x->au
793 else
794 enable_irq(wcd937x->hp
795 break;
796 case SND_SOC_DAPM_PRE_PMD:
797 if (wcd937x->ear_rx_path & EAR
798 disable_irq_nosync(wcd
799 else
800 disable_irq_nosync(wcd
801 break;
802 case SND_SOC_DAPM_POST_PMD:
803 if (!wcd937x->comp1_enable)
804 snd_soc_component_upda
805
806
807 usleep_range(7000, 7010);
808 wcd_clsh_ctrl_set_state(wcd937
809 WCD_CL
810 WCD_CL
811 hph_mo
812 snd_soc_component_update_bits(
813
814
815 if (wcd937x->ear_rx_path & EAR
816 snd_soc_component_upda
817
818
819 else
820 snd_soc_component_upda
821
822
823 break;
824 }
825
826 return 0;
827 }
828
829 static int wcd937x_enable_rx1(struct snd_soc_d
830 struct snd_kcont
831 int event)
832 {
833 struct snd_soc_component *component =
834
835 if (event == SND_SOC_DAPM_POST_PMD) {
836 wcd937x_rx_clk_disable(compone
837 snd_soc_component_update_bits(
838
839
840 }
841
842 return 0;
843 }
844
845 static int wcd937x_enable_rx2(struct snd_soc_d
846 struct snd_kcont
847 {
848 struct snd_soc_component *component =
849
850 if (event == SND_SOC_DAPM_POST_PMD) {
851 wcd937x_rx_clk_disable(compone
852 snd_soc_component_update_bits(
853
854
855 }
856
857 return 0;
858 }
859
860 static int wcd937x_enable_rx3(struct snd_soc_d
861 struct snd_kcont
862 int event)
863 {
864 struct snd_soc_component *component =
865
866 if (event == SND_SOC_DAPM_POST_PMD) {
867 usleep_range(6000, 6010);
868 wcd937x_rx_clk_disable(compone
869 snd_soc_component_update_bits(
870
871
872 }
873
874 return 0;
875 }
876
877 static int wcd937x_get_micb_vout_ctl_val(u32 m
878 {
879 if (micb_mv < 1000 || micb_mv > 2850)
880 pr_err("Unsupported micbias vo
881 return -EINVAL;
882 }
883
884 return (micb_mv - 1000) / 50;
885 }
886
887 static int wcd937x_tx_swr_ctrl(struct snd_soc_
888 struct snd_kcon
889 {
890 struct snd_soc_component *component =
891 struct wcd937x_priv *wcd937x = snd_soc
892 bool use_amic3 = snd_soc_component_rea
893
894 /* Enable BCS for Headset mic */
895 if (event == SND_SOC_DAPM_PRE_PMU && s
896 if (w->shift == 1 && !use_amic
897 set_bit(AMIC2_BCS_ENAB
898
899 return 0;
900 }
901
902 static int wcd937x_codec_enable_adc(struct snd
903 struct snd
904 {
905 struct snd_soc_component *component =
906 struct wcd937x_priv *wcd937x = snd_soc
907
908 switch (event) {
909 case SND_SOC_DAPM_PRE_PMU:
910 atomic_inc(&wcd937x->ana_clk_c
911 snd_soc_component_update_bits(
912
913 snd_soc_component_update_bits(
914
915 snd_soc_component_update_bits(
916
917 break;
918 case SND_SOC_DAPM_POST_PMD:
919 if (w->shift == 1 && test_bit(
920 clear_bit(AMIC2_BCS_EN
921
922 snd_soc_component_update_bits(
923
924 break;
925 }
926
927 return 0;
928 }
929
930 static int wcd937x_enable_req(struct snd_soc_d
931 struct snd_kcont
932 {
933 struct snd_soc_component *component =
934 struct wcd937x_priv *wcd937x = snd_soc
935
936 switch (event) {
937 case SND_SOC_DAPM_PRE_PMU:
938 snd_soc_component_update_bits(
939
940 snd_soc_component_update_bits(
941
942 snd_soc_component_update_bits(
943
944 snd_soc_component_update_bits(
945
946 snd_soc_component_update_bits(
947
948 snd_soc_component_update_bits(
949
950 snd_soc_component_update_bits(
951
952 snd_soc_component_update_bits(
953
954 snd_soc_component_update_bits(
955
956 break;
957 case SND_SOC_DAPM_POST_PMD:
958 snd_soc_component_update_bits(
959
960 snd_soc_component_update_bits(
961
962 snd_soc_component_update_bits(
963
964 snd_soc_component_update_bits(
965
966
967 atomic_dec(&wcd937x->ana_clk_c
968 if (atomic_read(&wcd937x->ana_
969 snd_soc_component_upda
970
971
972 atomic_set(&wcd937x->a
973 }
974
975 snd_soc_component_update_bits(
976
977
978 break;
979 }
980
981 return 0;
982 }
983
984 static int wcd937x_codec_enable_dmic(struct sn
985 struct sn
986 int event
987 {
988 struct snd_soc_component *component =
989 u16 dmic_clk_reg;
990
991 switch (w->shift) {
992 case 0:
993 case 1:
994 dmic_clk_reg = WCD937X_DIGITAL
995 break;
996 case 2:
997 case 3:
998 dmic_clk_reg = WCD937X_DIGITAL
999 break;
1000 case 4:
1001 case 5:
1002 dmic_clk_reg = WCD937X_DIGITA
1003 break;
1004 default:
1005 dev_err(component->dev, "Inva
1006 return -EINVAL;
1007 }
1008
1009 switch (event) {
1010 case SND_SOC_DAPM_PRE_PMU:
1011 snd_soc_component_update_bits
1012
1013
1014 snd_soc_component_update_bits
1015
1016 snd_soc_component_update_bits
1017
1018 snd_soc_component_update_bits
1019
1020 break;
1021 }
1022
1023 return 0;
1024 }
1025
1026 static int wcd937x_micbias_control(struct snd
1027 int micb_n
1028 {
1029 struct wcd937x_priv *wcd937x = snd_so
1030 int micb_index = micb_num - 1;
1031 u16 micb_reg;
1032
1033 if (micb_index < 0 || (micb_index > W
1034 dev_err(component->dev, "Inva
1035 return -EINVAL;
1036 }
1037 switch (micb_num) {
1038 case MIC_BIAS_1:
1039 micb_reg = WCD937X_ANA_MICB1;
1040 break;
1041 case MIC_BIAS_2:
1042 micb_reg = WCD937X_ANA_MICB2;
1043 break;
1044 case MIC_BIAS_3:
1045 micb_reg = WCD937X_ANA_MICB3;
1046 break;
1047 default:
1048 dev_err(component->dev, "Inva
1049 return -EINVAL;
1050 }
1051
1052 mutex_lock(&wcd937x->micb_lock);
1053 switch (req) {
1054 case MICB_PULLUP_ENABLE:
1055 wcd937x->pullup_ref[micb_inde
1056 if (wcd937x->pullup_ref[micb_
1057 wcd937x->micb_ref[micb_in
1058 snd_soc_component_upd
1059
1060 break;
1061 case MICB_PULLUP_DISABLE:
1062 if (wcd937x->pullup_ref[micb_
1063 wcd937x->pullup_ref[m
1064 if (wcd937x->pullup_ref[micb_
1065 wcd937x->micb_ref[micb_in
1066 snd_soc_component_upd
1067
1068 break;
1069 case MICB_ENABLE:
1070 wcd937x->micb_ref[micb_index]
1071 atomic_inc(&wcd937x->ana_clk_
1072 if (wcd937x->micb_ref[micb_in
1073 snd_soc_component_upd
1074
1075
1076 snd_soc_component_upd
1077
1078
1079 snd_soc_component_upd
1080
1081
1082 snd_soc_component_upd
1083
1084
1085 snd_soc_component_upd
1086
1087
1088 snd_soc_component_upd
1089
1090
1091 if (micb_num == MIC_B
1092 wcd_mbhc_even
1093
1094
1095 if (micb_num == MIC_B
1096 wcd_mbhc_even
1097
1098 }
1099 break;
1100 case MICB_DISABLE:
1101 atomic_dec(&wcd937x->ana_clk_
1102 if (wcd937x->micb_ref[micb_in
1103 wcd937x->micb_ref[mic
1104 if (wcd937x->micb_ref[micb_in
1105 wcd937x->pullup_ref[micb_
1106 snd_soc_component_upd
1107
1108 else if (wcd937x->micb_ref[mi
1109 wcd937x->pullup_ref[
1110 if (micb_num == MIC_B
1111 wcd_mbhc_even
1112
1113
1114 snd_soc_component_upd
1115
1116 if (micb_num == MIC_B
1117 wcd_mbhc_even
1118
1119 }
1120
1121 if (is_dapm && micb_num == MI
1122 wcd_mbhc_event_notify
1123
1124 if (atomic_read(&wcd937x->ana
1125 snd_soc_component_upd
1126
1127
1128 atomic_set(&wcd937x->
1129 }
1130 break;
1131 }
1132 mutex_unlock(&wcd937x->micb_lock);
1133
1134 return 0;
1135 }
1136
1137 static int __wcd937x_codec_enable_micbias(str
1138 int
1139 {
1140 struct snd_soc_component *component =
1141 int micb_num = w->shift;
1142
1143 switch (event) {
1144 case SND_SOC_DAPM_PRE_PMU:
1145 wcd937x_micbias_control(compo
1146 MICB_
1147 break;
1148 case SND_SOC_DAPM_POST_PMU:
1149 usleep_range(1000, 1100);
1150 break;
1151 case SND_SOC_DAPM_POST_PMD:
1152 wcd937x_micbias_control(compo
1153 MICB_
1154 break;
1155 }
1156
1157 return 0;
1158 }
1159
1160 static int wcd937x_codec_enable_micbias(struc
1161 struc
1162 int e
1163 {
1164 return __wcd937x_codec_enable_micbias
1165 }
1166
1167 static int __wcd937x_codec_enable_micbias_pul
1168
1169 {
1170 struct snd_soc_component *component =
1171 int micb_num = w->shift;
1172
1173 switch (event) {
1174 case SND_SOC_DAPM_PRE_PMU:
1175 wcd937x_micbias_control(compo
1176 break;
1177 case SND_SOC_DAPM_POST_PMU:
1178 usleep_range(1000, 1100);
1179 break;
1180 case SND_SOC_DAPM_POST_PMD:
1181 wcd937x_micbias_control(compo
1182 break;
1183 }
1184
1185 return 0;
1186 }
1187
1188 static int wcd937x_codec_enable_micbias_pullu
1189
1190
1191 {
1192 return __wcd937x_codec_enable_micbias
1193 }
1194
1195 static int wcd937x_connect_port(struct wcd937
1196 {
1197 struct sdw_port_config *port_config =
1198 const struct wcd937x_sdw_ch_info *ch_
1199 u8 port_num = ch_info->port_num;
1200 u8 ch_mask = ch_info->ch_mask;
1201
1202 port_config->num = port_num;
1203
1204 if (enable)
1205 port_config->ch_mask |= ch_ma
1206 else
1207 port_config->ch_mask &= ~ch_m
1208
1209 return 0;
1210 }
1211
1212 static int wcd937x_rx_hph_mode_get(struct snd
1213 struct snd
1214 {
1215 struct snd_soc_component *component =
1216 struct wcd937x_priv *wcd937x = snd_so
1217
1218 ucontrol->value.integer.value[0] = wc
1219 return 0;
1220 }
1221
1222 static int wcd937x_rx_hph_mode_put(struct snd
1223 struct snd
1224 {
1225 struct snd_soc_component *component =
1226 snd_soc_kcont
1227 struct wcd937x_priv *wcd937x = snd_so
1228 u32 mode_val;
1229
1230 mode_val = ucontrol->value.enumerated
1231
1232 if (!mode_val)
1233 mode_val = CLS_AB;
1234
1235 if (mode_val == wcd937x->hph_mode)
1236 return 0;
1237
1238 switch (mode_val) {
1239 case CLS_H_NORMAL:
1240 case CLS_H_HIFI:
1241 case CLS_H_LP:
1242 case CLS_AB:
1243 case CLS_H_LOHIFI:
1244 case CLS_H_ULP:
1245 case CLS_AB_LP:
1246 case CLS_AB_HIFI:
1247 wcd937x->hph_mode = mode_val;
1248 return 1;
1249 }
1250
1251 dev_dbg(component->dev, "%s: Invalid
1252 return -EINVAL;
1253 }
1254
1255 static int wcd937x_get_compander(struct snd_k
1256 struct snd_c
1257 {
1258 struct snd_soc_component *component =
1259 struct wcd937x_priv *wcd937x = snd_so
1260 struct soc_mixer_control *mc;
1261 bool hphr;
1262
1263 mc = (struct soc_mixer_control *)(kco
1264 hphr = mc->shift;
1265
1266 ucontrol->value.integer.value[0] = hp
1267
1268 return 0;
1269 }
1270
1271 static int wcd937x_set_compander(struct snd_k
1272 struct snd_c
1273 {
1274 struct snd_soc_component *component =
1275 struct wcd937x_priv *wcd937x = snd_so
1276 struct wcd937x_sdw_priv *wcd = wcd937
1277 int value = ucontrol->value.integer.v
1278 struct soc_mixer_control *mc;
1279 int portidx;
1280 bool hphr;
1281
1282 mc = (struct soc_mixer_control *)(kco
1283 hphr = mc->shift;
1284
1285 if (hphr) {
1286 if (value == wcd937x->comp2_e
1287 return 0;
1288
1289 wcd937x->comp2_enable = value
1290 } else {
1291 if (value == wcd937x->comp1_e
1292 return 0;
1293
1294 wcd937x->comp1_enable = value
1295 }
1296
1297 portidx = wcd->ch_info[mc->reg].port_
1298
1299 if (value)
1300 wcd937x_connect_port(wcd, por
1301 else
1302 wcd937x_connect_port(wcd, por
1303
1304 return 1;
1305 }
1306
1307 static int wcd937x_get_swr_port(struct snd_kc
1308 struct snd_ct
1309 {
1310 struct soc_mixer_control *mixer = (st
1311 struct snd_soc_component *comp = snd_
1312 struct wcd937x_priv *wcd937x = snd_so
1313 struct wcd937x_sdw_priv *wcd;
1314 int dai_id = mixer->shift;
1315 int ch_idx = mixer->reg;
1316 int portidx;
1317
1318 wcd = wcd937x->sdw_priv[dai_id];
1319 portidx = wcd->ch_info[ch_idx].port_n
1320
1321 ucontrol->value.integer.value[0] = wc
1322
1323 return 0;
1324 }
1325
1326 static int wcd937x_set_swr_port(struct snd_kc
1327 struct snd_ct
1328 {
1329 struct soc_mixer_control *mixer = (st
1330 struct snd_soc_component *comp = snd_
1331 struct wcd937x_priv *wcd937x = snd_so
1332 struct wcd937x_sdw_priv *wcd;
1333 int dai_id = mixer->shift;
1334 int ch_idx = mixer->reg;
1335 int portidx;
1336 bool enable;
1337
1338 wcd = wcd937x->sdw_priv[dai_id];
1339
1340 portidx = wcd->ch_info[ch_idx].port_n
1341
1342 enable = ucontrol->value.integer.valu
1343
1344 if (enable == wcd->port_enable[portid
1345 wcd937x_connect_port(wcd, por
1346 return 0;
1347 }
1348
1349 wcd->port_enable[portidx] = enable;
1350 wcd937x_connect_port(wcd, portidx, ch
1351
1352 return 1;
1353 }
1354
1355 static const char * const rx_hph_mode_mux_tex
1356 "CLS_H_NORMAL", "CLS_H_INVALID", "CLS
1357 "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_AB_
1358 };
1359
1360 static const struct soc_enum rx_hph_mode_mux_
1361 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph
1362
1363 /* MBHC related */
1364 static void wcd937x_mbhc_clk_setup(struct snd
1365 bool enabl
1366 {
1367 snd_soc_component_write_field(compone
1368 WCD937X
1369 }
1370
1371 static void wcd937x_mbhc_mbhc_bias_control(st
1372 bo
1373 {
1374 snd_soc_component_write_field(compone
1375 WCD937X
1376 }
1377
1378 static void wcd937x_mbhc_program_btn_thr(stru
1379 int
1380 int
1381 {
1382 int i, vth;
1383
1384 if (num_btn > WCD_MBHC_DEF_BUTTONS) {
1385 dev_err(component->dev, "%s:
1386 __func__, num_btn);
1387 return;
1388 }
1389
1390 for (i = 0; i < num_btn; i++) {
1391 vth = ((btn_high[i] * 2) / 25
1392 snd_soc_component_write_field
1393
1394 }
1395 }
1396
1397 static bool wcd937x_mbhc_micb_en_status(struc
1398 {
1399 u8 val;
1400
1401 if (micb_num == MIC_BIAS_2) {
1402 val = snd_soc_component_read_
1403
1404
1405 if (val == WCD937X_MICB_ENABL
1406 return true;
1407 }
1408 return false;
1409 }
1410
1411 static void wcd937x_mbhc_hph_l_pull_up_contro
1412
1413 {
1414 /* Default pull up current to 2uA */
1415 if (pull_up_cur > HS_PULLUP_I_OFF ||
1416 pull_up_cur = HS_PULLUP_I_2P0
1417
1418 snd_soc_component_write_field(compone
1419 WCD937X
1420 WCD937X
1421 }
1422
1423 static int wcd937x_mbhc_request_micbias(struc
1424 int m
1425 {
1426 return wcd937x_micbias_control(compon
1427 }
1428
1429 static void wcd937x_mbhc_micb_ramp_control(st
1430 bo
1431 {
1432 if (enable) {
1433 snd_soc_component_write_field
1434
1435 snd_soc_component_write_field
1436
1437 } else {
1438 snd_soc_component_write_field
1439
1440 snd_soc_component_write_field
1441
1442 }
1443 }
1444
1445 static int wcd937x_mbhc_micb_adjust_voltage(s
1446 i
1447 {
1448 struct wcd937x_priv *wcd937x = snd_so
1449 int cur_vout_ctl, req_vout_ctl, micb_
1450
1451 switch (micb_num) {
1452 case MIC_BIAS_1:
1453 micb_reg = WCD937X_ANA_MICB1;
1454 break;
1455 case MIC_BIAS_2:
1456 micb_reg = WCD937X_ANA_MICB2;
1457 break;
1458 case MIC_BIAS_3:
1459 micb_reg = WCD937X_ANA_MICB3;
1460 break;
1461 default:
1462 return -EINVAL;
1463 }
1464 mutex_lock(&wcd937x->micb_lock);
1465 /*
1466 * If requested micbias voltage is sa
1467 * voltage, then just return. Otherwi
1468 * per requested value. If micbias is
1469 * to avoid slow micbias ramp-up or d
1470 * momentarily, change the micbias va
1471 * micbias.
1472 */
1473 micb_en = snd_soc_component_read_fiel
1474
1475 cur_vout_ctl = snd_soc_component_read
1476
1477
1478 req_vout_ctl = wcd937x_get_micb_vout_
1479 if (req_vout_ctl < 0) {
1480 ret = -EINVAL;
1481 goto exit;
1482 }
1483
1484 if (cur_vout_ctl == req_vout_ctl) {
1485 ret = 0;
1486 goto exit;
1487 }
1488
1489 if (micb_en == WCD937X_MICB_ENABLE)
1490 snd_soc_component_write_field
1491
1492
1493
1494 snd_soc_component_write_field(compone
1495 WCD937X
1496 req_vou
1497
1498 if (micb_en == WCD937X_MICB_ENABLE) {
1499 snd_soc_component_write_field
1500
1501
1502 /*
1503 * Add 2ms delay as per HW re
1504 * micbias
1505 */
1506 usleep_range(2000, 2100);
1507 }
1508 exit:
1509 mutex_unlock(&wcd937x->micb_lock);
1510 return ret;
1511 }
1512
1513 static int wcd937x_mbhc_micb_ctrl_threshold_m
1514
1515 {
1516 struct wcd937x_priv *wcd937x = snd_so
1517 int micb_mv;
1518
1519 if (micb_num != MIC_BIAS_2)
1520 return -EINVAL;
1521 /*
1522 * If device tree micbias level is al
1523 * voltage needed to detect threshold
1524 * not change the micbias, just retur
1525 */
1526 if (wcd937x->micb2_mv >= WCD_MBHC_THR
1527 return 0;
1528
1529 micb_mv = req_en ? WCD_MBHC_THR_HS_MI
1530
1531 return wcd937x_mbhc_micb_adjust_volta
1532 }
1533
1534 static void wcd937x_mbhc_get_result_params(st
1535 s1
1536 in
1537 {
1538 struct wcd937x_priv *wcd937x = snd_so
1539 int i;
1540 int val, val1;
1541 s16 c1;
1542 s32 x1, d1;
1543 s32 denom;
1544 static const int minCode_param[] = {
1545 3277, 1639, 820, 410, 205, 10
1546 };
1547
1548 regmap_update_bits(wcd937x->regmap, W
1549 for (i = 0; i < WCD937X_ZDET_NUM_MEAS
1550 regmap_read(wcd937x->regmap,
1551 if (val & 0x80)
1552 break;
1553 }
1554 val = val << 0x8;
1555 regmap_read(wcd937x->regmap, WCD937X_
1556 val |= val1;
1557 regmap_update_bits(wcd937x->regmap, W
1558 x1 = WCD937X_MBHC_GET_X1(val);
1559 c1 = WCD937X_MBHC_GET_C1(val);
1560 /* If ramp is not complete, give addi
1561 if (c1 < 2 && x1)
1562 usleep_range(5000, 5050);
1563
1564 if (!c1 || !x1) {
1565 dev_err(component->dev, "Impe
1566 c1, x1);
1567 goto ramp_down;
1568 }
1569 d1 = d1_a[c1];
1570 denom = (x1 * d1) - (1 << (14 - noff)
1571 if (denom > 0)
1572 *zdet = (WCD937X_MBHC_ZDET_CO
1573 else if (x1 < minCode_param[noff])
1574 *zdet = WCD937X_ZDET_FLOATING
1575
1576 dev_err(component->dev, "%s: d1=%d, c
1577 __func__, d1, c1, x1, *zdet);
1578 ramp_down:
1579 i = 0;
1580 while (x1) {
1581 regmap_read(wcd937x->regmap,
1582 WCD937X_ANA_MBHC_
1583 regmap_read(wcd937x->regmap,
1584 WCD937X_ANA_MBHC_
1585 val = val << 0x08;
1586 val |= val1;
1587 x1 = WCD937X_MBHC_GET_X1(val)
1588 i++;
1589 if (i == WCD937X_ZDET_NUM_MEA
1590 break;
1591 }
1592 }
1593
1594 static void wcd937x_mbhc_zdet_ramp(struct snd
1595 struct wcd
1596 s32 *zl, s
1597 {
1598 struct wcd937x_priv *wcd937x = snd_so
1599 s32 zdet = 0;
1600
1601 snd_soc_component_write_field(compone
1602 WCD937X
1603 snd_soc_component_update_bits(compone
1604 WCD937X
1605 snd_soc_component_update_bits(compone
1606 WCD937X
1607 snd_soc_component_update_bits(compone
1608 WCD937X
1609 snd_soc_component_write_field(compone
1610 WCD937X
1611 snd_soc_component_update_bits(compone
1612 0x0F, z
1613
1614 if (!zl)
1615 goto z_right;
1616 /* Start impedance measurement for HP
1617 regmap_update_bits(wcd937x->regmap,
1618 WCD937X_ANA_MBHC_Z
1619 wcd937x_mbhc_get_result_params(compon
1620 regmap_update_bits(wcd937x->regmap,
1621 WCD937X_ANA_MBHC_Z
1622
1623 *zl = zdet;
1624
1625 z_right:
1626 if (!zr)
1627 return;
1628 /* Start impedance measurement for HP
1629 regmap_update_bits(wcd937x->regmap,
1630 WCD937X_ANA_MBHC_Z
1631 wcd937x_mbhc_get_result_params(compon
1632 regmap_update_bits(wcd937x->regmap,
1633 WCD937X_ANA_MBHC_Z
1634
1635 *zr = zdet;
1636 }
1637
1638 static void wcd937x_wcd_mbhc_qfuse_cal(struct
1639 s32 *z
1640 {
1641 s16 q1;
1642 int q1_cal;
1643
1644 if (*z_val < (WCD937X_ZDET_VAL_400 /
1645 q1 = snd_soc_component_read(c
1646 W
1647 else
1648 q1 = snd_soc_component_read(c
1649 W
1650 if (q1 & 0x80)
1651 q1_cal = (10000 - ((q1 & 0x7F
1652 else
1653 q1_cal = (10000 + (q1 * 25));
1654 if (q1_cal > 0)
1655 *z_val = ((*z_val) * 10000) /
1656 }
1657
1658 static void wcd937x_wcd_mbhc_calc_impedance(s
1659 u
1660 {
1661 struct wcd937x_priv *wcd937x = snd_so
1662 s16 reg0, reg1, reg2, reg3, reg4;
1663 s32 z1l, z1r, z1ls;
1664 int zMono, z_diff1, z_diff2;
1665 bool is_fsm_disable = false;
1666 struct wcd937x_mbhc_zdet_param zdet_p
1667 {4, 0, 4, 0x08, 0x14, 0x18},
1668 {2, 0, 3, 0x18, 0x7C, 0x90},
1669 {1, 4, 5, 0x18, 0x7C, 0x90},
1670 {1, 6, 7, 0x18, 0x7C, 0x90},
1671 };
1672 struct wcd937x_mbhc_zdet_param *zdet_
1673 s16 d1_a[][4] = {
1674 {0, 30, 90, 30},
1675 {0, 30, 30, 5},
1676 {0, 30, 30, 5},
1677 {0, 30, 30, 5},
1678 };
1679 s16 *d1 = NULL;
1680
1681 reg0 = snd_soc_component_read(compone
1682 reg1 = snd_soc_component_read(compone
1683 reg2 = snd_soc_component_read(compone
1684 reg3 = snd_soc_component_read(compone
1685 reg4 = snd_soc_component_read(compone
1686
1687 if (snd_soc_component_read(component,
1688 is_fsm_disable = true;
1689 regmap_update_bits(wcd937x->r
1690 WCD937X_AN
1691 }
1692
1693 /* For NO-jack, disable L_DET_EN befo
1694 if (wcd937x->mbhc_cfg.hphl_swh)
1695 regmap_update_bits(wcd937x->r
1696 WCD937X_AN
1697
1698 /* Turn off 100k pull down on HPHL */
1699 regmap_update_bits(wcd937x->regmap,
1700 WCD937X_ANA_MBHC_M
1701
1702 /* Disable surge protection before im
1703 * This is done to give correct value
1704 */
1705 regmap_update_bits(wcd937x->regmap,
1706 WCD937X_HPH_SURGE_
1707 /* 1ms delay needed after disable sur
1708 usleep_range(1000, 1010);
1709
1710 /* First get impedance on Left */
1711 d1 = d1_a[1];
1712 zdet_param_ptr = &zdet_param[1];
1713 wcd937x_mbhc_zdet_ramp(component, zde
1714
1715 if (!WCD937X_MBHC_IS_SECOND_RAMP_REQU
1716 goto left_ch_impedance;
1717
1718 /* Second ramp for left ch */
1719 if (z1l < WCD937X_ZDET_VAL_32) {
1720 zdet_param_ptr = &zdet_param[
1721 d1 = d1_a[0];
1722 } else if ((z1l > WCD937X_ZDET_VAL_40
1723 (z1l <= WCD937X_ZDET_VAL_12
1724 zdet_param_ptr = &zdet_param[
1725 d1 = d1_a[2];
1726 } else if (z1l > WCD937X_ZDET_VAL_120
1727 zdet_param_ptr = &zdet_param[
1728 d1 = d1_a[3];
1729 }
1730 wcd937x_mbhc_zdet_ramp(component, zde
1731
1732 left_ch_impedance:
1733 if (z1l == WCD937X_ZDET_FLOATING_IMPE
1734 z1l > WCD937X_ZDET_VAL_100K) {
1735 *zl = WCD937X_ZDET_FLOATING_I
1736 zdet_param_ptr = &zdet_param[
1737 d1 = d1_a[1];
1738 } else {
1739 *zl = z1l / 1000;
1740 wcd937x_wcd_mbhc_qfuse_cal(co
1741 }
1742
1743 /* Start of right impedance ramp and
1744 wcd937x_mbhc_zdet_ramp(component, zde
1745 if (WCD937X_MBHC_IS_SECOND_RAMP_REQUI
1746 if ((z1r > WCD937X_ZDET_VAL_1
1747 zdet_param_ptr->noff ==
1748 ((*zl) != WCD937X_ZDET_F
1749 goto right_ch_impedan
1750 /* Second ramp for right ch *
1751 if (z1r < WCD937X_ZDET_VAL_32
1752 zdet_param_ptr = &zde
1753 d1 = d1_a[0];
1754 } else if ((z1r > WCD937X_ZDE
1755 (z1r <= WCD937X_ZDET_
1756 zdet_param_ptr = &zde
1757 d1 = d1_a[2];
1758 } else if (z1r > WCD937X_ZDET
1759 zdet_param_ptr = &zde
1760 d1 = d1_a[3];
1761 }
1762 wcd937x_mbhc_zdet_ramp(compon
1763 }
1764 right_ch_impedance:
1765 if (z1r == WCD937X_ZDET_FLOATING_IMPE
1766 z1r > WCD937X_ZDET_VAL_100K) {
1767 *zr = WCD937X_ZDET_FLOATING_I
1768 } else {
1769 *zr = z1r / 1000;
1770 wcd937x_wcd_mbhc_qfuse_cal(co
1771 }
1772
1773 /* Mono/stereo detection */
1774 if ((*zl == WCD937X_ZDET_FLOATING_IMP
1775 (*zr == WCD937X_ZDET_FLOATING_IMP
1776 dev_err(component->dev,
1777 "%s: plug type is inv
1778 __func__);
1779 goto zdet_complete;
1780 }
1781 if ((*zl == WCD937X_ZDET_FLOATING_IMP
1782 (*zr == WCD937X_ZDET_FLOATING_IMP
1783 ((*zl < WCD_MONO_HS_MIN_THR) && (
1784 ((*zl > WCD_MONO_HS_MIN_THR) && (
1785 wcd_mbhc_set_hph_type(wcd937x
1786 goto zdet_complete;
1787 }
1788 snd_soc_component_write_field(compone
1789 WCD937X
1790 snd_soc_component_write_field(compone
1791 WCD937X
1792 if (*zl < (WCD937X_ZDET_VAL_32 / 1000
1793 wcd937x_mbhc_zdet_ramp(compon
1794 else
1795 wcd937x_mbhc_zdet_ramp(compon
1796 snd_soc_component_write_field(compone
1797 WCD937X
1798 snd_soc_component_write_field(compone
1799 WCD937X
1800 z1ls /= 1000;
1801 wcd937x_wcd_mbhc_qfuse_cal(component,
1802 /* Parallel of left Z and 9 ohm pull
1803 zMono = ((*zl) * 9) / ((*zl) + 9);
1804 z_diff1 = (z1ls > zMono) ? (z1ls - zM
1805 z_diff2 = ((*zl) > z1ls) ? ((*zl) - z
1806 if ((z_diff1 * (*zl + z1ls)) > (z_dif
1807 wcd_mbhc_set_hph_type(wcd937x
1808 else
1809 wcd_mbhc_set_hph_type(wcd937x
1810
1811 /* Enable surge protection again afte
1812 regmap_update_bits(wcd937x->regmap,
1813 WCD937X_HPH_SURGE_
1814 zdet_complete:
1815 snd_soc_component_write(component, WC
1816 snd_soc_component_write(component, WC
1817 snd_soc_component_write(component, WC
1818 /* Turn on 100k pull down on HPHL */
1819 regmap_update_bits(wcd937x->regmap,
1820 WCD937X_ANA_MBHC_M
1821
1822 /* For NO-jack, re-enable L_DET_EN af
1823 if (wcd937x->mbhc_cfg.hphl_swh)
1824 regmap_update_bits(wcd937x->r
1825 WCD937X_AN
1826
1827 snd_soc_component_write(component, WC
1828 snd_soc_component_write(component, WC
1829 if (is_fsm_disable)
1830 regmap_update_bits(wcd937x->r
1831 WCD937X_AN
1832 }
1833
1834 static void wcd937x_mbhc_gnd_det_ctrl(struct
1835 bool en
1836 {
1837 if (enable) {
1838 snd_soc_component_write_field
1839
1840 snd_soc_component_write_field
1841
1842 } else {
1843 snd_soc_component_write_field
1844
1845 snd_soc_component_write_field
1846
1847 }
1848 }
1849
1850 static void wcd937x_mbhc_hph_pull_down_ctrl(s
1851 b
1852 {
1853 snd_soc_component_write_field(compone
1854 WCD937X
1855 snd_soc_component_write_field(compone
1856 WCD937X
1857 }
1858
1859 static void wcd937x_mbhc_moisture_config(stru
1860 {
1861 struct wcd937x_priv *wcd937x = snd_so
1862
1863 if (wcd937x->mbhc_cfg.moist_rref == R
1864 snd_soc_component_write_field
1865
1866 return;
1867 }
1868
1869 /* Do not enable moisture detection i
1870 if (!wcd937x->mbhc_cfg.hphl_swh) {
1871 dev_err(component->dev, "%s:
1872 __func__);
1873 snd_soc_component_write_field
1874
1875 return;
1876 }
1877
1878 snd_soc_component_write_field(compone
1879 WCD937X
1880 }
1881
1882 static void wcd937x_mbhc_moisture_detect_en(s
1883 {
1884 struct wcd937x_priv *wcd937x = snd_so
1885
1886 if (enable)
1887 snd_soc_component_write_field
1888
1889 else
1890 snd_soc_component_write_field
1891
1892 }
1893
1894 static bool wcd937x_mbhc_get_moisture_status(
1895 {
1896 struct wcd937x_priv *wcd937x = snd_so
1897 bool ret = false;
1898
1899 if (wcd937x->mbhc_cfg.moist_rref == R
1900 snd_soc_component_write_field
1901
1902 goto done;
1903 }
1904
1905 /* Do not enable moisture detection i
1906 if (!wcd937x->mbhc_cfg.hphl_swh) {
1907 dev_err(component->dev, "%s:
1908 __func__);
1909 snd_soc_component_write_field
1910
1911 goto done;
1912 }
1913
1914 /*
1915 * If moisture_en is already enabled,
1916 * detection.
1917 */
1918 if (snd_soc_component_read_field(comp
1919 goto done;
1920
1921 wcd937x_mbhc_moisture_detect_en(compo
1922 /* Read moisture comparator status */
1923 ret = ((snd_soc_component_read(compon
1924 & 0x20
1925 done:
1926 return ret;
1927 }
1928
1929 static void wcd937x_mbhc_moisture_polling_ctr
1930
1931 {
1932 snd_soc_component_write_field(compone
1933 WCD937X
1934 WCD937X
1935 }
1936
1937 static const struct wcd_mbhc_cb mbhc_cb = {
1938 .clk_setup = wcd937x_mbhc_clk_setup,
1939 .mbhc_bias = wcd937x_mbhc_mbhc_bias_c
1940 .set_btn_thr = wcd937x_mbhc_program_b
1941 .micbias_enable_status = wcd937x_mbhc
1942 .hph_pull_up_control_v2 = wcd937x_mbh
1943 .mbhc_micbias_control = wcd937x_mbhc_
1944 .mbhc_micb_ramp_control = wcd937x_mbh
1945 .mbhc_micb_ctrl_thr_mic = wcd937x_mbh
1946 .compute_impedance = wcd937x_wcd_mbhc
1947 .mbhc_gnd_det_ctrl = wcd937x_mbhc_gnd
1948 .hph_pull_down_ctrl = wcd937x_mbhc_hp
1949 .mbhc_moisture_config = wcd937x_mbhc_
1950 .mbhc_get_moisture_status = wcd937x_m
1951 .mbhc_moisture_polling_ctrl = wcd937x
1952 .mbhc_moisture_detect_en = wcd937x_mb
1953 };
1954
1955 static int wcd937x_get_hph_type(struct snd_kc
1956 struct snd_ct
1957 {
1958 struct snd_soc_component *component =
1959 struct wcd937x_priv *wcd937x = snd_so
1960
1961 ucontrol->value.integer.value[0] = wc
1962
1963 return 0;
1964 }
1965
1966 static int wcd937x_hph_impedance_get(struct s
1967 struct s
1968 {
1969 u32 zl, zr;
1970 bool hphr;
1971 struct soc_mixer_control *mc;
1972 struct snd_soc_component *component =
1973 snd_s
1974 struct wcd937x_priv *wcd937x = snd_so
1975
1976 mc = (struct soc_mixer_control *)(kco
1977 hphr = mc->shift;
1978 wcd_mbhc_get_impedance(wcd937x->wcd_m
1979 ucontrol->value.integer.value[0] = hp
1980
1981 return 0;
1982 }
1983
1984 static const struct snd_kcontrol_new hph_type
1985 SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_
1986 wcd937x_get_hph_type,
1987 };
1988
1989 static const struct snd_kcontrol_new impedanc
1990 SOC_SINGLE_EXT("HPHL Impedance", 0, 0
1991 wcd937x_hph_impedance_
1992 SOC_SINGLE_EXT("HPHR Impedance", 0, 1
1993 wcd937x_hph_impedance_
1994 };
1995
1996 static int wcd937x_mbhc_init(struct snd_soc_c
1997 {
1998 struct wcd937x_priv *wcd937x = snd_so
1999 struct wcd_mbhc_intr *intr_ids = &wcd
2000
2001 intr_ids->mbhc_sw_intr = regmap_irq_g
2002
2003 intr_ids->mbhc_btn_press_intr = regma
2004
2005 intr_ids->mbhc_btn_release_intr = reg
2006
2007 intr_ids->mbhc_hs_ins_intr = regmap_i
2008
2009 intr_ids->mbhc_hs_rem_intr = regmap_i
2010
2011 intr_ids->hph_left_ocp = regmap_irq_g
2012
2013 intr_ids->hph_right_ocp = regmap_irq_
2014
2015
2016 wcd937x->wcd_mbhc = wcd_mbhc_init(com
2017 if (IS_ERR(wcd937x->wcd_mbhc))
2018 return PTR_ERR(wcd937x->wcd_m
2019
2020 snd_soc_add_component_controls(compon
2021 ARRAY_
2022 snd_soc_add_component_controls(compon
2023 ARRAY_
2024
2025 return 0;
2026 }
2027
2028 static void wcd937x_mbhc_deinit(struct snd_so
2029 {
2030 struct wcd937x_priv *wcd937x = snd_so
2031
2032 wcd_mbhc_deinit(wcd937x->wcd_mbhc);
2033 }
2034
2035 /* END MBHC */
2036
2037 static const struct snd_kcontrol_new wcd937x_
2038 SOC_SINGLE_TLV("EAR_PA Volume", WCD93
2039 2, 0x10, 0, ear_pa_gai
2040 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mo
2041 wcd937x_rx_hph_mode_get,
2042
2043 SOC_SINGLE_EXT("HPHL_COMP Switch", SN
2044 wcd937x_get_compander,
2045 SOC_SINGLE_EXT("HPHR_COMP Switch", SN
2046 wcd937x_get_compander,
2047
2048 SOC_SINGLE_TLV("HPHL Volume", WCD937X
2049 SOC_SINGLE_TLV("HPHR Volume", WCD937X
2050 SOC_SINGLE_TLV("ADC1 Volume", WCD937X
2051 SOC_SINGLE_TLV("ADC2 Volume", WCD937X
2052 SOC_SINGLE_TLV("ADC3 Volume", WCD937X
2053
2054 SOC_SINGLE_EXT("HPHL Switch", WCD937X
2055 wcd937x_get_swr_port,
2056 SOC_SINGLE_EXT("HPHR Switch", WCD937X
2057 wcd937x_get_swr_port,
2058 SOC_SINGLE_EXT("LO Switch", WCD937X_L
2059 wcd937x_get_swr_port,
2060
2061 SOC_SINGLE_EXT("ADC1 Switch", WCD937X
2062 wcd937x_get_swr_port,
2063 SOC_SINGLE_EXT("ADC2 Switch", WCD937X
2064 wcd937x_get_swr_port,
2065 SOC_SINGLE_EXT("ADC3 Switch", WCD937X
2066 wcd937x_get_swr_port,
2067 SOC_SINGLE_EXT("DMIC0 Switch", WCD937
2068 wcd937x_get_swr_port,
2069 SOC_SINGLE_EXT("DMIC1 Switch", WCD937
2070 wcd937x_get_swr_port,
2071 SOC_SINGLE_EXT("MBHC Switch", WCD937X
2072 wcd937x_get_swr_port,
2073 SOC_SINGLE_EXT("DMIC2 Switch", WCD937
2074 wcd937x_get_swr_port,
2075 SOC_SINGLE_EXT("DMIC3 Switch", WCD937
2076 wcd937x_get_swr_port,
2077 SOC_SINGLE_EXT("DMIC4 Switch", WCD937
2078 wcd937x_get_swr_port,
2079 SOC_SINGLE_EXT("DMIC5 Switch", WCD937
2080 wcd937x_get_swr_port,
2081 };
2082
2083 static const struct snd_kcontrol_new adc1_swi
2084 SOC_DAPM_SINGLE("Switch", SND_SOC_NOP
2085 };
2086
2087 static const struct snd_kcontrol_new adc2_swi
2088 SOC_DAPM_SINGLE("Switch", SND_SOC_NOP
2089 };
2090
2091 static const struct snd_kcontrol_new adc3_swi
2092 SOC_DAPM_SINGLE("Switch", SND_SOC_NOP
2093 };
2094
2095 static const struct snd_kcontrol_new dmic1_sw
2096 SOC_DAPM_SINGLE("Switch", SND_SOC_NOP
2097 };
2098
2099 static const struct snd_kcontrol_new dmic2_sw
2100 SOC_DAPM_SINGLE("Switch", SND_SOC_NOP
2101 };
2102
2103 static const struct snd_kcontrol_new dmic3_sw
2104 SOC_DAPM_SINGLE("Switch", SND_SOC_NOP
2105 };
2106
2107 static const struct snd_kcontrol_new dmic4_sw
2108 SOC_DAPM_SINGLE("Switch", SND_SOC_NOP
2109 };
2110
2111 static const struct snd_kcontrol_new dmic5_sw
2112 SOC_DAPM_SINGLE("Switch", SND_SOC_NOP
2113 };
2114
2115 static const struct snd_kcontrol_new dmic6_sw
2116 SOC_DAPM_SINGLE("Switch", SND_SOC_NOP
2117 };
2118
2119 static const struct snd_kcontrol_new ear_rdac
2120 SOC_DAPM_SINGLE("Switch", SND_SOC_NOP
2121 };
2122
2123 static const struct snd_kcontrol_new aux_rdac
2124 SOC_DAPM_SINGLE("Switch", SND_SOC_NOP
2125 };
2126
2127 static const struct snd_kcontrol_new hphl_rda
2128 SOC_DAPM_SINGLE("Switch", SND_SOC_NOP
2129 };
2130
2131 static const struct snd_kcontrol_new hphr_rda
2132 SOC_DAPM_SINGLE("Switch", SND_SOC_NOP
2133 };
2134
2135 static const char * const adc2_mux_text[] = {
2136 "INP2", "INP3"
2137 };
2138
2139 static const char * const rdac3_mux_text[] =
2140 "RX1", "RX3"
2141 };
2142
2143 static const struct soc_enum adc2_enum =
2144 SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2
2145 ARRAY_SIZE(adc2_mux_t
2146
2147 static const struct soc_enum rdac3_enum =
2148 SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_E
2149 ARRAY_SIZE(rdac3_mux_
2150
2151 static const struct snd_kcontrol_new tx_adc2_
2152
2153 static const struct snd_kcontrol_new rx_rdac3
2154
2155 static const struct snd_soc_dapm_widget wcd93
2156 /* Input widgets */
2157 SND_SOC_DAPM_INPUT("AMIC1"),
2158 SND_SOC_DAPM_INPUT("AMIC2"),
2159 SND_SOC_DAPM_INPUT("AMIC3"),
2160 SND_SOC_DAPM_INPUT("IN1_HPHL"),
2161 SND_SOC_DAPM_INPUT("IN2_HPHR"),
2162 SND_SOC_DAPM_INPUT("IN3_AUX"),
2163
2164 /* TX widgets */
2165 SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_
2166 wcd937x_codec_enab
2167 SND_SOC_DAPM_PRE_P
2168 SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_
2169 wcd937x_codec_enab
2170 SND_SOC_DAPM_PRE_P
2171
2172 SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_
2173 NULL, 0, wcd937x
2174 SND_SOC_DAPM_PRE
2175 SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_
2176 NULL, 0, wcd937x
2177 SND_SOC_DAPM_PRE
2178
2179 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_
2180
2181 /* TX mixers */
2182 SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SN
2183 adc1_switch, ARR
2184 wcd937x_tx_swr_c
2185 SND_SOC_DAPM_POS
2186 SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SN
2187 adc2_switch, ARR
2188 wcd937x_tx_swr_c
2189 SND_SOC_DAPM_POS
2190
2191 /* MIC_BIAS widgets */
2192 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_
2193 wcd937x_codec_ena
2194 SND_SOC_DAPM_PRE_
2195 SND_SOC_DAPM_POST
2196 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_
2197 wcd937x_codec_ena
2198 SND_SOC_DAPM_PRE_
2199 SND_SOC_DAPM_POST
2200 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_
2201 wcd937x_codec_ena
2202 SND_SOC_DAPM_PRE_
2203 SND_SOC_DAPM_POST
2204
2205 SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_S
2206 SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1
2207
2208 /* RX widgets */
2209 SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X
2210 wcd937x_codec_enab
2211 SND_SOC_DAPM_PRE_P
2212 SND_SOC_DAPM_PRE_P
2213 SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X
2214 wcd937x_codec_enab
2215 SND_SOC_DAPM_PRE_P
2216 SND_SOC_DAPM_PRE_P
2217 SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937
2218 wcd937x_codec_enab
2219 SND_SOC_DAPM_PRE_P
2220 SND_SOC_DAPM_PRE_P
2221 SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937
2222 wcd937x_codec_enab
2223 SND_SOC_DAPM_PRE_P
2224 SND_SOC_DAPM_PRE_P
2225
2226 SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND
2227 wcd937x_codec_hphl
2228 SND_SOC_DAPM_PRE_P
2229 SND_SOC_DAPM_PRE_P
2230 SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND
2231 wcd937x_codec_hphr
2232 SND_SOC_DAPM_PRE_P
2233 SND_SOC_DAPM_PRE_P
2234 SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND
2235 wcd937x_codec_ear_
2236 SND_SOC_DAPM_PRE_P
2237 SND_SOC_DAPM_PRE_P
2238 SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND
2239 wcd937x_codec_aux_
2240 SND_SOC_DAPM_PRE_P
2241 SND_SOC_DAPM_PRE_P
2242
2243 SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC
2244
2245 SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_N
2246 wcd937x_enable_r
2247 SND_SOC_DAPM_POS
2248 SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_N
2249 wcd937x_enable_r
2250 SND_SOC_DAPM_POS
2251 SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_N
2252 wcd937x_enable_r
2253 SND_SOC_DAPM_POS
2254
2255 /* RX mixer widgets*/
2256 SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SO
2257 ear_rdac_switch, A
2258 SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SO
2259 aux_rdac_switch, A
2260 SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_S
2261 hphl_rdac_switch,
2262 SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_S
2263 hphr_rdac_switch,
2264
2265 /* TX output widgets */
2266 SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
2267 SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
2268 SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
2269 SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
2270
2271 /* RX output widgets */
2272 SND_SOC_DAPM_OUTPUT("EAR"),
2273 SND_SOC_DAPM_OUTPUT("AUX"),
2274 SND_SOC_DAPM_OUTPUT("HPHL"),
2275 SND_SOC_DAPM_OUTPUT("HPHR"),
2276
2277 /* MIC_BIAS pull up widgets */
2278 SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", S
2279 wcd937x_codec_ena
2280 SND_SOC_DAPM_PRE_
2281 SND_SOC_DAPM_POST
2282 SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", S
2283 wcd937x_codec_ena
2284 SND_SOC_DAPM_PRE_
2285 SND_SOC_DAPM_POST
2286 SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", S
2287 wcd937x_codec_ena
2288 SND_SOC_DAPM_PRE_
2289 SND_SOC_DAPM_POST
2290 };
2291
2292 static const struct snd_soc_dapm_widget wcd93
2293 /* Input widgets */
2294 SND_SOC_DAPM_INPUT("AMIC4"),
2295
2296 /* TX widgets */
2297 SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_
2298 wcd937x_codec_enab
2299 SND_SOC_DAPM_PRE_P
2300
2301 SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_
2302 NULL, 0, wcd937x
2303 SND_SOC_DAPM_PRE
2304
2305 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND
2306 wcd937x_codec_enab
2307 SND_SOC_DAPM_PRE_P
2308 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND
2309 wcd937x_codec_enab
2310 SND_SOC_DAPM_PRE_P
2311 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND
2312 wcd937x_codec_enab
2313 SND_SOC_DAPM_PRE_P
2314 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND
2315 wcd937x_codec_enab
2316 SND_SOC_DAPM_PRE_P
2317 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND
2318 wcd937x_codec_enab
2319 SND_SOC_DAPM_PRE_P
2320 SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND
2321 wcd937x_codec_enab
2322 SND_SOC_DAPM_PRE_P
2323
2324 /* TX mixer widgets */
2325 SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", S
2326 0, dmic1_switch,
2327 wcd937x_tx_swr_c
2328 SND_SOC_DAPM_POS
2329 SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", S
2330 0, dmic2_switch,
2331 wcd937x_tx_swr_c
2332 SND_SOC_DAPM_POS
2333 SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", S
2334 0, dmic3_switch,
2335 wcd937x_tx_swr_c
2336 SND_SOC_DAPM_POS
2337 SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", S
2338 0, dmic4_switch,
2339 wcd937x_tx_swr_c
2340 SND_SOC_DAPM_POS
2341 SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", S
2342 0, dmic5_switch,
2343 wcd937x_tx_swr_c
2344 SND_SOC_DAPM_POS
2345 SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", S
2346 0, dmic6_switch,
2347 wcd937x_tx_swr_c
2348 SND_SOC_DAPM_POS
2349 SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SN
2350 ARRAY_SIZE(adc3_
2351 SND_SOC_DAPM_PRE
2352
2353 /* Output widgets */
2354 SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
2355 SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
2356 SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
2357 SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
2358 SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
2359 SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
2360 };
2361
2362 static const struct snd_soc_dapm_route wcd937
2363 { "ADC1_OUTPUT", NULL, "ADC1_MIXER" }
2364 { "ADC1_MIXER", "Switch", "ADC1 REQ"
2365 { "ADC1 REQ", NULL, "ADC1" },
2366 { "ADC1", NULL, "AMIC1" },
2367
2368 { "ADC2_OUTPUT", NULL, "ADC2_MIXER" }
2369 { "ADC2_MIXER", "Switch", "ADC2 REQ"
2370 { "ADC2 REQ", NULL, "ADC2" },
2371 { "ADC2", NULL, "ADC2 MUX" },
2372 { "ADC2 MUX", "INP3", "AMIC3" },
2373 { "ADC2 MUX", "INP2", "AMIC2" },
2374
2375 { "IN1_HPHL", NULL, "VDD_BUCK" },
2376 { "IN1_HPHL", NULL, "CLS_H_PORT" },
2377 { "RX1", NULL, "IN1_HPHL" },
2378 { "RDAC1", NULL, "RX1" },
2379 { "HPHL_RDAC", "Switch", "RDAC1" },
2380 { "HPHL PGA", NULL, "HPHL_RDAC" },
2381 { "HPHL", NULL, "HPHL PGA" },
2382
2383 { "IN2_HPHR", NULL, "VDD_BUCK" },
2384 { "IN2_HPHR", NULL, "CLS_H_PORT" },
2385 { "RX2", NULL, "IN2_HPHR" },
2386 { "RDAC2", NULL, "RX2" },
2387 { "HPHR_RDAC", "Switch", "RDAC2" },
2388 { "HPHR PGA", NULL, "HPHR_RDAC" },
2389 { "HPHR", NULL, "HPHR PGA" },
2390
2391 { "IN3_AUX", NULL, "VDD_BUCK" },
2392 { "IN3_AUX", NULL, "CLS_H_PORT" },
2393 { "RX3", NULL, "IN3_AUX" },
2394 { "RDAC4", NULL, "RX3" },
2395 { "AUX_RDAC", "Switch", "RDAC4" },
2396 { "AUX PGA", NULL, "AUX_RDAC" },
2397 { "AUX", NULL, "AUX PGA" },
2398
2399 { "RDAC3_MUX", "RX3", "RX3" },
2400 { "RDAC3_MUX", "RX1", "RX1" },
2401 { "RDAC3", NULL, "RDAC3_MUX" },
2402 { "EAR_RDAC", "Switch", "RDAC3" },
2403 { "EAR PGA", NULL, "EAR_RDAC" },
2404 { "EAR", NULL, "EAR PGA" },
2405 };
2406
2407 static const struct snd_soc_dapm_route wcd937
2408 { "ADC3_OUTPUT", NULL, "ADC3_MIXER" }
2409 { "ADC3_OUTPUT", NULL, "ADC3_MIXER" }
2410 { "ADC3_MIXER", "Switch", "ADC3 REQ"
2411 { "ADC3 REQ", NULL, "ADC3" },
2412 { "ADC3", NULL, "AMIC4" },
2413
2414 { "DMIC1_OUTPUT", NULL, "DMIC1_MIXER"
2415 { "DMIC1_MIXER", "Switch", "DMIC1" },
2416
2417 { "DMIC2_OUTPUT", NULL, "DMIC2_MIXER"
2418 { "DMIC2_MIXER", "Switch", "DMIC2" },
2419
2420 { "DMIC3_OUTPUT", NULL, "DMIC3_MIXER"
2421 { "DMIC3_MIXER", "Switch", "DMIC3" },
2422
2423 { "DMIC4_OUTPUT", NULL, "DMIC4_MIXER"
2424 { "DMIC4_MIXER", "Switch", "DMIC4" },
2425
2426 { "DMIC5_OUTPUT", NULL, "DMIC5_MIXER"
2427 { "DMIC5_MIXER", "Switch", "DMIC5" },
2428
2429 { "DMIC6_OUTPUT", NULL, "DMIC6_MIXER"
2430 { "DMIC6_MIXER", "Switch", "DMIC6" },
2431 };
2432
2433 static int wcd937x_set_micbias_data(struct wc
2434 {
2435 int vout_ctl[3];
2436
2437 /* Set micbias voltage */
2438 vout_ctl[0] = wcd937x_get_micb_vout_c
2439 vout_ctl[1] = wcd937x_get_micb_vout_c
2440 vout_ctl[2] = wcd937x_get_micb_vout_c
2441 if ((vout_ctl[0] | vout_ctl[1] | vout
2442 return -EINVAL;
2443
2444 regmap_update_bits(wcd937x->regmap, W
2445 regmap_update_bits(wcd937x->regmap, W
2446 regmap_update_bits(wcd937x->regmap, W
2447
2448 return 0;
2449 }
2450
2451 static irqreturn_t wcd937x_wd_handle_irq(int
2452 {
2453 return IRQ_HANDLED;
2454 }
2455
2456 static const struct irq_chip wcd_irq_chip = {
2457 .name = "WCD937x",
2458 };
2459
2460 static int wcd_irq_chip_map(struct irq_domain
2461 irq_hw_number_t h
2462 {
2463 irq_set_chip_and_handler(virq, &wcd_i
2464 irq_set_nested_thread(virq, 1);
2465 irq_set_noprobe(virq);
2466
2467 return 0;
2468 }
2469
2470 static const struct irq_domain_ops wcd_domain
2471 .map = wcd_irq_chip_map,
2472 };
2473
2474 static int wcd937x_irq_init(struct wcd937x_pr
2475 {
2476 wcd->virq = irq_domain_add_linear(NUL
2477 if (!(wcd->virq)) {
2478 dev_err(dev, "%s: Failed to a
2479 return -EINVAL;
2480 }
2481
2482 return devm_regmap_add_irq_chip(dev,
2483 irq_c
2484 IRQF_
2485 &wcd-
2486 }
2487
2488 static int wcd937x_soc_codec_probe(struct snd
2489 {
2490 struct snd_soc_dapm_context *dapm = s
2491 struct wcd937x_priv *wcd937x = snd_so
2492 struct sdw_slave *tx_sdw_dev = wcd937
2493 struct device *dev = component->dev;
2494 unsigned long time_left;
2495 int i, ret;
2496 u32 chipid;
2497
2498 time_left = wait_for_completion_timeo
2499
2500 if (!time_left) {
2501 dev_err(dev, "soundwire devic
2502 return -ETIMEDOUT;
2503 }
2504
2505 snd_soc_component_init_regmap(compone
2506 ret = pm_runtime_resume_and_get(dev);
2507 if (ret < 0)
2508 return ret;
2509
2510 chipid = (snd_soc_component_read(comp
2511 WCD9
2512 if (chipid != CHIPID_WCD9370 && chipi
2513 dev_err(dev, "Got unknown chi
2514 pm_runtime_put(dev);
2515 return -EINVAL;
2516 }
2517
2518 wcd937x->clsh_info = wcd_clsh_ctrl_al
2519 if (IS_ERR(wcd937x->clsh_info)) {
2520 pm_runtime_put(dev);
2521 return PTR_ERR(wcd937x->clsh_
2522 }
2523
2524 wcd937x_io_init(wcd937x->regmap);
2525 /* Set all interrupts as edge trigger
2526 for (i = 0; i < wcd937x_regmap_irq_ch
2527 regmap_write(wcd937x->regmap,
2528
2529 pm_runtime_put(dev);
2530
2531 wcd937x->hphr_pdm_wd_int = regmap_irq
2532
2533 wcd937x->hphl_pdm_wd_int = regmap_irq
2534
2535 wcd937x->aux_pdm_wd_int = regmap_irq_
2536
2537
2538 /* Request for watchdog interrupt */
2539 ret = devm_request_threaded_irq(dev,
2540 IRQF_
2541 "HPHR
2542 if (ret)
2543 dev_err(dev, "Failed to reque
2544
2545 ret = devm_request_threaded_irq(dev,
2546 IRQF_
2547 "HPHL
2548 if (ret)
2549 dev_err(dev, "Failed to reque
2550
2551 ret = devm_request_threaded_irq(dev,
2552 IRQF_
2553 "AUX
2554 if (ret)
2555 dev_err(dev, "Failed to reque
2556
2557 /* Disable watchdog interrupt for HPH
2558 disable_irq_nosync(wcd937x->hphr_pdm_
2559 disable_irq_nosync(wcd937x->hphl_pdm_
2560 disable_irq_nosync(wcd937x->aux_pdm_w
2561
2562 if (chipid == CHIPID_WCD9375) {
2563 ret = snd_soc_dapm_new_contro
2564
2565 if (ret < 0) {
2566 dev_err(component->de
2567 return ret;
2568 }
2569
2570 ret = snd_soc_dapm_add_routes
2571
2572 if (ret < 0) {
2573 dev_err(component->de
2574 return ret;
2575 }
2576 }
2577
2578 ret = wcd937x_mbhc_init(component);
2579 if (ret)
2580 dev_err(component->dev, "mbhc
2581
2582 return ret;
2583 }
2584
2585 static void wcd937x_soc_codec_remove(struct s
2586 {
2587 struct wcd937x_priv *wcd937x = snd_so
2588
2589 wcd937x_mbhc_deinit(component);
2590 free_irq(wcd937x->aux_pdm_wd_int, wcd
2591 free_irq(wcd937x->hphl_pdm_wd_int, wc
2592 free_irq(wcd937x->hphr_pdm_wd_int, wc
2593
2594 wcd_clsh_ctrl_free(wcd937x->clsh_info
2595 }
2596
2597 static int wcd937x_codec_set_jack(struct snd_
2598 struct snd_
2599 {
2600 struct wcd937x_priv *wcd = dev_get_dr
2601 int ret = 0;
2602
2603 if (jack)
2604 ret = wcd_mbhc_start(wcd->wcd
2605 else
2606 wcd_mbhc_stop(wcd->wcd_mbhc);
2607
2608 return ret;
2609 }
2610
2611 static const struct snd_soc_component_driver
2612 .name = "wcd937x_codec",
2613 .probe = wcd937x_soc_codec_probe,
2614 .remove = wcd937x_soc_codec_remove,
2615 .controls = wcd937x_snd_controls,
2616 .num_controls = ARRAY_SIZE(wcd937x_sn
2617 .dapm_widgets = wcd937x_dapm_widgets,
2618 .num_dapm_widgets = ARRAY_SIZE(wcd937
2619 .dapm_routes = wcd937x_audio_map,
2620 .num_dapm_routes = ARRAY_SIZE(wcd937x
2621 .set_jack = wcd937x_codec_set_jack,
2622 .endianness = 1,
2623 };
2624
2625 static void wcd937x_dt_parse_micbias_info(str
2626 {
2627 struct device_node *np = dev->of_node
2628 u32 prop_val = 0;
2629 int ret = 0;
2630
2631 ret = of_property_read_u32(np, "qcom,
2632 if (!ret)
2633 wcd->micb1_mv = prop_val / 10
2634 else
2635 dev_warn(dev, "Micbias1 DT pr
2636
2637 ret = of_property_read_u32(np, "qcom,
2638 if (!ret)
2639 wcd->micb2_mv = prop_val / 10
2640 else
2641 dev_warn(dev, "Micbias2 DT pr
2642
2643 ret = of_property_read_u32(np, "qcom,
2644 if (!ret)
2645 wcd->micb3_mv = prop_val / 10
2646 else
2647 dev_warn(dev, "Micbias3 DT pr
2648 }
2649
2650 static bool wcd937x_swap_gnd_mic(struct snd_s
2651 {
2652 int value;
2653 struct wcd937x_priv *wcd937x;
2654
2655 wcd937x = snd_soc_component_get_drvda
2656
2657 value = gpiod_get_value(wcd937x->us_e
2658 gpiod_set_value(wcd937x->us_euro_gpio
2659
2660 return true;
2661 }
2662
2663 static int wcd937x_codec_hw_params(struct snd
2664 struct snd
2665 struct snd
2666 {
2667 struct wcd937x_priv *wcd937x = dev_ge
2668 struct wcd937x_sdw_priv *wcd = wcd937
2669
2670 return wcd937x_sdw_hw_params(wcd, sub
2671 }
2672
2673 static int wcd937x_codec_free(struct snd_pcm_
2674 struct snd_soc_
2675 {
2676 struct wcd937x_priv *wcd937x = dev_ge
2677 struct wcd937x_sdw_priv *wcd = wcd937
2678
2679 return sdw_stream_remove_slave(wcd->s
2680 }
2681
2682 static int wcd937x_codec_set_sdw_stream(struc
2683 void
2684 {
2685 struct wcd937x_priv *wcd937x = dev_ge
2686 struct wcd937x_sdw_priv *wcd = wcd937
2687
2688 wcd->sruntime = stream;
2689
2690 return 0;
2691 }
2692
2693 static const struct snd_soc_dai_ops wcd937x_s
2694 .hw_params = wcd937x_codec_hw_params,
2695 .hw_free = wcd937x_codec_free,
2696 .set_stream = wcd937x_codec_set_sdw_s
2697 };
2698
2699 static struct snd_soc_dai_driver wcd937x_dais
2700 [0] = {
2701 .name = "wcd937x-sdw-rx",
2702 .playback = {
2703 .stream_name = "WCD A
2704 .rates = WCD937X_RATE
2705 .formats = WCD937X_FO
2706 .rate_min = 8000,
2707 .rate_max = 384000,
2708 .channels_min = 1,
2709 .channels_max = 4,
2710 },
2711 .ops = &wcd937x_sdw_dai_ops,
2712 },
2713 [1] = {
2714 .name = "wcd937x-sdw-tx",
2715 .capture = {
2716 .stream_name = "WCD A
2717 .rates = WCD937X_RATE
2718 .formats = WCD937X_FO
2719 .rate_min = 8000,
2720 .rate_max = 192000,
2721 .channels_min = 1,
2722 .channels_max = 4,
2723 },
2724 .ops = &wcd937x_sdw_dai_ops,
2725 },
2726 };
2727
2728 static int wcd937x_bind(struct device *dev)
2729 {
2730 struct wcd937x_priv *wcd937x = dev_ge
2731 int ret;
2732
2733 /* Give the SDW subdevices some more
2734 usleep_range(5000, 5010);
2735
2736 ret = component_bind_all(dev, wcd937x
2737 if (ret) {
2738 dev_err(dev, "Slave bind fail
2739 return ret;
2740 }
2741
2742 wcd937x->rxdev = wcd937x_sdw_device_g
2743 if (!wcd937x->rxdev) {
2744 dev_err(dev, "could not find
2745 return -EINVAL;
2746 }
2747
2748 wcd937x->sdw_priv[AIF1_PB] = dev_get_
2749 wcd937x->sdw_priv[AIF1_PB]->wcd937x =
2750
2751 wcd937x->txdev = wcd937x_sdw_device_g
2752 if (!wcd937x->txdev) {
2753 dev_err(dev, "could not find
2754 return -EINVAL;
2755 }
2756
2757 wcd937x->sdw_priv[AIF1_CAP] = dev_get
2758 wcd937x->sdw_priv[AIF1_CAP]->wcd937x
2759 wcd937x->tx_sdw_dev = dev_to_sdw_dev(
2760 if (!wcd937x->tx_sdw_dev) {
2761 dev_err(dev, "could not get t
2762 return -EINVAL;
2763 }
2764
2765 /*
2766 * As TX is the main CSR reg interfac
2767 * expicilty add the dependency link
2768 */
2769 if (!device_link_add(wcd937x->rxdev,
2770 DL_FLAG_STATELES
2771 dev_err(dev, "Could not devli
2772 return -EINVAL;
2773 }
2774
2775 if (!device_link_add(dev, wcd937x->tx
2776 DL_FLAG_STATELES
2777 dev_err(dev, "Could not devli
2778 return -EINVAL;
2779 }
2780
2781 if (!device_link_add(dev, wcd937x->rx
2782 DL_FLAG_STATELES
2783 dev_err(dev, "Could not devli
2784 return -EINVAL;
2785 }
2786
2787 wcd937x->regmap = dev_get_regmap(&wcd
2788 if (!wcd937x->regmap) {
2789 dev_err(dev, "could not get T
2790 return -EINVAL;
2791 }
2792
2793 ret = wcd937x_irq_init(wcd937x, dev);
2794 if (ret) {
2795 dev_err(dev, "IRQ init failed
2796 return ret;
2797 }
2798
2799 wcd937x->sdw_priv[AIF1_PB]->slave_irq
2800 wcd937x->sdw_priv[AIF1_CAP]->slave_ir
2801
2802 ret = wcd937x_set_micbias_data(wcd937
2803 if (ret < 0) {
2804 dev_err(dev, "Bad micbias pda
2805 return ret;
2806 }
2807
2808 ret = snd_soc_register_component(dev,
2809 wcd9
2810 if (ret)
2811 dev_err(dev, "Codec registrat
2812
2813 return ret;
2814 }
2815
2816 static void wcd937x_unbind(struct device *dev
2817 {
2818 struct wcd937x_priv *wcd937x = dev_ge
2819
2820 snd_soc_unregister_component(dev);
2821 device_link_remove(dev, wcd937x->txde
2822 device_link_remove(dev, wcd937x->rxde
2823 device_link_remove(wcd937x->rxdev, wc
2824 component_unbind_all(dev, wcd937x);
2825 mutex_destroy(&wcd937x->micb_lock);
2826 }
2827
2828 static const struct component_master_ops wcd9
2829 .bind = wcd937x_bind,
2830 .unbind = wcd937x_unbind,
2831 };
2832
2833 static int wcd937x_add_slave_components(struc
2834 struc
2835 struc
2836 {
2837 struct device_node *np = dev->of_node
2838
2839 wcd937x->rxnode = of_parse_phandle(np
2840 if (!wcd937x->rxnode) {
2841 dev_err(dev, "Couldn't parse
2842 return -ENODEV;
2843 }
2844 of_node_get(wcd937x->rxnode);
2845 component_match_add_release(dev, matc
2846 component
2847
2848 wcd937x->txnode = of_parse_phandle(np
2849 if (!wcd937x->txnode) {
2850 dev_err(dev, "Couldn't parse
2851 return -ENODEV;
2852 }
2853 of_node_get(wcd937x->txnode);
2854 component_match_add_release(dev, matc
2855 component
2856
2857 return 0;
2858 }
2859
2860 static int wcd937x_probe(struct platform_devi
2861 {
2862 struct component_match *match = NULL;
2863 struct device *dev = &pdev->dev;
2864 struct wcd937x_priv *wcd937x;
2865 struct wcd_mbhc_config *cfg;
2866 int ret;
2867
2868 wcd937x = devm_kzalloc(dev, sizeof(*w
2869 if (!wcd937x)
2870 return -ENOMEM;
2871
2872 dev_set_drvdata(dev, wcd937x);
2873 mutex_init(&wcd937x->micb_lock);
2874
2875 wcd937x->reset_gpio = devm_gpiod_get(
2876 if (IS_ERR(wcd937x->reset_gpio))
2877 return dev_err_probe(dev, PTR
2878 "failed
2879
2880 wcd937x->us_euro_gpio = devm_gpiod_ge
2881 if (IS_ERR(wcd937x->us_euro_gpio))
2882 return dev_err_probe(dev, PTR
2883 "us-euro swap
2884
2885 cfg = &wcd937x->mbhc_cfg;
2886 cfg->swap_gnd_mic = wcd937x_swap_gnd_
2887
2888 wcd937x->supplies[0].supply = "vdd-rx
2889 wcd937x->supplies[1].supply = "vdd-px
2890 wcd937x->supplies[2].supply = "vdd-mi
2891 wcd937x->supplies[3].supply = "vdd-bu
2892
2893 ret = devm_regulator_bulk_get(dev, WC
2894 if (ret)
2895 return dev_err_probe(dev, ret
2896
2897 ret = regulator_bulk_enable(WCD937X_M
2898 if (ret) {
2899 regulator_bulk_free(WCD937X_M
2900 return dev_err_probe(dev, ret
2901 }
2902
2903 wcd937x_dt_parse_micbias_info(dev, wc
2904
2905 cfg->mbhc_micbias = MIC_BIAS_2;
2906 cfg->anc_micbias = MIC_BIAS_2;
2907 cfg->v_hs_max = WCD_MBHC_HS_V_MAX;
2908 cfg->num_btn = WCD937X_MBHC_MAX_BUTTO
2909 cfg->micb_mv = wcd937x->micb2_mv;
2910 cfg->linein_th = 5000;
2911 cfg->hs_thr = 1700;
2912 cfg->hph_thr = 50;
2913
2914 wcd_dt_parse_mbhc_data(dev, &wcd937x-
2915
2916 ret = wcd937x_add_slave_components(wc
2917 if (ret)
2918 goto err_disable_regulators;
2919
2920 wcd937x_reset(wcd937x);
2921
2922 ret = component_master_add_with_match
2923 if (ret)
2924 goto err_disable_regulators;
2925
2926 pm_runtime_set_autosuspend_delay(dev,
2927 pm_runtime_use_autosuspend(dev);
2928 pm_runtime_mark_last_busy(dev);
2929 pm_runtime_set_active(dev);
2930 pm_runtime_enable(dev);
2931 pm_runtime_idle(dev);
2932
2933 return 0;
2934
2935 err_disable_regulators:
2936 regulator_bulk_disable(WCD937X_MAX_BU
2937 regulator_bulk_free(WCD937X_MAX_BULK_
2938
2939 return ret;
2940 }
2941
2942 static void wcd937x_remove(struct platform_de
2943 {
2944 struct device *dev = &pdev->dev;
2945 struct wcd937x_priv *wcd937x = dev_ge
2946
2947 component_master_del(&pdev->dev, &wcd
2948
2949 pm_runtime_disable(dev);
2950 pm_runtime_set_suspended(dev);
2951 pm_runtime_dont_use_autosuspend(dev);
2952
2953 regulator_bulk_disable(WCD937X_MAX_BU
2954 regulator_bulk_free(WCD937X_MAX_BULK_
2955 }
2956
2957 #if defined(CONFIG_OF)
2958 static const struct of_device_id wcd937x_of_m
2959 { .compatible = "qcom,wcd9370-codec"
2960 { .compatible = "qcom,wcd9375-codec"
2961 { }
2962 };
2963 MODULE_DEVICE_TABLE(of, wcd937x_of_match);
2964 #endif
2965
2966 static struct platform_driver wcd937x_codec_d
2967 .probe = wcd937x_probe,
2968 .remove = wcd937x_remove,
2969 .driver = {
2970 .name = "wcd937x_codec",
2971 .of_match_table = of_match_pt
2972 .suppress_bind_attrs = true,
2973 },
2974 };
2975
2976 module_platform_driver(wcd937x_codec_driver);
2977 MODULE_DESCRIPTION("WCD937X Codec driver");
2978 MODULE_LICENSE("GPL");
2979
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