1 /* SPDX-License-Identifier: GPL-2.0-or-later * <<
2 /* 1 /*
3 * wm8753.h -- audio driver for WM8753 2 * wm8753.h -- audio driver for WM8753
4 * 3 *
5 * Copyright 2003 Wolfson Microelectronics PLC 4 * Copyright 2003 Wolfson Microelectronics PLC.
6 * Author: Liam Girdwood <lrg@slimlogic.co.uk> 5 * Author: Liam Girdwood <lrg@slimlogic.co.uk>
>> 6 *
>> 7 * This program is free software; you can redistribute it and/or modify it
>> 8 * under the terms of the GNU General Public License as published by the
>> 9 * Free Software Foundation; either version 2 of the License, or (at your
>> 10 * option) any later version.
>> 11 *
7 */ 12 */
8 13
9 #ifndef _WM8753_H 14 #ifndef _WM8753_H
10 #define _WM8753_H 15 #define _WM8753_H
11 16
12 /* WM8753 register space */ 17 /* WM8753 register space */
13 18
14 #define WM8753_DAC 0x01 19 #define WM8753_DAC 0x01
15 #define WM8753_ADC 0x02 20 #define WM8753_ADC 0x02
16 #define WM8753_PCM 0x03 21 #define WM8753_PCM 0x03
17 #define WM8753_HIFI 0x04 22 #define WM8753_HIFI 0x04
18 #define WM8753_IOCTL 0x05 23 #define WM8753_IOCTL 0x05
19 #define WM8753_SRATE1 0x06 24 #define WM8753_SRATE1 0x06
20 #define WM8753_SRATE2 0x07 25 #define WM8753_SRATE2 0x07
21 #define WM8753_LDAC 0x08 26 #define WM8753_LDAC 0x08
22 #define WM8753_RDAC 0x09 27 #define WM8753_RDAC 0x09
23 #define WM8753_BASS 0x0a 28 #define WM8753_BASS 0x0a
24 #define WM8753_TREBLE 0x0b 29 #define WM8753_TREBLE 0x0b
25 #define WM8753_ALC1 0x0c 30 #define WM8753_ALC1 0x0c
26 #define WM8753_ALC2 0x0d 31 #define WM8753_ALC2 0x0d
27 #define WM8753_ALC3 0x0e 32 #define WM8753_ALC3 0x0e
28 #define WM8753_NGATE 0x0f 33 #define WM8753_NGATE 0x0f
29 #define WM8753_LADC 0x10 34 #define WM8753_LADC 0x10
30 #define WM8753_RADC 0x11 35 #define WM8753_RADC 0x11
31 #define WM8753_ADCTL1 0x12 36 #define WM8753_ADCTL1 0x12
32 #define WM8753_3D 0x13 37 #define WM8753_3D 0x13
33 #define WM8753_PWR1 0x14 38 #define WM8753_PWR1 0x14
34 #define WM8753_PWR2 0x15 39 #define WM8753_PWR2 0x15
35 #define WM8753_PWR3 0x16 40 #define WM8753_PWR3 0x16
36 #define WM8753_PWR4 0x17 41 #define WM8753_PWR4 0x17
37 #define WM8753_ID 0x18 42 #define WM8753_ID 0x18
38 #define WM8753_INTPOL 0x19 43 #define WM8753_INTPOL 0x19
39 #define WM8753_INTEN 0x1a 44 #define WM8753_INTEN 0x1a
40 #define WM8753_GPIO1 0x1b 45 #define WM8753_GPIO1 0x1b
41 #define WM8753_GPIO2 0x1c 46 #define WM8753_GPIO2 0x1c
42 #define WM8753_RESET 0x1f 47 #define WM8753_RESET 0x1f
43 #define WM8753_RECMIX1 0x20 48 #define WM8753_RECMIX1 0x20
44 #define WM8753_RECMIX2 0x21 49 #define WM8753_RECMIX2 0x21
45 #define WM8753_LOUTM1 0x22 50 #define WM8753_LOUTM1 0x22
46 #define WM8753_LOUTM2 0x23 51 #define WM8753_LOUTM2 0x23
47 #define WM8753_ROUTM1 0x24 52 #define WM8753_ROUTM1 0x24
48 #define WM8753_ROUTM2 0x25 53 #define WM8753_ROUTM2 0x25
49 #define WM8753_MOUTM1 0x26 54 #define WM8753_MOUTM1 0x26
50 #define WM8753_MOUTM2 0x27 55 #define WM8753_MOUTM2 0x27
51 #define WM8753_LOUT1V 0x28 56 #define WM8753_LOUT1V 0x28
52 #define WM8753_ROUT1V 0x29 57 #define WM8753_ROUT1V 0x29
53 #define WM8753_LOUT2V 0x2a 58 #define WM8753_LOUT2V 0x2a
54 #define WM8753_ROUT2V 0x2b 59 #define WM8753_ROUT2V 0x2b
55 #define WM8753_MOUTV 0x2c 60 #define WM8753_MOUTV 0x2c
56 #define WM8753_OUTCTL 0x2d 61 #define WM8753_OUTCTL 0x2d
57 #define WM8753_ADCIN 0x2e 62 #define WM8753_ADCIN 0x2e
58 #define WM8753_INCTL1 0x2f 63 #define WM8753_INCTL1 0x2f
59 #define WM8753_INCTL2 0x30 64 #define WM8753_INCTL2 0x30
60 #define WM8753_LINVOL 0x31 65 #define WM8753_LINVOL 0x31
61 #define WM8753_RINVOL 0x32 66 #define WM8753_RINVOL 0x32
62 #define WM8753_MICBIAS 0x33 67 #define WM8753_MICBIAS 0x33
63 #define WM8753_CLOCK 0x34 68 #define WM8753_CLOCK 0x34
64 #define WM8753_PLL1CTL1 0x35 69 #define WM8753_PLL1CTL1 0x35
65 #define WM8753_PLL1CTL2 0x36 70 #define WM8753_PLL1CTL2 0x36
66 #define WM8753_PLL1CTL3 0x37 71 #define WM8753_PLL1CTL3 0x37
67 #define WM8753_PLL1CTL4 0x38 72 #define WM8753_PLL1CTL4 0x38
68 #define WM8753_PLL2CTL1 0x39 73 #define WM8753_PLL2CTL1 0x39
69 #define WM8753_PLL2CTL2 0x3a 74 #define WM8753_PLL2CTL2 0x3a
70 #define WM8753_PLL2CTL3 0x3b 75 #define WM8753_PLL2CTL3 0x3b
71 #define WM8753_PLL2CTL4 0x3c 76 #define WM8753_PLL2CTL4 0x3c
72 #define WM8753_BIASCTL 0x3d 77 #define WM8753_BIASCTL 0x3d
73 #define WM8753_ADCTL2 0x3f 78 #define WM8753_ADCTL2 0x3f
74 79
75 #define WM8753_PLL1 0 80 #define WM8753_PLL1 0
76 #define WM8753_PLL2 1 81 #define WM8753_PLL2 1
77 82
78 /* clock inputs */ 83 /* clock inputs */
79 #define WM8753_MCLK 0 84 #define WM8753_MCLK 0
80 #define WM8753_PCMCLK 1 85 #define WM8753_PCMCLK 1
81 86
82 /* clock divider id's */ 87 /* clock divider id's */
83 #define WM8753_PCMDIV 0 88 #define WM8753_PCMDIV 0
84 #define WM8753_BCLKDIV 1 89 #define WM8753_BCLKDIV 1
85 #define WM8753_VXCLKDIV 2 90 #define WM8753_VXCLKDIV 2
86 91
87 /* PCM clock dividers */ 92 /* PCM clock dividers */
88 #define WM8753_PCM_DIV_1 (0 << 6) 93 #define WM8753_PCM_DIV_1 (0 << 6)
89 #define WM8753_PCM_DIV_3 (2 << 6) 94 #define WM8753_PCM_DIV_3 (2 << 6)
90 #define WM8753_PCM_DIV_5_5 (3 << 6) 95 #define WM8753_PCM_DIV_5_5 (3 << 6)
91 #define WM8753_PCM_DIV_2 (4 << 6) 96 #define WM8753_PCM_DIV_2 (4 << 6)
92 #define WM8753_PCM_DIV_4 (5 << 6) 97 #define WM8753_PCM_DIV_4 (5 << 6)
93 #define WM8753_PCM_DIV_6 (6 << 6) 98 #define WM8753_PCM_DIV_6 (6 << 6)
94 #define WM8753_PCM_DIV_8 (7 << 6) 99 #define WM8753_PCM_DIV_8 (7 << 6)
95 100
96 /* BCLK clock dividers */ 101 /* BCLK clock dividers */
97 #define WM8753_BCLK_DIV_1 (0 << 3) 102 #define WM8753_BCLK_DIV_1 (0 << 3)
98 #define WM8753_BCLK_DIV_2 (1 << 3) 103 #define WM8753_BCLK_DIV_2 (1 << 3)
99 #define WM8753_BCLK_DIV_4 (2 << 3) 104 #define WM8753_BCLK_DIV_4 (2 << 3)
100 #define WM8753_BCLK_DIV_8 (3 << 3) 105 #define WM8753_BCLK_DIV_8 (3 << 3)
101 #define WM8753_BCLK_DIV_16 (4 << 3) 106 #define WM8753_BCLK_DIV_16 (4 << 3)
102 107
103 /* VXCLK clock dividers */ 108 /* VXCLK clock dividers */
104 #define WM8753_VXCLK_DIV_1 (0 << 6) 109 #define WM8753_VXCLK_DIV_1 (0 << 6)
105 #define WM8753_VXCLK_DIV_2 (1 << 6) 110 #define WM8753_VXCLK_DIV_2 (1 << 6)
106 #define WM8753_VXCLK_DIV_4 (2 << 6) 111 #define WM8753_VXCLK_DIV_4 (2 << 6)
107 #define WM8753_VXCLK_DIV_8 (3 << 6) 112 #define WM8753_VXCLK_DIV_8 (3 << 6)
108 #define WM8753_VXCLK_DIV_16 (4 << 6) 113 #define WM8753_VXCLK_DIV_16 (4 << 6)
109 114
110 #endif 115 #endif
111 116
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