1 /* SPDX-License-Identifier: GPL-2.0-or-later * 1 2 /* 3 * wm8903.h - WM8903 audio codec interface 4 * 5 * Copyright 2008 Wolfson Microelectronics PLC 6 * Author: Mark Brown <broonie@opensource.wolf 7 */ 8 9 #ifndef _WM8903_H 10 #define _WM8903_H 11 12 #include <linux/i2c.h> 13 14 extern int wm8903_mic_detect(struct snd_soc_co 15 struct snd_soc_ja 16 int det, int shrt 17 18 19 /* 20 * Register values. 21 */ 22 #define WM8903_SW_RESET_AND_ID 23 #define WM8903_REVISION_NUMBER 24 #define WM8903_BIAS_CONTROL_0 25 #define WM8903_VMID_CONTROL_0 26 #define WM8903_MIC_BIAS_CONTROL_0 27 #define WM8903_ANALOGUE_DAC_0 28 #define WM8903_ANALOGUE_ADC_0 29 #define WM8903_POWER_MANAGEMENT_0 30 #define WM8903_POWER_MANAGEMENT_1 31 #define WM8903_POWER_MANAGEMENT_2 32 #define WM8903_POWER_MANAGEMENT_3 33 #define WM8903_POWER_MANAGEMENT_4 34 #define WM8903_POWER_MANAGEMENT_5 35 #define WM8903_POWER_MANAGEMENT_6 36 #define WM8903_CLOCK_RATES_0 37 #define WM8903_CLOCK_RATES_1 38 #define WM8903_CLOCK_RATES_2 39 #define WM8903_AUDIO_INTERFACE_0 40 #define WM8903_AUDIO_INTERFACE_1 41 #define WM8903_AUDIO_INTERFACE_2 42 #define WM8903_AUDIO_INTERFACE_3 43 #define WM8903_DAC_DIGITAL_VOLUME_LEFT 44 #define WM8903_DAC_DIGITAL_VOLUME_RIGHT 45 #define WM8903_DAC_DIGITAL_0 46 #define WM8903_DAC_DIGITAL_1 47 #define WM8903_ADC_DIGITAL_VOLUME_LEFT 48 #define WM8903_ADC_DIGITAL_VOLUME_RIGHT 49 #define WM8903_ADC_DIGITAL_0 50 #define WM8903_DIGITAL_MICROPHONE_0 51 #define WM8903_DRC_0 52 #define WM8903_DRC_1 53 #define WM8903_DRC_2 54 #define WM8903_DRC_3 55 #define WM8903_ANALOGUE_LEFT_INPUT_0 56 #define WM8903_ANALOGUE_RIGHT_INPUT_0 57 #define WM8903_ANALOGUE_LEFT_INPUT_1 58 #define WM8903_ANALOGUE_RIGHT_INPUT_1 59 #define WM8903_ANALOGUE_LEFT_MIX_0 60 #define WM8903_ANALOGUE_RIGHT_MIX_0 61 #define WM8903_ANALOGUE_SPK_MIX_LEFT_0 62 #define WM8903_ANALOGUE_SPK_MIX_LEFT_1 63 #define WM8903_ANALOGUE_SPK_MIX_RIGHT_0 64 #define WM8903_ANALOGUE_SPK_MIX_RIGHT_1 65 #define WM8903_ANALOGUE_OUT1_LEFT 66 #define WM8903_ANALOGUE_OUT1_RIGHT 67 #define WM8903_ANALOGUE_OUT2_LEFT 68 #define WM8903_ANALOGUE_OUT2_RIGHT 69 #define WM8903_ANALOGUE_OUT3_LEFT 70 #define WM8903_ANALOGUE_OUT3_RIGHT 71 #define WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0 72 #define WM8903_DC_SERVO_0 73 #define WM8903_DC_SERVO_2 74 #define WM8903_DC_SERVO_4 75 #define WM8903_DC_SERVO_5 76 #define WM8903_DC_SERVO_6 77 #define WM8903_DC_SERVO_7 78 #define WM8903_DC_SERVO_READBACK_1 79 #define WM8903_DC_SERVO_READBACK_2 80 #define WM8903_DC_SERVO_READBACK_3 81 #define WM8903_DC_SERVO_READBACK_4 82 #define WM8903_ANALOGUE_HP_0 83 #define WM8903_ANALOGUE_LINEOUT_0 84 #define WM8903_CHARGE_PUMP_0 85 #define WM8903_CLASS_W_0 86 #define WM8903_WRITE_SEQUENCER_0 87 #define WM8903_WRITE_SEQUENCER_1 88 #define WM8903_WRITE_SEQUENCER_2 89 #define WM8903_WRITE_SEQUENCER_3 90 #define WM8903_WRITE_SEQUENCER_4 91 #define WM8903_CONTROL_INTERFACE 92 #define WM8903_GPIO_CONTROL_1 93 #define WM8903_GPIO_CONTROL_2 94 #define WM8903_GPIO_CONTROL_3 95 #define WM8903_GPIO_CONTROL_4 96 #define WM8903_GPIO_CONTROL_5 97 #define WM8903_INTERRUPT_STATUS_1 98 #define WM8903_INTERRUPT_STATUS_1_MASK 99 #define WM8903_INTERRUPT_POLARITY_1 100 #define WM8903_INTERRUPT_CONTROL 101 #define WM8903_CLOCK_RATE_TEST_4 102 #define WM8903_ANALOGUE_OUTPUT_BIAS_0 103 104 #define WM8903_REGISTER_COUNT 105 #define WM8903_MAX_REGISTER 106 107 /* 108 * Field Definitions. 109 */ 110 111 /* 112 * R0 (0x00) - SW Reset and ID 113 */ 114 #define WM8903_SW_RESET_DEV_ID1_MASK 115 #define WM8903_SW_RESET_DEV_ID1_SHIFT 116 #define WM8903_SW_RESET_DEV_ID1_WIDTH 117 118 /* 119 * R1 (0x01) - Revision Number 120 */ 121 #define WM8903_CHIP_REV_MASK 122 #define WM8903_CHIP_REV_SHIFT 123 #define WM8903_CHIP_REV_WIDTH 124 125 /* 126 * R4 (0x04) - Bias Control 0 127 */ 128 #define WM8903_POBCTRL 129 #define WM8903_POBCTRL_MASK 130 #define WM8903_POBCTRL_SHIFT 131 #define WM8903_POBCTRL_WIDTH 132 #define WM8903_ISEL_MASK 133 #define WM8903_ISEL_SHIFT 134 #define WM8903_ISEL_WIDTH 135 #define WM8903_STARTUP_BIAS_ENA 136 #define WM8903_STARTUP_BIAS_ENA_MASK 137 #define WM8903_STARTUP_BIAS_ENA_SHIFT 138 #define WM8903_STARTUP_BIAS_ENA_WIDTH 139 #define WM8903_BIAS_ENA 140 #define WM8903_BIAS_ENA_MASK 141 #define WM8903_BIAS_ENA_SHIFT 142 #define WM8903_BIAS_ENA_WIDTH 143 144 /* 145 * R5 (0x05) - VMID Control 0 146 */ 147 #define WM8903_VMID_TIE_ENA 148 #define WM8903_VMID_TIE_ENA_MASK 149 #define WM8903_VMID_TIE_ENA_SHIFT 150 #define WM8903_VMID_TIE_ENA_WIDTH 151 #define WM8903_BUFIO_ENA 152 #define WM8903_BUFIO_ENA_MASK 153 #define WM8903_BUFIO_ENA_SHIFT 154 #define WM8903_BUFIO_ENA_WIDTH 155 #define WM8903_VMID_IO_ENA 156 #define WM8903_VMID_IO_ENA_MASK 157 #define WM8903_VMID_IO_ENA_SHIFT 158 #define WM8903_VMID_IO_ENA_WIDTH 159 #define WM8903_VMID_SOFT_MASK 160 #define WM8903_VMID_SOFT_SHIFT 161 #define WM8903_VMID_SOFT_WIDTH 162 #define WM8903_VMID_RES_MASK 163 #define WM8903_VMID_RES_SHIFT 164 #define WM8903_VMID_RES_WIDTH 165 #define WM8903_VMID_BUF_ENA 166 #define WM8903_VMID_BUF_ENA_MASK 167 #define WM8903_VMID_BUF_ENA_SHIFT 168 #define WM8903_VMID_BUF_ENA_WIDTH 169 170 #define WM8903_VMID_RES_50K 171 #define WM8903_VMID_RES_250K 172 #define WM8903_VMID_RES_5K 173 174 /* 175 * R8 (0x08) - Analogue DAC 0 176 */ 177 #define WM8903_DACBIAS_SEL_MASK 178 #define WM8903_DACBIAS_SEL_SHIFT 179 #define WM8903_DACBIAS_SEL_WIDTH 180 #define WM8903_DACVMID_BIAS_SEL_MASK 181 #define WM8903_DACVMID_BIAS_SEL_SHIFT 182 #define WM8903_DACVMID_BIAS_SEL_WIDTH 183 184 /* 185 * R10 (0x0A) - Analogue ADC 0 186 */ 187 #define WM8903_ADC_OSR128 188 #define WM8903_ADC_OSR128_MASK 189 #define WM8903_ADC_OSR128_SHIFT 190 #define WM8903_ADC_OSR128_WIDTH 191 192 /* 193 * R12 (0x0C) - Power Management 0 194 */ 195 #define WM8903_INL_ENA 196 #define WM8903_INL_ENA_MASK 197 #define WM8903_INL_ENA_SHIFT 198 #define WM8903_INL_ENA_WIDTH 199 #define WM8903_INR_ENA 200 #define WM8903_INR_ENA_MASK 201 #define WM8903_INR_ENA_SHIFT 202 #define WM8903_INR_ENA_WIDTH 203 204 /* 205 * R13 (0x0D) - Power Management 1 206 */ 207 #define WM8903_MIXOUTL_ENA 208 #define WM8903_MIXOUTL_ENA_MASK 209 #define WM8903_MIXOUTL_ENA_SHIFT 210 #define WM8903_MIXOUTL_ENA_WIDTH 211 #define WM8903_MIXOUTR_ENA 212 #define WM8903_MIXOUTR_ENA_MASK 213 #define WM8903_MIXOUTR_ENA_SHIFT 214 #define WM8903_MIXOUTR_ENA_WIDTH 215 216 /* 217 * R14 (0x0E) - Power Management 2 218 */ 219 #define WM8903_HPL_PGA_ENA 220 #define WM8903_HPL_PGA_ENA_MASK 221 #define WM8903_HPL_PGA_ENA_SHIFT 222 #define WM8903_HPL_PGA_ENA_WIDTH 223 #define WM8903_HPR_PGA_ENA 224 #define WM8903_HPR_PGA_ENA_MASK 225 #define WM8903_HPR_PGA_ENA_SHIFT 226 #define WM8903_HPR_PGA_ENA_WIDTH 227 228 /* 229 * R15 (0x0F) - Power Management 3 230 */ 231 #define WM8903_LINEOUTL_PGA_ENA 232 #define WM8903_LINEOUTL_PGA_ENA_MASK 233 #define WM8903_LINEOUTL_PGA_ENA_SHIFT 234 #define WM8903_LINEOUTL_PGA_ENA_WIDTH 235 #define WM8903_LINEOUTR_PGA_ENA 236 #define WM8903_LINEOUTR_PGA_ENA_MASK 237 #define WM8903_LINEOUTR_PGA_ENA_SHIFT 238 #define WM8903_LINEOUTR_PGA_ENA_WIDTH 239 240 /* 241 * R16 (0x10) - Power Management 4 242 */ 243 #define WM8903_MIXSPKL_ENA 244 #define WM8903_MIXSPKL_ENA_MASK 245 #define WM8903_MIXSPKL_ENA_SHIFT 246 #define WM8903_MIXSPKL_ENA_WIDTH 247 #define WM8903_MIXSPKR_ENA 248 #define WM8903_MIXSPKR_ENA_MASK 249 #define WM8903_MIXSPKR_ENA_SHIFT 250 #define WM8903_MIXSPKR_ENA_WIDTH 251 252 /* 253 * R17 (0x11) - Power Management 5 254 */ 255 #define WM8903_SPKL_ENA 256 #define WM8903_SPKL_ENA_MASK 257 #define WM8903_SPKL_ENA_SHIFT 258 #define WM8903_SPKL_ENA_WIDTH 259 #define WM8903_SPKR_ENA 260 #define WM8903_SPKR_ENA_MASK 261 #define WM8903_SPKR_ENA_SHIFT 262 #define WM8903_SPKR_ENA_WIDTH 263 264 /* 265 * R18 (0x12) - Power Management 6 266 */ 267 #define WM8903_DACL_ENA 268 #define WM8903_DACL_ENA_MASK 269 #define WM8903_DACL_ENA_SHIFT 270 #define WM8903_DACL_ENA_WIDTH 271 #define WM8903_DACR_ENA 272 #define WM8903_DACR_ENA_MASK 273 #define WM8903_DACR_ENA_SHIFT 274 #define WM8903_DACR_ENA_WIDTH 275 #define WM8903_ADCL_ENA 276 #define WM8903_ADCL_ENA_MASK 277 #define WM8903_ADCL_ENA_SHIFT 278 #define WM8903_ADCL_ENA_WIDTH 279 #define WM8903_ADCR_ENA 280 #define WM8903_ADCR_ENA_MASK 281 #define WM8903_ADCR_ENA_SHIFT 282 #define WM8903_ADCR_ENA_WIDTH 283 284 /* 285 * R20 (0x14) - Clock Rates 0 286 */ 287 #define WM8903_MCLKDIV2 288 #define WM8903_MCLKDIV2_MASK 289 #define WM8903_MCLKDIV2_SHIFT 290 #define WM8903_MCLKDIV2_WIDTH 291 292 /* 293 * R21 (0x15) - Clock Rates 1 294 */ 295 #define WM8903_CLK_SYS_RATE_MASK 296 #define WM8903_CLK_SYS_RATE_SHIFT 297 #define WM8903_CLK_SYS_RATE_WIDTH 298 #define WM8903_CLK_SYS_MODE_MASK 299 #define WM8903_CLK_SYS_MODE_SHIFT 300 #define WM8903_CLK_SYS_MODE_WIDTH 301 #define WM8903_SAMPLE_RATE_MASK 302 #define WM8903_SAMPLE_RATE_SHIFT 303 #define WM8903_SAMPLE_RATE_WIDTH 304 305 /* 306 * R22 (0x16) - Clock Rates 2 307 */ 308 #define WM8903_CLK_SYS_ENA 309 #define WM8903_CLK_SYS_ENA_MASK 310 #define WM8903_CLK_SYS_ENA_SHIFT 311 #define WM8903_CLK_SYS_ENA_WIDTH 312 #define WM8903_CLK_DSP_ENA 313 #define WM8903_CLK_DSP_ENA_MASK 314 #define WM8903_CLK_DSP_ENA_SHIFT 315 #define WM8903_CLK_DSP_ENA_WIDTH 316 #define WM8903_TO_ENA 317 #define WM8903_TO_ENA_MASK 318 #define WM8903_TO_ENA_SHIFT 319 #define WM8903_TO_ENA_WIDTH 320 321 /* 322 * R24 (0x18) - Audio Interface 0 323 */ 324 #define WM8903_DACL_DATINV 325 #define WM8903_DACL_DATINV_MASK 326 #define WM8903_DACL_DATINV_SHIFT 327 #define WM8903_DACL_DATINV_WIDTH 328 #define WM8903_DACR_DATINV 329 #define WM8903_DACR_DATINV_MASK 330 #define WM8903_DACR_DATINV_SHIFT 331 #define WM8903_DACR_DATINV_WIDTH 332 #define WM8903_DAC_BOOST_MASK 333 #define WM8903_DAC_BOOST_SHIFT 334 #define WM8903_DAC_BOOST_WIDTH 335 #define WM8903_LOOPBACK 336 #define WM8903_LOOPBACK_MASK 337 #define WM8903_LOOPBACK_SHIFT 338 #define WM8903_LOOPBACK_WIDTH 339 #define WM8903_AIFADCL_SRC 340 #define WM8903_AIFADCL_SRC_MASK 341 #define WM8903_AIFADCL_SRC_SHIFT 342 #define WM8903_AIFADCL_SRC_WIDTH 343 #define WM8903_AIFADCR_SRC 344 #define WM8903_AIFADCR_SRC_MASK 345 #define WM8903_AIFADCR_SRC_SHIFT 346 #define WM8903_AIFADCR_SRC_WIDTH 347 #define WM8903_AIFDACL_SRC 348 #define WM8903_AIFDACL_SRC_MASK 349 #define WM8903_AIFDACL_SRC_SHIFT 350 #define WM8903_AIFDACL_SRC_WIDTH 351 #define WM8903_AIFDACR_SRC 352 #define WM8903_AIFDACR_SRC_MASK 353 #define WM8903_AIFDACR_SRC_SHIFT 354 #define WM8903_AIFDACR_SRC_WIDTH 355 #define WM8903_ADC_COMP 356 #define WM8903_ADC_COMP_MASK 357 #define WM8903_ADC_COMP_SHIFT 358 #define WM8903_ADC_COMP_WIDTH 359 #define WM8903_ADC_COMPMODE 360 #define WM8903_ADC_COMPMODE_MASK 361 #define WM8903_ADC_COMPMODE_SHIFT 362 #define WM8903_ADC_COMPMODE_WIDTH 363 #define WM8903_DAC_COMP 364 #define WM8903_DAC_COMP_MASK 365 #define WM8903_DAC_COMP_SHIFT 366 #define WM8903_DAC_COMP_WIDTH 367 #define WM8903_DAC_COMPMODE 368 #define WM8903_DAC_COMPMODE_MASK 369 #define WM8903_DAC_COMPMODE_SHIFT 370 #define WM8903_DAC_COMPMODE_WIDTH 371 372 /* 373 * R25 (0x19) - Audio Interface 1 374 */ 375 #define WM8903_AIFDAC_TDM 376 #define WM8903_AIFDAC_TDM_MASK 377 #define WM8903_AIFDAC_TDM_SHIFT 378 #define WM8903_AIFDAC_TDM_WIDTH 379 #define WM8903_AIFDAC_TDM_CHAN 380 #define WM8903_AIFDAC_TDM_CHAN_MASK 381 #define WM8903_AIFDAC_TDM_CHAN_SHIFT 382 #define WM8903_AIFDAC_TDM_CHAN_WIDTH 383 #define WM8903_AIFADC_TDM 384 #define WM8903_AIFADC_TDM_MASK 385 #define WM8903_AIFADC_TDM_SHIFT 386 #define WM8903_AIFADC_TDM_WIDTH 387 #define WM8903_AIFADC_TDM_CHAN 388 #define WM8903_AIFADC_TDM_CHAN_MASK 389 #define WM8903_AIFADC_TDM_CHAN_SHIFT 390 #define WM8903_AIFADC_TDM_CHAN_WIDTH 391 #define WM8903_LRCLK_DIR 392 #define WM8903_LRCLK_DIR_MASK 393 #define WM8903_LRCLK_DIR_SHIFT 394 #define WM8903_LRCLK_DIR_WIDTH 395 #define WM8903_AIF_BCLK_INV 396 #define WM8903_AIF_BCLK_INV_MASK 397 #define WM8903_AIF_BCLK_INV_SHIFT 398 #define WM8903_AIF_BCLK_INV_WIDTH 399 #define WM8903_BCLK_DIR 400 #define WM8903_BCLK_DIR_MASK 401 #define WM8903_BCLK_DIR_SHIFT 402 #define WM8903_BCLK_DIR_WIDTH 403 #define WM8903_AIF_LRCLK_INV 404 #define WM8903_AIF_LRCLK_INV_MASK 405 #define WM8903_AIF_LRCLK_INV_SHIFT 406 #define WM8903_AIF_LRCLK_INV_WIDTH 407 #define WM8903_AIF_WL_MASK 408 #define WM8903_AIF_WL_SHIFT 409 #define WM8903_AIF_WL_WIDTH 410 #define WM8903_AIF_FMT_MASK 411 #define WM8903_AIF_FMT_SHIFT 412 #define WM8903_AIF_FMT_WIDTH 413 414 /* 415 * R26 (0x1A) - Audio Interface 2 416 */ 417 #define WM8903_BCLK_DIV_MASK 418 #define WM8903_BCLK_DIV_SHIFT 419 #define WM8903_BCLK_DIV_WIDTH 420 421 /* 422 * R27 (0x1B) - Audio Interface 3 423 */ 424 #define WM8903_LRCLK_RATE_MASK 425 #define WM8903_LRCLK_RATE_SHIFT 426 #define WM8903_LRCLK_RATE_WIDTH 427 428 /* 429 * R30 (0x1E) - DAC Digital Volume Left 430 */ 431 #define WM8903_DACVU 432 #define WM8903_DACVU_MASK 433 #define WM8903_DACVU_SHIFT 434 #define WM8903_DACVU_WIDTH 435 #define WM8903_DACL_VOL_MASK 436 #define WM8903_DACL_VOL_SHIFT 437 #define WM8903_DACL_VOL_WIDTH 438 439 /* 440 * R31 (0x1F) - DAC Digital Volume Right 441 */ 442 #define WM8903_DACVU 443 #define WM8903_DACVU_MASK 444 #define WM8903_DACVU_SHIFT 445 #define WM8903_DACVU_WIDTH 446 #define WM8903_DACR_VOL_MASK 447 #define WM8903_DACR_VOL_SHIFT 448 #define WM8903_DACR_VOL_WIDTH 449 450 /* 451 * R32 (0x20) - DAC Digital 0 452 */ 453 #define WM8903_ADCL_DAC_SVOL_MASK 454 #define WM8903_ADCL_DAC_SVOL_SHIFT 455 #define WM8903_ADCL_DAC_SVOL_WIDTH 456 #define WM8903_ADCR_DAC_SVOL_MASK 457 #define WM8903_ADCR_DAC_SVOL_SHIFT 458 #define WM8903_ADCR_DAC_SVOL_WIDTH 459 #define WM8903_ADC_TO_DACL_MASK 460 #define WM8903_ADC_TO_DACL_SHIFT 461 #define WM8903_ADC_TO_DACL_WIDTH 462 #define WM8903_ADC_TO_DACR_MASK 463 #define WM8903_ADC_TO_DACR_SHIFT 464 #define WM8903_ADC_TO_DACR_WIDTH 465 466 /* 467 * R33 (0x21) - DAC Digital 1 468 */ 469 #define WM8903_DAC_MONO 470 #define WM8903_DAC_MONO_MASK 471 #define WM8903_DAC_MONO_SHIFT 472 #define WM8903_DAC_MONO_WIDTH 473 #define WM8903_DAC_SB_FILT 474 #define WM8903_DAC_SB_FILT_MASK 475 #define WM8903_DAC_SB_FILT_SHIFT 476 #define WM8903_DAC_SB_FILT_WIDTH 477 #define WM8903_DAC_MUTERATE 478 #define WM8903_DAC_MUTERATE_MASK 479 #define WM8903_DAC_MUTERATE_SHIFT 480 #define WM8903_DAC_MUTERATE_WIDTH 481 #define WM8903_DAC_MUTEMODE 482 #define WM8903_DAC_MUTEMODE_MASK 483 #define WM8903_DAC_MUTEMODE_SHIFT 484 #define WM8903_DAC_MUTEMODE_WIDTH 485 #define WM8903_DAC_MUTE 486 #define WM8903_DAC_MUTE_MASK 487 #define WM8903_DAC_MUTE_SHIFT 488 #define WM8903_DAC_MUTE_WIDTH 489 #define WM8903_DEEMPH_MASK 490 #define WM8903_DEEMPH_SHIFT 491 #define WM8903_DEEMPH_WIDTH 492 493 /* 494 * R36 (0x24) - ADC Digital Volume Left 495 */ 496 #define WM8903_ADCVU 497 #define WM8903_ADCVU_MASK 498 #define WM8903_ADCVU_SHIFT 499 #define WM8903_ADCVU_WIDTH 500 #define WM8903_ADCL_VOL_MASK 501 #define WM8903_ADCL_VOL_SHIFT 502 #define WM8903_ADCL_VOL_WIDTH 503 504 /* 505 * R37 (0x25) - ADC Digital Volume Right 506 */ 507 #define WM8903_ADCVU 508 #define WM8903_ADCVU_MASK 509 #define WM8903_ADCVU_SHIFT 510 #define WM8903_ADCVU_WIDTH 511 #define WM8903_ADCR_VOL_MASK 512 #define WM8903_ADCR_VOL_SHIFT 513 #define WM8903_ADCR_VOL_WIDTH 514 515 /* 516 * R38 (0x26) - ADC Digital 0 517 */ 518 #define WM8903_ADC_HPF_CUT_MASK 519 #define WM8903_ADC_HPF_CUT_SHIFT 520 #define WM8903_ADC_HPF_CUT_WIDTH 521 #define WM8903_ADC_HPF_ENA 522 #define WM8903_ADC_HPF_ENA_MASK 523 #define WM8903_ADC_HPF_ENA_SHIFT 524 #define WM8903_ADC_HPF_ENA_WIDTH 525 #define WM8903_ADCL_DATINV 526 #define WM8903_ADCL_DATINV_MASK 527 #define WM8903_ADCL_DATINV_SHIFT 528 #define WM8903_ADCL_DATINV_WIDTH 529 #define WM8903_ADCR_DATINV 530 #define WM8903_ADCR_DATINV_MASK 531 #define WM8903_ADCR_DATINV_SHIFT 532 #define WM8903_ADCR_DATINV_WIDTH 533 534 /* 535 * R39 (0x27) - Digital Microphone 0 536 */ 537 #define WM8903_DIGMIC_MODE_SEL 538 #define WM8903_DIGMIC_MODE_SEL_MASK 539 #define WM8903_DIGMIC_MODE_SEL_SHIFT 540 #define WM8903_DIGMIC_MODE_SEL_WIDTH 541 #define WM8903_DIGMIC_CLK_SEL_L_MASK 542 #define WM8903_DIGMIC_CLK_SEL_L_SHIFT 543 #define WM8903_DIGMIC_CLK_SEL_L_WIDTH 544 #define WM8903_DIGMIC_CLK_SEL_R_MASK 545 #define WM8903_DIGMIC_CLK_SEL_R_SHIFT 546 #define WM8903_DIGMIC_CLK_SEL_R_WIDTH 547 #define WM8903_DIGMIC_CLK_SEL_RT_MASK 548 #define WM8903_DIGMIC_CLK_SEL_RT_SHIFT 549 #define WM8903_DIGMIC_CLK_SEL_RT_WIDTH 550 #define WM8903_DIGMIC_CLK_SEL_MASK 551 #define WM8903_DIGMIC_CLK_SEL_SHIFT 552 #define WM8903_DIGMIC_CLK_SEL_WIDTH 553 554 /* 555 * R40 (0x28) - DRC 0 556 */ 557 #define WM8903_DRC_ENA 558 #define WM8903_DRC_ENA_MASK 559 #define WM8903_DRC_ENA_SHIFT 560 #define WM8903_DRC_ENA_WIDTH 561 #define WM8903_DRC_THRESH_HYST_MASK 562 #define WM8903_DRC_THRESH_HYST_SHIFT 563 #define WM8903_DRC_THRESH_HYST_WIDTH 564 #define WM8903_DRC_STARTUP_GAIN_MASK 565 #define WM8903_DRC_STARTUP_GAIN_SHIFT 566 #define WM8903_DRC_STARTUP_GAIN_WIDTH 567 #define WM8903_DRC_FF_DELAY 568 #define WM8903_DRC_FF_DELAY_MASK 569 #define WM8903_DRC_FF_DELAY_SHIFT 570 #define WM8903_DRC_FF_DELAY_WIDTH 571 #define WM8903_DRC_SMOOTH_ENA 572 #define WM8903_DRC_SMOOTH_ENA_MASK 573 #define WM8903_DRC_SMOOTH_ENA_SHIFT 574 #define WM8903_DRC_SMOOTH_ENA_WIDTH 575 #define WM8903_DRC_QR_ENA 576 #define WM8903_DRC_QR_ENA_MASK 577 #define WM8903_DRC_QR_ENA_SHIFT 578 #define WM8903_DRC_QR_ENA_WIDTH 579 #define WM8903_DRC_ANTICLIP_ENA 580 #define WM8903_DRC_ANTICLIP_ENA_MASK 581 #define WM8903_DRC_ANTICLIP_ENA_SHIFT 582 #define WM8903_DRC_ANTICLIP_ENA_WIDTH 583 #define WM8903_DRC_HYST_ENA 584 #define WM8903_DRC_HYST_ENA_MASK 585 #define WM8903_DRC_HYST_ENA_SHIFT 586 #define WM8903_DRC_HYST_ENA_WIDTH 587 588 /* 589 * R41 (0x29) - DRC 1 590 */ 591 #define WM8903_DRC_ATTACK_RATE_MASK 592 #define WM8903_DRC_ATTACK_RATE_SHIFT 593 #define WM8903_DRC_ATTACK_RATE_WIDTH 594 #define WM8903_DRC_DECAY_RATE_MASK 595 #define WM8903_DRC_DECAY_RATE_SHIFT 596 #define WM8903_DRC_DECAY_RATE_WIDTH 597 #define WM8903_DRC_THRESH_QR_MASK 598 #define WM8903_DRC_THRESH_QR_SHIFT 599 #define WM8903_DRC_THRESH_QR_WIDTH 600 #define WM8903_DRC_RATE_QR_MASK 601 #define WM8903_DRC_RATE_QR_SHIFT 602 #define WM8903_DRC_RATE_QR_WIDTH 603 #define WM8903_DRC_MINGAIN_MASK 604 #define WM8903_DRC_MINGAIN_SHIFT 605 #define WM8903_DRC_MINGAIN_WIDTH 606 #define WM8903_DRC_MAXGAIN_MASK 607 #define WM8903_DRC_MAXGAIN_SHIFT 608 #define WM8903_DRC_MAXGAIN_WIDTH 609 610 /* 611 * R42 (0x2A) - DRC 2 612 */ 613 #define WM8903_DRC_R0_SLOPE_COMP_MASK 614 #define WM8903_DRC_R0_SLOPE_COMP_SHIFT 615 #define WM8903_DRC_R0_SLOPE_COMP_WIDTH 616 #define WM8903_DRC_R1_SLOPE_COMP_MASK 617 #define WM8903_DRC_R1_SLOPE_COMP_SHIFT 618 #define WM8903_DRC_R1_SLOPE_COMP_WIDTH 619 620 /* 621 * R43 (0x2B) - DRC 3 622 */ 623 #define WM8903_DRC_THRESH_COMP_MASK 624 #define WM8903_DRC_THRESH_COMP_SHIFT 625 #define WM8903_DRC_THRESH_COMP_WIDTH 626 #define WM8903_DRC_AMP_COMP_MASK 627 #define WM8903_DRC_AMP_COMP_SHIFT 628 #define WM8903_DRC_AMP_COMP_WIDTH 629 630 /* 631 * R44 (0x2C) - Analogue Left Input 0 632 */ 633 #define WM8903_LINMUTE 634 #define WM8903_LINMUTE_MASK 635 #define WM8903_LINMUTE_SHIFT 636 #define WM8903_LINMUTE_WIDTH 637 #define WM8903_LIN_VOL_MASK 638 #define WM8903_LIN_VOL_SHIFT 639 #define WM8903_LIN_VOL_WIDTH 640 641 /* 642 * R45 (0x2D) - Analogue Right Input 0 643 */ 644 #define WM8903_RINMUTE 645 #define WM8903_RINMUTE_MASK 646 #define WM8903_RINMUTE_SHIFT 647 #define WM8903_RINMUTE_WIDTH 648 #define WM8903_RIN_VOL_MASK 649 #define WM8903_RIN_VOL_SHIFT 650 #define WM8903_RIN_VOL_WIDTH 651 652 /* 653 * R46 (0x2E) - Analogue Left Input 1 654 */ 655 #define WM8903_INL_CM_ENA 656 #define WM8903_INL_CM_ENA_MASK 657 #define WM8903_INL_CM_ENA_SHIFT 658 #define WM8903_INL_CM_ENA_WIDTH 659 #define WM8903_L_IP_SEL_N_MASK 660 #define WM8903_L_IP_SEL_N_SHIFT 661 #define WM8903_L_IP_SEL_N_WIDTH 662 #define WM8903_L_IP_SEL_P_MASK 663 #define WM8903_L_IP_SEL_P_SHIFT 664 #define WM8903_L_IP_SEL_P_WIDTH 665 #define WM8903_L_MODE_MASK 666 #define WM8903_L_MODE_SHIFT 667 #define WM8903_L_MODE_WIDTH 668 669 /* 670 * R47 (0x2F) - Analogue Right Input 1 671 */ 672 #define WM8903_INR_CM_ENA 673 #define WM8903_INR_CM_ENA_MASK 674 #define WM8903_INR_CM_ENA_SHIFT 675 #define WM8903_INR_CM_ENA_WIDTH 676 #define WM8903_R_IP_SEL_N_MASK 677 #define WM8903_R_IP_SEL_N_SHIFT 678 #define WM8903_R_IP_SEL_N_WIDTH 679 #define WM8903_R_IP_SEL_P_MASK 680 #define WM8903_R_IP_SEL_P_SHIFT 681 #define WM8903_R_IP_SEL_P_WIDTH 682 #define WM8903_R_MODE_MASK 683 #define WM8903_R_MODE_SHIFT 684 #define WM8903_R_MODE_WIDTH 685 686 /* 687 * R50 (0x32) - Analogue Left Mix 0 688 */ 689 #define WM8903_DACL_TO_MIXOUTL 690 #define WM8903_DACL_TO_MIXOUTL_MASK 691 #define WM8903_DACL_TO_MIXOUTL_SHIFT 692 #define WM8903_DACL_TO_MIXOUTL_WIDTH 693 #define WM8903_DACR_TO_MIXOUTL 694 #define WM8903_DACR_TO_MIXOUTL_MASK 695 #define WM8903_DACR_TO_MIXOUTL_SHIFT 696 #define WM8903_DACR_TO_MIXOUTL_WIDTH 697 #define WM8903_BYPASSL_TO_MIXOUTL 698 #define WM8903_BYPASSL_TO_MIXOUTL_MASK 699 #define WM8903_BYPASSL_TO_MIXOUTL_SHIFT 700 #define WM8903_BYPASSL_TO_MIXOUTL_WIDTH 701 #define WM8903_BYPASSR_TO_MIXOUTL 702 #define WM8903_BYPASSR_TO_MIXOUTL_MASK 703 #define WM8903_BYPASSR_TO_MIXOUTL_SHIFT 704 #define WM8903_BYPASSR_TO_MIXOUTL_WIDTH 705 706 /* 707 * R51 (0x33) - Analogue Right Mix 0 708 */ 709 #define WM8903_DACL_TO_MIXOUTR 710 #define WM8903_DACL_TO_MIXOUTR_MASK 711 #define WM8903_DACL_TO_MIXOUTR_SHIFT 712 #define WM8903_DACL_TO_MIXOUTR_WIDTH 713 #define WM8903_DACR_TO_MIXOUTR 714 #define WM8903_DACR_TO_MIXOUTR_MASK 715 #define WM8903_DACR_TO_MIXOUTR_SHIFT 716 #define WM8903_DACR_TO_MIXOUTR_WIDTH 717 #define WM8903_BYPASSL_TO_MIXOUTR 718 #define WM8903_BYPASSL_TO_MIXOUTR_MASK 719 #define WM8903_BYPASSL_TO_MIXOUTR_SHIFT 720 #define WM8903_BYPASSL_TO_MIXOUTR_WIDTH 721 #define WM8903_BYPASSR_TO_MIXOUTR 722 #define WM8903_BYPASSR_TO_MIXOUTR_MASK 723 #define WM8903_BYPASSR_TO_MIXOUTR_SHIFT 724 #define WM8903_BYPASSR_TO_MIXOUTR_WIDTH 725 726 /* 727 * R52 (0x34) - Analogue Spk Mix Left 0 728 */ 729 #define WM8903_DACL_TO_MIXSPKL 730 #define WM8903_DACL_TO_MIXSPKL_MASK 731 #define WM8903_DACL_TO_MIXSPKL_SHIFT 732 #define WM8903_DACL_TO_MIXSPKL_WIDTH 733 #define WM8903_DACR_TO_MIXSPKL 734 #define WM8903_DACR_TO_MIXSPKL_MASK 735 #define WM8903_DACR_TO_MIXSPKL_SHIFT 736 #define WM8903_DACR_TO_MIXSPKL_WIDTH 737 #define WM8903_BYPASSL_TO_MIXSPKL 738 #define WM8903_BYPASSL_TO_MIXSPKL_MASK 739 #define WM8903_BYPASSL_TO_MIXSPKL_SHIFT 740 #define WM8903_BYPASSL_TO_MIXSPKL_WIDTH 741 #define WM8903_BYPASSR_TO_MIXSPKL 742 #define WM8903_BYPASSR_TO_MIXSPKL_MASK 743 #define WM8903_BYPASSR_TO_MIXSPKL_SHIFT 744 #define WM8903_BYPASSR_TO_MIXSPKL_WIDTH 745 746 /* 747 * R53 (0x35) - Analogue Spk Mix Left 1 748 */ 749 #define WM8903_DACL_MIXSPKL_VOL 750 #define WM8903_DACL_MIXSPKL_VOL_MASK 751 #define WM8903_DACL_MIXSPKL_VOL_SHIFT 752 #define WM8903_DACL_MIXSPKL_VOL_WIDTH 753 #define WM8903_DACR_MIXSPKL_VOL 754 #define WM8903_DACR_MIXSPKL_VOL_MASK 755 #define WM8903_DACR_MIXSPKL_VOL_SHIFT 756 #define WM8903_DACR_MIXSPKL_VOL_WIDTH 757 #define WM8903_BYPASSL_MIXSPKL_VOL 758 #define WM8903_BYPASSL_MIXSPKL_VOL_MASK 759 #define WM8903_BYPASSL_MIXSPKL_VOL_SHIFT 760 #define WM8903_BYPASSL_MIXSPKL_VOL_WIDTH 761 #define WM8903_BYPASSR_MIXSPKL_VOL 762 #define WM8903_BYPASSR_MIXSPKL_VOL_MASK 763 #define WM8903_BYPASSR_MIXSPKL_VOL_SHIFT 764 #define WM8903_BYPASSR_MIXSPKL_VOL_WIDTH 765 766 /* 767 * R54 (0x36) - Analogue Spk Mix Right 0 768 */ 769 #define WM8903_DACL_TO_MIXSPKR 770 #define WM8903_DACL_TO_MIXSPKR_MASK 771 #define WM8903_DACL_TO_MIXSPKR_SHIFT 772 #define WM8903_DACL_TO_MIXSPKR_WIDTH 773 #define WM8903_DACR_TO_MIXSPKR 774 #define WM8903_DACR_TO_MIXSPKR_MASK 775 #define WM8903_DACR_TO_MIXSPKR_SHIFT 776 #define WM8903_DACR_TO_MIXSPKR_WIDTH 777 #define WM8903_BYPASSL_TO_MIXSPKR 778 #define WM8903_BYPASSL_TO_MIXSPKR_MASK 779 #define WM8903_BYPASSL_TO_MIXSPKR_SHIFT 780 #define WM8903_BYPASSL_TO_MIXSPKR_WIDTH 781 #define WM8903_BYPASSR_TO_MIXSPKR 782 #define WM8903_BYPASSR_TO_MIXSPKR_MASK 783 #define WM8903_BYPASSR_TO_MIXSPKR_SHIFT 784 #define WM8903_BYPASSR_TO_MIXSPKR_WIDTH 785 786 /* 787 * R55 (0x37) - Analogue Spk Mix Right 1 788 */ 789 #define WM8903_DACL_MIXSPKR_VOL 790 #define WM8903_DACL_MIXSPKR_VOL_MASK 791 #define WM8903_DACL_MIXSPKR_VOL_SHIFT 792 #define WM8903_DACL_MIXSPKR_VOL_WIDTH 793 #define WM8903_DACR_MIXSPKR_VOL 794 #define WM8903_DACR_MIXSPKR_VOL_MASK 795 #define WM8903_DACR_MIXSPKR_VOL_SHIFT 796 #define WM8903_DACR_MIXSPKR_VOL_WIDTH 797 #define WM8903_BYPASSL_MIXSPKR_VOL 798 #define WM8903_BYPASSL_MIXSPKR_VOL_MASK 799 #define WM8903_BYPASSL_MIXSPKR_VOL_SHIFT 800 #define WM8903_BYPASSL_MIXSPKR_VOL_WIDTH 801 #define WM8903_BYPASSR_MIXSPKR_VOL 802 #define WM8903_BYPASSR_MIXSPKR_VOL_MASK 803 #define WM8903_BYPASSR_MIXSPKR_VOL_SHIFT 804 #define WM8903_BYPASSR_MIXSPKR_VOL_WIDTH 805 806 /* 807 * R57 (0x39) - Analogue OUT1 Left 808 */ 809 #define WM8903_HPL_MUTE 810 #define WM8903_HPL_MUTE_MASK 811 #define WM8903_HPL_MUTE_SHIFT 812 #define WM8903_HPL_MUTE_WIDTH 813 #define WM8903_HPOUTVU 814 #define WM8903_HPOUTVU_MASK 815 #define WM8903_HPOUTVU_SHIFT 816 #define WM8903_HPOUTVU_WIDTH 817 #define WM8903_HPOUTLZC 818 #define WM8903_HPOUTLZC_MASK 819 #define WM8903_HPOUTLZC_SHIFT 820 #define WM8903_HPOUTLZC_WIDTH 821 #define WM8903_HPOUTL_VOL_MASK 822 #define WM8903_HPOUTL_VOL_SHIFT 823 #define WM8903_HPOUTL_VOL_WIDTH 824 825 /* 826 * R58 (0x3A) - Analogue OUT1 Right 827 */ 828 #define WM8903_HPR_MUTE 829 #define WM8903_HPR_MUTE_MASK 830 #define WM8903_HPR_MUTE_SHIFT 831 #define WM8903_HPR_MUTE_WIDTH 832 #define WM8903_HPOUTVU 833 #define WM8903_HPOUTVU_MASK 834 #define WM8903_HPOUTVU_SHIFT 835 #define WM8903_HPOUTVU_WIDTH 836 #define WM8903_HPOUTRZC 837 #define WM8903_HPOUTRZC_MASK 838 #define WM8903_HPOUTRZC_SHIFT 839 #define WM8903_HPOUTRZC_WIDTH 840 #define WM8903_HPOUTR_VOL_MASK 841 #define WM8903_HPOUTR_VOL_SHIFT 842 #define WM8903_HPOUTR_VOL_WIDTH 843 844 /* 845 * R59 (0x3B) - Analogue OUT2 Left 846 */ 847 #define WM8903_LINEOUTL_MUTE 848 #define WM8903_LINEOUTL_MUTE_MASK 849 #define WM8903_LINEOUTL_MUTE_SHIFT 850 #define WM8903_LINEOUTL_MUTE_WIDTH 851 #define WM8903_LINEOUTVU 852 #define WM8903_LINEOUTVU_MASK 853 #define WM8903_LINEOUTVU_SHIFT 854 #define WM8903_LINEOUTVU_WIDTH 855 #define WM8903_LINEOUTLZC 856 #define WM8903_LINEOUTLZC_MASK 857 #define WM8903_LINEOUTLZC_SHIFT 858 #define WM8903_LINEOUTLZC_WIDTH 859 #define WM8903_LINEOUTL_VOL_MASK 860 #define WM8903_LINEOUTL_VOL_SHIFT 861 #define WM8903_LINEOUTL_VOL_WIDTH 862 863 /* 864 * R60 (0x3C) - Analogue OUT2 Right 865 */ 866 #define WM8903_LINEOUTR_MUTE 867 #define WM8903_LINEOUTR_MUTE_MASK 868 #define WM8903_LINEOUTR_MUTE_SHIFT 869 #define WM8903_LINEOUTR_MUTE_WIDTH 870 #define WM8903_LINEOUTVU 871 #define WM8903_LINEOUTVU_MASK 872 #define WM8903_LINEOUTVU_SHIFT 873 #define WM8903_LINEOUTVU_WIDTH 874 #define WM8903_LINEOUTRZC 875 #define WM8903_LINEOUTRZC_MASK 876 #define WM8903_LINEOUTRZC_SHIFT 877 #define WM8903_LINEOUTRZC_WIDTH 878 #define WM8903_LINEOUTR_VOL_MASK 879 #define WM8903_LINEOUTR_VOL_SHIFT 880 #define WM8903_LINEOUTR_VOL_WIDTH 881 882 /* 883 * R62 (0x3E) - Analogue OUT3 Left 884 */ 885 #define WM8903_SPKL_MUTE 886 #define WM8903_SPKL_MUTE_MASK 887 #define WM8903_SPKL_MUTE_SHIFT 888 #define WM8903_SPKL_MUTE_WIDTH 889 #define WM8903_SPKVU 890 #define WM8903_SPKVU_MASK 891 #define WM8903_SPKVU_SHIFT 892 #define WM8903_SPKVU_WIDTH 893 #define WM8903_SPKLZC 894 #define WM8903_SPKLZC_MASK 895 #define WM8903_SPKLZC_SHIFT 896 #define WM8903_SPKLZC_WIDTH 897 #define WM8903_SPKL_VOL_MASK 898 #define WM8903_SPKL_VOL_SHIFT 899 #define WM8903_SPKL_VOL_WIDTH 900 901 /* 902 * R63 (0x3F) - Analogue OUT3 Right 903 */ 904 #define WM8903_SPKR_MUTE 905 #define WM8903_SPKR_MUTE_MASK 906 #define WM8903_SPKR_MUTE_SHIFT 907 #define WM8903_SPKR_MUTE_WIDTH 908 #define WM8903_SPKVU 909 #define WM8903_SPKVU_MASK 910 #define WM8903_SPKVU_SHIFT 911 #define WM8903_SPKVU_WIDTH 912 #define WM8903_SPKRZC 913 #define WM8903_SPKRZC_MASK 914 #define WM8903_SPKRZC_SHIFT 915 #define WM8903_SPKRZC_WIDTH 916 #define WM8903_SPKR_VOL_MASK 917 #define WM8903_SPKR_VOL_SHIFT 918 #define WM8903_SPKR_VOL_WIDTH 919 920 /* 921 * R65 (0x41) - Analogue SPK Output Control 0 922 */ 923 #define WM8903_SPK_DISCHARGE 924 #define WM8903_SPK_DISCHARGE_MASK 925 #define WM8903_SPK_DISCHARGE_SHIFT 926 #define WM8903_SPK_DISCHARGE_WIDTH 927 #define WM8903_VROI 928 #define WM8903_VROI_MASK 929 #define WM8903_VROI_SHIFT 930 #define WM8903_VROI_WIDTH 931 932 /* 933 * R67 (0x43) - DC Servo 0 934 */ 935 #define WM8903_DCS_MASTER_ENA 936 #define WM8903_DCS_MASTER_ENA_MASK 937 #define WM8903_DCS_MASTER_ENA_SHIFT 938 #define WM8903_DCS_MASTER_ENA_WIDTH 939 #define WM8903_DCS_ENA_MASK 940 #define WM8903_DCS_ENA_SHIFT 941 #define WM8903_DCS_ENA_WIDTH 942 943 /* 944 * R69 (0x45) - DC Servo 2 945 */ 946 #define WM8903_DCS_MODE_MASK 947 #define WM8903_DCS_MODE_SHIFT 948 #define WM8903_DCS_MODE_WIDTH 949 950 /* 951 * R90 (0x5A) - Analogue HP 0 952 */ 953 #define WM8903_HPL_RMV_SHORT 954 #define WM8903_HPL_RMV_SHORT_MASK 955 #define WM8903_HPL_RMV_SHORT_SHIFT 956 #define WM8903_HPL_RMV_SHORT_WIDTH 957 #define WM8903_HPL_ENA_OUTP 958 #define WM8903_HPL_ENA_OUTP_MASK 959 #define WM8903_HPL_ENA_OUTP_SHIFT 960 #define WM8903_HPL_ENA_OUTP_WIDTH 961 #define WM8903_HPL_ENA_DLY 962 #define WM8903_HPL_ENA_DLY_MASK 963 #define WM8903_HPL_ENA_DLY_SHIFT 964 #define WM8903_HPL_ENA_DLY_WIDTH 965 #define WM8903_HPL_ENA 966 #define WM8903_HPL_ENA_MASK 967 #define WM8903_HPL_ENA_SHIFT 968 #define WM8903_HPL_ENA_WIDTH 969 #define WM8903_HPR_RMV_SHORT 970 #define WM8903_HPR_RMV_SHORT_MASK 971 #define WM8903_HPR_RMV_SHORT_SHIFT 972 #define WM8903_HPR_RMV_SHORT_WIDTH 973 #define WM8903_HPR_ENA_OUTP 974 #define WM8903_HPR_ENA_OUTP_MASK 975 #define WM8903_HPR_ENA_OUTP_SHIFT 976 #define WM8903_HPR_ENA_OUTP_WIDTH 977 #define WM8903_HPR_ENA_DLY 978 #define WM8903_HPR_ENA_DLY_MASK 979 #define WM8903_HPR_ENA_DLY_SHIFT 980 #define WM8903_HPR_ENA_DLY_WIDTH 981 #define WM8903_HPR_ENA 982 #define WM8903_HPR_ENA_MASK 983 #define WM8903_HPR_ENA_SHIFT 984 #define WM8903_HPR_ENA_WIDTH 985 986 /* 987 * R94 (0x5E) - Analogue Lineout 0 988 */ 989 #define WM8903_LINEOUTL_RMV_SHORT 990 #define WM8903_LINEOUTL_RMV_SHORT_MASK 991 #define WM8903_LINEOUTL_RMV_SHORT_SHIFT 992 #define WM8903_LINEOUTL_RMV_SHORT_WIDTH 993 #define WM8903_LINEOUTL_ENA_OUTP 994 #define WM8903_LINEOUTL_ENA_OUTP_MASK 995 #define WM8903_LINEOUTL_ENA_OUTP_SHIFT 996 #define WM8903_LINEOUTL_ENA_OUTP_WIDTH 997 #define WM8903_LINEOUTL_ENA_DLY 998 #define WM8903_LINEOUTL_ENA_DLY_MASK 999 #define WM8903_LINEOUTL_ENA_DLY_SHIFT 1000 #define WM8903_LINEOUTL_ENA_DLY_WIDTH 1001 #define WM8903_LINEOUTL_ENA 1002 #define WM8903_LINEOUTL_ENA_MASK 1003 #define WM8903_LINEOUTL_ENA_SHIFT 1004 #define WM8903_LINEOUTL_ENA_WIDTH 1005 #define WM8903_LINEOUTR_RMV_SHORT 1006 #define WM8903_LINEOUTR_RMV_SHORT_MASK 1007 #define WM8903_LINEOUTR_RMV_SHORT_SHIFT 1008 #define WM8903_LINEOUTR_RMV_SHORT_WIDTH 1009 #define WM8903_LINEOUTR_ENA_OUTP 1010 #define WM8903_LINEOUTR_ENA_OUTP_MASK 1011 #define WM8903_LINEOUTR_ENA_OUTP_SHIFT 1012 #define WM8903_LINEOUTR_ENA_OUTP_WIDTH 1013 #define WM8903_LINEOUTR_ENA_DLY 1014 #define WM8903_LINEOUTR_ENA_DLY_MASK 1015 #define WM8903_LINEOUTR_ENA_DLY_SHIFT 1016 #define WM8903_LINEOUTR_ENA_DLY_WIDTH 1017 #define WM8903_LINEOUTR_ENA 1018 #define WM8903_LINEOUTR_ENA_MASK 1019 #define WM8903_LINEOUTR_ENA_SHIFT 1020 #define WM8903_LINEOUTR_ENA_WIDTH 1021 1022 /* 1023 * R98 (0x62) - Charge Pump 0 1024 */ 1025 #define WM8903_CP_ENA 1026 #define WM8903_CP_ENA_MASK 1027 #define WM8903_CP_ENA_SHIFT 1028 #define WM8903_CP_ENA_WIDTH 1029 1030 /* 1031 * R104 (0x68) - Class W 0 1032 */ 1033 #define WM8903_CP_DYN_FREQ 1034 #define WM8903_CP_DYN_FREQ_MASK 1035 #define WM8903_CP_DYN_FREQ_SHIFT 1036 #define WM8903_CP_DYN_FREQ_WIDTH 1037 #define WM8903_CP_DYN_V 1038 #define WM8903_CP_DYN_V_MASK 1039 #define WM8903_CP_DYN_V_SHIFT 1040 #define WM8903_CP_DYN_V_WIDTH 1041 1042 /* 1043 * R108 (0x6C) - Write Sequencer 0 1044 */ 1045 #define WM8903_WSEQ_ENA 1046 #define WM8903_WSEQ_ENA_MASK 1047 #define WM8903_WSEQ_ENA_SHIFT 1048 #define WM8903_WSEQ_ENA_WIDTH 1049 #define WM8903_WSEQ_WRITE_INDEX_MASK 1050 #define WM8903_WSEQ_WRITE_INDEX_SHIFT 1051 #define WM8903_WSEQ_WRITE_INDEX_WIDTH 1052 1053 /* 1054 * R109 (0x6D) - Write Sequencer 1 1055 */ 1056 #define WM8903_WSEQ_DATA_WIDTH_MASK 1057 #define WM8903_WSEQ_DATA_WIDTH_SHIFT 1058 #define WM8903_WSEQ_DATA_WIDTH_WIDTH 1059 #define WM8903_WSEQ_DATA_START_MASK 1060 #define WM8903_WSEQ_DATA_START_SHIFT 1061 #define WM8903_WSEQ_DATA_START_WIDTH 1062 #define WM8903_WSEQ_ADDR_MASK 1063 #define WM8903_WSEQ_ADDR_SHIFT 1064 #define WM8903_WSEQ_ADDR_WIDTH 1065 1066 /* 1067 * R110 (0x6E) - Write Sequencer 2 1068 */ 1069 #define WM8903_WSEQ_EOS 1070 #define WM8903_WSEQ_EOS_MASK 1071 #define WM8903_WSEQ_EOS_SHIFT 1072 #define WM8903_WSEQ_EOS_WIDTH 1073 #define WM8903_WSEQ_DELAY_MASK 1074 #define WM8903_WSEQ_DELAY_SHIFT 1075 #define WM8903_WSEQ_DELAY_WIDTH 1076 #define WM8903_WSEQ_DATA_MASK 1077 #define WM8903_WSEQ_DATA_SHIFT 1078 #define WM8903_WSEQ_DATA_WIDTH 1079 1080 /* 1081 * R111 (0x6F) - Write Sequencer 3 1082 */ 1083 #define WM8903_WSEQ_ABORT 1084 #define WM8903_WSEQ_ABORT_MASK 1085 #define WM8903_WSEQ_ABORT_SHIFT 1086 #define WM8903_WSEQ_ABORT_WIDTH 1087 #define WM8903_WSEQ_START 1088 #define WM8903_WSEQ_START_MASK 1089 #define WM8903_WSEQ_START_SHIFT 1090 #define WM8903_WSEQ_START_WIDTH 1091 #define WM8903_WSEQ_START_INDEX_MASK 1092 #define WM8903_WSEQ_START_INDEX_SHIFT 1093 #define WM8903_WSEQ_START_INDEX_WIDTH 1094 1095 /* 1096 * R112 (0x70) - Write Sequencer 4 1097 */ 1098 #define WM8903_WSEQ_CURRENT_INDEX_MASK 1099 #define WM8903_WSEQ_CURRENT_INDEX_SHIFT 1100 #define WM8903_WSEQ_CURRENT_INDEX_WIDTH 1101 #define WM8903_WSEQ_BUSY 1102 #define WM8903_WSEQ_BUSY_MASK 1103 #define WM8903_WSEQ_BUSY_SHIFT 1104 #define WM8903_WSEQ_BUSY_WIDTH 1105 1106 /* 1107 * R114 (0x72) - Control Interface 1108 */ 1109 #define WM8903_MASK_WRITE_ENA 1110 #define WM8903_MASK_WRITE_ENA_MASK 1111 #define WM8903_MASK_WRITE_ENA_SHIFT 1112 #define WM8903_MASK_WRITE_ENA_WIDTH 1113 1114 /* 1115 * R121 (0x79) - Interrupt Status 1 1116 */ 1117 #define WM8903_MICSHRT_EINT 1118 #define WM8903_MICSHRT_EINT_MASK 1119 #define WM8903_MICSHRT_EINT_SHIFT 1120 #define WM8903_MICSHRT_EINT_WIDTH 1121 #define WM8903_MICDET_EINT 1122 #define WM8903_MICDET_EINT_MASK 1123 #define WM8903_MICDET_EINT_SHIFT 1124 #define WM8903_MICDET_EINT_WIDTH 1125 #define WM8903_WSEQ_BUSY_EINT 1126 #define WM8903_WSEQ_BUSY_EINT_MASK 1127 #define WM8903_WSEQ_BUSY_EINT_SHIFT 1128 #define WM8903_WSEQ_BUSY_EINT_WIDTH 1129 #define WM8903_GP5_EINT 1130 #define WM8903_GP5_EINT_MASK 1131 #define WM8903_GP5_EINT_SHIFT 1132 #define WM8903_GP5_EINT_WIDTH 1133 #define WM8903_GP4_EINT 1134 #define WM8903_GP4_EINT_MASK 1135 #define WM8903_GP4_EINT_SHIFT 1136 #define WM8903_GP4_EINT_WIDTH 1137 #define WM8903_GP3_EINT 1138 #define WM8903_GP3_EINT_MASK 1139 #define WM8903_GP3_EINT_SHIFT 1140 #define WM8903_GP3_EINT_WIDTH 1141 #define WM8903_GP2_EINT 1142 #define WM8903_GP2_EINT_MASK 1143 #define WM8903_GP2_EINT_SHIFT 1144 #define WM8903_GP2_EINT_WIDTH 1145 #define WM8903_GP1_EINT 1146 #define WM8903_GP1_EINT_MASK 1147 #define WM8903_GP1_EINT_SHIFT 1148 #define WM8903_GP1_EINT_WIDTH 1149 1150 /* 1151 * R122 (0x7A) - Interrupt Status 1 Mask 1152 */ 1153 #define WM8903_IM_MICSHRT_EINT 1154 #define WM8903_IM_MICSHRT_EINT_MASK 1155 #define WM8903_IM_MICSHRT_EINT_SHIFT 1156 #define WM8903_IM_MICSHRT_EINT_WIDTH 1157 #define WM8903_IM_MICDET_EINT 1158 #define WM8903_IM_MICDET_EINT_MASK 1159 #define WM8903_IM_MICDET_EINT_SHIFT 1160 #define WM8903_IM_MICDET_EINT_WIDTH 1161 #define WM8903_IM_WSEQ_BUSY_EINT 1162 #define WM8903_IM_WSEQ_BUSY_EINT_MASK 1163 #define WM8903_IM_WSEQ_BUSY_EINT_SHIFT 1164 #define WM8903_IM_WSEQ_BUSY_EINT_WIDTH 1165 #define WM8903_IM_GP5_EINT 1166 #define WM8903_IM_GP5_EINT_MASK 1167 #define WM8903_IM_GP5_EINT_SHIFT 1168 #define WM8903_IM_GP5_EINT_WIDTH 1169 #define WM8903_IM_GP4_EINT 1170 #define WM8903_IM_GP4_EINT_MASK 1171 #define WM8903_IM_GP4_EINT_SHIFT 1172 #define WM8903_IM_GP4_EINT_WIDTH 1173 #define WM8903_IM_GP3_EINT 1174 #define WM8903_IM_GP3_EINT_MASK 1175 #define WM8903_IM_GP3_EINT_SHIFT 1176 #define WM8903_IM_GP3_EINT_WIDTH 1177 #define WM8903_IM_GP2_EINT 1178 #define WM8903_IM_GP2_EINT_MASK 1179 #define WM8903_IM_GP2_EINT_SHIFT 1180 #define WM8903_IM_GP2_EINT_WIDTH 1181 #define WM8903_IM_GP1_EINT 1182 #define WM8903_IM_GP1_EINT_MASK 1183 #define WM8903_IM_GP1_EINT_SHIFT 1184 #define WM8903_IM_GP1_EINT_WIDTH 1185 1186 /* 1187 * R123 (0x7B) - Interrupt Polarity 1 1188 */ 1189 #define WM8903_MICSHRT_INV 1190 #define WM8903_MICSHRT_INV_MASK 1191 #define WM8903_MICSHRT_INV_SHIFT 1192 #define WM8903_MICSHRT_INV_WIDTH 1193 #define WM8903_MICDET_INV 1194 #define WM8903_MICDET_INV_MASK 1195 #define WM8903_MICDET_INV_SHIFT 1196 #define WM8903_MICDET_INV_WIDTH 1197 1198 /* 1199 * R126 (0x7E) - Interrupt Control 1200 */ 1201 #define WM8903_IRQ_POL 1202 #define WM8903_IRQ_POL_MASK 1203 #define WM8903_IRQ_POL_SHIFT 1204 #define WM8903_IRQ_POL_WIDTH 1205 1206 /* 1207 * R164 (0xA4) - Clock Rate Test 4 1208 */ 1209 #define WM8903_ADC_DIG_MIC 1210 #define WM8903_ADC_DIG_MIC_MASK 1211 #define WM8903_ADC_DIG_MIC_SHIFT 1212 #define WM8903_ADC_DIG_MIC_WIDTH 1213 1214 /* 1215 * R172 (0xAC) - Analogue Output Bias 0 1216 */ 1217 #define WM8903_PGA_BIAS_MASK 1218 #define WM8903_PGA_BIAS_SHIFT 1219 #define WM8903_PGA_BIAS_WIDTH 1220 1221 #endif 1222
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