1 // SPDX-License-Identifier: GPL-2.0-or-later <<
2 /* 1 /*
3 * wm8990.c -- WM8990 ALSA Soc Audio driver 2 * wm8990.c -- WM8990 ALSA Soc Audio driver
4 * 3 *
5 * Copyright 2008 Wolfson Microelectronics PLC 4 * Copyright 2008 Wolfson Microelectronics PLC.
6 * Author: Liam Girdwood <lrg@slimlogic.co.uk> 5 * Author: Liam Girdwood <lrg@slimlogic.co.uk>
>> 6 *
>> 7 * This program is free software; you can redistribute it and/or modify it
>> 8 * under the terms of the GNU General Public License as published by the
>> 9 * Free Software Foundation; either version 2 of the License, or (at your
>> 10 * option) any later version.
7 */ 11 */
8 12
9 #include <linux/module.h> 13 #include <linux/module.h>
10 #include <linux/moduleparam.h> 14 #include <linux/moduleparam.h>
11 #include <linux/kernel.h> 15 #include <linux/kernel.h>
12 #include <linux/init.h> 16 #include <linux/init.h>
13 #include <linux/delay.h> 17 #include <linux/delay.h>
14 #include <linux/pm.h> 18 #include <linux/pm.h>
15 #include <linux/i2c.h> 19 #include <linux/i2c.h>
16 #include <linux/regmap.h> 20 #include <linux/regmap.h>
17 #include <linux/slab.h> 21 #include <linux/slab.h>
18 #include <sound/core.h> 22 #include <sound/core.h>
19 #include <sound/pcm.h> 23 #include <sound/pcm.h>
20 #include <sound/pcm_params.h> 24 #include <sound/pcm_params.h>
21 #include <sound/soc.h> 25 #include <sound/soc.h>
22 #include <sound/initval.h> 26 #include <sound/initval.h>
23 #include <sound/tlv.h> 27 #include <sound/tlv.h>
24 #include <asm/div64.h> 28 #include <asm/div64.h>
25 29
26 #include "wm8990.h" 30 #include "wm8990.h"
27 31
28 /* codec private data */ 32 /* codec private data */
29 struct wm8990_priv { 33 struct wm8990_priv {
30 struct regmap *regmap; 34 struct regmap *regmap;
31 unsigned int sysclk; 35 unsigned int sysclk;
32 unsigned int pcmclk; 36 unsigned int pcmclk;
33 }; 37 };
34 38
35 #define wm8990_reset(c) snd_soc_component_writ !! 39 static bool wm8990_volatile_register(struct device *dev, unsigned int reg)
>> 40 {
>> 41 switch (reg) {
>> 42 case WM8990_RESET:
>> 43 return 1;
>> 44 default:
>> 45 return 0;
>> 46 }
>> 47 }
>> 48
>> 49 static const struct reg_default wm8990_reg_defaults[] = {
>> 50 { 1, 0x0000 }, /* R1 - Power Management (1) */
>> 51 { 2, 0x6000 }, /* R2 - Power Management (2) */
>> 52 { 3, 0x0000 }, /* R3 - Power Management (3) */
>> 53 { 4, 0x4050 }, /* R4 - Audio Interface (1) */
>> 54 { 5, 0x4000 }, /* R5 - Audio Interface (2) */
>> 55 { 6, 0x01C8 }, /* R6 - Clocking (1) */
>> 56 { 7, 0x0000 }, /* R7 - Clocking (2) */
>> 57 { 8, 0x0040 }, /* R8 - Audio Interface (3) */
>> 58 { 9, 0x0040 }, /* R9 - Audio Interface (4) */
>> 59 { 10, 0x0004 }, /* R10 - DAC CTRL */
>> 60 { 11, 0x00C0 }, /* R11 - Left DAC Digital Volume */
>> 61 { 12, 0x00C0 }, /* R12 - Right DAC Digital Volume */
>> 62 { 13, 0x0000 }, /* R13 - Digital Side Tone */
>> 63 { 14, 0x0100 }, /* R14 - ADC CTRL */
>> 64 { 15, 0x00C0 }, /* R15 - Left ADC Digital Volume */
>> 65 { 16, 0x00C0 }, /* R16 - Right ADC Digital Volume */
>> 66
>> 67 { 18, 0x0000 }, /* R18 - GPIO CTRL 1 */
>> 68 { 19, 0x1000 }, /* R19 - GPIO1 & GPIO2 */
>> 69 { 20, 0x1010 }, /* R20 - GPIO3 & GPIO4 */
>> 70 { 21, 0x1010 }, /* R21 - GPIO5 & GPIO6 */
>> 71 { 22, 0x8000 }, /* R22 - GPIOCTRL 2 */
>> 72 { 23, 0x0800 }, /* R23 - GPIO_POL */
>> 73 { 24, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
>> 74 { 25, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
>> 75 { 26, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
>> 76 { 27, 0x008B }, /* R27 - Right Line Input 3&4 Volume */
>> 77 { 28, 0x0000 }, /* R28 - Left Output Volume */
>> 78 { 29, 0x0000 }, /* R29 - Right Output Volume */
>> 79 { 30, 0x0066 }, /* R30 - Line Outputs Volume */
>> 80 { 31, 0x0022 }, /* R31 - Out3/4 Volume */
>> 81 { 32, 0x0079 }, /* R32 - Left OPGA Volume */
>> 82 { 33, 0x0079 }, /* R33 - Right OPGA Volume */
>> 83 { 34, 0x0003 }, /* R34 - Speaker Volume */
>> 84 { 35, 0x0003 }, /* R35 - ClassD1 */
>> 85
>> 86 { 37, 0x0100 }, /* R37 - ClassD3 */
>> 87 { 38, 0x0079 }, /* R38 - ClassD4 */
>> 88 { 39, 0x0000 }, /* R39 - Input Mixer1 */
>> 89 { 40, 0x0000 }, /* R40 - Input Mixer2 */
>> 90 { 41, 0x0000 }, /* R41 - Input Mixer3 */
>> 91 { 42, 0x0000 }, /* R42 - Input Mixer4 */
>> 92 { 43, 0x0000 }, /* R43 - Input Mixer5 */
>> 93 { 44, 0x0000 }, /* R44 - Input Mixer6 */
>> 94 { 45, 0x0000 }, /* R45 - Output Mixer1 */
>> 95 { 46, 0x0000 }, /* R46 - Output Mixer2 */
>> 96 { 47, 0x0000 }, /* R47 - Output Mixer3 */
>> 97 { 48, 0x0000 }, /* R48 - Output Mixer4 */
>> 98 { 49, 0x0000 }, /* R49 - Output Mixer5 */
>> 99 { 50, 0x0000 }, /* R50 - Output Mixer6 */
>> 100 { 51, 0x0180 }, /* R51 - Out3/4 Mixer */
>> 101 { 52, 0x0000 }, /* R52 - Line Mixer1 */
>> 102 { 53, 0x0000 }, /* R53 - Line Mixer2 */
>> 103 { 54, 0x0000 }, /* R54 - Speaker Mixer */
>> 104 { 55, 0x0000 }, /* R55 - Additional Control */
>> 105 { 56, 0x0000 }, /* R56 - AntiPOP1 */
>> 106 { 57, 0x0000 }, /* R57 - AntiPOP2 */
>> 107 { 58, 0x0000 }, /* R58 - MICBIAS */
>> 108
>> 109 { 60, 0x0008 }, /* R60 - PLL1 */
>> 110 { 61, 0x0031 }, /* R61 - PLL2 */
>> 111 { 62, 0x0026 }, /* R62 - PLL3 */
>> 112 };
>> 113
>> 114 #define wm8990_reset(c) snd_soc_write(c, WM8990_RESET, 0)
>> 115
>> 116 static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 600, 0);
36 117
37 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, 118 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
38 119
39 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, 120 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, 0, -2100, 0);
40 121
41 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, 122 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
42 123
>> 124 static const DECLARE_TLV_DB_SCALE(out_omix_tlv, -600, 0, 0);
>> 125
43 static const DECLARE_TLV_DB_SCALE(out_dac_tlv, 126 static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
44 127
45 static const DECLARE_TLV_DB_SCALE(in_adc_tlv, 128 static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0);
46 129
47 static const DECLARE_TLV_DB_SCALE(out_sidetone 130 static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
48 131
49 static int wm899x_outpga_put_volsw_vu(struct s 132 static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
50 struct snd_ctl_elem_value *ucontrol) 133 struct snd_ctl_elem_value *ucontrol)
51 { 134 {
52 struct snd_soc_component *component = !! 135 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
53 struct soc_mixer_control *mc = 136 struct soc_mixer_control *mc =
54 (struct soc_mixer_control *)kc 137 (struct soc_mixer_control *)kcontrol->private_value;
55 int reg = mc->reg; 138 int reg = mc->reg;
56 int ret; 139 int ret;
57 u16 val; 140 u16 val;
58 141
59 ret = snd_soc_put_volsw(kcontrol, ucon 142 ret = snd_soc_put_volsw(kcontrol, ucontrol);
60 if (ret < 0) 143 if (ret < 0)
61 return ret; 144 return ret;
62 145
63 /* now hit the volume update bits (alw 146 /* now hit the volume update bits (always bit 8) */
64 val = snd_soc_component_read(component !! 147 val = snd_soc_read(codec, reg);
65 return snd_soc_component_write(compone !! 148 return snd_soc_write(codec, reg, val | 0x0100);
66 } 149 }
67 150
68 #define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, 151 #define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\
69 tlv_array) \ 152 tlv_array) \
70 SOC_SINGLE_EXT_TLV(xname, reg, shift, 153 SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, \
71 snd_soc_get_volsw, wm899x_outp 154 snd_soc_get_volsw, wm899x_outpga_put_volsw_vu, tlv_array)
72 155
73 156
74 static const char *wm8990_digital_sidetone[] = 157 static const char *wm8990_digital_sidetone[] =
75 {"None", "Left ADC", "Right ADC", "Res 158 {"None", "Left ADC", "Right ADC", "Reserved"};
76 159
77 static SOC_ENUM_SINGLE_DECL(wm8990_left_digita 160 static SOC_ENUM_SINGLE_DECL(wm8990_left_digital_sidetone_enum,
78 WM8990_DIGITAL_SID 161 WM8990_DIGITAL_SIDE_TONE,
79 WM8990_ADC_TO_DACL 162 WM8990_ADC_TO_DACL_SHIFT,
80 wm8990_digital_sid 163 wm8990_digital_sidetone);
81 164
82 static SOC_ENUM_SINGLE_DECL(wm8990_right_digit 165 static SOC_ENUM_SINGLE_DECL(wm8990_right_digital_sidetone_enum,
83 WM8990_DIGITAL_SID 166 WM8990_DIGITAL_SIDE_TONE,
84 WM8990_ADC_TO_DACR 167 WM8990_ADC_TO_DACR_SHIFT,
85 wm8990_digital_sid 168 wm8990_digital_sidetone);
86 169
87 static const char *wm8990_adcmode[] = 170 static const char *wm8990_adcmode[] =
88 {"Hi-fi mode", "Voice mode 1", "Voice 171 {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
89 172
90 static SOC_ENUM_SINGLE_DECL(wm8990_right_adcmo 173 static SOC_ENUM_SINGLE_DECL(wm8990_right_adcmode_enum,
91 WM8990_ADC_CTRL, 174 WM8990_ADC_CTRL,
92 WM8990_ADC_HPF_CUT 175 WM8990_ADC_HPF_CUT_SHIFT,
93 wm8990_adcmode); 176 wm8990_adcmode);
94 177
95 static const struct snd_kcontrol_new wm8990_sn 178 static const struct snd_kcontrol_new wm8990_snd_controls[] = {
96 /* INMIXL */ 179 /* INMIXL */
97 SOC_SINGLE("LIN12 PGA Boost", WM8990_INPUT_MIX 180 SOC_SINGLE("LIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L12MNBST_BIT, 1, 0),
98 SOC_SINGLE("LIN34 PGA Boost", WM8990_INPUT_MIX 181 SOC_SINGLE("LIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L34MNBST_BIT, 1, 0),
99 /* INMIXR */ 182 /* INMIXR */
100 SOC_SINGLE("RIN12 PGA Boost", WM8990_INPUT_MIX 183 SOC_SINGLE("RIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R12MNBST_BIT, 1, 0),
101 SOC_SINGLE("RIN34 PGA Boost", WM8990_INPUT_MIX 184 SOC_SINGLE("RIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R34MNBST_BIT, 1, 0),
102 185
103 /* LOMIX */ 186 /* LOMIX */
104 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8 187 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER3,
105 WM8990_LLI3LOVOL_SHIFT, WM8990_LLI3LOV 188 WM8990_LLI3LOVOL_SHIFT, WM8990_LLI3LOVOL_MASK, 1, out_mix_tlv),
106 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume" 189 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
107 WM8990_LR12LOVOL_SHIFT, WM8990_LR12LOV 190 WM8990_LR12LOVOL_SHIFT, WM8990_LR12LOVOL_MASK, 1, out_mix_tlv),
108 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume" 191 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
109 WM8990_LL12LOVOL_SHIFT, WM8990_LL12LOV 192 WM8990_LL12LOVOL_SHIFT, WM8990_LL12LOVOL_MASK, 1, out_mix_tlv),
110 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8 193 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER5,
111 WM8990_LRI3LOVOL_SHIFT, WM8990_LRI3LOV 194 WM8990_LRI3LOVOL_SHIFT, WM8990_LRI3LOVOL_MASK, 1, out_mix_tlv),
112 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", 195 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
113 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL 196 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
114 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", 197 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
115 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL 198 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
116 199
117 /* ROMIX */ 200 /* ROMIX */
118 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8 201 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER4,
119 WM8990_RRI3ROVOL_SHIFT, WM8990_RRI3ROV 202 WM8990_RRI3ROVOL_SHIFT, WM8990_RRI3ROVOL_MASK, 1, out_mix_tlv),
120 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume" 203 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
121 WM8990_RL12ROVOL_SHIFT, WM8990_RL12ROV 204 WM8990_RL12ROVOL_SHIFT, WM8990_RL12ROVOL_MASK, 1, out_mix_tlv),
122 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume" 205 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
123 WM8990_RR12ROVOL_SHIFT, WM8990_RR12ROV 206 WM8990_RR12ROVOL_SHIFT, WM8990_RR12ROVOL_MASK, 1, out_mix_tlv),
124 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8 207 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER6,
125 WM8990_RLI3ROVOL_SHIFT, WM8990_RLI3ROV 208 WM8990_RLI3ROVOL_SHIFT, WM8990_RLI3ROVOL_MASK, 1, out_mix_tlv),
126 SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", 209 SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
127 WM8990_RLBROVOL_SHIFT, WM8990_RLBROVOL 210 WM8990_RLBROVOL_SHIFT, WM8990_RLBROVOL_MASK, 1, out_mix_tlv),
128 SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", 211 SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
129 WM8990_RRBROVOL_SHIFT, WM8990_RRBROVOL 212 WM8990_RRBROVOL_SHIFT, WM8990_RRBROVOL_MASK, 1, out_mix_tlv),
130 213
131 /* LOUT */ 214 /* LOUT */
132 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", 215 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8990_LEFT_OUTPUT_VOLUME,
133 WM8990_LOUTVOL_SHIFT, WM8990_LOUTVOL_M 216 WM8990_LOUTVOL_SHIFT, WM8990_LOUTVOL_MASK, 0, out_pga_tlv),
134 SOC_SINGLE("LOUT ZC", WM8990_LEFT_OUTPUT_VOLUM 217 SOC_SINGLE("LOUT ZC", WM8990_LEFT_OUTPUT_VOLUME, WM8990_LOZC_BIT, 1, 0),
135 218
136 /* ROUT */ 219 /* ROUT */
137 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", 220 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8990_RIGHT_OUTPUT_VOLUME,
138 WM8990_ROUTVOL_SHIFT, WM8990_ROUTVOL_M 221 WM8990_ROUTVOL_SHIFT, WM8990_ROUTVOL_MASK, 0, out_pga_tlv),
139 SOC_SINGLE("ROUT ZC", WM8990_RIGHT_OUTPUT_VOLU 222 SOC_SINGLE("ROUT ZC", WM8990_RIGHT_OUTPUT_VOLUME, WM8990_ROZC_BIT, 1, 0),
140 223
141 /* LOPGA */ 224 /* LOPGA */
142 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", 225 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8990_LEFT_OPGA_VOLUME,
143 WM8990_LOPGAVOL_SHIFT, WM8990_LOPGAVOL 226 WM8990_LOPGAVOL_SHIFT, WM8990_LOPGAVOL_MASK, 0, out_pga_tlv),
144 SOC_SINGLE("LOPGA ZC Switch", WM8990_LEFT_OPGA 227 SOC_SINGLE("LOPGA ZC Switch", WM8990_LEFT_OPGA_VOLUME,
145 WM8990_LOPGAZC_BIT, 1, 0), 228 WM8990_LOPGAZC_BIT, 1, 0),
146 229
147 /* ROPGA */ 230 /* ROPGA */
148 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", 231 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8990_RIGHT_OPGA_VOLUME,
149 WM8990_ROPGAVOL_SHIFT, WM8990_ROPGAVOL 232 WM8990_ROPGAVOL_SHIFT, WM8990_ROPGAVOL_MASK, 0, out_pga_tlv),
150 SOC_SINGLE("ROPGA ZC Switch", WM8990_RIGHT_OPG 233 SOC_SINGLE("ROPGA ZC Switch", WM8990_RIGHT_OPGA_VOLUME,
151 WM8990_ROPGAZC_BIT, 1, 0), 234 WM8990_ROPGAZC_BIT, 1, 0),
152 235
153 SOC_SINGLE("LON Mute Switch", WM8990_LINE_OUTP 236 SOC_SINGLE("LON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
154 WM8990_LONMUTE_BIT, 1, 0), 237 WM8990_LONMUTE_BIT, 1, 0),
155 SOC_SINGLE("LOP Mute Switch", WM8990_LINE_OUTP 238 SOC_SINGLE("LOP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
156 WM8990_LOPMUTE_BIT, 1, 0), 239 WM8990_LOPMUTE_BIT, 1, 0),
157 SOC_SINGLE("LOP Attenuation Switch", WM8990_LI 240 SOC_SINGLE("LOP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
158 WM8990_LOATTN_BIT, 1, 0), 241 WM8990_LOATTN_BIT, 1, 0),
159 SOC_SINGLE("RON Mute Switch", WM8990_LINE_OUTP 242 SOC_SINGLE("RON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
160 WM8990_RONMUTE_BIT, 1, 0), 243 WM8990_RONMUTE_BIT, 1, 0),
161 SOC_SINGLE("ROP Mute Switch", WM8990_LINE_OUTP 244 SOC_SINGLE("ROP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
162 WM8990_ROPMUTE_BIT, 1, 0), 245 WM8990_ROPMUTE_BIT, 1, 0),
163 SOC_SINGLE("ROP Attenuation Switch", WM8990_LI 246 SOC_SINGLE("ROP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
164 WM8990_ROATTN_BIT, 1, 0), 247 WM8990_ROATTN_BIT, 1, 0),
165 248
166 SOC_SINGLE("OUT3 Mute Switch", WM8990_OUT3_4_V 249 SOC_SINGLE("OUT3 Mute Switch", WM8990_OUT3_4_VOLUME,
167 WM8990_OUT3MUTE_BIT, 1, 0), 250 WM8990_OUT3MUTE_BIT, 1, 0),
168 SOC_SINGLE("OUT3 Attenuation Switch", WM8990_O 251 SOC_SINGLE("OUT3 Attenuation Switch", WM8990_OUT3_4_VOLUME,
169 WM8990_OUT3ATTN_BIT, 1, 0), 252 WM8990_OUT3ATTN_BIT, 1, 0),
170 253
171 SOC_SINGLE("OUT4 Mute Switch", WM8990_OUT3_4_V 254 SOC_SINGLE("OUT4 Mute Switch", WM8990_OUT3_4_VOLUME,
172 WM8990_OUT4MUTE_BIT, 1, 0), 255 WM8990_OUT4MUTE_BIT, 1, 0),
173 SOC_SINGLE("OUT4 Attenuation Switch", WM8990_O 256 SOC_SINGLE("OUT4 Attenuation Switch", WM8990_OUT3_4_VOLUME,
174 WM8990_OUT4ATTN_BIT, 1, 0), 257 WM8990_OUT4ATTN_BIT, 1, 0),
175 258
176 SOC_SINGLE("Speaker Mode Switch", WM8990_CLASS 259 SOC_SINGLE("Speaker Mode Switch", WM8990_CLASSD1,
177 WM8990_CDMODE_BIT, 1, 0), 260 WM8990_CDMODE_BIT, 1, 0),
178 261
179 SOC_SINGLE("Speaker Output Attenuation Volume" 262 SOC_SINGLE("Speaker Output Attenuation Volume", WM8990_SPEAKER_VOLUME,
180 WM8990_SPKATTN_SHIFT, WM8990_SPKATTN_M 263 WM8990_SPKATTN_SHIFT, WM8990_SPKATTN_MASK, 0),
181 SOC_SINGLE("Speaker DC Boost Volume", WM8990_C 264 SOC_SINGLE("Speaker DC Boost Volume", WM8990_CLASSD3,
182 WM8990_DCGAIN_SHIFT, WM8990_DCGAIN_MAS 265 WM8990_DCGAIN_SHIFT, WM8990_DCGAIN_MASK, 0),
183 SOC_SINGLE("Speaker AC Boost Volume", WM8990_C 266 SOC_SINGLE("Speaker AC Boost Volume", WM8990_CLASSD3,
184 WM8990_ACGAIN_SHIFT, WM8990_ACGAIN_MAS 267 WM8990_ACGAIN_SHIFT, WM8990_ACGAIN_MASK, 0),
185 SOC_SINGLE_TLV("Speaker Volume", WM8990_CLASSD 268 SOC_SINGLE_TLV("Speaker Volume", WM8990_CLASSD4,
186 WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MAS 269 WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MASK, 0, out_pga_tlv),
187 SOC_SINGLE("Speaker ZC Switch", WM8990_CLASSD4 270 SOC_SINGLE("Speaker ZC Switch", WM8990_CLASSD4,
188 WM8990_SPKZC_SHIFT, WM8990_SPKZC_MASK, 271 WM8990_SPKZC_SHIFT, WM8990_SPKZC_MASK, 0),
189 272
190 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digit 273 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
191 WM8990_LEFT_DAC_DIGITAL_VOLUME, 274 WM8990_LEFT_DAC_DIGITAL_VOLUME,
192 WM8990_DACL_VOL_SHIFT, 275 WM8990_DACL_VOL_SHIFT,
193 WM8990_DACL_VOL_MASK, 276 WM8990_DACL_VOL_MASK,
194 0, 277 0,
195 out_dac_tlv), 278 out_dac_tlv),
196 279
197 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digi 280 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
198 WM8990_RIGHT_DAC_DIGITAL_VOLUME, 281 WM8990_RIGHT_DAC_DIGITAL_VOLUME,
199 WM8990_DACR_VOL_SHIFT, 282 WM8990_DACR_VOL_SHIFT,
200 WM8990_DACR_VOL_MASK, 283 WM8990_DACR_VOL_MASK,
201 0, 284 0,
202 out_dac_tlv), 285 out_dac_tlv),
203 286
204 SOC_ENUM("Left Digital Sidetone", wm8990_left_ 287 SOC_ENUM("Left Digital Sidetone", wm8990_left_digital_sidetone_enum),
205 SOC_ENUM("Right Digital Sidetone", wm8990_righ 288 SOC_ENUM("Right Digital Sidetone", wm8990_right_digital_sidetone_enum),
206 289
207 SOC_SINGLE_TLV("Left Digital Sidetone Volume", 290 SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
208 WM8990_ADCL_DAC_SVOL_SHIFT, WM8990_ADC 291 WM8990_ADCL_DAC_SVOL_SHIFT, WM8990_ADCL_DAC_SVOL_MASK, 0,
209 out_sidetone_tlv), 292 out_sidetone_tlv),
210 SOC_SINGLE_TLV("Right Digital Sidetone Volume" 293 SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
211 WM8990_ADCR_DAC_SVOL_SHIFT, WM8990_ADC 294 WM8990_ADCR_DAC_SVOL_SHIFT, WM8990_ADCR_DAC_SVOL_MASK, 0,
212 out_sidetone_tlv), 295 out_sidetone_tlv),
213 296
214 SOC_SINGLE("ADC Digital High Pass Filter Switc 297 SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8990_ADC_CTRL,
215 WM8990_ADC_HPF_ENA_BIT, 1, 0), 298 WM8990_ADC_HPF_ENA_BIT, 1, 0),
216 299
217 SOC_ENUM("ADC HPF Mode", wm8990_right_adcmode_ 300 SOC_ENUM("ADC HPF Mode", wm8990_right_adcmode_enum),
218 301
219 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digit 302 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
220 WM8990_LEFT_ADC_DIGITAL_VOLUME, 303 WM8990_LEFT_ADC_DIGITAL_VOLUME,
221 WM8990_ADCL_VOL_SHIFT, 304 WM8990_ADCL_VOL_SHIFT,
222 WM8990_ADCL_VOL_MASK, 305 WM8990_ADCL_VOL_MASK,
223 0, 306 0,
224 in_adc_tlv), 307 in_adc_tlv),
225 308
226 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digi 309 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
227 WM8990_RIGHT_ADC_DIGITAL_VOLUME, 310 WM8990_RIGHT_ADC_DIGITAL_VOLUME,
228 WM8990_ADCR_VOL_SHIFT, 311 WM8990_ADCR_VOL_SHIFT,
229 WM8990_ADCR_VOL_MASK, 312 WM8990_ADCR_VOL_MASK,
230 0, 313 0,
231 in_adc_tlv), 314 in_adc_tlv),
232 315
233 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume", 316 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
234 WM8990_LEFT_LINE_INPUT_1_2_VOLUME, 317 WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
235 WM8990_LIN12VOL_SHIFT, 318 WM8990_LIN12VOL_SHIFT,
236 WM8990_LIN12VOL_MASK, 319 WM8990_LIN12VOL_MASK,
237 0, 320 0,
238 in_pga_tlv), 321 in_pga_tlv),
239 322
240 SOC_SINGLE("LIN12 ZC Switch", WM8990_LEFT_LINE 323 SOC_SINGLE("LIN12 ZC Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
241 WM8990_LI12ZC_BIT, 1, 0), 324 WM8990_LI12ZC_BIT, 1, 0),
242 325
243 SOC_SINGLE("LIN12 Mute Switch", WM8990_LEFT_LI 326 SOC_SINGLE("LIN12 Mute Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
244 WM8990_LI12MUTE_BIT, 1, 0), 327 WM8990_LI12MUTE_BIT, 1, 0),
245 328
246 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume", 329 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
247 WM8990_LEFT_LINE_INPUT_3_4_VOLUME, 330 WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
248 WM8990_LIN34VOL_SHIFT, 331 WM8990_LIN34VOL_SHIFT,
249 WM8990_LIN34VOL_MASK, 332 WM8990_LIN34VOL_MASK,
250 0, 333 0,
251 in_pga_tlv), 334 in_pga_tlv),
252 335
253 SOC_SINGLE("LIN34 ZC Switch", WM8990_LEFT_LINE 336 SOC_SINGLE("LIN34 ZC Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
254 WM8990_LI34ZC_BIT, 1, 0), 337 WM8990_LI34ZC_BIT, 1, 0),
255 338
256 SOC_SINGLE("LIN34 Mute Switch", WM8990_LEFT_LI 339 SOC_SINGLE("LIN34 Mute Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
257 WM8990_LI34MUTE_BIT, 1, 0), 340 WM8990_LI34MUTE_BIT, 1, 0),
258 341
259 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume", 342 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
260 WM8990_RIGHT_LINE_INPUT_1_2_VOLUME, 343 WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
261 WM8990_RIN12VOL_SHIFT, 344 WM8990_RIN12VOL_SHIFT,
262 WM8990_RIN12VOL_MASK, 345 WM8990_RIN12VOL_MASK,
263 0, 346 0,
264 in_pga_tlv), 347 in_pga_tlv),
265 348
266 SOC_SINGLE("RIN12 ZC Switch", WM8990_RIGHT_LIN 349 SOC_SINGLE("RIN12 ZC Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
267 WM8990_RI12ZC_BIT, 1, 0), 350 WM8990_RI12ZC_BIT, 1, 0),
268 351
269 SOC_SINGLE("RIN12 Mute Switch", WM8990_RIGHT_L 352 SOC_SINGLE("RIN12 Mute Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
270 WM8990_RI12MUTE_BIT, 1, 0), 353 WM8990_RI12MUTE_BIT, 1, 0),
271 354
272 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume", 355 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
273 WM8990_RIGHT_LINE_INPUT_3_4_VOLUME, 356 WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
274 WM8990_RIN34VOL_SHIFT, 357 WM8990_RIN34VOL_SHIFT,
275 WM8990_RIN34VOL_MASK, 358 WM8990_RIN34VOL_MASK,
276 0, 359 0,
277 in_pga_tlv), 360 in_pga_tlv),
278 361
279 SOC_SINGLE("RIN34 ZC Switch", WM8990_RIGHT_LIN 362 SOC_SINGLE("RIN34 ZC Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
280 WM8990_RI34ZC_BIT, 1, 0), 363 WM8990_RI34ZC_BIT, 1, 0),
281 364
282 SOC_SINGLE("RIN34 Mute Switch", WM8990_RIGHT_L 365 SOC_SINGLE("RIN34 Mute Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
283 WM8990_RI34MUTE_BIT, 1, 0), 366 WM8990_RI34MUTE_BIT, 1, 0),
284 367
285 }; 368 };
286 369
287 /* 370 /*
288 * _DAPM_ Controls 371 * _DAPM_ Controls
289 */ 372 */
290 373
291 static int outmixer_event(struct snd_soc_dapm_ 374 static int outmixer_event(struct snd_soc_dapm_widget *w,
292 struct snd_kcontrol *kcontrol, int eve 375 struct snd_kcontrol *kcontrol, int event)
293 { 376 {
294 struct snd_soc_component *component = !! 377 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
295 u32 reg_shift = kcontrol->private_valu 378 u32 reg_shift = kcontrol->private_value & 0xfff;
296 int ret = 0; 379 int ret = 0;
297 u16 reg; 380 u16 reg;
298 381
299 switch (reg_shift) { 382 switch (reg_shift) {
300 case WM8990_SPEAKER_MIXER | (WM8990_LD 383 case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) :
301 reg = snd_soc_component_read(c !! 384 reg = snd_soc_read(codec, WM8990_OUTPUT_MIXER1);
302 if (reg & WM8990_LDLO) { 385 if (reg & WM8990_LDLO) {
303 printk(KERN_WARNING 386 printk(KERN_WARNING
304 "Cannot set as Output 387 "Cannot set as Output Mixer 1 LDLO Set\n");
305 ret = -1; 388 ret = -1;
306 } 389 }
307 break; 390 break;
308 case WM8990_SPEAKER_MIXER | (WM8990_RD 391 case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8):
309 reg = snd_soc_component_read(c !! 392 reg = snd_soc_read(codec, WM8990_OUTPUT_MIXER2);
310 if (reg & WM8990_RDRO) { 393 if (reg & WM8990_RDRO) {
311 printk(KERN_WARNING 394 printk(KERN_WARNING
312 "Cannot set as Output 395 "Cannot set as Output Mixer 2 RDRO Set\n");
313 ret = -1; 396 ret = -1;
314 } 397 }
315 break; 398 break;
316 case WM8990_OUTPUT_MIXER1 | (WM8990_LD 399 case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8):
317 reg = snd_soc_component_read(c !! 400 reg = snd_soc_read(codec, WM8990_SPEAKER_MIXER);
318 if (reg & WM8990_LDSPK) { 401 if (reg & WM8990_LDSPK) {
319 printk(KERN_WARNING 402 printk(KERN_WARNING
320 "Cannot set as Speaker 403 "Cannot set as Speaker Mixer LDSPK Set\n");
321 ret = -1; 404 ret = -1;
322 } 405 }
323 break; 406 break;
324 case WM8990_OUTPUT_MIXER2 | (WM8990_RD 407 case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8):
325 reg = snd_soc_component_read(c !! 408 reg = snd_soc_read(codec, WM8990_SPEAKER_MIXER);
326 if (reg & WM8990_RDSPK) { 409 if (reg & WM8990_RDSPK) {
327 printk(KERN_WARNING 410 printk(KERN_WARNING
328 "Cannot set as Speaker 411 "Cannot set as Speaker Mixer RDSPK Set\n");
329 ret = -1; 412 ret = -1;
330 } 413 }
331 break; 414 break;
332 } 415 }
333 416
334 return ret; 417 return ret;
335 } 418 }
336 419
337 /* INMIX dB values */ 420 /* INMIX dB values */
338 static const DECLARE_TLV_DB_SCALE(in_mix_tlv, 421 static const DECLARE_TLV_DB_SCALE(in_mix_tlv, -1200, 600, 0);
339 422
340 /* Left In PGA Connections */ 423 /* Left In PGA Connections */
341 static const struct snd_kcontrol_new wm8990_da 424 static const struct snd_kcontrol_new wm8990_dapm_lin12_pga_controls[] = {
342 SOC_DAPM_SINGLE("LIN1 Switch", WM8990_INPUT_MI 425 SOC_DAPM_SINGLE("LIN1 Switch", WM8990_INPUT_MIXER2, WM8990_LMN1_BIT, 1, 0),
343 SOC_DAPM_SINGLE("LIN2 Switch", WM8990_INPUT_MI 426 SOC_DAPM_SINGLE("LIN2 Switch", WM8990_INPUT_MIXER2, WM8990_LMP2_BIT, 1, 0),
344 }; 427 };
345 428
346 static const struct snd_kcontrol_new wm8990_da 429 static const struct snd_kcontrol_new wm8990_dapm_lin34_pga_controls[] = {
347 SOC_DAPM_SINGLE("LIN3 Switch", WM8990_INPUT_MI 430 SOC_DAPM_SINGLE("LIN3 Switch", WM8990_INPUT_MIXER2, WM8990_LMN3_BIT, 1, 0),
348 SOC_DAPM_SINGLE("LIN4 Switch", WM8990_INPUT_MI 431 SOC_DAPM_SINGLE("LIN4 Switch", WM8990_INPUT_MIXER2, WM8990_LMP4_BIT, 1, 0),
349 }; 432 };
350 433
351 /* Right In PGA Connections */ 434 /* Right In PGA Connections */
352 static const struct snd_kcontrol_new wm8990_da 435 static const struct snd_kcontrol_new wm8990_dapm_rin12_pga_controls[] = {
353 SOC_DAPM_SINGLE("RIN1 Switch", WM8990_INPUT_MI 436 SOC_DAPM_SINGLE("RIN1 Switch", WM8990_INPUT_MIXER2, WM8990_RMN1_BIT, 1, 0),
354 SOC_DAPM_SINGLE("RIN2 Switch", WM8990_INPUT_MI 437 SOC_DAPM_SINGLE("RIN2 Switch", WM8990_INPUT_MIXER2, WM8990_RMP2_BIT, 1, 0),
355 }; 438 };
356 439
357 static const struct snd_kcontrol_new wm8990_da 440 static const struct snd_kcontrol_new wm8990_dapm_rin34_pga_controls[] = {
358 SOC_DAPM_SINGLE("RIN3 Switch", WM8990_INPUT_MI 441 SOC_DAPM_SINGLE("RIN3 Switch", WM8990_INPUT_MIXER2, WM8990_RMN3_BIT, 1, 0),
359 SOC_DAPM_SINGLE("RIN4 Switch", WM8990_INPUT_MI 442 SOC_DAPM_SINGLE("RIN4 Switch", WM8990_INPUT_MIXER2, WM8990_RMP4_BIT, 1, 0),
360 }; 443 };
361 444
362 /* INMIXL */ 445 /* INMIXL */
363 static const struct snd_kcontrol_new wm8990_da 446 static const struct snd_kcontrol_new wm8990_dapm_inmixl_controls[] = {
364 SOC_DAPM_SINGLE_TLV("Record Left Volume", WM89 447 SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8990_INPUT_MIXER3,
365 WM8990_LDBVOL_SHIFT, WM8990_LDBVOL_MAS 448 WM8990_LDBVOL_SHIFT, WM8990_LDBVOL_MASK, 0, in_mix_tlv),
366 SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8990_INPU 449 SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8990_INPUT_MIXER5, WM8990_LI2BVOL_SHIFT,
367 7, 0, in_mix_tlv), 450 7, 0, in_mix_tlv),
368 SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPU 451 SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
369 1, 0), 452 1, 0),
370 SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPU 453 SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
371 1, 0), 454 1, 0),
372 }; 455 };
373 456
374 /* INMIXR */ 457 /* INMIXR */
375 static const struct snd_kcontrol_new wm8990_da 458 static const struct snd_kcontrol_new wm8990_dapm_inmixr_controls[] = {
376 SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8 459 SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8990_INPUT_MIXER4,
377 WM8990_RDBVOL_SHIFT, WM8990_RDBVOL_MAS 460 WM8990_RDBVOL_SHIFT, WM8990_RDBVOL_MASK, 0, in_mix_tlv),
378 SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8990_INPU 461 SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8990_INPUT_MIXER6, WM8990_RI2BVOL_SHIFT,
379 7, 0, in_mix_tlv), 462 7, 0, in_mix_tlv),
380 SOC_DAPM_SINGLE("RINPGA12 Switch", WM8990_INPU 463 SOC_DAPM_SINGLE("RINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
381 1, 0), 464 1, 0),
382 SOC_DAPM_SINGLE("RINPGA34 Switch", WM8990_INPU 465 SOC_DAPM_SINGLE("RINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
383 1, 0), 466 1, 0),
384 }; 467 };
385 468
386 /* AINLMUX */ 469 /* AINLMUX */
387 static const char *wm8990_ainlmux[] = 470 static const char *wm8990_ainlmux[] =
388 {"INMIXL Mix", "RXVOICE Mix", "DIFFINL 471 {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
389 472
390 static SOC_ENUM_SINGLE_DECL(wm8990_ainlmux_enu 473 static SOC_ENUM_SINGLE_DECL(wm8990_ainlmux_enum,
391 WM8990_INPUT_MIXER 474 WM8990_INPUT_MIXER1, WM8990_AINLMODE_SHIFT,
392 wm8990_ainlmux); 475 wm8990_ainlmux);
393 476
394 static const struct snd_kcontrol_new wm8990_da 477 static const struct snd_kcontrol_new wm8990_dapm_ainlmux_controls =
395 SOC_DAPM_ENUM("Route", wm8990_ainlmux_enum); 478 SOC_DAPM_ENUM("Route", wm8990_ainlmux_enum);
396 479
397 /* DIFFINL */ 480 /* DIFFINL */
398 481
399 /* AINRMUX */ 482 /* AINRMUX */
400 static const char *wm8990_ainrmux[] = 483 static const char *wm8990_ainrmux[] =
401 {"INMIXR Mix", "RXVOICE Mix", "DIFFINR 484 {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
402 485
403 static SOC_ENUM_SINGLE_DECL(wm8990_ainrmux_enu 486 static SOC_ENUM_SINGLE_DECL(wm8990_ainrmux_enum,
404 WM8990_INPUT_MIXER 487 WM8990_INPUT_MIXER1, WM8990_AINRMODE_SHIFT,
405 wm8990_ainrmux); 488 wm8990_ainrmux);
406 489
407 static const struct snd_kcontrol_new wm8990_da 490 static const struct snd_kcontrol_new wm8990_dapm_ainrmux_controls =
408 SOC_DAPM_ENUM("Route", wm8990_ainrmux_enum); 491 SOC_DAPM_ENUM("Route", wm8990_ainrmux_enum);
409 492
>> 493 /* RXVOICE */
>> 494 static const struct snd_kcontrol_new wm8990_dapm_rxvoice_controls[] = {
>> 495 SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8990_INPUT_MIXER5, WM8990_LR4BVOL_SHIFT,
>> 496 WM8990_LR4BVOL_MASK, 0, in_mix_tlv),
>> 497 SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8990_INPUT_MIXER6, WM8990_RL4BVOL_SHIFT,
>> 498 WM8990_RL4BVOL_MASK, 0, in_mix_tlv),
>> 499 };
>> 500
410 /* LOMIX */ 501 /* LOMIX */
411 static const struct snd_kcontrol_new wm8990_da 502 static const struct snd_kcontrol_new wm8990_dapm_lomix_controls[] = {
412 SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch 503 SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
413 WM8990_LRBLO_BIT, 1, 0), 504 WM8990_LRBLO_BIT, 1, 0),
414 SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch" 505 SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
415 WM8990_LLBLO_BIT, 1, 0), 506 WM8990_LLBLO_BIT, 1, 0),
416 SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM 507 SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
417 WM8990_LRI3LO_BIT, 1, 0), 508 WM8990_LRI3LO_BIT, 1, 0),
418 SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM 509 SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
419 WM8990_LLI3LO_BIT, 1, 0), 510 WM8990_LLI3LO_BIT, 1, 0),
420 SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch 511 SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
421 WM8990_LR12LO_BIT, 1, 0), 512 WM8990_LR12LO_BIT, 1, 0),
422 SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch 513 SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
423 WM8990_LL12LO_BIT, 1, 0), 514 WM8990_LL12LO_BIT, 1, 0),
424 SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM899 515 SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8990_OUTPUT_MIXER1,
425 WM8990_LDLO_BIT, 1, 0), 516 WM8990_LDLO_BIT, 1, 0),
426 }; 517 };
427 518
428 /* ROMIX */ 519 /* ROMIX */
429 static const struct snd_kcontrol_new wm8990_da 520 static const struct snd_kcontrol_new wm8990_dapm_romix_controls[] = {
430 SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch" 521 SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
431 WM8990_RLBRO_BIT, 1, 0), 522 WM8990_RLBRO_BIT, 1, 0),
432 SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch 523 SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
433 WM8990_RRBRO_BIT, 1, 0), 524 WM8990_RRBRO_BIT, 1, 0),
434 SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM 525 SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
435 WM8990_RLI3RO_BIT, 1, 0), 526 WM8990_RLI3RO_BIT, 1, 0),
436 SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM 527 SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
437 WM8990_RRI3RO_BIT, 1, 0), 528 WM8990_RRI3RO_BIT, 1, 0),
438 SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch 529 SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
439 WM8990_RL12RO_BIT, 1, 0), 530 WM8990_RL12RO_BIT, 1, 0),
440 SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch 531 SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
441 WM8990_RR12RO_BIT, 1, 0), 532 WM8990_RR12RO_BIT, 1, 0),
442 SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM89 533 SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8990_OUTPUT_MIXER2,
443 WM8990_RDRO_BIT, 1, 0), 534 WM8990_RDRO_BIT, 1, 0),
444 }; 535 };
445 536
446 /* LONMIX */ 537 /* LONMIX */
447 static const struct snd_kcontrol_new wm8990_da 538 static const struct snd_kcontrol_new wm8990_dapm_lonmix_controls[] = {
448 SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch" 539 SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
449 WM8990_LLOPGALON_BIT, 1, 0), 540 WM8990_LLOPGALON_BIT, 1, 0),
450 SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch 541 SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER1,
451 WM8990_LROPGALON_BIT, 1, 0), 542 WM8990_LROPGALON_BIT, 1, 0),
452 SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", 543 SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8990_LINE_MIXER1,
453 WM8990_LOPLON_BIT, 1, 0), 544 WM8990_LOPLON_BIT, 1, 0),
454 }; 545 };
455 546
456 /* LOPMIX */ 547 /* LOPMIX */
457 static const struct snd_kcontrol_new wm8990_da 548 static const struct snd_kcontrol_new wm8990_dapm_lopmix_controls[] = {
458 SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switc 549 SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER1,
459 WM8990_LR12LOP_BIT, 1, 0), 550 WM8990_LR12LOP_BIT, 1, 0),
460 SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch 551 SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER1,
461 WM8990_LL12LOP_BIT, 1, 0), 552 WM8990_LL12LOP_BIT, 1, 0),
462 SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch" 553 SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
463 WM8990_LLOPGALOP_BIT, 1, 0), 554 WM8990_LLOPGALOP_BIT, 1, 0),
464 }; 555 };
465 556
466 /* RONMIX */ 557 /* RONMIX */
467 static const struct snd_kcontrol_new wm8990_da 558 static const struct snd_kcontrol_new wm8990_dapm_ronmix_controls[] = {
468 SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch 559 SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
469 WM8990_RROPGARON_BIT, 1, 0), 560 WM8990_RROPGARON_BIT, 1, 0),
470 SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch" 561 SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER2,
471 WM8990_RLOPGARON_BIT, 1, 0), 562 WM8990_RLOPGARON_BIT, 1, 0),
472 SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", 563 SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8990_LINE_MIXER2,
473 WM8990_ROPRON_BIT, 1, 0), 564 WM8990_ROPRON_BIT, 1, 0),
474 }; 565 };
475 566
476 /* ROPMIX */ 567 /* ROPMIX */
477 static const struct snd_kcontrol_new wm8990_da 568 static const struct snd_kcontrol_new wm8990_dapm_ropmix_controls[] = {
478 SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch 569 SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER2,
479 WM8990_RL12ROP_BIT, 1, 0), 570 WM8990_RL12ROP_BIT, 1, 0),
480 SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switc 571 SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER2,
481 WM8990_RR12ROP_BIT, 1, 0), 572 WM8990_RR12ROP_BIT, 1, 0),
482 SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch 573 SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
483 WM8990_RROPGAROP_BIT, 1, 0), 574 WM8990_RROPGAROP_BIT, 1, 0),
484 }; 575 };
485 576
486 /* OUT3MIX */ 577 /* OUT3MIX */
487 static const struct snd_kcontrol_new wm8990_da 578 static const struct snd_kcontrol_new wm8990_dapm_out3mix_controls[] = {
488 SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switc 579 SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
489 WM8990_LI4O3_BIT, 1, 0), 580 WM8990_LI4O3_BIT, 1, 0),
490 SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", 581 SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8990_OUT3_4_MIXER,
491 WM8990_LPGAO3_BIT, 1, 0), 582 WM8990_LPGAO3_BIT, 1, 0),
492 }; 583 };
493 584
494 /* OUT4MIX */ 585 /* OUT4MIX */
495 static const struct snd_kcontrol_new wm8990_da 586 static const struct snd_kcontrol_new wm8990_dapm_out4mix_controls[] = {
496 SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch" 587 SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8990_OUT3_4_MIXER,
497 WM8990_RPGAO4_BIT, 1, 0), 588 WM8990_RPGAO4_BIT, 1, 0),
498 SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switc 589 SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
499 WM8990_RI4O4_BIT, 1, 0), 590 WM8990_RI4O4_BIT, 1, 0),
500 }; 591 };
501 592
502 /* SPKMIX */ 593 /* SPKMIX */
503 static const struct snd_kcontrol_new wm8990_da 594 static const struct snd_kcontrol_new wm8990_dapm_spkmix_controls[] = {
504 SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", W 595 SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
505 WM8990_LI2SPK_BIT, 1, 0), 596 WM8990_LI2SPK_BIT, 1, 0),
506 SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", W 597 SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8990_SPEAKER_MIXER,
507 WM8990_LB2SPK_BIT, 1, 0), 598 WM8990_LB2SPK_BIT, 1, 0),
508 SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch" 599 SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8990_SPEAKER_MIXER,
509 WM8990_LOPGASPK_BIT, 1, 0), 600 WM8990_LOPGASPK_BIT, 1, 0),
510 SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM89 601 SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8990_SPEAKER_MIXER,
511 WM8990_LDSPK_BIT, 1, 0), 602 WM8990_LDSPK_BIT, 1, 0),
512 SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8 603 SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8990_SPEAKER_MIXER,
513 WM8990_RDSPK_BIT, 1, 0), 604 WM8990_RDSPK_BIT, 1, 0),
514 SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch 605 SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8990_SPEAKER_MIXER,
515 WM8990_ROPGASPK_BIT, 1, 0), 606 WM8990_ROPGASPK_BIT, 1, 0),
516 SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", W 607 SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8990_SPEAKER_MIXER,
517 WM8990_RL12ROP_BIT, 1, 0), 608 WM8990_RL12ROP_BIT, 1, 0),
518 SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", W 609 SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
519 WM8990_RI2SPK_BIT, 1, 0), 610 WM8990_RI2SPK_BIT, 1, 0),
520 }; 611 };
521 612
522 static const struct snd_soc_dapm_widget wm8990 613 static const struct snd_soc_dapm_widget wm8990_dapm_widgets[] = {
523 /* Input Side */ 614 /* Input Side */
524 /* Input Lines */ 615 /* Input Lines */
525 SND_SOC_DAPM_INPUT("LIN1"), 616 SND_SOC_DAPM_INPUT("LIN1"),
526 SND_SOC_DAPM_INPUT("LIN2"), 617 SND_SOC_DAPM_INPUT("LIN2"),
527 SND_SOC_DAPM_INPUT("LIN3"), 618 SND_SOC_DAPM_INPUT("LIN3"),
528 SND_SOC_DAPM_INPUT("LIN4/RXN"), 619 SND_SOC_DAPM_INPUT("LIN4/RXN"),
529 SND_SOC_DAPM_INPUT("RIN3"), 620 SND_SOC_DAPM_INPUT("RIN3"),
530 SND_SOC_DAPM_INPUT("RIN4/RXP"), 621 SND_SOC_DAPM_INPUT("RIN4/RXP"),
531 SND_SOC_DAPM_INPUT("RIN1"), 622 SND_SOC_DAPM_INPUT("RIN1"),
532 SND_SOC_DAPM_INPUT("RIN2"), 623 SND_SOC_DAPM_INPUT("RIN2"),
533 SND_SOC_DAPM_INPUT("Internal ADC Source"), 624 SND_SOC_DAPM_INPUT("Internal ADC Source"),
534 625
535 SND_SOC_DAPM_SUPPLY("INL", WM8990_POWER_MANAGE 626 SND_SOC_DAPM_SUPPLY("INL", WM8990_POWER_MANAGEMENT_2, WM8990_AINL_ENA_BIT, 0,
536 NULL, 0), 627 NULL, 0),
537 SND_SOC_DAPM_SUPPLY("INR", WM8990_POWER_MANAGE 628 SND_SOC_DAPM_SUPPLY("INR", WM8990_POWER_MANAGEMENT_2, WM8990_AINR_ENA_BIT, 0,
538 NULL, 0), 629 NULL, 0),
539 630
540 /* DACs */ 631 /* DACs */
541 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", W 632 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8990_POWER_MANAGEMENT_2,
542 WM8990_ADCL_ENA_BIT, 0), 633 WM8990_ADCL_ENA_BIT, 0),
543 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", 634 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8990_POWER_MANAGEMENT_2,
544 WM8990_ADCR_ENA_BIT, 0), 635 WM8990_ADCR_ENA_BIT, 0),
545 636
546 /* Input PGAs */ 637 /* Input PGAs */
547 SND_SOC_DAPM_MIXER("LIN12 PGA", WM8990_POWER_M 638 SND_SOC_DAPM_MIXER("LIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN12_ENA_BIT,
548 0, &wm8990_dapm_lin12_pga_controls[0], 639 0, &wm8990_dapm_lin12_pga_controls[0],
549 ARRAY_SIZE(wm8990_dapm_lin12_pga_contr 640 ARRAY_SIZE(wm8990_dapm_lin12_pga_controls)),
550 SND_SOC_DAPM_MIXER("LIN34 PGA", WM8990_POWER_M 641 SND_SOC_DAPM_MIXER("LIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN34_ENA_BIT,
551 0, &wm8990_dapm_lin34_pga_controls[0], 642 0, &wm8990_dapm_lin34_pga_controls[0],
552 ARRAY_SIZE(wm8990_dapm_lin34_pga_contr 643 ARRAY_SIZE(wm8990_dapm_lin34_pga_controls)),
553 SND_SOC_DAPM_MIXER("RIN12 PGA", WM8990_POWER_M 644 SND_SOC_DAPM_MIXER("RIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN12_ENA_BIT,
554 0, &wm8990_dapm_rin12_pga_controls[0], 645 0, &wm8990_dapm_rin12_pga_controls[0],
555 ARRAY_SIZE(wm8990_dapm_rin12_pga_contr 646 ARRAY_SIZE(wm8990_dapm_rin12_pga_controls)),
556 SND_SOC_DAPM_MIXER("RIN34 PGA", WM8990_POWER_M 647 SND_SOC_DAPM_MIXER("RIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN34_ENA_BIT,
557 0, &wm8990_dapm_rin34_pga_controls[0], 648 0, &wm8990_dapm_rin34_pga_controls[0],
558 ARRAY_SIZE(wm8990_dapm_rin34_pga_contr 649 ARRAY_SIZE(wm8990_dapm_rin34_pga_controls)),
559 650
560 /* INMIXL */ 651 /* INMIXL */
561 SND_SOC_DAPM_MIXER("INMIXL", SND_SOC_NOPM, 0, 652 SND_SOC_DAPM_MIXER("INMIXL", SND_SOC_NOPM, 0, 0,
562 &wm8990_dapm_inmixl_controls[0], 653 &wm8990_dapm_inmixl_controls[0],
563 ARRAY_SIZE(wm8990_dapm_inmixl_controls 654 ARRAY_SIZE(wm8990_dapm_inmixl_controls)),
564 655
565 /* AINLMUX */ 656 /* AINLMUX */
566 SND_SOC_DAPM_MUX("AINLMUX", SND_SOC_NOPM, 0, 0 657 SND_SOC_DAPM_MUX("AINLMUX", SND_SOC_NOPM, 0, 0, &wm8990_dapm_ainlmux_controls),
567 658
568 /* INMIXR */ 659 /* INMIXR */
569 SND_SOC_DAPM_MIXER("INMIXR", SND_SOC_NOPM, 0, 660 SND_SOC_DAPM_MIXER("INMIXR", SND_SOC_NOPM, 0, 0,
570 &wm8990_dapm_inmixr_controls[0], 661 &wm8990_dapm_inmixr_controls[0],
571 ARRAY_SIZE(wm8990_dapm_inmixr_controls 662 ARRAY_SIZE(wm8990_dapm_inmixr_controls)),
572 663
573 /* AINRMUX */ 664 /* AINRMUX */
574 SND_SOC_DAPM_MUX("AINRMUX", SND_SOC_NOPM, 0, 0 665 SND_SOC_DAPM_MUX("AINRMUX", SND_SOC_NOPM, 0, 0, &wm8990_dapm_ainrmux_controls),
575 666
576 /* Output Side */ 667 /* Output Side */
577 /* DACs */ 668 /* DACs */
578 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", 669 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8990_POWER_MANAGEMENT_3,
579 WM8990_DACL_ENA_BIT, 0), 670 WM8990_DACL_ENA_BIT, 0),
580 SND_SOC_DAPM_DAC("Right DAC", "Right Playback" 671 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8990_POWER_MANAGEMENT_3,
581 WM8990_DACR_ENA_BIT, 0), 672 WM8990_DACR_ENA_BIT, 0),
582 673
583 /* LOMIX */ 674 /* LOMIX */
584 SND_SOC_DAPM_MIXER_E("LOMIX", WM8990_POWER_MAN 675 SND_SOC_DAPM_MIXER_E("LOMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOMIX_ENA_BIT,
585 0, &wm8990_dapm_lomix_controls[0], 676 0, &wm8990_dapm_lomix_controls[0],
586 ARRAY_SIZE(wm8990_dapm_lomix_controls) 677 ARRAY_SIZE(wm8990_dapm_lomix_controls),
587 outmixer_event, SND_SOC_DAPM_PRE_REG), 678 outmixer_event, SND_SOC_DAPM_PRE_REG),
588 679
589 /* LONMIX */ 680 /* LONMIX */
590 SND_SOC_DAPM_MIXER("LONMIX", WM8990_POWER_MANA 681 SND_SOC_DAPM_MIXER("LONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LON_ENA_BIT, 0,
591 &wm8990_dapm_lonmix_controls[0], 682 &wm8990_dapm_lonmix_controls[0],
592 ARRAY_SIZE(wm8990_dapm_lonmix_controls 683 ARRAY_SIZE(wm8990_dapm_lonmix_controls)),
593 684
594 /* LOPMIX */ 685 /* LOPMIX */
595 SND_SOC_DAPM_MIXER("LOPMIX", WM8990_POWER_MANA 686 SND_SOC_DAPM_MIXER("LOPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOP_ENA_BIT, 0,
596 &wm8990_dapm_lopmix_controls[0], 687 &wm8990_dapm_lopmix_controls[0],
597 ARRAY_SIZE(wm8990_dapm_lopmix_controls 688 ARRAY_SIZE(wm8990_dapm_lopmix_controls)),
598 689
599 /* OUT3MIX */ 690 /* OUT3MIX */
600 SND_SOC_DAPM_MIXER("OUT3MIX", WM8990_POWER_MAN 691 SND_SOC_DAPM_MIXER("OUT3MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT3_ENA_BIT, 0,
601 &wm8990_dapm_out3mix_controls[0], 692 &wm8990_dapm_out3mix_controls[0],
602 ARRAY_SIZE(wm8990_dapm_out3mix_control 693 ARRAY_SIZE(wm8990_dapm_out3mix_controls)),
603 694
604 /* SPKMIX */ 695 /* SPKMIX */
605 SND_SOC_DAPM_MIXER_E("SPKMIX", WM8990_POWER_MA 696 SND_SOC_DAPM_MIXER_E("SPKMIX", WM8990_POWER_MANAGEMENT_1, WM8990_SPK_ENA_BIT, 0,
606 &wm8990_dapm_spkmix_controls[0], 697 &wm8990_dapm_spkmix_controls[0],
607 ARRAY_SIZE(wm8990_dapm_spkmix_controls 698 ARRAY_SIZE(wm8990_dapm_spkmix_controls), outmixer_event,
608 SND_SOC_DAPM_PRE_REG), 699 SND_SOC_DAPM_PRE_REG),
609 700
610 /* OUT4MIX */ 701 /* OUT4MIX */
611 SND_SOC_DAPM_MIXER("OUT4MIX", WM8990_POWER_MAN 702 SND_SOC_DAPM_MIXER("OUT4MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT4_ENA_BIT, 0,
612 &wm8990_dapm_out4mix_controls[0], 703 &wm8990_dapm_out4mix_controls[0],
613 ARRAY_SIZE(wm8990_dapm_out4mix_control 704 ARRAY_SIZE(wm8990_dapm_out4mix_controls)),
614 705
615 /* ROPMIX */ 706 /* ROPMIX */
616 SND_SOC_DAPM_MIXER("ROPMIX", WM8990_POWER_MANA 707 SND_SOC_DAPM_MIXER("ROPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROP_ENA_BIT, 0,
617 &wm8990_dapm_ropmix_controls[0], 708 &wm8990_dapm_ropmix_controls[0],
618 ARRAY_SIZE(wm8990_dapm_ropmix_controls 709 ARRAY_SIZE(wm8990_dapm_ropmix_controls)),
619 710
620 /* RONMIX */ 711 /* RONMIX */
621 SND_SOC_DAPM_MIXER("RONMIX", WM8990_POWER_MANA 712 SND_SOC_DAPM_MIXER("RONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_RON_ENA_BIT, 0,
622 &wm8990_dapm_ronmix_controls[0], 713 &wm8990_dapm_ronmix_controls[0],
623 ARRAY_SIZE(wm8990_dapm_ronmix_controls 714 ARRAY_SIZE(wm8990_dapm_ronmix_controls)),
624 715
625 /* ROMIX */ 716 /* ROMIX */
626 SND_SOC_DAPM_MIXER_E("ROMIX", WM8990_POWER_MAN 717 SND_SOC_DAPM_MIXER_E("ROMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROMIX_ENA_BIT,
627 0, &wm8990_dapm_romix_controls[0], 718 0, &wm8990_dapm_romix_controls[0],
628 ARRAY_SIZE(wm8990_dapm_romix_controls) 719 ARRAY_SIZE(wm8990_dapm_romix_controls),
629 outmixer_event, SND_SOC_DAPM_PRE_REG), 720 outmixer_event, SND_SOC_DAPM_PRE_REG),
630 721
631 /* LOUT PGA */ 722 /* LOUT PGA */
632 SND_SOC_DAPM_PGA("LOUT PGA", WM8990_POWER_MANA 723 SND_SOC_DAPM_PGA("LOUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_LOUT_ENA_BIT, 0,
633 NULL, 0), 724 NULL, 0),
634 725
635 /* ROUT PGA */ 726 /* ROUT PGA */
636 SND_SOC_DAPM_PGA("ROUT PGA", WM8990_POWER_MANA 727 SND_SOC_DAPM_PGA("ROUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_ROUT_ENA_BIT, 0,
637 NULL, 0), 728 NULL, 0),
638 729
639 /* LOPGA */ 730 /* LOPGA */
640 SND_SOC_DAPM_PGA("LOPGA", WM8990_POWER_MANAGEM 731 SND_SOC_DAPM_PGA("LOPGA", WM8990_POWER_MANAGEMENT_3, WM8990_LOPGA_ENA_BIT, 0,
641 NULL, 0), 732 NULL, 0),
642 733
643 /* ROPGA */ 734 /* ROPGA */
644 SND_SOC_DAPM_PGA("ROPGA", WM8990_POWER_MANAGEM 735 SND_SOC_DAPM_PGA("ROPGA", WM8990_POWER_MANAGEMENT_3, WM8990_ROPGA_ENA_BIT, 0,
645 NULL, 0), 736 NULL, 0),
646 737
647 /* MICBIAS */ 738 /* MICBIAS */
648 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8990_POWER_MA 739 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8990_POWER_MANAGEMENT_1,
649 WM8990_MICBIAS_ENA_BIT, 0, 740 WM8990_MICBIAS_ENA_BIT, 0, NULL, 0),
650 741
651 SND_SOC_DAPM_OUTPUT("LON"), 742 SND_SOC_DAPM_OUTPUT("LON"),
652 SND_SOC_DAPM_OUTPUT("LOP"), 743 SND_SOC_DAPM_OUTPUT("LOP"),
653 SND_SOC_DAPM_OUTPUT("OUT3"), 744 SND_SOC_DAPM_OUTPUT("OUT3"),
654 SND_SOC_DAPM_OUTPUT("LOUT"), 745 SND_SOC_DAPM_OUTPUT("LOUT"),
655 SND_SOC_DAPM_OUTPUT("SPKN"), 746 SND_SOC_DAPM_OUTPUT("SPKN"),
656 SND_SOC_DAPM_OUTPUT("SPKP"), 747 SND_SOC_DAPM_OUTPUT("SPKP"),
657 SND_SOC_DAPM_OUTPUT("ROUT"), 748 SND_SOC_DAPM_OUTPUT("ROUT"),
658 SND_SOC_DAPM_OUTPUT("OUT4"), 749 SND_SOC_DAPM_OUTPUT("OUT4"),
659 SND_SOC_DAPM_OUTPUT("ROP"), 750 SND_SOC_DAPM_OUTPUT("ROP"),
660 SND_SOC_DAPM_OUTPUT("RON"), 751 SND_SOC_DAPM_OUTPUT("RON"),
661 752
662 SND_SOC_DAPM_OUTPUT("Internal DAC Sink"), 753 SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
663 }; 754 };
664 755
665 static const struct snd_soc_dapm_route wm8990_ 756 static const struct snd_soc_dapm_route wm8990_dapm_routes[] = {
666 /* Make DACs turn on when playing even 757 /* Make DACs turn on when playing even if not mixed into any outputs */
667 {"Internal DAC Sink", NULL, "Left DAC" 758 {"Internal DAC Sink", NULL, "Left DAC"},
668 {"Internal DAC Sink", NULL, "Right DAC 759 {"Internal DAC Sink", NULL, "Right DAC"},
669 760
670 /* Make ADCs turn on when recording ev 761 /* Make ADCs turn on when recording even if not mixed from any inputs */
671 {"Left ADC", NULL, "Internal ADC Sourc 762 {"Left ADC", NULL, "Internal ADC Source"},
672 {"Right ADC", NULL, "Internal ADC Sour 763 {"Right ADC", NULL, "Internal ADC Source"},
673 764
674 {"AINLMUX", NULL, "INL"}, 765 {"AINLMUX", NULL, "INL"},
675 {"INMIXL", NULL, "INL"}, 766 {"INMIXL", NULL, "INL"},
676 {"AINRMUX", NULL, "INR"}, 767 {"AINRMUX", NULL, "INR"},
677 {"INMIXR", NULL, "INR"}, 768 {"INMIXR", NULL, "INR"},
678 769
679 /* Input Side */ 770 /* Input Side */
680 /* LIN12 PGA */ 771 /* LIN12 PGA */
681 {"LIN12 PGA", "LIN1 Switch", "LIN1"}, 772 {"LIN12 PGA", "LIN1 Switch", "LIN1"},
682 {"LIN12 PGA", "LIN2 Switch", "LIN2"}, 773 {"LIN12 PGA", "LIN2 Switch", "LIN2"},
683 /* LIN34 PGA */ 774 /* LIN34 PGA */
684 {"LIN34 PGA", "LIN3 Switch", "LIN3"}, 775 {"LIN34 PGA", "LIN3 Switch", "LIN3"},
685 {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN 776 {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"},
686 /* INMIXL */ 777 /* INMIXL */
687 {"INMIXL", "Record Left Volume", "LOMI 778 {"INMIXL", "Record Left Volume", "LOMIX"},
688 {"INMIXL", "LIN2 Volume", "LIN2"}, 779 {"INMIXL", "LIN2 Volume", "LIN2"},
689 {"INMIXL", "LINPGA12 Switch", "LIN12 P 780 {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
690 {"INMIXL", "LINPGA34 Switch", "LIN34 P 781 {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
691 /* AINLMUX */ 782 /* AINLMUX */
692 {"AINLMUX", "INMIXL Mix", "INMIXL"}, 783 {"AINLMUX", "INMIXL Mix", "INMIXL"},
693 {"AINLMUX", "DIFFINL Mix", "LIN12 PGA" 784 {"AINLMUX", "DIFFINL Mix", "LIN12 PGA"},
694 {"AINLMUX", "DIFFINL Mix", "LIN34 PGA" 785 {"AINLMUX", "DIFFINL Mix", "LIN34 PGA"},
695 {"AINLMUX", "RXVOICE Mix", "LIN4/RXN"} 786 {"AINLMUX", "RXVOICE Mix", "LIN4/RXN"},
696 {"AINLMUX", "RXVOICE Mix", "RIN4/RXP"} 787 {"AINLMUX", "RXVOICE Mix", "RIN4/RXP"},
697 /* ADC */ 788 /* ADC */
698 {"Left ADC", NULL, "AINLMUX"}, 789 {"Left ADC", NULL, "AINLMUX"},
699 790
700 /* RIN12 PGA */ 791 /* RIN12 PGA */
701 {"RIN12 PGA", "RIN1 Switch", "RIN1"}, 792 {"RIN12 PGA", "RIN1 Switch", "RIN1"},
702 {"RIN12 PGA", "RIN2 Switch", "RIN2"}, 793 {"RIN12 PGA", "RIN2 Switch", "RIN2"},
703 /* RIN34 PGA */ 794 /* RIN34 PGA */
704 {"RIN34 PGA", "RIN3 Switch", "RIN3"}, 795 {"RIN34 PGA", "RIN3 Switch", "RIN3"},
705 {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP 796 {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"},
706 /* INMIXL */ 797 /* INMIXL */
707 {"INMIXR", "Record Right Volume", "ROM 798 {"INMIXR", "Record Right Volume", "ROMIX"},
708 {"INMIXR", "RIN2 Volume", "RIN2"}, 799 {"INMIXR", "RIN2 Volume", "RIN2"},
709 {"INMIXR", "RINPGA12 Switch", "RIN12 P 800 {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
710 {"INMIXR", "RINPGA34 Switch", "RIN34 P 801 {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
711 /* AINRMUX */ 802 /* AINRMUX */
712 {"AINRMUX", "INMIXR Mix", "INMIXR"}, 803 {"AINRMUX", "INMIXR Mix", "INMIXR"},
713 {"AINRMUX", "DIFFINR Mix", "RIN12 PGA" 804 {"AINRMUX", "DIFFINR Mix", "RIN12 PGA"},
714 {"AINRMUX", "DIFFINR Mix", "RIN34 PGA" 805 {"AINRMUX", "DIFFINR Mix", "RIN34 PGA"},
715 {"AINRMUX", "RXVOICE Mix", "LIN4/RXN"} 806 {"AINRMUX", "RXVOICE Mix", "LIN4/RXN"},
716 {"AINRMUX", "RXVOICE Mix", "RIN4/RXP"} 807 {"AINRMUX", "RXVOICE Mix", "RIN4/RXP"},
717 /* ADC */ 808 /* ADC */
718 {"Right ADC", NULL, "AINRMUX"}, 809 {"Right ADC", NULL, "AINRMUX"},
719 810
720 /* LOMIX */ 811 /* LOMIX */
721 {"LOMIX", "LOMIX RIN3 Bypass Switch", 812 {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
722 {"LOMIX", "LOMIX LIN3 Bypass Switch", 813 {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
723 {"LOMIX", "LOMIX LIN12 PGA Bypass Swit 814 {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
724 {"LOMIX", "LOMIX RIN12 PGA Bypass Swit 815 {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
725 {"LOMIX", "LOMIX Right ADC Bypass Swit 816 {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"},
726 {"LOMIX", "LOMIX Left ADC Bypass Switc 817 {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"},
727 {"LOMIX", "LOMIX Left DAC Switch", "Le 818 {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
728 819
729 /* ROMIX */ 820 /* ROMIX */
730 {"ROMIX", "ROMIX RIN3 Bypass Switch", 821 {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
731 {"ROMIX", "ROMIX LIN3 Bypass Switch", 822 {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
732 {"ROMIX", "ROMIX LIN12 PGA Bypass Swit 823 {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
733 {"ROMIX", "ROMIX RIN12 PGA Bypass Swit 824 {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
734 {"ROMIX", "ROMIX Right ADC Bypass Swit 825 {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"},
735 {"ROMIX", "ROMIX Left ADC Bypass Switc 826 {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"},
736 {"ROMIX", "ROMIX Right DAC Switch", "R 827 {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
737 828
738 /* SPKMIX */ 829 /* SPKMIX */
739 {"SPKMIX", "SPKMIX LIN2 Bypass Switch" 830 {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
740 {"SPKMIX", "SPKMIX RIN2 Bypass Switch" 831 {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
741 {"SPKMIX", "SPKMIX LADC Bypass Switch" 832 {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"},
742 {"SPKMIX", "SPKMIX RADC Bypass Switch" 833 {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"},
743 {"SPKMIX", "SPKMIX Left Mixer PGA Swit 834 {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
744 {"SPKMIX", "SPKMIX Right Mixer PGA Swi 835 {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
745 {"SPKMIX", "SPKMIX Right DAC Switch", 836 {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
746 {"SPKMIX", "SPKMIX Left DAC Switch", " 837 {"SPKMIX", "SPKMIX Left DAC Switch", "Left DAC"},
747 838
748 /* LONMIX */ 839 /* LONMIX */
749 {"LONMIX", "LONMIX Left Mixer PGA Swit 840 {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
750 {"LONMIX", "LONMIX Right Mixer PGA Swi 841 {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
751 {"LONMIX", "LONMIX Inverted LOP Switch 842 {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
752 843
753 /* LOPMIX */ 844 /* LOPMIX */
754 {"LOPMIX", "LOPMIX Right Mic Bypass Sw 845 {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
755 {"LOPMIX", "LOPMIX Left Mic Bypass Swi 846 {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
756 {"LOPMIX", "LOPMIX Left Mixer PGA Swit 847 {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
757 848
758 /* OUT3MIX */ 849 /* OUT3MIX */
759 {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass S 850 {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"},
760 {"OUT3MIX", "OUT3MIX Left Out PGA Swit 851 {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
761 852
762 /* OUT4MIX */ 853 /* OUT4MIX */
763 {"OUT4MIX", "OUT4MIX Right Out PGA Swi 854 {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
764 {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass S 855 {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"},
765 856
766 /* RONMIX */ 857 /* RONMIX */
767 {"RONMIX", "RONMIX Right Mixer PGA Swi 858 {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
768 {"RONMIX", "RONMIX Left Mixer PGA Swit 859 {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
769 {"RONMIX", "RONMIX Inverted ROP Switch 860 {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
770 861
771 /* ROPMIX */ 862 /* ROPMIX */
772 {"ROPMIX", "ROPMIX Left Mic Bypass Swi 863 {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
773 {"ROPMIX", "ROPMIX Right Mic Bypass Sw 864 {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
774 {"ROPMIX", "ROPMIX Right Mixer PGA Swi 865 {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
775 866
776 /* Out Mixer PGAs */ 867 /* Out Mixer PGAs */
777 {"LOPGA", NULL, "LOMIX"}, 868 {"LOPGA", NULL, "LOMIX"},
778 {"ROPGA", NULL, "ROMIX"}, 869 {"ROPGA", NULL, "ROMIX"},
779 870
780 {"LOUT PGA", NULL, "LOMIX"}, 871 {"LOUT PGA", NULL, "LOMIX"},
781 {"ROUT PGA", NULL, "ROMIX"}, 872 {"ROUT PGA", NULL, "ROMIX"},
782 873
783 /* Output Pins */ 874 /* Output Pins */
784 {"LON", NULL, "LONMIX"}, 875 {"LON", NULL, "LONMIX"},
785 {"LOP", NULL, "LOPMIX"}, 876 {"LOP", NULL, "LOPMIX"},
786 {"OUT3", NULL, "OUT3MIX"}, 877 {"OUT3", NULL, "OUT3MIX"},
787 {"LOUT", NULL, "LOUT PGA"}, 878 {"LOUT", NULL, "LOUT PGA"},
788 {"SPKN", NULL, "SPKMIX"}, 879 {"SPKN", NULL, "SPKMIX"},
789 {"ROUT", NULL, "ROUT PGA"}, 880 {"ROUT", NULL, "ROUT PGA"},
790 {"OUT4", NULL, "OUT4MIX"}, 881 {"OUT4", NULL, "OUT4MIX"},
791 {"ROP", NULL, "ROPMIX"}, 882 {"ROP", NULL, "ROPMIX"},
792 {"RON", NULL, "RONMIX"}, 883 {"RON", NULL, "RONMIX"},
793 }; 884 };
794 885
795 /* PLL divisors */ 886 /* PLL divisors */
796 struct _pll_div { 887 struct _pll_div {
797 u32 div2; 888 u32 div2;
798 u32 n; 889 u32 n;
799 u32 k; 890 u32 k;
800 }; 891 };
801 892
802 /* The size in bits of the pll divide multipli 893 /* The size in bits of the pll divide multiplied by 10
803 * to allow rounding later */ 894 * to allow rounding later */
804 #define FIXED_PLL_SIZE ((1 << 16) * 10) 895 #define FIXED_PLL_SIZE ((1 << 16) * 10)
805 896
806 static void pll_factors(struct _pll_div *pll_d 897 static void pll_factors(struct _pll_div *pll_div, unsigned int target,
807 unsigned int source) 898 unsigned int source)
808 { 899 {
809 u64 Kpart; 900 u64 Kpart;
810 unsigned int K, Ndiv, Nmod; 901 unsigned int K, Ndiv, Nmod;
811 902
812 903
813 Ndiv = target / source; 904 Ndiv = target / source;
814 if (Ndiv < 6) { 905 if (Ndiv < 6) {
815 source >>= 1; 906 source >>= 1;
816 pll_div->div2 = 1; 907 pll_div->div2 = 1;
817 Ndiv = target / source; 908 Ndiv = target / source;
818 } else 909 } else
819 pll_div->div2 = 0; 910 pll_div->div2 = 0;
820 911
821 if ((Ndiv < 6) || (Ndiv > 12)) 912 if ((Ndiv < 6) || (Ndiv > 12))
822 printk(KERN_WARNING 913 printk(KERN_WARNING
823 "WM8990 N value outwith recomm 914 "WM8990 N value outwith recommended range! N = %u\n", Ndiv);
824 915
825 pll_div->n = Ndiv; 916 pll_div->n = Ndiv;
826 Nmod = target % source; 917 Nmod = target % source;
827 Kpart = FIXED_PLL_SIZE * (long long)Nm 918 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
828 919
829 do_div(Kpart, source); 920 do_div(Kpart, source);
830 921
831 K = Kpart & 0xFFFFFFFF; 922 K = Kpart & 0xFFFFFFFF;
832 923
833 /* Check if we need to round */ 924 /* Check if we need to round */
834 if ((K % 10) >= 5) 925 if ((K % 10) >= 5)
835 K += 5; 926 K += 5;
836 927
837 /* Move down to proper range now round 928 /* Move down to proper range now rounding is done */
838 K /= 10; 929 K /= 10;
839 930
840 pll_div->k = K; 931 pll_div->k = K;
841 } 932 }
842 933
843 static int wm8990_set_dai_pll(struct snd_soc_d 934 static int wm8990_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
844 int source, unsigned int freq_ 935 int source, unsigned int freq_in, unsigned int freq_out)
845 { 936 {
846 struct snd_soc_component *component = !! 937 struct snd_soc_codec *codec = codec_dai->codec;
847 struct _pll_div pll_div; 938 struct _pll_div pll_div;
848 939
849 if (freq_in && freq_out) { 940 if (freq_in && freq_out) {
850 pll_factors(&pll_div, freq_out 941 pll_factors(&pll_div, freq_out * 4, freq_in);
851 942
852 /* Turn on PLL */ 943 /* Turn on PLL */
853 snd_soc_component_update_bits( !! 944 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_2,
854 WM8990_PLL 945 WM8990_PLL_ENA, WM8990_PLL_ENA);
855 946
856 /* sysclk comes from PLL */ 947 /* sysclk comes from PLL */
857 snd_soc_component_update_bits( !! 948 snd_soc_update_bits(codec, WM8990_CLOCKING_2,
858 WM8990_SYS 949 WM8990_SYSCLK_SRC, WM8990_SYSCLK_SRC);
859 950
860 /* set up N , fractional mode 951 /* set up N , fractional mode and pre-divisor if necessary */
861 snd_soc_component_write(compon !! 952 snd_soc_write(codec, WM8990_PLL1, pll_div.n | WM8990_SDM |
862 (pll_div.div2?WM8990_P 953 (pll_div.div2?WM8990_PRESCALE:0));
863 snd_soc_component_write(compon !! 954 snd_soc_write(codec, WM8990_PLL2, (u8)(pll_div.k>>8));
864 snd_soc_component_write(compon !! 955 snd_soc_write(codec, WM8990_PLL3, (u8)(pll_div.k & 0xFF));
865 } else { 956 } else {
866 /* Turn off PLL */ 957 /* Turn off PLL */
867 snd_soc_component_update_bits( !! 958 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_2,
868 WM8990_PLL 959 WM8990_PLL_ENA, 0);
869 } 960 }
870 return 0; 961 return 0;
871 } 962 }
872 963
873 /* 964 /*
874 * Clock after PLL and dividers 965 * Clock after PLL and dividers
875 */ 966 */
876 static int wm8990_set_dai_sysclk(struct snd_so 967 static int wm8990_set_dai_sysclk(struct snd_soc_dai *codec_dai,
877 int clk_id, unsigned int freq, 968 int clk_id, unsigned int freq, int dir)
878 { 969 {
879 struct snd_soc_component *component = !! 970 struct snd_soc_codec *codec = codec_dai->codec;
880 struct wm8990_priv *wm8990 = snd_soc_c !! 971 struct wm8990_priv *wm8990 = snd_soc_codec_get_drvdata(codec);
881 972
882 wm8990->sysclk = freq; 973 wm8990->sysclk = freq;
883 return 0; 974 return 0;
884 } 975 }
885 976
886 /* 977 /*
887 * Set's ADC and Voice DAC format. 978 * Set's ADC and Voice DAC format.
888 */ 979 */
889 static int wm8990_set_dai_fmt(struct snd_soc_d 980 static int wm8990_set_dai_fmt(struct snd_soc_dai *codec_dai,
890 unsigned int fmt) 981 unsigned int fmt)
891 { 982 {
892 struct snd_soc_component *component = !! 983 struct snd_soc_codec *codec = codec_dai->codec;
893 u16 audio1, audio3; 984 u16 audio1, audio3;
894 985
895 audio1 = snd_soc_component_read(compon !! 986 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1);
896 audio3 = snd_soc_component_read(compon !! 987 audio3 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_3);
897 988
898 /* set master/slave audio interface */ 989 /* set master/slave audio interface */
899 switch (fmt & SND_SOC_DAIFMT_MASTER_MA 990 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
900 case SND_SOC_DAIFMT_CBS_CFS: 991 case SND_SOC_DAIFMT_CBS_CFS:
901 audio3 &= ~WM8990_AIF_MSTR1; 992 audio3 &= ~WM8990_AIF_MSTR1;
902 break; 993 break;
903 case SND_SOC_DAIFMT_CBM_CFM: 994 case SND_SOC_DAIFMT_CBM_CFM:
904 audio3 |= WM8990_AIF_MSTR1; 995 audio3 |= WM8990_AIF_MSTR1;
905 break; 996 break;
906 default: 997 default:
907 return -EINVAL; 998 return -EINVAL;
908 } 999 }
909 1000
910 audio1 &= ~WM8990_AIF_FMT_MASK; 1001 audio1 &= ~WM8990_AIF_FMT_MASK;
911 1002
912 /* interface format */ 1003 /* interface format */
913 switch (fmt & SND_SOC_DAIFMT_FORMAT_MA 1004 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
914 case SND_SOC_DAIFMT_I2S: 1005 case SND_SOC_DAIFMT_I2S:
915 audio1 |= WM8990_AIF_TMF_I2S; 1006 audio1 |= WM8990_AIF_TMF_I2S;
916 audio1 &= ~WM8990_AIF_LRCLK_IN 1007 audio1 &= ~WM8990_AIF_LRCLK_INV;
917 break; 1008 break;
918 case SND_SOC_DAIFMT_RIGHT_J: 1009 case SND_SOC_DAIFMT_RIGHT_J:
919 audio1 |= WM8990_AIF_TMF_RIGHT 1010 audio1 |= WM8990_AIF_TMF_RIGHTJ;
920 audio1 &= ~WM8990_AIF_LRCLK_IN 1011 audio1 &= ~WM8990_AIF_LRCLK_INV;
921 break; 1012 break;
922 case SND_SOC_DAIFMT_LEFT_J: 1013 case SND_SOC_DAIFMT_LEFT_J:
923 audio1 |= WM8990_AIF_TMF_LEFTJ 1014 audio1 |= WM8990_AIF_TMF_LEFTJ;
924 audio1 &= ~WM8990_AIF_LRCLK_IN 1015 audio1 &= ~WM8990_AIF_LRCLK_INV;
925 break; 1016 break;
926 case SND_SOC_DAIFMT_DSP_A: 1017 case SND_SOC_DAIFMT_DSP_A:
927 audio1 |= WM8990_AIF_TMF_DSP; 1018 audio1 |= WM8990_AIF_TMF_DSP;
928 audio1 &= ~WM8990_AIF_LRCLK_IN 1019 audio1 &= ~WM8990_AIF_LRCLK_INV;
929 break; 1020 break;
930 case SND_SOC_DAIFMT_DSP_B: 1021 case SND_SOC_DAIFMT_DSP_B:
931 audio1 |= WM8990_AIF_TMF_DSP | 1022 audio1 |= WM8990_AIF_TMF_DSP | WM8990_AIF_LRCLK_INV;
932 break; 1023 break;
933 default: 1024 default:
934 return -EINVAL; 1025 return -EINVAL;
935 } 1026 }
936 1027
937 snd_soc_component_write(component, WM8 !! 1028 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
938 snd_soc_component_write(component, WM8 !! 1029 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_3, audio3);
939 return 0; 1030 return 0;
940 } 1031 }
941 1032
942 static int wm8990_set_dai_clkdiv(struct snd_so 1033 static int wm8990_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
943 int div_id, int div) 1034 int div_id, int div)
944 { 1035 {
945 struct snd_soc_component *component = !! 1036 struct snd_soc_codec *codec = codec_dai->codec;
946 1037
947 switch (div_id) { 1038 switch (div_id) {
948 case WM8990_MCLK_DIV: 1039 case WM8990_MCLK_DIV:
949 snd_soc_component_update_bits( !! 1040 snd_soc_update_bits(codec, WM8990_CLOCKING_2,
950 WM8990_MCL 1041 WM8990_MCLK_DIV_MASK, div);
951 break; 1042 break;
952 case WM8990_DACCLK_DIV: 1043 case WM8990_DACCLK_DIV:
953 snd_soc_component_update_bits( !! 1044 snd_soc_update_bits(codec, WM8990_CLOCKING_2,
954 WM8990_DAC 1045 WM8990_DAC_CLKDIV_MASK, div);
955 break; 1046 break;
956 case WM8990_ADCCLK_DIV: 1047 case WM8990_ADCCLK_DIV:
957 snd_soc_component_update_bits( !! 1048 snd_soc_update_bits(codec, WM8990_CLOCKING_2,
958 WM8990_ADC 1049 WM8990_ADC_CLKDIV_MASK, div);
959 break; 1050 break;
960 case WM8990_BCLK_DIV: 1051 case WM8990_BCLK_DIV:
961 snd_soc_component_update_bits( !! 1052 snd_soc_update_bits(codec, WM8990_CLOCKING_1,
962 WM8990_BCL 1053 WM8990_BCLK_DIV_MASK, div);
963 break; 1054 break;
964 default: 1055 default:
965 return -EINVAL; 1056 return -EINVAL;
966 } 1057 }
967 1058
968 return 0; 1059 return 0;
969 } 1060 }
970 1061
971 /* 1062 /*
972 * Set PCM DAI bit size and sample rate. 1063 * Set PCM DAI bit size and sample rate.
973 */ 1064 */
974 static int wm8990_hw_params(struct snd_pcm_sub 1065 static int wm8990_hw_params(struct snd_pcm_substream *substream,
975 struct snd_pcm_hw_ 1066 struct snd_pcm_hw_params *params,
976 struct snd_soc_dai 1067 struct snd_soc_dai *dai)
977 { 1068 {
978 struct snd_soc_component *component = !! 1069 struct snd_soc_codec *codec = dai->codec;
979 u16 audio1 = snd_soc_component_read(co !! 1070 u16 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1);
980 1071
981 audio1 &= ~WM8990_AIF_WL_MASK; 1072 audio1 &= ~WM8990_AIF_WL_MASK;
982 /* bit size */ 1073 /* bit size */
983 switch (params_width(params)) { 1074 switch (params_width(params)) {
984 case 16: 1075 case 16:
985 break; 1076 break;
986 case 20: 1077 case 20:
987 audio1 |= WM8990_AIF_WL_20BITS 1078 audio1 |= WM8990_AIF_WL_20BITS;
988 break; 1079 break;
989 case 24: 1080 case 24:
990 audio1 |= WM8990_AIF_WL_24BITS 1081 audio1 |= WM8990_AIF_WL_24BITS;
991 break; 1082 break;
992 case 32: 1083 case 32:
993 audio1 |= WM8990_AIF_WL_32BITS 1084 audio1 |= WM8990_AIF_WL_32BITS;
994 break; 1085 break;
995 } 1086 }
996 1087
997 snd_soc_component_write(component, WM8 !! 1088 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
998 return 0; 1089 return 0;
999 } 1090 }
1000 1091
1001 static int wm8990_mute(struct snd_soc_dai *da !! 1092 static int wm8990_mute(struct snd_soc_dai *dai, int mute)
1002 { 1093 {
1003 struct snd_soc_component *component = !! 1094 struct snd_soc_codec *codec = dai->codec;
1004 u16 val; 1095 u16 val;
1005 1096
1006 val = snd_soc_component_read(compone !! 1097 val = snd_soc_read(codec, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE;
1007 1098
1008 if (mute) 1099 if (mute)
1009 snd_soc_component_write(compo !! 1100 snd_soc_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE);
1010 else 1101 else
1011 snd_soc_component_write(compo !! 1102 snd_soc_write(codec, WM8990_DAC_CTRL, val);
1012 1103
1013 return 0; 1104 return 0;
1014 } 1105 }
1015 1106
1016 static int wm8990_set_bias_level(struct snd_s !! 1107 static int wm8990_set_bias_level(struct snd_soc_codec *codec,
1017 enum snd_soc_bias_level level) 1108 enum snd_soc_bias_level level)
1018 { 1109 {
1019 struct wm8990_priv *wm8990 = snd_soc_ !! 1110 struct wm8990_priv *wm8990 = snd_soc_codec_get_drvdata(codec);
1020 int ret; 1111 int ret;
1021 1112
1022 switch (level) { 1113 switch (level) {
1023 case SND_SOC_BIAS_ON: 1114 case SND_SOC_BIAS_ON:
1024 break; 1115 break;
1025 1116
1026 case SND_SOC_BIAS_PREPARE: 1117 case SND_SOC_BIAS_PREPARE:
1027 /* VMID=2*50k */ 1118 /* VMID=2*50k */
1028 snd_soc_component_update_bits !! 1119 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_1,
1029 WM8990_VM 1120 WM8990_VMID_MODE_MASK, 0x2);
1030 break; 1121 break;
1031 1122
1032 case SND_SOC_BIAS_STANDBY: 1123 case SND_SOC_BIAS_STANDBY:
1033 if (snd_soc_component_get_bia !! 1124 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
1034 ret = regcache_sync(w 1125 ret = regcache_sync(wm8990->regmap);
1035 if (ret < 0) { 1126 if (ret < 0) {
1036 dev_err(compo !! 1127 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
1037 return ret; 1128 return ret;
1038 } 1129 }
1039 1130
1040 /* Enable all output 1131 /* Enable all output discharge bits */
1041 snd_soc_component_wri !! 1132 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
1042 WM8990_DIS_RL 1133 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1043 WM8990_DIS_OU 1134 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1044 WM8990_DIS_RO 1135 WM8990_DIS_ROUT);
1045 1136
1046 /* Enable POBCTRL, SO 1137 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
1047 snd_soc_component_wri !! 1138 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1048 WM8990_B 1139 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1049 WM8990_V 1140 WM8990_VMIDTOG);
1050 1141
1051 /* Delay to allow out 1142 /* Delay to allow output caps to discharge */
1052 msleep(300); 1143 msleep(300);
1053 1144
1054 /* Disable VMIDTOG */ 1145 /* Disable VMIDTOG */
1055 snd_soc_component_wri !! 1146 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1056 WM8990_B 1147 WM8990_BUFDCOPEN | WM8990_POBCTRL);
1057 1148
1058 /* disable all output 1149 /* disable all output discharge bits */
1059 snd_soc_component_wri !! 1150 snd_soc_write(codec, WM8990_ANTIPOP1, 0);
1060 1151
1061 /* Enable outputs */ 1152 /* Enable outputs */
1062 snd_soc_component_wri !! 1153 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1b00);
1063 1154
1064 msleep(50); 1155 msleep(50);
1065 1156
1066 /* Enable VMID at 2x5 1157 /* Enable VMID at 2x50k */
1067 snd_soc_component_wri !! 1158 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f02);
1068 1159
1069 msleep(100); 1160 msleep(100);
1070 1161
1071 /* Enable VREF */ 1162 /* Enable VREF */
1072 snd_soc_component_wri !! 1163 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
1073 1164
1074 msleep(600); 1165 msleep(600);
1075 1166
1076 /* Enable BUFIOEN */ 1167 /* Enable BUFIOEN */
1077 snd_soc_component_wri !! 1168 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1078 WM8990_B 1169 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1079 WM8990_B 1170 WM8990_BUFIOEN);
1080 1171
1081 /* Disable outputs */ 1172 /* Disable outputs */
1082 snd_soc_component_wri !! 1173 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x3);
1083 1174
1084 /* disable POBCTRL, S 1175 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1085 snd_soc_component_wri !! 1176 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_BUFIOEN);
1086 1177
1087 /* Enable workaround 1178 /* Enable workaround for ADC clocking issue. */
1088 snd_soc_component_wri !! 1179 snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0x2);
1089 snd_soc_component_wri !! 1180 snd_soc_write(codec, WM8990_EXT_CTL1, 0xa003);
1090 snd_soc_component_wri !! 1181 snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0);
1091 } 1182 }
1092 1183
1093 /* VMID=2*250k */ 1184 /* VMID=2*250k */
1094 snd_soc_component_update_bits !! 1185 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_1,
1095 WM8990_VM 1186 WM8990_VMID_MODE_MASK, 0x4);
1096 break; 1187 break;
1097 1188
1098 case SND_SOC_BIAS_OFF: 1189 case SND_SOC_BIAS_OFF:
1099 /* Enable POBCTRL and SOFT_ST 1190 /* Enable POBCTRL and SOFT_ST */
1100 snd_soc_component_write(compo !! 1191 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1101 WM8990_POBCTRL | WM89 1192 WM8990_POBCTRL | WM8990_BUFIOEN);
1102 1193
1103 /* Enable POBCTRL, SOFT_ST an 1194 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
1104 snd_soc_component_write(compo !! 1195 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1105 WM8990_BUFDCOPEN | WM 1196 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1106 WM8990_BUFIOEN); 1197 WM8990_BUFIOEN);
1107 1198
1108 /* mute DAC */ 1199 /* mute DAC */
1109 snd_soc_component_update_bits !! 1200 snd_soc_update_bits(codec, WM8990_DAC_CTRL,
1110 WM8990_DA 1201 WM8990_DAC_MUTE, WM8990_DAC_MUTE);
1111 1202
1112 /* Enable any disabled output 1203 /* Enable any disabled outputs */
1113 snd_soc_component_write(compo !! 1204 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
1114 1205
1115 /* Disable VMID */ 1206 /* Disable VMID */
1116 snd_soc_component_write(compo !! 1207 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f01);
1117 1208
1118 msleep(300); 1209 msleep(300);
1119 1210
1120 /* Enable all output discharg 1211 /* Enable all output discharge bits */
1121 snd_soc_component_write(compo !! 1212 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
1122 WM8990_DIS_RLINE | WM 1213 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1123 WM8990_DIS_OUT4 | WM8 1214 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1124 WM8990_DIS_ROUT); 1215 WM8990_DIS_ROUT);
1125 1216
1126 /* Disable VREF */ 1217 /* Disable VREF */
1127 snd_soc_component_write(compo !! 1218 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x0);
1128 1219
1129 /* disable POBCTRL, SOFT_ST a 1220 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1130 snd_soc_component_write(compo !! 1221 snd_soc_write(codec, WM8990_ANTIPOP2, 0x0);
1131 1222
1132 regcache_mark_dirty(wm8990->r 1223 regcache_mark_dirty(wm8990->regmap);
1133 break; 1224 break;
1134 } 1225 }
1135 1226
1136 return 0; 1227 return 0;
1137 } 1228 }
1138 1229
1139 #define WM8990_RATES (SNDRV_PCM_RATE_8000 | S 1230 #define WM8990_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
1140 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE 1231 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
1141 SNDRV_PCM_RATE_48000) 1232 SNDRV_PCM_RATE_48000)
1142 1233
1143 #define WM8990_FORMATS (SNDRV_PCM_FMTBIT_S16_ 1234 #define WM8990_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1144 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_F 1235 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1145 1236
1146 /* 1237 /*
1147 * The WM8990 supports 2 different and mutual 1238 * The WM8990 supports 2 different and mutually exclusive DAI
1148 * configurations. 1239 * configurations.
1149 * 1240 *
1150 * 1. ADC/DAC on Primary Interface 1241 * 1. ADC/DAC on Primary Interface
1151 * 2. ADC on Primary Interface/DAC on seconda 1242 * 2. ADC on Primary Interface/DAC on secondary
1152 */ 1243 */
1153 static const struct snd_soc_dai_ops wm8990_da 1244 static const struct snd_soc_dai_ops wm8990_dai_ops = {
1154 .hw_params = wm8990_hw_params, 1245 .hw_params = wm8990_hw_params,
1155 .mute_stream = wm8990_mute, !! 1246 .digital_mute = wm8990_mute,
1156 .set_fmt = wm8990_set_dai_fmt, 1247 .set_fmt = wm8990_set_dai_fmt,
1157 .set_clkdiv = wm8990_set_dai_clkd 1248 .set_clkdiv = wm8990_set_dai_clkdiv,
1158 .set_pll = wm8990_set_dai_pll, 1249 .set_pll = wm8990_set_dai_pll,
1159 .set_sysclk = wm8990_set_dai_sysc 1250 .set_sysclk = wm8990_set_dai_sysclk,
1160 .no_capture_mute = 1, <<
1161 }; 1251 };
1162 1252
1163 static struct snd_soc_dai_driver wm8990_dai = 1253 static struct snd_soc_dai_driver wm8990_dai = {
1164 /* ADC/DAC on primary */ 1254 /* ADC/DAC on primary */
1165 .name = "wm8990-hifi", 1255 .name = "wm8990-hifi",
1166 .playback = { 1256 .playback = {
1167 .stream_name = "Playback", 1257 .stream_name = "Playback",
1168 .channels_min = 1, 1258 .channels_min = 1,
1169 .channels_max = 2, 1259 .channels_max = 2,
1170 .rates = WM8990_RATES, 1260 .rates = WM8990_RATES,
1171 .formats = WM8990_FORMATS,}, 1261 .formats = WM8990_FORMATS,},
1172 .capture = { 1262 .capture = {
1173 .stream_name = "Capture", 1263 .stream_name = "Capture",
1174 .channels_min = 1, 1264 .channels_min = 1,
1175 .channels_max = 2, 1265 .channels_max = 2,
1176 .rates = WM8990_RATES, 1266 .rates = WM8990_RATES,
1177 .formats = WM8990_FORMATS,}, 1267 .formats = WM8990_FORMATS,},
1178 .ops = &wm8990_dai_ops, 1268 .ops = &wm8990_dai_ops,
1179 }; 1269 };
1180 1270
1181 /* 1271 /*
1182 * initialise the WM8990 driver 1272 * initialise the WM8990 driver
1183 * register the mixer and dsp interfaces with 1273 * register the mixer and dsp interfaces with the kernel
1184 */ 1274 */
1185 static int wm8990_probe(struct snd_soc_compon !! 1275 static int wm8990_probe(struct snd_soc_codec *codec)
1186 { 1276 {
1187 wm8990_reset(component); !! 1277 wm8990_reset(codec);
1188 1278
1189 /* charge output caps */ 1279 /* charge output caps */
1190 snd_soc_component_force_bias_level(co !! 1280 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_STANDBY);
1191 1281
1192 snd_soc_component_update_bits(compone !! 1282 snd_soc_update_bits(codec, WM8990_AUDIO_INTERFACE_4,
1193 WM8990_ALRCGPIO1, 1283 WM8990_ALRCGPIO1, WM8990_ALRCGPIO1);
1194 1284
1195 snd_soc_component_update_bits(compone !! 1285 snd_soc_update_bits(codec, WM8990_GPIO1_GPIO2,
1196 WM8990_GPIO1_SEL_ 1286 WM8990_GPIO1_SEL_MASK, 1);
1197 1287
1198 snd_soc_component_update_bits(compone !! 1288 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_2,
1199 WM8990_OPCLK_ENA, 1289 WM8990_OPCLK_ENA, WM8990_OPCLK_ENA);
1200 1290
1201 snd_soc_component_write(component, WM !! 1291 snd_soc_write(codec, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
1202 snd_soc_component_write(component, WM !! 1292 snd_soc_write(codec, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
1203 1293
1204 return 0; 1294 return 0;
1205 } 1295 }
1206 1296
1207 static const struct snd_soc_component_driver !! 1297 static const struct snd_soc_codec_driver soc_codec_dev_wm8990 = {
1208 .probe = wm8990_prob !! 1298 .probe = wm8990_probe,
1209 .set_bias_level = wm8990_set_ !! 1299 .set_bias_level = wm8990_set_bias_level,
1210 .controls = wm8990_snd_ !! 1300 .suspend_bias_off = true,
1211 .num_controls = ARRAY_SIZE( !! 1301
1212 .dapm_widgets = wm8990_dapm !! 1302 .component_driver = {
1213 .num_dapm_widgets = ARRAY_SIZE( !! 1303 .controls = wm8990_snd_controls,
1214 .dapm_routes = wm8990_dapm !! 1304 .num_controls = ARRAY_SIZE(wm8990_snd_controls),
1215 .num_dapm_routes = ARRAY_SIZE( !! 1305 .dapm_widgets = wm8990_dapm_widgets,
1216 .suspend_bias_off = 1, !! 1306 .num_dapm_widgets = ARRAY_SIZE(wm8990_dapm_widgets),
1217 .idle_bias_on = 1, !! 1307 .dapm_routes = wm8990_dapm_routes,
1218 .use_pmdown_time = 1, !! 1308 .num_dapm_routes = ARRAY_SIZE(wm8990_dapm_routes),
1219 .endianness = 1, !! 1309 },
>> 1310 };
>> 1311
>> 1312 static const struct regmap_config wm8990_regmap = {
>> 1313 .reg_bits = 8,
>> 1314 .val_bits = 16,
>> 1315
>> 1316 .max_register = WM8990_PLL3,
>> 1317 .volatile_reg = wm8990_volatile_register,
>> 1318 .reg_defaults = wm8990_reg_defaults,
>> 1319 .num_reg_defaults = ARRAY_SIZE(wm8990_reg_defaults),
>> 1320 .cache_type = REGCACHE_RBTREE,
1220 }; 1321 };
1221 1322
1222 static int wm8990_i2c_probe(struct i2c_client !! 1323 static int wm8990_i2c_probe(struct i2c_client *i2c,
>> 1324 const struct i2c_device_id *id)
1223 { 1325 {
1224 struct wm8990_priv *wm8990; 1326 struct wm8990_priv *wm8990;
1225 int ret; 1327 int ret;
1226 1328
1227 wm8990 = devm_kzalloc(&i2c->dev, size 1329 wm8990 = devm_kzalloc(&i2c->dev, sizeof(struct wm8990_priv),
1228 GFP_KERNEL); 1330 GFP_KERNEL);
1229 if (wm8990 == NULL) 1331 if (wm8990 == NULL)
1230 return -ENOMEM; 1332 return -ENOMEM;
1231 1333
1232 i2c_set_clientdata(i2c, wm8990); 1334 i2c_set_clientdata(i2c, wm8990);
1233 1335
1234 ret = devm_snd_soc_register_component !! 1336 ret = snd_soc_register_codec(&i2c->dev,
1235 &soc_component_dev_wm !! 1337 &soc_codec_dev_wm8990, &wm8990_dai, 1);
1236 1338
1237 return ret; 1339 return ret;
1238 } 1340 }
1239 1341
>> 1342 static int wm8990_i2c_remove(struct i2c_client *client)
>> 1343 {
>> 1344 snd_soc_unregister_codec(&client->dev);
>> 1345
>> 1346 return 0;
>> 1347 }
>> 1348
1240 static const struct i2c_device_id wm8990_i2c_ 1349 static const struct i2c_device_id wm8990_i2c_id[] = {
1241 { "wm8990" }, !! 1350 { "wm8990", 0 },
1242 { } 1351 { }
1243 }; 1352 };
1244 MODULE_DEVICE_TABLE(i2c, wm8990_i2c_id); 1353 MODULE_DEVICE_TABLE(i2c, wm8990_i2c_id);
1245 1354
1246 static struct i2c_driver wm8990_i2c_driver = 1355 static struct i2c_driver wm8990_i2c_driver = {
1247 .driver = { 1356 .driver = {
1248 .name = "wm8990", 1357 .name = "wm8990",
1249 }, 1358 },
1250 .probe = wm8990_i2c_probe, !! 1359 .probe = wm8990_i2c_probe,
>> 1360 .remove = wm8990_i2c_remove,
1251 .id_table = wm8990_i2c_id, 1361 .id_table = wm8990_i2c_id,
1252 }; 1362 };
1253 1363
1254 module_i2c_driver(wm8990_i2c_driver); 1364 module_i2c_driver(wm8990_i2c_driver);
1255 1365
1256 MODULE_DESCRIPTION("ASoC WM8990 driver"); 1366 MODULE_DESCRIPTION("ASoC WM8990 driver");
1257 MODULE_AUTHOR("Liam Girdwood"); 1367 MODULE_AUTHOR("Liam Girdwood");
1258 MODULE_LICENSE("GPL"); 1368 MODULE_LICENSE("GPL");
1259 1369
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