1 // SPDX-License-Identifier: GPL-2.0-or-later 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* 2 /*
3 * wm8990.c -- WM8990 ALSA Soc Audio driver 3 * wm8990.c -- WM8990 ALSA Soc Audio driver
4 * 4 *
5 * Copyright 2008 Wolfson Microelectronics PLC 5 * Copyright 2008 Wolfson Microelectronics PLC.
6 * Author: Liam Girdwood <lrg@slimlogic.co.uk> 6 * Author: Liam Girdwood <lrg@slimlogic.co.uk>
7 */ 7 */
8 8
9 #include <linux/module.h> 9 #include <linux/module.h>
10 #include <linux/moduleparam.h> 10 #include <linux/moduleparam.h>
11 #include <linux/kernel.h> 11 #include <linux/kernel.h>
12 #include <linux/init.h> 12 #include <linux/init.h>
13 #include <linux/delay.h> 13 #include <linux/delay.h>
14 #include <linux/pm.h> 14 #include <linux/pm.h>
15 #include <linux/i2c.h> 15 #include <linux/i2c.h>
16 #include <linux/regmap.h> 16 #include <linux/regmap.h>
17 #include <linux/slab.h> 17 #include <linux/slab.h>
18 #include <sound/core.h> 18 #include <sound/core.h>
19 #include <sound/pcm.h> 19 #include <sound/pcm.h>
20 #include <sound/pcm_params.h> 20 #include <sound/pcm_params.h>
21 #include <sound/soc.h> 21 #include <sound/soc.h>
22 #include <sound/initval.h> 22 #include <sound/initval.h>
23 #include <sound/tlv.h> 23 #include <sound/tlv.h>
24 #include <asm/div64.h> 24 #include <asm/div64.h>
25 25
26 #include "wm8990.h" 26 #include "wm8990.h"
27 27
28 /* codec private data */ 28 /* codec private data */
29 struct wm8990_priv { 29 struct wm8990_priv {
30 struct regmap *regmap; 30 struct regmap *regmap;
31 unsigned int sysclk; 31 unsigned int sysclk;
32 unsigned int pcmclk; 32 unsigned int pcmclk;
33 }; 33 };
34 34
35 #define wm8990_reset(c) snd_soc_component_writ 35 #define wm8990_reset(c) snd_soc_component_write(c, WM8990_RESET, 0)
36 36
37 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, 37 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
38 38
39 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, 39 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, 0, -2100, 0);
40 40
41 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, 41 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
42 42
43 static const DECLARE_TLV_DB_SCALE(out_dac_tlv, 43 static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
44 44
45 static const DECLARE_TLV_DB_SCALE(in_adc_tlv, 45 static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0);
46 46
47 static const DECLARE_TLV_DB_SCALE(out_sidetone 47 static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
48 48
49 static int wm899x_outpga_put_volsw_vu(struct s 49 static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
50 struct snd_ctl_elem_value *ucontrol) 50 struct snd_ctl_elem_value *ucontrol)
51 { 51 {
52 struct snd_soc_component *component = 52 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
53 struct soc_mixer_control *mc = 53 struct soc_mixer_control *mc =
54 (struct soc_mixer_control *)kc 54 (struct soc_mixer_control *)kcontrol->private_value;
55 int reg = mc->reg; 55 int reg = mc->reg;
56 int ret; 56 int ret;
57 u16 val; 57 u16 val;
58 58
59 ret = snd_soc_put_volsw(kcontrol, ucon 59 ret = snd_soc_put_volsw(kcontrol, ucontrol);
60 if (ret < 0) 60 if (ret < 0)
61 return ret; 61 return ret;
62 62
63 /* now hit the volume update bits (alw 63 /* now hit the volume update bits (always bit 8) */
64 val = snd_soc_component_read(component 64 val = snd_soc_component_read(component, reg);
65 return snd_soc_component_write(compone 65 return snd_soc_component_write(component, reg, val | 0x0100);
66 } 66 }
67 67
68 #define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, 68 #define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\
69 tlv_array) \ 69 tlv_array) \
70 SOC_SINGLE_EXT_TLV(xname, reg, shift, 70 SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, \
71 snd_soc_get_volsw, wm899x_outp 71 snd_soc_get_volsw, wm899x_outpga_put_volsw_vu, tlv_array)
72 72
73 73
74 static const char *wm8990_digital_sidetone[] = 74 static const char *wm8990_digital_sidetone[] =
75 {"None", "Left ADC", "Right ADC", "Res 75 {"None", "Left ADC", "Right ADC", "Reserved"};
76 76
77 static SOC_ENUM_SINGLE_DECL(wm8990_left_digita 77 static SOC_ENUM_SINGLE_DECL(wm8990_left_digital_sidetone_enum,
78 WM8990_DIGITAL_SID 78 WM8990_DIGITAL_SIDE_TONE,
79 WM8990_ADC_TO_DACL 79 WM8990_ADC_TO_DACL_SHIFT,
80 wm8990_digital_sid 80 wm8990_digital_sidetone);
81 81
82 static SOC_ENUM_SINGLE_DECL(wm8990_right_digit 82 static SOC_ENUM_SINGLE_DECL(wm8990_right_digital_sidetone_enum,
83 WM8990_DIGITAL_SID 83 WM8990_DIGITAL_SIDE_TONE,
84 WM8990_ADC_TO_DACR 84 WM8990_ADC_TO_DACR_SHIFT,
85 wm8990_digital_sid 85 wm8990_digital_sidetone);
86 86
87 static const char *wm8990_adcmode[] = 87 static const char *wm8990_adcmode[] =
88 {"Hi-fi mode", "Voice mode 1", "Voice 88 {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
89 89
90 static SOC_ENUM_SINGLE_DECL(wm8990_right_adcmo 90 static SOC_ENUM_SINGLE_DECL(wm8990_right_adcmode_enum,
91 WM8990_ADC_CTRL, 91 WM8990_ADC_CTRL,
92 WM8990_ADC_HPF_CUT 92 WM8990_ADC_HPF_CUT_SHIFT,
93 wm8990_adcmode); 93 wm8990_adcmode);
94 94
95 static const struct snd_kcontrol_new wm8990_sn 95 static const struct snd_kcontrol_new wm8990_snd_controls[] = {
96 /* INMIXL */ 96 /* INMIXL */
97 SOC_SINGLE("LIN12 PGA Boost", WM8990_INPUT_MIX 97 SOC_SINGLE("LIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L12MNBST_BIT, 1, 0),
98 SOC_SINGLE("LIN34 PGA Boost", WM8990_INPUT_MIX 98 SOC_SINGLE("LIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L34MNBST_BIT, 1, 0),
99 /* INMIXR */ 99 /* INMIXR */
100 SOC_SINGLE("RIN12 PGA Boost", WM8990_INPUT_MIX 100 SOC_SINGLE("RIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R12MNBST_BIT, 1, 0),
101 SOC_SINGLE("RIN34 PGA Boost", WM8990_INPUT_MIX 101 SOC_SINGLE("RIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R34MNBST_BIT, 1, 0),
102 102
103 /* LOMIX */ 103 /* LOMIX */
104 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8 104 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER3,
105 WM8990_LLI3LOVOL_SHIFT, WM8990_LLI3LOV 105 WM8990_LLI3LOVOL_SHIFT, WM8990_LLI3LOVOL_MASK, 1, out_mix_tlv),
106 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume" 106 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
107 WM8990_LR12LOVOL_SHIFT, WM8990_LR12LOV 107 WM8990_LR12LOVOL_SHIFT, WM8990_LR12LOVOL_MASK, 1, out_mix_tlv),
108 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume" 108 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
109 WM8990_LL12LOVOL_SHIFT, WM8990_LL12LOV 109 WM8990_LL12LOVOL_SHIFT, WM8990_LL12LOVOL_MASK, 1, out_mix_tlv),
110 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8 110 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER5,
111 WM8990_LRI3LOVOL_SHIFT, WM8990_LRI3LOV 111 WM8990_LRI3LOVOL_SHIFT, WM8990_LRI3LOVOL_MASK, 1, out_mix_tlv),
112 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", 112 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
113 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL 113 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
114 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", 114 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
115 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL 115 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
116 116
117 /* ROMIX */ 117 /* ROMIX */
118 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8 118 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER4,
119 WM8990_RRI3ROVOL_SHIFT, WM8990_RRI3ROV 119 WM8990_RRI3ROVOL_SHIFT, WM8990_RRI3ROVOL_MASK, 1, out_mix_tlv),
120 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume" 120 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
121 WM8990_RL12ROVOL_SHIFT, WM8990_RL12ROV 121 WM8990_RL12ROVOL_SHIFT, WM8990_RL12ROVOL_MASK, 1, out_mix_tlv),
122 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume" 122 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
123 WM8990_RR12ROVOL_SHIFT, WM8990_RR12ROV 123 WM8990_RR12ROVOL_SHIFT, WM8990_RR12ROVOL_MASK, 1, out_mix_tlv),
124 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8 124 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER6,
125 WM8990_RLI3ROVOL_SHIFT, WM8990_RLI3ROV 125 WM8990_RLI3ROVOL_SHIFT, WM8990_RLI3ROVOL_MASK, 1, out_mix_tlv),
126 SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", 126 SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
127 WM8990_RLBROVOL_SHIFT, WM8990_RLBROVOL 127 WM8990_RLBROVOL_SHIFT, WM8990_RLBROVOL_MASK, 1, out_mix_tlv),
128 SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", 128 SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
129 WM8990_RRBROVOL_SHIFT, WM8990_RRBROVOL 129 WM8990_RRBROVOL_SHIFT, WM8990_RRBROVOL_MASK, 1, out_mix_tlv),
130 130
131 /* LOUT */ 131 /* LOUT */
132 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", 132 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8990_LEFT_OUTPUT_VOLUME,
133 WM8990_LOUTVOL_SHIFT, WM8990_LOUTVOL_M 133 WM8990_LOUTVOL_SHIFT, WM8990_LOUTVOL_MASK, 0, out_pga_tlv),
134 SOC_SINGLE("LOUT ZC", WM8990_LEFT_OUTPUT_VOLUM 134 SOC_SINGLE("LOUT ZC", WM8990_LEFT_OUTPUT_VOLUME, WM8990_LOZC_BIT, 1, 0),
135 135
136 /* ROUT */ 136 /* ROUT */
137 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", 137 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8990_RIGHT_OUTPUT_VOLUME,
138 WM8990_ROUTVOL_SHIFT, WM8990_ROUTVOL_M 138 WM8990_ROUTVOL_SHIFT, WM8990_ROUTVOL_MASK, 0, out_pga_tlv),
139 SOC_SINGLE("ROUT ZC", WM8990_RIGHT_OUTPUT_VOLU 139 SOC_SINGLE("ROUT ZC", WM8990_RIGHT_OUTPUT_VOLUME, WM8990_ROZC_BIT, 1, 0),
140 140
141 /* LOPGA */ 141 /* LOPGA */
142 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", 142 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8990_LEFT_OPGA_VOLUME,
143 WM8990_LOPGAVOL_SHIFT, WM8990_LOPGAVOL 143 WM8990_LOPGAVOL_SHIFT, WM8990_LOPGAVOL_MASK, 0, out_pga_tlv),
144 SOC_SINGLE("LOPGA ZC Switch", WM8990_LEFT_OPGA 144 SOC_SINGLE("LOPGA ZC Switch", WM8990_LEFT_OPGA_VOLUME,
145 WM8990_LOPGAZC_BIT, 1, 0), 145 WM8990_LOPGAZC_BIT, 1, 0),
146 146
147 /* ROPGA */ 147 /* ROPGA */
148 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", 148 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8990_RIGHT_OPGA_VOLUME,
149 WM8990_ROPGAVOL_SHIFT, WM8990_ROPGAVOL 149 WM8990_ROPGAVOL_SHIFT, WM8990_ROPGAVOL_MASK, 0, out_pga_tlv),
150 SOC_SINGLE("ROPGA ZC Switch", WM8990_RIGHT_OPG 150 SOC_SINGLE("ROPGA ZC Switch", WM8990_RIGHT_OPGA_VOLUME,
151 WM8990_ROPGAZC_BIT, 1, 0), 151 WM8990_ROPGAZC_BIT, 1, 0),
152 152
153 SOC_SINGLE("LON Mute Switch", WM8990_LINE_OUTP 153 SOC_SINGLE("LON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
154 WM8990_LONMUTE_BIT, 1, 0), 154 WM8990_LONMUTE_BIT, 1, 0),
155 SOC_SINGLE("LOP Mute Switch", WM8990_LINE_OUTP 155 SOC_SINGLE("LOP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
156 WM8990_LOPMUTE_BIT, 1, 0), 156 WM8990_LOPMUTE_BIT, 1, 0),
157 SOC_SINGLE("LOP Attenuation Switch", WM8990_LI 157 SOC_SINGLE("LOP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
158 WM8990_LOATTN_BIT, 1, 0), 158 WM8990_LOATTN_BIT, 1, 0),
159 SOC_SINGLE("RON Mute Switch", WM8990_LINE_OUTP 159 SOC_SINGLE("RON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
160 WM8990_RONMUTE_BIT, 1, 0), 160 WM8990_RONMUTE_BIT, 1, 0),
161 SOC_SINGLE("ROP Mute Switch", WM8990_LINE_OUTP 161 SOC_SINGLE("ROP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
162 WM8990_ROPMUTE_BIT, 1, 0), 162 WM8990_ROPMUTE_BIT, 1, 0),
163 SOC_SINGLE("ROP Attenuation Switch", WM8990_LI 163 SOC_SINGLE("ROP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
164 WM8990_ROATTN_BIT, 1, 0), 164 WM8990_ROATTN_BIT, 1, 0),
165 165
166 SOC_SINGLE("OUT3 Mute Switch", WM8990_OUT3_4_V 166 SOC_SINGLE("OUT3 Mute Switch", WM8990_OUT3_4_VOLUME,
167 WM8990_OUT3MUTE_BIT, 1, 0), 167 WM8990_OUT3MUTE_BIT, 1, 0),
168 SOC_SINGLE("OUT3 Attenuation Switch", WM8990_O 168 SOC_SINGLE("OUT3 Attenuation Switch", WM8990_OUT3_4_VOLUME,
169 WM8990_OUT3ATTN_BIT, 1, 0), 169 WM8990_OUT3ATTN_BIT, 1, 0),
170 170
171 SOC_SINGLE("OUT4 Mute Switch", WM8990_OUT3_4_V 171 SOC_SINGLE("OUT4 Mute Switch", WM8990_OUT3_4_VOLUME,
172 WM8990_OUT4MUTE_BIT, 1, 0), 172 WM8990_OUT4MUTE_BIT, 1, 0),
173 SOC_SINGLE("OUT4 Attenuation Switch", WM8990_O 173 SOC_SINGLE("OUT4 Attenuation Switch", WM8990_OUT3_4_VOLUME,
174 WM8990_OUT4ATTN_BIT, 1, 0), 174 WM8990_OUT4ATTN_BIT, 1, 0),
175 175
176 SOC_SINGLE("Speaker Mode Switch", WM8990_CLASS 176 SOC_SINGLE("Speaker Mode Switch", WM8990_CLASSD1,
177 WM8990_CDMODE_BIT, 1, 0), 177 WM8990_CDMODE_BIT, 1, 0),
178 178
179 SOC_SINGLE("Speaker Output Attenuation Volume" 179 SOC_SINGLE("Speaker Output Attenuation Volume", WM8990_SPEAKER_VOLUME,
180 WM8990_SPKATTN_SHIFT, WM8990_SPKATTN_M 180 WM8990_SPKATTN_SHIFT, WM8990_SPKATTN_MASK, 0),
181 SOC_SINGLE("Speaker DC Boost Volume", WM8990_C 181 SOC_SINGLE("Speaker DC Boost Volume", WM8990_CLASSD3,
182 WM8990_DCGAIN_SHIFT, WM8990_DCGAIN_MAS 182 WM8990_DCGAIN_SHIFT, WM8990_DCGAIN_MASK, 0),
183 SOC_SINGLE("Speaker AC Boost Volume", WM8990_C 183 SOC_SINGLE("Speaker AC Boost Volume", WM8990_CLASSD3,
184 WM8990_ACGAIN_SHIFT, WM8990_ACGAIN_MAS 184 WM8990_ACGAIN_SHIFT, WM8990_ACGAIN_MASK, 0),
185 SOC_SINGLE_TLV("Speaker Volume", WM8990_CLASSD 185 SOC_SINGLE_TLV("Speaker Volume", WM8990_CLASSD4,
186 WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MAS 186 WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MASK, 0, out_pga_tlv),
187 SOC_SINGLE("Speaker ZC Switch", WM8990_CLASSD4 187 SOC_SINGLE("Speaker ZC Switch", WM8990_CLASSD4,
188 WM8990_SPKZC_SHIFT, WM8990_SPKZC_MASK, 188 WM8990_SPKZC_SHIFT, WM8990_SPKZC_MASK, 0),
189 189
190 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digit 190 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
191 WM8990_LEFT_DAC_DIGITAL_VOLUME, 191 WM8990_LEFT_DAC_DIGITAL_VOLUME,
192 WM8990_DACL_VOL_SHIFT, 192 WM8990_DACL_VOL_SHIFT,
193 WM8990_DACL_VOL_MASK, 193 WM8990_DACL_VOL_MASK,
194 0, 194 0,
195 out_dac_tlv), 195 out_dac_tlv),
196 196
197 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digi 197 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
198 WM8990_RIGHT_DAC_DIGITAL_VOLUME, 198 WM8990_RIGHT_DAC_DIGITAL_VOLUME,
199 WM8990_DACR_VOL_SHIFT, 199 WM8990_DACR_VOL_SHIFT,
200 WM8990_DACR_VOL_MASK, 200 WM8990_DACR_VOL_MASK,
201 0, 201 0,
202 out_dac_tlv), 202 out_dac_tlv),
203 203
204 SOC_ENUM("Left Digital Sidetone", wm8990_left_ 204 SOC_ENUM("Left Digital Sidetone", wm8990_left_digital_sidetone_enum),
205 SOC_ENUM("Right Digital Sidetone", wm8990_righ 205 SOC_ENUM("Right Digital Sidetone", wm8990_right_digital_sidetone_enum),
206 206
207 SOC_SINGLE_TLV("Left Digital Sidetone Volume", 207 SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
208 WM8990_ADCL_DAC_SVOL_SHIFT, WM8990_ADC 208 WM8990_ADCL_DAC_SVOL_SHIFT, WM8990_ADCL_DAC_SVOL_MASK, 0,
209 out_sidetone_tlv), 209 out_sidetone_tlv),
210 SOC_SINGLE_TLV("Right Digital Sidetone Volume" 210 SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
211 WM8990_ADCR_DAC_SVOL_SHIFT, WM8990_ADC 211 WM8990_ADCR_DAC_SVOL_SHIFT, WM8990_ADCR_DAC_SVOL_MASK, 0,
212 out_sidetone_tlv), 212 out_sidetone_tlv),
213 213
214 SOC_SINGLE("ADC Digital High Pass Filter Switc 214 SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8990_ADC_CTRL,
215 WM8990_ADC_HPF_ENA_BIT, 1, 0), 215 WM8990_ADC_HPF_ENA_BIT, 1, 0),
216 216
217 SOC_ENUM("ADC HPF Mode", wm8990_right_adcmode_ 217 SOC_ENUM("ADC HPF Mode", wm8990_right_adcmode_enum),
218 218
219 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digit 219 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
220 WM8990_LEFT_ADC_DIGITAL_VOLUME, 220 WM8990_LEFT_ADC_DIGITAL_VOLUME,
221 WM8990_ADCL_VOL_SHIFT, 221 WM8990_ADCL_VOL_SHIFT,
222 WM8990_ADCL_VOL_MASK, 222 WM8990_ADCL_VOL_MASK,
223 0, 223 0,
224 in_adc_tlv), 224 in_adc_tlv),
225 225
226 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digi 226 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
227 WM8990_RIGHT_ADC_DIGITAL_VOLUME, 227 WM8990_RIGHT_ADC_DIGITAL_VOLUME,
228 WM8990_ADCR_VOL_SHIFT, 228 WM8990_ADCR_VOL_SHIFT,
229 WM8990_ADCR_VOL_MASK, 229 WM8990_ADCR_VOL_MASK,
230 0, 230 0,
231 in_adc_tlv), 231 in_adc_tlv),
232 232
233 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume", 233 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
234 WM8990_LEFT_LINE_INPUT_1_2_VOLUME, 234 WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
235 WM8990_LIN12VOL_SHIFT, 235 WM8990_LIN12VOL_SHIFT,
236 WM8990_LIN12VOL_MASK, 236 WM8990_LIN12VOL_MASK,
237 0, 237 0,
238 in_pga_tlv), 238 in_pga_tlv),
239 239
240 SOC_SINGLE("LIN12 ZC Switch", WM8990_LEFT_LINE 240 SOC_SINGLE("LIN12 ZC Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
241 WM8990_LI12ZC_BIT, 1, 0), 241 WM8990_LI12ZC_BIT, 1, 0),
242 242
243 SOC_SINGLE("LIN12 Mute Switch", WM8990_LEFT_LI 243 SOC_SINGLE("LIN12 Mute Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
244 WM8990_LI12MUTE_BIT, 1, 0), 244 WM8990_LI12MUTE_BIT, 1, 0),
245 245
246 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume", 246 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
247 WM8990_LEFT_LINE_INPUT_3_4_VOLUME, 247 WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
248 WM8990_LIN34VOL_SHIFT, 248 WM8990_LIN34VOL_SHIFT,
249 WM8990_LIN34VOL_MASK, 249 WM8990_LIN34VOL_MASK,
250 0, 250 0,
251 in_pga_tlv), 251 in_pga_tlv),
252 252
253 SOC_SINGLE("LIN34 ZC Switch", WM8990_LEFT_LINE 253 SOC_SINGLE("LIN34 ZC Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
254 WM8990_LI34ZC_BIT, 1, 0), 254 WM8990_LI34ZC_BIT, 1, 0),
255 255
256 SOC_SINGLE("LIN34 Mute Switch", WM8990_LEFT_LI 256 SOC_SINGLE("LIN34 Mute Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
257 WM8990_LI34MUTE_BIT, 1, 0), 257 WM8990_LI34MUTE_BIT, 1, 0),
258 258
259 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume", 259 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
260 WM8990_RIGHT_LINE_INPUT_1_2_VOLUME, 260 WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
261 WM8990_RIN12VOL_SHIFT, 261 WM8990_RIN12VOL_SHIFT,
262 WM8990_RIN12VOL_MASK, 262 WM8990_RIN12VOL_MASK,
263 0, 263 0,
264 in_pga_tlv), 264 in_pga_tlv),
265 265
266 SOC_SINGLE("RIN12 ZC Switch", WM8990_RIGHT_LIN 266 SOC_SINGLE("RIN12 ZC Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
267 WM8990_RI12ZC_BIT, 1, 0), 267 WM8990_RI12ZC_BIT, 1, 0),
268 268
269 SOC_SINGLE("RIN12 Mute Switch", WM8990_RIGHT_L 269 SOC_SINGLE("RIN12 Mute Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
270 WM8990_RI12MUTE_BIT, 1, 0), 270 WM8990_RI12MUTE_BIT, 1, 0),
271 271
272 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume", 272 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
273 WM8990_RIGHT_LINE_INPUT_3_4_VOLUME, 273 WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
274 WM8990_RIN34VOL_SHIFT, 274 WM8990_RIN34VOL_SHIFT,
275 WM8990_RIN34VOL_MASK, 275 WM8990_RIN34VOL_MASK,
276 0, 276 0,
277 in_pga_tlv), 277 in_pga_tlv),
278 278
279 SOC_SINGLE("RIN34 ZC Switch", WM8990_RIGHT_LIN 279 SOC_SINGLE("RIN34 ZC Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
280 WM8990_RI34ZC_BIT, 1, 0), 280 WM8990_RI34ZC_BIT, 1, 0),
281 281
282 SOC_SINGLE("RIN34 Mute Switch", WM8990_RIGHT_L 282 SOC_SINGLE("RIN34 Mute Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
283 WM8990_RI34MUTE_BIT, 1, 0), 283 WM8990_RI34MUTE_BIT, 1, 0),
284 284
285 }; 285 };
286 286
287 /* 287 /*
288 * _DAPM_ Controls 288 * _DAPM_ Controls
289 */ 289 */
290 290
291 static int outmixer_event(struct snd_soc_dapm_ 291 static int outmixer_event(struct snd_soc_dapm_widget *w,
292 struct snd_kcontrol *kcontrol, int eve 292 struct snd_kcontrol *kcontrol, int event)
293 { 293 {
294 struct snd_soc_component *component = 294 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
295 u32 reg_shift = kcontrol->private_valu 295 u32 reg_shift = kcontrol->private_value & 0xfff;
296 int ret = 0; 296 int ret = 0;
297 u16 reg; 297 u16 reg;
298 298
299 switch (reg_shift) { 299 switch (reg_shift) {
300 case WM8990_SPEAKER_MIXER | (WM8990_LD 300 case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) :
301 reg = snd_soc_component_read(c 301 reg = snd_soc_component_read(component, WM8990_OUTPUT_MIXER1);
302 if (reg & WM8990_LDLO) { 302 if (reg & WM8990_LDLO) {
303 printk(KERN_WARNING 303 printk(KERN_WARNING
304 "Cannot set as Output 304 "Cannot set as Output Mixer 1 LDLO Set\n");
305 ret = -1; 305 ret = -1;
306 } 306 }
307 break; 307 break;
308 case WM8990_SPEAKER_MIXER | (WM8990_RD 308 case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8):
309 reg = snd_soc_component_read(c 309 reg = snd_soc_component_read(component, WM8990_OUTPUT_MIXER2);
310 if (reg & WM8990_RDRO) { 310 if (reg & WM8990_RDRO) {
311 printk(KERN_WARNING 311 printk(KERN_WARNING
312 "Cannot set as Output 312 "Cannot set as Output Mixer 2 RDRO Set\n");
313 ret = -1; 313 ret = -1;
314 } 314 }
315 break; 315 break;
316 case WM8990_OUTPUT_MIXER1 | (WM8990_LD 316 case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8):
317 reg = snd_soc_component_read(c 317 reg = snd_soc_component_read(component, WM8990_SPEAKER_MIXER);
318 if (reg & WM8990_LDSPK) { 318 if (reg & WM8990_LDSPK) {
319 printk(KERN_WARNING 319 printk(KERN_WARNING
320 "Cannot set as Speaker 320 "Cannot set as Speaker Mixer LDSPK Set\n");
321 ret = -1; 321 ret = -1;
322 } 322 }
323 break; 323 break;
324 case WM8990_OUTPUT_MIXER2 | (WM8990_RD 324 case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8):
325 reg = snd_soc_component_read(c 325 reg = snd_soc_component_read(component, WM8990_SPEAKER_MIXER);
326 if (reg & WM8990_RDSPK) { 326 if (reg & WM8990_RDSPK) {
327 printk(KERN_WARNING 327 printk(KERN_WARNING
328 "Cannot set as Speaker 328 "Cannot set as Speaker Mixer RDSPK Set\n");
329 ret = -1; 329 ret = -1;
330 } 330 }
331 break; 331 break;
332 } 332 }
333 333
334 return ret; 334 return ret;
335 } 335 }
336 336
337 /* INMIX dB values */ 337 /* INMIX dB values */
338 static const DECLARE_TLV_DB_SCALE(in_mix_tlv, 338 static const DECLARE_TLV_DB_SCALE(in_mix_tlv, -1200, 600, 0);
339 339
340 /* Left In PGA Connections */ 340 /* Left In PGA Connections */
341 static const struct snd_kcontrol_new wm8990_da 341 static const struct snd_kcontrol_new wm8990_dapm_lin12_pga_controls[] = {
342 SOC_DAPM_SINGLE("LIN1 Switch", WM8990_INPUT_MI 342 SOC_DAPM_SINGLE("LIN1 Switch", WM8990_INPUT_MIXER2, WM8990_LMN1_BIT, 1, 0),
343 SOC_DAPM_SINGLE("LIN2 Switch", WM8990_INPUT_MI 343 SOC_DAPM_SINGLE("LIN2 Switch", WM8990_INPUT_MIXER2, WM8990_LMP2_BIT, 1, 0),
344 }; 344 };
345 345
346 static const struct snd_kcontrol_new wm8990_da 346 static const struct snd_kcontrol_new wm8990_dapm_lin34_pga_controls[] = {
347 SOC_DAPM_SINGLE("LIN3 Switch", WM8990_INPUT_MI 347 SOC_DAPM_SINGLE("LIN3 Switch", WM8990_INPUT_MIXER2, WM8990_LMN3_BIT, 1, 0),
348 SOC_DAPM_SINGLE("LIN4 Switch", WM8990_INPUT_MI 348 SOC_DAPM_SINGLE("LIN4 Switch", WM8990_INPUT_MIXER2, WM8990_LMP4_BIT, 1, 0),
349 }; 349 };
350 350
351 /* Right In PGA Connections */ 351 /* Right In PGA Connections */
352 static const struct snd_kcontrol_new wm8990_da 352 static const struct snd_kcontrol_new wm8990_dapm_rin12_pga_controls[] = {
353 SOC_DAPM_SINGLE("RIN1 Switch", WM8990_INPUT_MI 353 SOC_DAPM_SINGLE("RIN1 Switch", WM8990_INPUT_MIXER2, WM8990_RMN1_BIT, 1, 0),
354 SOC_DAPM_SINGLE("RIN2 Switch", WM8990_INPUT_MI 354 SOC_DAPM_SINGLE("RIN2 Switch", WM8990_INPUT_MIXER2, WM8990_RMP2_BIT, 1, 0),
355 }; 355 };
356 356
357 static const struct snd_kcontrol_new wm8990_da 357 static const struct snd_kcontrol_new wm8990_dapm_rin34_pga_controls[] = {
358 SOC_DAPM_SINGLE("RIN3 Switch", WM8990_INPUT_MI 358 SOC_DAPM_SINGLE("RIN3 Switch", WM8990_INPUT_MIXER2, WM8990_RMN3_BIT, 1, 0),
359 SOC_DAPM_SINGLE("RIN4 Switch", WM8990_INPUT_MI 359 SOC_DAPM_SINGLE("RIN4 Switch", WM8990_INPUT_MIXER2, WM8990_RMP4_BIT, 1, 0),
360 }; 360 };
361 361
362 /* INMIXL */ 362 /* INMIXL */
363 static const struct snd_kcontrol_new wm8990_da 363 static const struct snd_kcontrol_new wm8990_dapm_inmixl_controls[] = {
364 SOC_DAPM_SINGLE_TLV("Record Left Volume", WM89 364 SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8990_INPUT_MIXER3,
365 WM8990_LDBVOL_SHIFT, WM8990_LDBVOL_MAS 365 WM8990_LDBVOL_SHIFT, WM8990_LDBVOL_MASK, 0, in_mix_tlv),
366 SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8990_INPU 366 SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8990_INPUT_MIXER5, WM8990_LI2BVOL_SHIFT,
367 7, 0, in_mix_tlv), 367 7, 0, in_mix_tlv),
368 SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPU 368 SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
369 1, 0), 369 1, 0),
370 SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPU 370 SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
371 1, 0), 371 1, 0),
372 }; 372 };
373 373
374 /* INMIXR */ 374 /* INMIXR */
375 static const struct snd_kcontrol_new wm8990_da 375 static const struct snd_kcontrol_new wm8990_dapm_inmixr_controls[] = {
376 SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8 376 SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8990_INPUT_MIXER4,
377 WM8990_RDBVOL_SHIFT, WM8990_RDBVOL_MAS 377 WM8990_RDBVOL_SHIFT, WM8990_RDBVOL_MASK, 0, in_mix_tlv),
378 SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8990_INPU 378 SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8990_INPUT_MIXER6, WM8990_RI2BVOL_SHIFT,
379 7, 0, in_mix_tlv), 379 7, 0, in_mix_tlv),
380 SOC_DAPM_SINGLE("RINPGA12 Switch", WM8990_INPU 380 SOC_DAPM_SINGLE("RINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
381 1, 0), 381 1, 0),
382 SOC_DAPM_SINGLE("RINPGA34 Switch", WM8990_INPU 382 SOC_DAPM_SINGLE("RINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
383 1, 0), 383 1, 0),
384 }; 384 };
385 385
386 /* AINLMUX */ 386 /* AINLMUX */
387 static const char *wm8990_ainlmux[] = 387 static const char *wm8990_ainlmux[] =
388 {"INMIXL Mix", "RXVOICE Mix", "DIFFINL 388 {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
389 389
390 static SOC_ENUM_SINGLE_DECL(wm8990_ainlmux_enu 390 static SOC_ENUM_SINGLE_DECL(wm8990_ainlmux_enum,
391 WM8990_INPUT_MIXER 391 WM8990_INPUT_MIXER1, WM8990_AINLMODE_SHIFT,
392 wm8990_ainlmux); 392 wm8990_ainlmux);
393 393
394 static const struct snd_kcontrol_new wm8990_da 394 static const struct snd_kcontrol_new wm8990_dapm_ainlmux_controls =
395 SOC_DAPM_ENUM("Route", wm8990_ainlmux_enum); 395 SOC_DAPM_ENUM("Route", wm8990_ainlmux_enum);
396 396
397 /* DIFFINL */ 397 /* DIFFINL */
398 398
399 /* AINRMUX */ 399 /* AINRMUX */
400 static const char *wm8990_ainrmux[] = 400 static const char *wm8990_ainrmux[] =
401 {"INMIXR Mix", "RXVOICE Mix", "DIFFINR 401 {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
402 402
403 static SOC_ENUM_SINGLE_DECL(wm8990_ainrmux_enu 403 static SOC_ENUM_SINGLE_DECL(wm8990_ainrmux_enum,
404 WM8990_INPUT_MIXER 404 WM8990_INPUT_MIXER1, WM8990_AINRMODE_SHIFT,
405 wm8990_ainrmux); 405 wm8990_ainrmux);
406 406
407 static const struct snd_kcontrol_new wm8990_da 407 static const struct snd_kcontrol_new wm8990_dapm_ainrmux_controls =
408 SOC_DAPM_ENUM("Route", wm8990_ainrmux_enum); 408 SOC_DAPM_ENUM("Route", wm8990_ainrmux_enum);
409 409
410 /* LOMIX */ 410 /* LOMIX */
411 static const struct snd_kcontrol_new wm8990_da 411 static const struct snd_kcontrol_new wm8990_dapm_lomix_controls[] = {
412 SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch 412 SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
413 WM8990_LRBLO_BIT, 1, 0), 413 WM8990_LRBLO_BIT, 1, 0),
414 SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch" 414 SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
415 WM8990_LLBLO_BIT, 1, 0), 415 WM8990_LLBLO_BIT, 1, 0),
416 SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM 416 SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
417 WM8990_LRI3LO_BIT, 1, 0), 417 WM8990_LRI3LO_BIT, 1, 0),
418 SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM 418 SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
419 WM8990_LLI3LO_BIT, 1, 0), 419 WM8990_LLI3LO_BIT, 1, 0),
420 SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch 420 SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
421 WM8990_LR12LO_BIT, 1, 0), 421 WM8990_LR12LO_BIT, 1, 0),
422 SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch 422 SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
423 WM8990_LL12LO_BIT, 1, 0), 423 WM8990_LL12LO_BIT, 1, 0),
424 SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM899 424 SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8990_OUTPUT_MIXER1,
425 WM8990_LDLO_BIT, 1, 0), 425 WM8990_LDLO_BIT, 1, 0),
426 }; 426 };
427 427
428 /* ROMIX */ 428 /* ROMIX */
429 static const struct snd_kcontrol_new wm8990_da 429 static const struct snd_kcontrol_new wm8990_dapm_romix_controls[] = {
430 SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch" 430 SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
431 WM8990_RLBRO_BIT, 1, 0), 431 WM8990_RLBRO_BIT, 1, 0),
432 SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch 432 SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
433 WM8990_RRBRO_BIT, 1, 0), 433 WM8990_RRBRO_BIT, 1, 0),
434 SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM 434 SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
435 WM8990_RLI3RO_BIT, 1, 0), 435 WM8990_RLI3RO_BIT, 1, 0),
436 SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM 436 SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
437 WM8990_RRI3RO_BIT, 1, 0), 437 WM8990_RRI3RO_BIT, 1, 0),
438 SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch 438 SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
439 WM8990_RL12RO_BIT, 1, 0), 439 WM8990_RL12RO_BIT, 1, 0),
440 SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch 440 SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
441 WM8990_RR12RO_BIT, 1, 0), 441 WM8990_RR12RO_BIT, 1, 0),
442 SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM89 442 SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8990_OUTPUT_MIXER2,
443 WM8990_RDRO_BIT, 1, 0), 443 WM8990_RDRO_BIT, 1, 0),
444 }; 444 };
445 445
446 /* LONMIX */ 446 /* LONMIX */
447 static const struct snd_kcontrol_new wm8990_da 447 static const struct snd_kcontrol_new wm8990_dapm_lonmix_controls[] = {
448 SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch" 448 SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
449 WM8990_LLOPGALON_BIT, 1, 0), 449 WM8990_LLOPGALON_BIT, 1, 0),
450 SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch 450 SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER1,
451 WM8990_LROPGALON_BIT, 1, 0), 451 WM8990_LROPGALON_BIT, 1, 0),
452 SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", 452 SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8990_LINE_MIXER1,
453 WM8990_LOPLON_BIT, 1, 0), 453 WM8990_LOPLON_BIT, 1, 0),
454 }; 454 };
455 455
456 /* LOPMIX */ 456 /* LOPMIX */
457 static const struct snd_kcontrol_new wm8990_da 457 static const struct snd_kcontrol_new wm8990_dapm_lopmix_controls[] = {
458 SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switc 458 SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER1,
459 WM8990_LR12LOP_BIT, 1, 0), 459 WM8990_LR12LOP_BIT, 1, 0),
460 SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch 460 SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER1,
461 WM8990_LL12LOP_BIT, 1, 0), 461 WM8990_LL12LOP_BIT, 1, 0),
462 SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch" 462 SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
463 WM8990_LLOPGALOP_BIT, 1, 0), 463 WM8990_LLOPGALOP_BIT, 1, 0),
464 }; 464 };
465 465
466 /* RONMIX */ 466 /* RONMIX */
467 static const struct snd_kcontrol_new wm8990_da 467 static const struct snd_kcontrol_new wm8990_dapm_ronmix_controls[] = {
468 SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch 468 SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
469 WM8990_RROPGARON_BIT, 1, 0), 469 WM8990_RROPGARON_BIT, 1, 0),
470 SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch" 470 SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER2,
471 WM8990_RLOPGARON_BIT, 1, 0), 471 WM8990_RLOPGARON_BIT, 1, 0),
472 SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", 472 SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8990_LINE_MIXER2,
473 WM8990_ROPRON_BIT, 1, 0), 473 WM8990_ROPRON_BIT, 1, 0),
474 }; 474 };
475 475
476 /* ROPMIX */ 476 /* ROPMIX */
477 static const struct snd_kcontrol_new wm8990_da 477 static const struct snd_kcontrol_new wm8990_dapm_ropmix_controls[] = {
478 SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch 478 SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER2,
479 WM8990_RL12ROP_BIT, 1, 0), 479 WM8990_RL12ROP_BIT, 1, 0),
480 SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switc 480 SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER2,
481 WM8990_RR12ROP_BIT, 1, 0), 481 WM8990_RR12ROP_BIT, 1, 0),
482 SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch 482 SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
483 WM8990_RROPGAROP_BIT, 1, 0), 483 WM8990_RROPGAROP_BIT, 1, 0),
484 }; 484 };
485 485
486 /* OUT3MIX */ 486 /* OUT3MIX */
487 static const struct snd_kcontrol_new wm8990_da 487 static const struct snd_kcontrol_new wm8990_dapm_out3mix_controls[] = {
488 SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switc 488 SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
489 WM8990_LI4O3_BIT, 1, 0), 489 WM8990_LI4O3_BIT, 1, 0),
490 SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", 490 SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8990_OUT3_4_MIXER,
491 WM8990_LPGAO3_BIT, 1, 0), 491 WM8990_LPGAO3_BIT, 1, 0),
492 }; 492 };
493 493
494 /* OUT4MIX */ 494 /* OUT4MIX */
495 static const struct snd_kcontrol_new wm8990_da 495 static const struct snd_kcontrol_new wm8990_dapm_out4mix_controls[] = {
496 SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch" 496 SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8990_OUT3_4_MIXER,
497 WM8990_RPGAO4_BIT, 1, 0), 497 WM8990_RPGAO4_BIT, 1, 0),
498 SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switc 498 SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
499 WM8990_RI4O4_BIT, 1, 0), 499 WM8990_RI4O4_BIT, 1, 0),
500 }; 500 };
501 501
502 /* SPKMIX */ 502 /* SPKMIX */
503 static const struct snd_kcontrol_new wm8990_da 503 static const struct snd_kcontrol_new wm8990_dapm_spkmix_controls[] = {
504 SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", W 504 SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
505 WM8990_LI2SPK_BIT, 1, 0), 505 WM8990_LI2SPK_BIT, 1, 0),
506 SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", W 506 SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8990_SPEAKER_MIXER,
507 WM8990_LB2SPK_BIT, 1, 0), 507 WM8990_LB2SPK_BIT, 1, 0),
508 SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch" 508 SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8990_SPEAKER_MIXER,
509 WM8990_LOPGASPK_BIT, 1, 0), 509 WM8990_LOPGASPK_BIT, 1, 0),
510 SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM89 510 SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8990_SPEAKER_MIXER,
511 WM8990_LDSPK_BIT, 1, 0), 511 WM8990_LDSPK_BIT, 1, 0),
512 SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8 512 SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8990_SPEAKER_MIXER,
513 WM8990_RDSPK_BIT, 1, 0), 513 WM8990_RDSPK_BIT, 1, 0),
514 SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch 514 SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8990_SPEAKER_MIXER,
515 WM8990_ROPGASPK_BIT, 1, 0), 515 WM8990_ROPGASPK_BIT, 1, 0),
516 SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", W 516 SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8990_SPEAKER_MIXER,
517 WM8990_RL12ROP_BIT, 1, 0), 517 WM8990_RL12ROP_BIT, 1, 0),
518 SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", W 518 SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
519 WM8990_RI2SPK_BIT, 1, 0), 519 WM8990_RI2SPK_BIT, 1, 0),
520 }; 520 };
521 521
522 static const struct snd_soc_dapm_widget wm8990 522 static const struct snd_soc_dapm_widget wm8990_dapm_widgets[] = {
523 /* Input Side */ 523 /* Input Side */
524 /* Input Lines */ 524 /* Input Lines */
525 SND_SOC_DAPM_INPUT("LIN1"), 525 SND_SOC_DAPM_INPUT("LIN1"),
526 SND_SOC_DAPM_INPUT("LIN2"), 526 SND_SOC_DAPM_INPUT("LIN2"),
527 SND_SOC_DAPM_INPUT("LIN3"), 527 SND_SOC_DAPM_INPUT("LIN3"),
528 SND_SOC_DAPM_INPUT("LIN4/RXN"), 528 SND_SOC_DAPM_INPUT("LIN4/RXN"),
529 SND_SOC_DAPM_INPUT("RIN3"), 529 SND_SOC_DAPM_INPUT("RIN3"),
530 SND_SOC_DAPM_INPUT("RIN4/RXP"), 530 SND_SOC_DAPM_INPUT("RIN4/RXP"),
531 SND_SOC_DAPM_INPUT("RIN1"), 531 SND_SOC_DAPM_INPUT("RIN1"),
532 SND_SOC_DAPM_INPUT("RIN2"), 532 SND_SOC_DAPM_INPUT("RIN2"),
533 SND_SOC_DAPM_INPUT("Internal ADC Source"), 533 SND_SOC_DAPM_INPUT("Internal ADC Source"),
534 534
535 SND_SOC_DAPM_SUPPLY("INL", WM8990_POWER_MANAGE 535 SND_SOC_DAPM_SUPPLY("INL", WM8990_POWER_MANAGEMENT_2, WM8990_AINL_ENA_BIT, 0,
536 NULL, 0), 536 NULL, 0),
537 SND_SOC_DAPM_SUPPLY("INR", WM8990_POWER_MANAGE 537 SND_SOC_DAPM_SUPPLY("INR", WM8990_POWER_MANAGEMENT_2, WM8990_AINR_ENA_BIT, 0,
538 NULL, 0), 538 NULL, 0),
539 539
540 /* DACs */ 540 /* DACs */
541 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", W 541 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8990_POWER_MANAGEMENT_2,
542 WM8990_ADCL_ENA_BIT, 0), 542 WM8990_ADCL_ENA_BIT, 0),
543 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", 543 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8990_POWER_MANAGEMENT_2,
544 WM8990_ADCR_ENA_BIT, 0), 544 WM8990_ADCR_ENA_BIT, 0),
545 545
546 /* Input PGAs */ 546 /* Input PGAs */
547 SND_SOC_DAPM_MIXER("LIN12 PGA", WM8990_POWER_M 547 SND_SOC_DAPM_MIXER("LIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN12_ENA_BIT,
548 0, &wm8990_dapm_lin12_pga_controls[0], 548 0, &wm8990_dapm_lin12_pga_controls[0],
549 ARRAY_SIZE(wm8990_dapm_lin12_pga_contr 549 ARRAY_SIZE(wm8990_dapm_lin12_pga_controls)),
550 SND_SOC_DAPM_MIXER("LIN34 PGA", WM8990_POWER_M 550 SND_SOC_DAPM_MIXER("LIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN34_ENA_BIT,
551 0, &wm8990_dapm_lin34_pga_controls[0], 551 0, &wm8990_dapm_lin34_pga_controls[0],
552 ARRAY_SIZE(wm8990_dapm_lin34_pga_contr 552 ARRAY_SIZE(wm8990_dapm_lin34_pga_controls)),
553 SND_SOC_DAPM_MIXER("RIN12 PGA", WM8990_POWER_M 553 SND_SOC_DAPM_MIXER("RIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN12_ENA_BIT,
554 0, &wm8990_dapm_rin12_pga_controls[0], 554 0, &wm8990_dapm_rin12_pga_controls[0],
555 ARRAY_SIZE(wm8990_dapm_rin12_pga_contr 555 ARRAY_SIZE(wm8990_dapm_rin12_pga_controls)),
556 SND_SOC_DAPM_MIXER("RIN34 PGA", WM8990_POWER_M 556 SND_SOC_DAPM_MIXER("RIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN34_ENA_BIT,
557 0, &wm8990_dapm_rin34_pga_controls[0], 557 0, &wm8990_dapm_rin34_pga_controls[0],
558 ARRAY_SIZE(wm8990_dapm_rin34_pga_contr 558 ARRAY_SIZE(wm8990_dapm_rin34_pga_controls)),
559 559
560 /* INMIXL */ 560 /* INMIXL */
561 SND_SOC_DAPM_MIXER("INMIXL", SND_SOC_NOPM, 0, 561 SND_SOC_DAPM_MIXER("INMIXL", SND_SOC_NOPM, 0, 0,
562 &wm8990_dapm_inmixl_controls[0], 562 &wm8990_dapm_inmixl_controls[0],
563 ARRAY_SIZE(wm8990_dapm_inmixl_controls 563 ARRAY_SIZE(wm8990_dapm_inmixl_controls)),
564 564
565 /* AINLMUX */ 565 /* AINLMUX */
566 SND_SOC_DAPM_MUX("AINLMUX", SND_SOC_NOPM, 0, 0 566 SND_SOC_DAPM_MUX("AINLMUX", SND_SOC_NOPM, 0, 0, &wm8990_dapm_ainlmux_controls),
567 567
568 /* INMIXR */ 568 /* INMIXR */
569 SND_SOC_DAPM_MIXER("INMIXR", SND_SOC_NOPM, 0, 569 SND_SOC_DAPM_MIXER("INMIXR", SND_SOC_NOPM, 0, 0,
570 &wm8990_dapm_inmixr_controls[0], 570 &wm8990_dapm_inmixr_controls[0],
571 ARRAY_SIZE(wm8990_dapm_inmixr_controls 571 ARRAY_SIZE(wm8990_dapm_inmixr_controls)),
572 572
573 /* AINRMUX */ 573 /* AINRMUX */
574 SND_SOC_DAPM_MUX("AINRMUX", SND_SOC_NOPM, 0, 0 574 SND_SOC_DAPM_MUX("AINRMUX", SND_SOC_NOPM, 0, 0, &wm8990_dapm_ainrmux_controls),
575 575
576 /* Output Side */ 576 /* Output Side */
577 /* DACs */ 577 /* DACs */
578 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", 578 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8990_POWER_MANAGEMENT_3,
579 WM8990_DACL_ENA_BIT, 0), 579 WM8990_DACL_ENA_BIT, 0),
580 SND_SOC_DAPM_DAC("Right DAC", "Right Playback" 580 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8990_POWER_MANAGEMENT_3,
581 WM8990_DACR_ENA_BIT, 0), 581 WM8990_DACR_ENA_BIT, 0),
582 582
583 /* LOMIX */ 583 /* LOMIX */
584 SND_SOC_DAPM_MIXER_E("LOMIX", WM8990_POWER_MAN 584 SND_SOC_DAPM_MIXER_E("LOMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOMIX_ENA_BIT,
585 0, &wm8990_dapm_lomix_controls[0], 585 0, &wm8990_dapm_lomix_controls[0],
586 ARRAY_SIZE(wm8990_dapm_lomix_controls) 586 ARRAY_SIZE(wm8990_dapm_lomix_controls),
587 outmixer_event, SND_SOC_DAPM_PRE_REG), 587 outmixer_event, SND_SOC_DAPM_PRE_REG),
588 588
589 /* LONMIX */ 589 /* LONMIX */
590 SND_SOC_DAPM_MIXER("LONMIX", WM8990_POWER_MANA 590 SND_SOC_DAPM_MIXER("LONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LON_ENA_BIT, 0,
591 &wm8990_dapm_lonmix_controls[0], 591 &wm8990_dapm_lonmix_controls[0],
592 ARRAY_SIZE(wm8990_dapm_lonmix_controls 592 ARRAY_SIZE(wm8990_dapm_lonmix_controls)),
593 593
594 /* LOPMIX */ 594 /* LOPMIX */
595 SND_SOC_DAPM_MIXER("LOPMIX", WM8990_POWER_MANA 595 SND_SOC_DAPM_MIXER("LOPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOP_ENA_BIT, 0,
596 &wm8990_dapm_lopmix_controls[0], 596 &wm8990_dapm_lopmix_controls[0],
597 ARRAY_SIZE(wm8990_dapm_lopmix_controls 597 ARRAY_SIZE(wm8990_dapm_lopmix_controls)),
598 598
599 /* OUT3MIX */ 599 /* OUT3MIX */
600 SND_SOC_DAPM_MIXER("OUT3MIX", WM8990_POWER_MAN 600 SND_SOC_DAPM_MIXER("OUT3MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT3_ENA_BIT, 0,
601 &wm8990_dapm_out3mix_controls[0], 601 &wm8990_dapm_out3mix_controls[0],
602 ARRAY_SIZE(wm8990_dapm_out3mix_control 602 ARRAY_SIZE(wm8990_dapm_out3mix_controls)),
603 603
604 /* SPKMIX */ 604 /* SPKMIX */
605 SND_SOC_DAPM_MIXER_E("SPKMIX", WM8990_POWER_MA 605 SND_SOC_DAPM_MIXER_E("SPKMIX", WM8990_POWER_MANAGEMENT_1, WM8990_SPK_ENA_BIT, 0,
606 &wm8990_dapm_spkmix_controls[0], 606 &wm8990_dapm_spkmix_controls[0],
607 ARRAY_SIZE(wm8990_dapm_spkmix_controls 607 ARRAY_SIZE(wm8990_dapm_spkmix_controls), outmixer_event,
608 SND_SOC_DAPM_PRE_REG), 608 SND_SOC_DAPM_PRE_REG),
609 609
610 /* OUT4MIX */ 610 /* OUT4MIX */
611 SND_SOC_DAPM_MIXER("OUT4MIX", WM8990_POWER_MAN 611 SND_SOC_DAPM_MIXER("OUT4MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT4_ENA_BIT, 0,
612 &wm8990_dapm_out4mix_controls[0], 612 &wm8990_dapm_out4mix_controls[0],
613 ARRAY_SIZE(wm8990_dapm_out4mix_control 613 ARRAY_SIZE(wm8990_dapm_out4mix_controls)),
614 614
615 /* ROPMIX */ 615 /* ROPMIX */
616 SND_SOC_DAPM_MIXER("ROPMIX", WM8990_POWER_MANA 616 SND_SOC_DAPM_MIXER("ROPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROP_ENA_BIT, 0,
617 &wm8990_dapm_ropmix_controls[0], 617 &wm8990_dapm_ropmix_controls[0],
618 ARRAY_SIZE(wm8990_dapm_ropmix_controls 618 ARRAY_SIZE(wm8990_dapm_ropmix_controls)),
619 619
620 /* RONMIX */ 620 /* RONMIX */
621 SND_SOC_DAPM_MIXER("RONMIX", WM8990_POWER_MANA 621 SND_SOC_DAPM_MIXER("RONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_RON_ENA_BIT, 0,
622 &wm8990_dapm_ronmix_controls[0], 622 &wm8990_dapm_ronmix_controls[0],
623 ARRAY_SIZE(wm8990_dapm_ronmix_controls 623 ARRAY_SIZE(wm8990_dapm_ronmix_controls)),
624 624
625 /* ROMIX */ 625 /* ROMIX */
626 SND_SOC_DAPM_MIXER_E("ROMIX", WM8990_POWER_MAN 626 SND_SOC_DAPM_MIXER_E("ROMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROMIX_ENA_BIT,
627 0, &wm8990_dapm_romix_controls[0], 627 0, &wm8990_dapm_romix_controls[0],
628 ARRAY_SIZE(wm8990_dapm_romix_controls) 628 ARRAY_SIZE(wm8990_dapm_romix_controls),
629 outmixer_event, SND_SOC_DAPM_PRE_REG), 629 outmixer_event, SND_SOC_DAPM_PRE_REG),
630 630
631 /* LOUT PGA */ 631 /* LOUT PGA */
632 SND_SOC_DAPM_PGA("LOUT PGA", WM8990_POWER_MANA 632 SND_SOC_DAPM_PGA("LOUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_LOUT_ENA_BIT, 0,
633 NULL, 0), 633 NULL, 0),
634 634
635 /* ROUT PGA */ 635 /* ROUT PGA */
636 SND_SOC_DAPM_PGA("ROUT PGA", WM8990_POWER_MANA 636 SND_SOC_DAPM_PGA("ROUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_ROUT_ENA_BIT, 0,
637 NULL, 0), 637 NULL, 0),
638 638
639 /* LOPGA */ 639 /* LOPGA */
640 SND_SOC_DAPM_PGA("LOPGA", WM8990_POWER_MANAGEM 640 SND_SOC_DAPM_PGA("LOPGA", WM8990_POWER_MANAGEMENT_3, WM8990_LOPGA_ENA_BIT, 0,
641 NULL, 0), 641 NULL, 0),
642 642
643 /* ROPGA */ 643 /* ROPGA */
644 SND_SOC_DAPM_PGA("ROPGA", WM8990_POWER_MANAGEM 644 SND_SOC_DAPM_PGA("ROPGA", WM8990_POWER_MANAGEMENT_3, WM8990_ROPGA_ENA_BIT, 0,
645 NULL, 0), 645 NULL, 0),
646 646
647 /* MICBIAS */ 647 /* MICBIAS */
648 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8990_POWER_MA 648 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8990_POWER_MANAGEMENT_1,
649 WM8990_MICBIAS_ENA_BIT, 0, 649 WM8990_MICBIAS_ENA_BIT, 0, NULL, 0),
650 650
651 SND_SOC_DAPM_OUTPUT("LON"), 651 SND_SOC_DAPM_OUTPUT("LON"),
652 SND_SOC_DAPM_OUTPUT("LOP"), 652 SND_SOC_DAPM_OUTPUT("LOP"),
653 SND_SOC_DAPM_OUTPUT("OUT3"), 653 SND_SOC_DAPM_OUTPUT("OUT3"),
654 SND_SOC_DAPM_OUTPUT("LOUT"), 654 SND_SOC_DAPM_OUTPUT("LOUT"),
655 SND_SOC_DAPM_OUTPUT("SPKN"), 655 SND_SOC_DAPM_OUTPUT("SPKN"),
656 SND_SOC_DAPM_OUTPUT("SPKP"), 656 SND_SOC_DAPM_OUTPUT("SPKP"),
657 SND_SOC_DAPM_OUTPUT("ROUT"), 657 SND_SOC_DAPM_OUTPUT("ROUT"),
658 SND_SOC_DAPM_OUTPUT("OUT4"), 658 SND_SOC_DAPM_OUTPUT("OUT4"),
659 SND_SOC_DAPM_OUTPUT("ROP"), 659 SND_SOC_DAPM_OUTPUT("ROP"),
660 SND_SOC_DAPM_OUTPUT("RON"), 660 SND_SOC_DAPM_OUTPUT("RON"),
661 661
662 SND_SOC_DAPM_OUTPUT("Internal DAC Sink"), 662 SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
663 }; 663 };
664 664
665 static const struct snd_soc_dapm_route wm8990_ 665 static const struct snd_soc_dapm_route wm8990_dapm_routes[] = {
666 /* Make DACs turn on when playing even 666 /* Make DACs turn on when playing even if not mixed into any outputs */
667 {"Internal DAC Sink", NULL, "Left DAC" 667 {"Internal DAC Sink", NULL, "Left DAC"},
668 {"Internal DAC Sink", NULL, "Right DAC 668 {"Internal DAC Sink", NULL, "Right DAC"},
669 669
670 /* Make ADCs turn on when recording ev 670 /* Make ADCs turn on when recording even if not mixed from any inputs */
671 {"Left ADC", NULL, "Internal ADC Sourc 671 {"Left ADC", NULL, "Internal ADC Source"},
672 {"Right ADC", NULL, "Internal ADC Sour 672 {"Right ADC", NULL, "Internal ADC Source"},
673 673
674 {"AINLMUX", NULL, "INL"}, 674 {"AINLMUX", NULL, "INL"},
675 {"INMIXL", NULL, "INL"}, 675 {"INMIXL", NULL, "INL"},
676 {"AINRMUX", NULL, "INR"}, 676 {"AINRMUX", NULL, "INR"},
677 {"INMIXR", NULL, "INR"}, 677 {"INMIXR", NULL, "INR"},
678 678
679 /* Input Side */ 679 /* Input Side */
680 /* LIN12 PGA */ 680 /* LIN12 PGA */
681 {"LIN12 PGA", "LIN1 Switch", "LIN1"}, 681 {"LIN12 PGA", "LIN1 Switch", "LIN1"},
682 {"LIN12 PGA", "LIN2 Switch", "LIN2"}, 682 {"LIN12 PGA", "LIN2 Switch", "LIN2"},
683 /* LIN34 PGA */ 683 /* LIN34 PGA */
684 {"LIN34 PGA", "LIN3 Switch", "LIN3"}, 684 {"LIN34 PGA", "LIN3 Switch", "LIN3"},
685 {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN 685 {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"},
686 /* INMIXL */ 686 /* INMIXL */
687 {"INMIXL", "Record Left Volume", "LOMI 687 {"INMIXL", "Record Left Volume", "LOMIX"},
688 {"INMIXL", "LIN2 Volume", "LIN2"}, 688 {"INMIXL", "LIN2 Volume", "LIN2"},
689 {"INMIXL", "LINPGA12 Switch", "LIN12 P 689 {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
690 {"INMIXL", "LINPGA34 Switch", "LIN34 P 690 {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
691 /* AINLMUX */ 691 /* AINLMUX */
692 {"AINLMUX", "INMIXL Mix", "INMIXL"}, 692 {"AINLMUX", "INMIXL Mix", "INMIXL"},
693 {"AINLMUX", "DIFFINL Mix", "LIN12 PGA" 693 {"AINLMUX", "DIFFINL Mix", "LIN12 PGA"},
694 {"AINLMUX", "DIFFINL Mix", "LIN34 PGA" 694 {"AINLMUX", "DIFFINL Mix", "LIN34 PGA"},
695 {"AINLMUX", "RXVOICE Mix", "LIN4/RXN"} 695 {"AINLMUX", "RXVOICE Mix", "LIN4/RXN"},
696 {"AINLMUX", "RXVOICE Mix", "RIN4/RXP"} 696 {"AINLMUX", "RXVOICE Mix", "RIN4/RXP"},
697 /* ADC */ 697 /* ADC */
698 {"Left ADC", NULL, "AINLMUX"}, 698 {"Left ADC", NULL, "AINLMUX"},
699 699
700 /* RIN12 PGA */ 700 /* RIN12 PGA */
701 {"RIN12 PGA", "RIN1 Switch", "RIN1"}, 701 {"RIN12 PGA", "RIN1 Switch", "RIN1"},
702 {"RIN12 PGA", "RIN2 Switch", "RIN2"}, 702 {"RIN12 PGA", "RIN2 Switch", "RIN2"},
703 /* RIN34 PGA */ 703 /* RIN34 PGA */
704 {"RIN34 PGA", "RIN3 Switch", "RIN3"}, 704 {"RIN34 PGA", "RIN3 Switch", "RIN3"},
705 {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP 705 {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"},
706 /* INMIXL */ 706 /* INMIXL */
707 {"INMIXR", "Record Right Volume", "ROM 707 {"INMIXR", "Record Right Volume", "ROMIX"},
708 {"INMIXR", "RIN2 Volume", "RIN2"}, 708 {"INMIXR", "RIN2 Volume", "RIN2"},
709 {"INMIXR", "RINPGA12 Switch", "RIN12 P 709 {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
710 {"INMIXR", "RINPGA34 Switch", "RIN34 P 710 {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
711 /* AINRMUX */ 711 /* AINRMUX */
712 {"AINRMUX", "INMIXR Mix", "INMIXR"}, 712 {"AINRMUX", "INMIXR Mix", "INMIXR"},
713 {"AINRMUX", "DIFFINR Mix", "RIN12 PGA" 713 {"AINRMUX", "DIFFINR Mix", "RIN12 PGA"},
714 {"AINRMUX", "DIFFINR Mix", "RIN34 PGA" 714 {"AINRMUX", "DIFFINR Mix", "RIN34 PGA"},
715 {"AINRMUX", "RXVOICE Mix", "LIN4/RXN"} 715 {"AINRMUX", "RXVOICE Mix", "LIN4/RXN"},
716 {"AINRMUX", "RXVOICE Mix", "RIN4/RXP"} 716 {"AINRMUX", "RXVOICE Mix", "RIN4/RXP"},
717 /* ADC */ 717 /* ADC */
718 {"Right ADC", NULL, "AINRMUX"}, 718 {"Right ADC", NULL, "AINRMUX"},
719 719
720 /* LOMIX */ 720 /* LOMIX */
721 {"LOMIX", "LOMIX RIN3 Bypass Switch", 721 {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
722 {"LOMIX", "LOMIX LIN3 Bypass Switch", 722 {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
723 {"LOMIX", "LOMIX LIN12 PGA Bypass Swit 723 {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
724 {"LOMIX", "LOMIX RIN12 PGA Bypass Swit 724 {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
725 {"LOMIX", "LOMIX Right ADC Bypass Swit 725 {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"},
726 {"LOMIX", "LOMIX Left ADC Bypass Switc 726 {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"},
727 {"LOMIX", "LOMIX Left DAC Switch", "Le 727 {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
728 728
729 /* ROMIX */ 729 /* ROMIX */
730 {"ROMIX", "ROMIX RIN3 Bypass Switch", 730 {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
731 {"ROMIX", "ROMIX LIN3 Bypass Switch", 731 {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
732 {"ROMIX", "ROMIX LIN12 PGA Bypass Swit 732 {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
733 {"ROMIX", "ROMIX RIN12 PGA Bypass Swit 733 {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
734 {"ROMIX", "ROMIX Right ADC Bypass Swit 734 {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"},
735 {"ROMIX", "ROMIX Left ADC Bypass Switc 735 {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"},
736 {"ROMIX", "ROMIX Right DAC Switch", "R 736 {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
737 737
738 /* SPKMIX */ 738 /* SPKMIX */
739 {"SPKMIX", "SPKMIX LIN2 Bypass Switch" 739 {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
740 {"SPKMIX", "SPKMIX RIN2 Bypass Switch" 740 {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
741 {"SPKMIX", "SPKMIX LADC Bypass Switch" 741 {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"},
742 {"SPKMIX", "SPKMIX RADC Bypass Switch" 742 {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"},
743 {"SPKMIX", "SPKMIX Left Mixer PGA Swit 743 {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
744 {"SPKMIX", "SPKMIX Right Mixer PGA Swi 744 {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
745 {"SPKMIX", "SPKMIX Right DAC Switch", 745 {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
746 {"SPKMIX", "SPKMIX Left DAC Switch", " 746 {"SPKMIX", "SPKMIX Left DAC Switch", "Left DAC"},
747 747
748 /* LONMIX */ 748 /* LONMIX */
749 {"LONMIX", "LONMIX Left Mixer PGA Swit 749 {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
750 {"LONMIX", "LONMIX Right Mixer PGA Swi 750 {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
751 {"LONMIX", "LONMIX Inverted LOP Switch 751 {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
752 752
753 /* LOPMIX */ 753 /* LOPMIX */
754 {"LOPMIX", "LOPMIX Right Mic Bypass Sw 754 {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
755 {"LOPMIX", "LOPMIX Left Mic Bypass Swi 755 {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
756 {"LOPMIX", "LOPMIX Left Mixer PGA Swit 756 {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
757 757
758 /* OUT3MIX */ 758 /* OUT3MIX */
759 {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass S 759 {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"},
760 {"OUT3MIX", "OUT3MIX Left Out PGA Swit 760 {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
761 761
762 /* OUT4MIX */ 762 /* OUT4MIX */
763 {"OUT4MIX", "OUT4MIX Right Out PGA Swi 763 {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
764 {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass S 764 {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"},
765 765
766 /* RONMIX */ 766 /* RONMIX */
767 {"RONMIX", "RONMIX Right Mixer PGA Swi 767 {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
768 {"RONMIX", "RONMIX Left Mixer PGA Swit 768 {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
769 {"RONMIX", "RONMIX Inverted ROP Switch 769 {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
770 770
771 /* ROPMIX */ 771 /* ROPMIX */
772 {"ROPMIX", "ROPMIX Left Mic Bypass Swi 772 {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
773 {"ROPMIX", "ROPMIX Right Mic Bypass Sw 773 {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
774 {"ROPMIX", "ROPMIX Right Mixer PGA Swi 774 {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
775 775
776 /* Out Mixer PGAs */ 776 /* Out Mixer PGAs */
777 {"LOPGA", NULL, "LOMIX"}, 777 {"LOPGA", NULL, "LOMIX"},
778 {"ROPGA", NULL, "ROMIX"}, 778 {"ROPGA", NULL, "ROMIX"},
779 779
780 {"LOUT PGA", NULL, "LOMIX"}, 780 {"LOUT PGA", NULL, "LOMIX"},
781 {"ROUT PGA", NULL, "ROMIX"}, 781 {"ROUT PGA", NULL, "ROMIX"},
782 782
783 /* Output Pins */ 783 /* Output Pins */
784 {"LON", NULL, "LONMIX"}, 784 {"LON", NULL, "LONMIX"},
785 {"LOP", NULL, "LOPMIX"}, 785 {"LOP", NULL, "LOPMIX"},
786 {"OUT3", NULL, "OUT3MIX"}, 786 {"OUT3", NULL, "OUT3MIX"},
787 {"LOUT", NULL, "LOUT PGA"}, 787 {"LOUT", NULL, "LOUT PGA"},
788 {"SPKN", NULL, "SPKMIX"}, 788 {"SPKN", NULL, "SPKMIX"},
789 {"ROUT", NULL, "ROUT PGA"}, 789 {"ROUT", NULL, "ROUT PGA"},
790 {"OUT4", NULL, "OUT4MIX"}, 790 {"OUT4", NULL, "OUT4MIX"},
791 {"ROP", NULL, "ROPMIX"}, 791 {"ROP", NULL, "ROPMIX"},
792 {"RON", NULL, "RONMIX"}, 792 {"RON", NULL, "RONMIX"},
793 }; 793 };
794 794
795 /* PLL divisors */ 795 /* PLL divisors */
796 struct _pll_div { 796 struct _pll_div {
797 u32 div2; 797 u32 div2;
798 u32 n; 798 u32 n;
799 u32 k; 799 u32 k;
800 }; 800 };
801 801
802 /* The size in bits of the pll divide multipli 802 /* The size in bits of the pll divide multiplied by 10
803 * to allow rounding later */ 803 * to allow rounding later */
804 #define FIXED_PLL_SIZE ((1 << 16) * 10) 804 #define FIXED_PLL_SIZE ((1 << 16) * 10)
805 805
806 static void pll_factors(struct _pll_div *pll_d 806 static void pll_factors(struct _pll_div *pll_div, unsigned int target,
807 unsigned int source) 807 unsigned int source)
808 { 808 {
809 u64 Kpart; 809 u64 Kpart;
810 unsigned int K, Ndiv, Nmod; 810 unsigned int K, Ndiv, Nmod;
811 811
812 812
813 Ndiv = target / source; 813 Ndiv = target / source;
814 if (Ndiv < 6) { 814 if (Ndiv < 6) {
815 source >>= 1; 815 source >>= 1;
816 pll_div->div2 = 1; 816 pll_div->div2 = 1;
817 Ndiv = target / source; 817 Ndiv = target / source;
818 } else 818 } else
819 pll_div->div2 = 0; 819 pll_div->div2 = 0;
820 820
821 if ((Ndiv < 6) || (Ndiv > 12)) 821 if ((Ndiv < 6) || (Ndiv > 12))
822 printk(KERN_WARNING 822 printk(KERN_WARNING
823 "WM8990 N value outwith recomm 823 "WM8990 N value outwith recommended range! N = %u\n", Ndiv);
824 824
825 pll_div->n = Ndiv; 825 pll_div->n = Ndiv;
826 Nmod = target % source; 826 Nmod = target % source;
827 Kpart = FIXED_PLL_SIZE * (long long)Nm 827 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
828 828
829 do_div(Kpart, source); 829 do_div(Kpart, source);
830 830
831 K = Kpart & 0xFFFFFFFF; 831 K = Kpart & 0xFFFFFFFF;
832 832
833 /* Check if we need to round */ 833 /* Check if we need to round */
834 if ((K % 10) >= 5) 834 if ((K % 10) >= 5)
835 K += 5; 835 K += 5;
836 836
837 /* Move down to proper range now round 837 /* Move down to proper range now rounding is done */
838 K /= 10; 838 K /= 10;
839 839
840 pll_div->k = K; 840 pll_div->k = K;
841 } 841 }
842 842
843 static int wm8990_set_dai_pll(struct snd_soc_d 843 static int wm8990_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
844 int source, unsigned int freq_ 844 int source, unsigned int freq_in, unsigned int freq_out)
845 { 845 {
846 struct snd_soc_component *component = 846 struct snd_soc_component *component = codec_dai->component;
847 struct _pll_div pll_div; 847 struct _pll_div pll_div;
848 848
849 if (freq_in && freq_out) { 849 if (freq_in && freq_out) {
850 pll_factors(&pll_div, freq_out 850 pll_factors(&pll_div, freq_out * 4, freq_in);
851 851
852 /* Turn on PLL */ 852 /* Turn on PLL */
853 snd_soc_component_update_bits( 853 snd_soc_component_update_bits(component, WM8990_POWER_MANAGEMENT_2,
854 WM8990_PLL 854 WM8990_PLL_ENA, WM8990_PLL_ENA);
855 855
856 /* sysclk comes from PLL */ 856 /* sysclk comes from PLL */
857 snd_soc_component_update_bits( 857 snd_soc_component_update_bits(component, WM8990_CLOCKING_2,
858 WM8990_SYS 858 WM8990_SYSCLK_SRC, WM8990_SYSCLK_SRC);
859 859
860 /* set up N , fractional mode 860 /* set up N , fractional mode and pre-divisor if necessary */
861 snd_soc_component_write(compon 861 snd_soc_component_write(component, WM8990_PLL1, pll_div.n | WM8990_SDM |
862 (pll_div.div2?WM8990_P 862 (pll_div.div2?WM8990_PRESCALE:0));
863 snd_soc_component_write(compon 863 snd_soc_component_write(component, WM8990_PLL2, (u8)(pll_div.k>>8));
864 snd_soc_component_write(compon 864 snd_soc_component_write(component, WM8990_PLL3, (u8)(pll_div.k & 0xFF));
865 } else { 865 } else {
866 /* Turn off PLL */ 866 /* Turn off PLL */
867 snd_soc_component_update_bits( 867 snd_soc_component_update_bits(component, WM8990_POWER_MANAGEMENT_2,
868 WM8990_PLL 868 WM8990_PLL_ENA, 0);
869 } 869 }
870 return 0; 870 return 0;
871 } 871 }
872 872
873 /* 873 /*
874 * Clock after PLL and dividers 874 * Clock after PLL and dividers
875 */ 875 */
876 static int wm8990_set_dai_sysclk(struct snd_so 876 static int wm8990_set_dai_sysclk(struct snd_soc_dai *codec_dai,
877 int clk_id, unsigned int freq, 877 int clk_id, unsigned int freq, int dir)
878 { 878 {
879 struct snd_soc_component *component = 879 struct snd_soc_component *component = codec_dai->component;
880 struct wm8990_priv *wm8990 = snd_soc_c 880 struct wm8990_priv *wm8990 = snd_soc_component_get_drvdata(component);
881 881
882 wm8990->sysclk = freq; 882 wm8990->sysclk = freq;
883 return 0; 883 return 0;
884 } 884 }
885 885
886 /* 886 /*
887 * Set's ADC and Voice DAC format. 887 * Set's ADC and Voice DAC format.
888 */ 888 */
889 static int wm8990_set_dai_fmt(struct snd_soc_d 889 static int wm8990_set_dai_fmt(struct snd_soc_dai *codec_dai,
890 unsigned int fmt) 890 unsigned int fmt)
891 { 891 {
892 struct snd_soc_component *component = 892 struct snd_soc_component *component = codec_dai->component;
893 u16 audio1, audio3; 893 u16 audio1, audio3;
894 894
895 audio1 = snd_soc_component_read(compon 895 audio1 = snd_soc_component_read(component, WM8990_AUDIO_INTERFACE_1);
896 audio3 = snd_soc_component_read(compon 896 audio3 = snd_soc_component_read(component, WM8990_AUDIO_INTERFACE_3);
897 897
898 /* set master/slave audio interface */ 898 /* set master/slave audio interface */
899 switch (fmt & SND_SOC_DAIFMT_MASTER_MA 899 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
900 case SND_SOC_DAIFMT_CBS_CFS: 900 case SND_SOC_DAIFMT_CBS_CFS:
901 audio3 &= ~WM8990_AIF_MSTR1; 901 audio3 &= ~WM8990_AIF_MSTR1;
902 break; 902 break;
903 case SND_SOC_DAIFMT_CBM_CFM: 903 case SND_SOC_DAIFMT_CBM_CFM:
904 audio3 |= WM8990_AIF_MSTR1; 904 audio3 |= WM8990_AIF_MSTR1;
905 break; 905 break;
906 default: 906 default:
907 return -EINVAL; 907 return -EINVAL;
908 } 908 }
909 909
910 audio1 &= ~WM8990_AIF_FMT_MASK; 910 audio1 &= ~WM8990_AIF_FMT_MASK;
911 911
912 /* interface format */ 912 /* interface format */
913 switch (fmt & SND_SOC_DAIFMT_FORMAT_MA 913 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
914 case SND_SOC_DAIFMT_I2S: 914 case SND_SOC_DAIFMT_I2S:
915 audio1 |= WM8990_AIF_TMF_I2S; 915 audio1 |= WM8990_AIF_TMF_I2S;
916 audio1 &= ~WM8990_AIF_LRCLK_IN 916 audio1 &= ~WM8990_AIF_LRCLK_INV;
917 break; 917 break;
918 case SND_SOC_DAIFMT_RIGHT_J: 918 case SND_SOC_DAIFMT_RIGHT_J:
919 audio1 |= WM8990_AIF_TMF_RIGHT 919 audio1 |= WM8990_AIF_TMF_RIGHTJ;
920 audio1 &= ~WM8990_AIF_LRCLK_IN 920 audio1 &= ~WM8990_AIF_LRCLK_INV;
921 break; 921 break;
922 case SND_SOC_DAIFMT_LEFT_J: 922 case SND_SOC_DAIFMT_LEFT_J:
923 audio1 |= WM8990_AIF_TMF_LEFTJ 923 audio1 |= WM8990_AIF_TMF_LEFTJ;
924 audio1 &= ~WM8990_AIF_LRCLK_IN 924 audio1 &= ~WM8990_AIF_LRCLK_INV;
925 break; 925 break;
926 case SND_SOC_DAIFMT_DSP_A: 926 case SND_SOC_DAIFMT_DSP_A:
927 audio1 |= WM8990_AIF_TMF_DSP; 927 audio1 |= WM8990_AIF_TMF_DSP;
928 audio1 &= ~WM8990_AIF_LRCLK_IN 928 audio1 &= ~WM8990_AIF_LRCLK_INV;
929 break; 929 break;
930 case SND_SOC_DAIFMT_DSP_B: 930 case SND_SOC_DAIFMT_DSP_B:
931 audio1 |= WM8990_AIF_TMF_DSP | 931 audio1 |= WM8990_AIF_TMF_DSP | WM8990_AIF_LRCLK_INV;
932 break; 932 break;
933 default: 933 default:
934 return -EINVAL; 934 return -EINVAL;
935 } 935 }
936 936
937 snd_soc_component_write(component, WM8 937 snd_soc_component_write(component, WM8990_AUDIO_INTERFACE_1, audio1);
938 snd_soc_component_write(component, WM8 938 snd_soc_component_write(component, WM8990_AUDIO_INTERFACE_3, audio3);
939 return 0; 939 return 0;
940 } 940 }
941 941
942 static int wm8990_set_dai_clkdiv(struct snd_so 942 static int wm8990_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
943 int div_id, int div) 943 int div_id, int div)
944 { 944 {
945 struct snd_soc_component *component = 945 struct snd_soc_component *component = codec_dai->component;
946 946
947 switch (div_id) { 947 switch (div_id) {
948 case WM8990_MCLK_DIV: 948 case WM8990_MCLK_DIV:
949 snd_soc_component_update_bits( 949 snd_soc_component_update_bits(component, WM8990_CLOCKING_2,
950 WM8990_MCL 950 WM8990_MCLK_DIV_MASK, div);
951 break; 951 break;
952 case WM8990_DACCLK_DIV: 952 case WM8990_DACCLK_DIV:
953 snd_soc_component_update_bits( 953 snd_soc_component_update_bits(component, WM8990_CLOCKING_2,
954 WM8990_DAC 954 WM8990_DAC_CLKDIV_MASK, div);
955 break; 955 break;
956 case WM8990_ADCCLK_DIV: 956 case WM8990_ADCCLK_DIV:
957 snd_soc_component_update_bits( 957 snd_soc_component_update_bits(component, WM8990_CLOCKING_2,
958 WM8990_ADC 958 WM8990_ADC_CLKDIV_MASK, div);
959 break; 959 break;
960 case WM8990_BCLK_DIV: 960 case WM8990_BCLK_DIV:
961 snd_soc_component_update_bits( 961 snd_soc_component_update_bits(component, WM8990_CLOCKING_1,
962 WM8990_BCL 962 WM8990_BCLK_DIV_MASK, div);
963 break; 963 break;
964 default: 964 default:
965 return -EINVAL; 965 return -EINVAL;
966 } 966 }
967 967
968 return 0; 968 return 0;
969 } 969 }
970 970
971 /* 971 /*
972 * Set PCM DAI bit size and sample rate. 972 * Set PCM DAI bit size and sample rate.
973 */ 973 */
974 static int wm8990_hw_params(struct snd_pcm_sub 974 static int wm8990_hw_params(struct snd_pcm_substream *substream,
975 struct snd_pcm_hw_ 975 struct snd_pcm_hw_params *params,
976 struct snd_soc_dai 976 struct snd_soc_dai *dai)
977 { 977 {
978 struct snd_soc_component *component = 978 struct snd_soc_component *component = dai->component;
979 u16 audio1 = snd_soc_component_read(co 979 u16 audio1 = snd_soc_component_read(component, WM8990_AUDIO_INTERFACE_1);
980 980
981 audio1 &= ~WM8990_AIF_WL_MASK; 981 audio1 &= ~WM8990_AIF_WL_MASK;
982 /* bit size */ 982 /* bit size */
983 switch (params_width(params)) { 983 switch (params_width(params)) {
984 case 16: 984 case 16:
985 break; 985 break;
986 case 20: 986 case 20:
987 audio1 |= WM8990_AIF_WL_20BITS 987 audio1 |= WM8990_AIF_WL_20BITS;
988 break; 988 break;
989 case 24: 989 case 24:
990 audio1 |= WM8990_AIF_WL_24BITS 990 audio1 |= WM8990_AIF_WL_24BITS;
991 break; 991 break;
992 case 32: 992 case 32:
993 audio1 |= WM8990_AIF_WL_32BITS 993 audio1 |= WM8990_AIF_WL_32BITS;
994 break; 994 break;
995 } 995 }
996 996
997 snd_soc_component_write(component, WM8 997 snd_soc_component_write(component, WM8990_AUDIO_INTERFACE_1, audio1);
998 return 0; 998 return 0;
999 } 999 }
1000 1000
1001 static int wm8990_mute(struct snd_soc_dai *da 1001 static int wm8990_mute(struct snd_soc_dai *dai, int mute, int direction)
1002 { 1002 {
1003 struct snd_soc_component *component = 1003 struct snd_soc_component *component = dai->component;
1004 u16 val; 1004 u16 val;
1005 1005
1006 val = snd_soc_component_read(compone 1006 val = snd_soc_component_read(component, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE;
1007 1007
1008 if (mute) 1008 if (mute)
1009 snd_soc_component_write(compo 1009 snd_soc_component_write(component, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE);
1010 else 1010 else
1011 snd_soc_component_write(compo 1011 snd_soc_component_write(component, WM8990_DAC_CTRL, val);
1012 1012
1013 return 0; 1013 return 0;
1014 } 1014 }
1015 1015
1016 static int wm8990_set_bias_level(struct snd_s 1016 static int wm8990_set_bias_level(struct snd_soc_component *component,
1017 enum snd_soc_bias_level level) 1017 enum snd_soc_bias_level level)
1018 { 1018 {
1019 struct wm8990_priv *wm8990 = snd_soc_ 1019 struct wm8990_priv *wm8990 = snd_soc_component_get_drvdata(component);
1020 int ret; 1020 int ret;
1021 1021
1022 switch (level) { 1022 switch (level) {
1023 case SND_SOC_BIAS_ON: 1023 case SND_SOC_BIAS_ON:
1024 break; 1024 break;
1025 1025
1026 case SND_SOC_BIAS_PREPARE: 1026 case SND_SOC_BIAS_PREPARE:
1027 /* VMID=2*50k */ 1027 /* VMID=2*50k */
1028 snd_soc_component_update_bits 1028 snd_soc_component_update_bits(component, WM8990_POWER_MANAGEMENT_1,
1029 WM8990_VM 1029 WM8990_VMID_MODE_MASK, 0x2);
1030 break; 1030 break;
1031 1031
1032 case SND_SOC_BIAS_STANDBY: 1032 case SND_SOC_BIAS_STANDBY:
1033 if (snd_soc_component_get_bia 1033 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1034 ret = regcache_sync(w 1034 ret = regcache_sync(wm8990->regmap);
1035 if (ret < 0) { 1035 if (ret < 0) {
1036 dev_err(compo 1036 dev_err(component->dev, "Failed to sync cache: %d\n", ret);
1037 return ret; 1037 return ret;
1038 } 1038 }
1039 1039
1040 /* Enable all output 1040 /* Enable all output discharge bits */
1041 snd_soc_component_wri 1041 snd_soc_component_write(component, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
1042 WM8990_DIS_RL 1042 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1043 WM8990_DIS_OU 1043 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1044 WM8990_DIS_RO 1044 WM8990_DIS_ROUT);
1045 1045
1046 /* Enable POBCTRL, SO 1046 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
1047 snd_soc_component_wri 1047 snd_soc_component_write(component, WM8990_ANTIPOP2, WM8990_SOFTST |
1048 WM8990_B 1048 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1049 WM8990_V 1049 WM8990_VMIDTOG);
1050 1050
1051 /* Delay to allow out 1051 /* Delay to allow output caps to discharge */
1052 msleep(300); 1052 msleep(300);
1053 1053
1054 /* Disable VMIDTOG */ 1054 /* Disable VMIDTOG */
1055 snd_soc_component_wri 1055 snd_soc_component_write(component, WM8990_ANTIPOP2, WM8990_SOFTST |
1056 WM8990_B 1056 WM8990_BUFDCOPEN | WM8990_POBCTRL);
1057 1057
1058 /* disable all output 1058 /* disable all output discharge bits */
1059 snd_soc_component_wri 1059 snd_soc_component_write(component, WM8990_ANTIPOP1, 0);
1060 1060
1061 /* Enable outputs */ 1061 /* Enable outputs */
1062 snd_soc_component_wri 1062 snd_soc_component_write(component, WM8990_POWER_MANAGEMENT_1, 0x1b00);
1063 1063
1064 msleep(50); 1064 msleep(50);
1065 1065
1066 /* Enable VMID at 2x5 1066 /* Enable VMID at 2x50k */
1067 snd_soc_component_wri 1067 snd_soc_component_write(component, WM8990_POWER_MANAGEMENT_1, 0x1f02);
1068 1068
1069 msleep(100); 1069 msleep(100);
1070 1070
1071 /* Enable VREF */ 1071 /* Enable VREF */
1072 snd_soc_component_wri 1072 snd_soc_component_write(component, WM8990_POWER_MANAGEMENT_1, 0x1f03);
1073 1073
1074 msleep(600); 1074 msleep(600);
1075 1075
1076 /* Enable BUFIOEN */ 1076 /* Enable BUFIOEN */
1077 snd_soc_component_wri 1077 snd_soc_component_write(component, WM8990_ANTIPOP2, WM8990_SOFTST |
1078 WM8990_B 1078 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1079 WM8990_B 1079 WM8990_BUFIOEN);
1080 1080
1081 /* Disable outputs */ 1081 /* Disable outputs */
1082 snd_soc_component_wri 1082 snd_soc_component_write(component, WM8990_POWER_MANAGEMENT_1, 0x3);
1083 1083
1084 /* disable POBCTRL, S 1084 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1085 snd_soc_component_wri 1085 snd_soc_component_write(component, WM8990_ANTIPOP2, WM8990_BUFIOEN);
1086 1086
1087 /* Enable workaround 1087 /* Enable workaround for ADC clocking issue. */
1088 snd_soc_component_wri 1088 snd_soc_component_write(component, WM8990_EXT_ACCESS_ENA, 0x2);
1089 snd_soc_component_wri 1089 snd_soc_component_write(component, WM8990_EXT_CTL1, 0xa003);
1090 snd_soc_component_wri 1090 snd_soc_component_write(component, WM8990_EXT_ACCESS_ENA, 0);
1091 } 1091 }
1092 1092
1093 /* VMID=2*250k */ 1093 /* VMID=2*250k */
1094 snd_soc_component_update_bits 1094 snd_soc_component_update_bits(component, WM8990_POWER_MANAGEMENT_1,
1095 WM8990_VM 1095 WM8990_VMID_MODE_MASK, 0x4);
1096 break; 1096 break;
1097 1097
1098 case SND_SOC_BIAS_OFF: 1098 case SND_SOC_BIAS_OFF:
1099 /* Enable POBCTRL and SOFT_ST 1099 /* Enable POBCTRL and SOFT_ST */
1100 snd_soc_component_write(compo 1100 snd_soc_component_write(component, WM8990_ANTIPOP2, WM8990_SOFTST |
1101 WM8990_POBCTRL | WM89 1101 WM8990_POBCTRL | WM8990_BUFIOEN);
1102 1102
1103 /* Enable POBCTRL, SOFT_ST an 1103 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
1104 snd_soc_component_write(compo 1104 snd_soc_component_write(component, WM8990_ANTIPOP2, WM8990_SOFTST |
1105 WM8990_BUFDCOPEN | WM 1105 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1106 WM8990_BUFIOEN); 1106 WM8990_BUFIOEN);
1107 1107
1108 /* mute DAC */ 1108 /* mute DAC */
1109 snd_soc_component_update_bits 1109 snd_soc_component_update_bits(component, WM8990_DAC_CTRL,
1110 WM8990_DA 1110 WM8990_DAC_MUTE, WM8990_DAC_MUTE);
1111 1111
1112 /* Enable any disabled output 1112 /* Enable any disabled outputs */
1113 snd_soc_component_write(compo 1113 snd_soc_component_write(component, WM8990_POWER_MANAGEMENT_1, 0x1f03);
1114 1114
1115 /* Disable VMID */ 1115 /* Disable VMID */
1116 snd_soc_component_write(compo 1116 snd_soc_component_write(component, WM8990_POWER_MANAGEMENT_1, 0x1f01);
1117 1117
1118 msleep(300); 1118 msleep(300);
1119 1119
1120 /* Enable all output discharg 1120 /* Enable all output discharge bits */
1121 snd_soc_component_write(compo 1121 snd_soc_component_write(component, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
1122 WM8990_DIS_RLINE | WM 1122 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1123 WM8990_DIS_OUT4 | WM8 1123 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1124 WM8990_DIS_ROUT); 1124 WM8990_DIS_ROUT);
1125 1125
1126 /* Disable VREF */ 1126 /* Disable VREF */
1127 snd_soc_component_write(compo 1127 snd_soc_component_write(component, WM8990_POWER_MANAGEMENT_1, 0x0);
1128 1128
1129 /* disable POBCTRL, SOFT_ST a 1129 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1130 snd_soc_component_write(compo 1130 snd_soc_component_write(component, WM8990_ANTIPOP2, 0x0);
1131 1131
1132 regcache_mark_dirty(wm8990->r 1132 regcache_mark_dirty(wm8990->regmap);
1133 break; 1133 break;
1134 } 1134 }
1135 1135
1136 return 0; 1136 return 0;
1137 } 1137 }
1138 1138
1139 #define WM8990_RATES (SNDRV_PCM_RATE_8000 | S 1139 #define WM8990_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
1140 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE 1140 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
1141 SNDRV_PCM_RATE_48000) 1141 SNDRV_PCM_RATE_48000)
1142 1142
1143 #define WM8990_FORMATS (SNDRV_PCM_FMTBIT_S16_ 1143 #define WM8990_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1144 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_F 1144 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1145 1145
1146 /* 1146 /*
1147 * The WM8990 supports 2 different and mutual 1147 * The WM8990 supports 2 different and mutually exclusive DAI
1148 * configurations. 1148 * configurations.
1149 * 1149 *
1150 * 1. ADC/DAC on Primary Interface 1150 * 1. ADC/DAC on Primary Interface
1151 * 2. ADC on Primary Interface/DAC on seconda 1151 * 2. ADC on Primary Interface/DAC on secondary
1152 */ 1152 */
1153 static const struct snd_soc_dai_ops wm8990_da 1153 static const struct snd_soc_dai_ops wm8990_dai_ops = {
1154 .hw_params = wm8990_hw_params, 1154 .hw_params = wm8990_hw_params,
1155 .mute_stream = wm8990_mute, 1155 .mute_stream = wm8990_mute,
1156 .set_fmt = wm8990_set_dai_fmt, 1156 .set_fmt = wm8990_set_dai_fmt,
1157 .set_clkdiv = wm8990_set_dai_clkd 1157 .set_clkdiv = wm8990_set_dai_clkdiv,
1158 .set_pll = wm8990_set_dai_pll, 1158 .set_pll = wm8990_set_dai_pll,
1159 .set_sysclk = wm8990_set_dai_sysc 1159 .set_sysclk = wm8990_set_dai_sysclk,
1160 .no_capture_mute = 1, 1160 .no_capture_mute = 1,
1161 }; 1161 };
1162 1162
1163 static struct snd_soc_dai_driver wm8990_dai = 1163 static struct snd_soc_dai_driver wm8990_dai = {
1164 /* ADC/DAC on primary */ 1164 /* ADC/DAC on primary */
1165 .name = "wm8990-hifi", 1165 .name = "wm8990-hifi",
1166 .playback = { 1166 .playback = {
1167 .stream_name = "Playback", 1167 .stream_name = "Playback",
1168 .channels_min = 1, 1168 .channels_min = 1,
1169 .channels_max = 2, 1169 .channels_max = 2,
1170 .rates = WM8990_RATES, 1170 .rates = WM8990_RATES,
1171 .formats = WM8990_FORMATS,}, 1171 .formats = WM8990_FORMATS,},
1172 .capture = { 1172 .capture = {
1173 .stream_name = "Capture", 1173 .stream_name = "Capture",
1174 .channels_min = 1, 1174 .channels_min = 1,
1175 .channels_max = 2, 1175 .channels_max = 2,
1176 .rates = WM8990_RATES, 1176 .rates = WM8990_RATES,
1177 .formats = WM8990_FORMATS,}, 1177 .formats = WM8990_FORMATS,},
1178 .ops = &wm8990_dai_ops, 1178 .ops = &wm8990_dai_ops,
1179 }; 1179 };
1180 1180
1181 /* 1181 /*
1182 * initialise the WM8990 driver 1182 * initialise the WM8990 driver
1183 * register the mixer and dsp interfaces with 1183 * register the mixer and dsp interfaces with the kernel
1184 */ 1184 */
1185 static int wm8990_probe(struct snd_soc_compon 1185 static int wm8990_probe(struct snd_soc_component *component)
1186 { 1186 {
1187 wm8990_reset(component); 1187 wm8990_reset(component);
1188 1188
1189 /* charge output caps */ 1189 /* charge output caps */
1190 snd_soc_component_force_bias_level(co 1190 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
1191 1191
1192 snd_soc_component_update_bits(compone 1192 snd_soc_component_update_bits(component, WM8990_AUDIO_INTERFACE_4,
1193 WM8990_ALRCGPIO1, 1193 WM8990_ALRCGPIO1, WM8990_ALRCGPIO1);
1194 1194
1195 snd_soc_component_update_bits(compone 1195 snd_soc_component_update_bits(component, WM8990_GPIO1_GPIO2,
1196 WM8990_GPIO1_SEL_ 1196 WM8990_GPIO1_SEL_MASK, 1);
1197 1197
1198 snd_soc_component_update_bits(compone 1198 snd_soc_component_update_bits(component, WM8990_POWER_MANAGEMENT_2,
1199 WM8990_OPCLK_ENA, 1199 WM8990_OPCLK_ENA, WM8990_OPCLK_ENA);
1200 1200
1201 snd_soc_component_write(component, WM 1201 snd_soc_component_write(component, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
1202 snd_soc_component_write(component, WM 1202 snd_soc_component_write(component, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
1203 1203
1204 return 0; 1204 return 0;
1205 } 1205 }
1206 1206
1207 static const struct snd_soc_component_driver 1207 static const struct snd_soc_component_driver soc_component_dev_wm8990 = {
1208 .probe = wm8990_prob 1208 .probe = wm8990_probe,
1209 .set_bias_level = wm8990_set_ 1209 .set_bias_level = wm8990_set_bias_level,
1210 .controls = wm8990_snd_ 1210 .controls = wm8990_snd_controls,
1211 .num_controls = ARRAY_SIZE( 1211 .num_controls = ARRAY_SIZE(wm8990_snd_controls),
1212 .dapm_widgets = wm8990_dapm 1212 .dapm_widgets = wm8990_dapm_widgets,
1213 .num_dapm_widgets = ARRAY_SIZE( 1213 .num_dapm_widgets = ARRAY_SIZE(wm8990_dapm_widgets),
1214 .dapm_routes = wm8990_dapm 1214 .dapm_routes = wm8990_dapm_routes,
1215 .num_dapm_routes = ARRAY_SIZE( 1215 .num_dapm_routes = ARRAY_SIZE(wm8990_dapm_routes),
1216 .suspend_bias_off = 1, 1216 .suspend_bias_off = 1,
1217 .idle_bias_on = 1, 1217 .idle_bias_on = 1,
1218 .use_pmdown_time = 1, 1218 .use_pmdown_time = 1,
1219 .endianness = 1, 1219 .endianness = 1,
1220 }; 1220 };
1221 1221
1222 static int wm8990_i2c_probe(struct i2c_client 1222 static int wm8990_i2c_probe(struct i2c_client *i2c)
1223 { 1223 {
1224 struct wm8990_priv *wm8990; 1224 struct wm8990_priv *wm8990;
1225 int ret; 1225 int ret;
1226 1226
1227 wm8990 = devm_kzalloc(&i2c->dev, size 1227 wm8990 = devm_kzalloc(&i2c->dev, sizeof(struct wm8990_priv),
1228 GFP_KERNEL); 1228 GFP_KERNEL);
1229 if (wm8990 == NULL) 1229 if (wm8990 == NULL)
1230 return -ENOMEM; 1230 return -ENOMEM;
1231 1231
1232 i2c_set_clientdata(i2c, wm8990); 1232 i2c_set_clientdata(i2c, wm8990);
1233 1233
1234 ret = devm_snd_soc_register_component 1234 ret = devm_snd_soc_register_component(&i2c->dev,
1235 &soc_component_dev_wm 1235 &soc_component_dev_wm8990, &wm8990_dai, 1);
1236 1236
1237 return ret; 1237 return ret;
1238 } 1238 }
1239 1239
1240 static const struct i2c_device_id wm8990_i2c_ 1240 static const struct i2c_device_id wm8990_i2c_id[] = {
1241 { "wm8990" }, !! 1241 { "wm8990", 0 },
1242 { } 1242 { }
1243 }; 1243 };
1244 MODULE_DEVICE_TABLE(i2c, wm8990_i2c_id); 1244 MODULE_DEVICE_TABLE(i2c, wm8990_i2c_id);
1245 1245
1246 static struct i2c_driver wm8990_i2c_driver = 1246 static struct i2c_driver wm8990_i2c_driver = {
1247 .driver = { 1247 .driver = {
1248 .name = "wm8990", 1248 .name = "wm8990",
1249 }, 1249 },
1250 .probe = wm8990_i2c_probe, !! 1250 .probe_new = wm8990_i2c_probe,
1251 .id_table = wm8990_i2c_id, 1251 .id_table = wm8990_i2c_id,
1252 }; 1252 };
1253 1253
1254 module_i2c_driver(wm8990_i2c_driver); 1254 module_i2c_driver(wm8990_i2c_driver);
1255 1255
1256 MODULE_DESCRIPTION("ASoC WM8990 driver"); 1256 MODULE_DESCRIPTION("ASoC WM8990 driver");
1257 MODULE_AUTHOR("Liam Girdwood"); 1257 MODULE_AUTHOR("Liam Girdwood");
1258 MODULE_LICENSE("GPL"); 1258 MODULE_LICENSE("GPL");
1259 1259
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