1 // SPDX-License-Identifier: GPL-2.0-or-later <<
2 /* 1 /*
3 * wm8996.c - WM8996 audio codec interface 2 * wm8996.c - WM8996 audio codec interface
4 * 3 *
5 * Copyright 2011-2 Wolfson Microelectronics P 4 * Copyright 2011-2 Wolfson Microelectronics PLC.
6 * Author: Mark Brown <broonie@opensource.wolf 5 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
>> 6 *
>> 7 * This program is free software; you can redistribute it and/or modify it
>> 8 * under the terms of the GNU General Public License as published by the
>> 9 * Free Software Foundation; either version 2 of the License, or (at your
>> 10 * option) any later version.
7 */ 11 */
8 12
9 #include <linux/module.h> 13 #include <linux/module.h>
10 #include <linux/moduleparam.h> 14 #include <linux/moduleparam.h>
11 #include <linux/init.h> 15 #include <linux/init.h>
12 #include <linux/completion.h> 16 #include <linux/completion.h>
13 #include <linux/delay.h> 17 #include <linux/delay.h>
14 #include <linux/pm.h> 18 #include <linux/pm.h>
15 #include <linux/gcd.h> 19 #include <linux/gcd.h>
16 #include <linux/gpio/driver.h> !! 20 #include <linux/gpio.h>
17 #include <linux/gpio/consumer.h> <<
18 #include <linux/i2c.h> 21 #include <linux/i2c.h>
19 #include <linux/regmap.h> 22 #include <linux/regmap.h>
20 #include <linux/regulator/consumer.h> 23 #include <linux/regulator/consumer.h>
21 #include <linux/slab.h> 24 #include <linux/slab.h>
22 #include <linux/workqueue.h> 25 #include <linux/workqueue.h>
23 #include <sound/core.h> 26 #include <sound/core.h>
24 #include <sound/jack.h> 27 #include <sound/jack.h>
25 #include <sound/pcm.h> 28 #include <sound/pcm.h>
26 #include <sound/pcm_params.h> 29 #include <sound/pcm_params.h>
27 #include <sound/soc.h> 30 #include <sound/soc.h>
28 #include <sound/initval.h> 31 #include <sound/initval.h>
29 #include <sound/tlv.h> 32 #include <sound/tlv.h>
30 #include <trace/events/asoc.h> 33 #include <trace/events/asoc.h>
31 34
32 #include <sound/wm8996.h> 35 #include <sound/wm8996.h>
33 #include "wm8996.h" 36 #include "wm8996.h"
34 37
35 #define WM8996_AIFS 2 38 #define WM8996_AIFS 2
36 39
37 #define HPOUT1L 1 40 #define HPOUT1L 1
38 #define HPOUT1R 2 41 #define HPOUT1R 2
39 #define HPOUT2L 4 42 #define HPOUT2L 4
40 #define HPOUT2R 8 43 #define HPOUT2R 8
41 44
42 #define WM8996_NUM_SUPPLIES 3 45 #define WM8996_NUM_SUPPLIES 3
43 static const char *wm8996_supply_names[WM8996_ 46 static const char *wm8996_supply_names[WM8996_NUM_SUPPLIES] = {
44 "DBVDD", 47 "DBVDD",
45 "AVDD1", 48 "AVDD1",
46 "AVDD2", 49 "AVDD2",
47 }; 50 };
48 51
49 struct wm8996_priv { 52 struct wm8996_priv {
50 struct device *dev; 53 struct device *dev;
51 struct regmap *regmap; 54 struct regmap *regmap;
52 struct snd_soc_component *component; !! 55 struct snd_soc_codec *codec;
53 56
54 struct gpio_desc *ldo_ena; !! 57 int ldo1ena;
55 58
56 int sysclk; 59 int sysclk;
57 int sysclk_src; 60 int sysclk_src;
58 61
59 int fll_src; 62 int fll_src;
60 int fll_fref; 63 int fll_fref;
61 int fll_fout; 64 int fll_fout;
62 65
63 struct completion fll_lock; 66 struct completion fll_lock;
64 67
65 u16 dcs_pending; 68 u16 dcs_pending;
66 struct completion dcs_done; 69 struct completion dcs_done;
67 70
68 u16 hpout_ena; 71 u16 hpout_ena;
69 u16 hpout_pending; 72 u16 hpout_pending;
70 73
71 struct regulator_bulk_data supplies[WM 74 struct regulator_bulk_data supplies[WM8996_NUM_SUPPLIES];
72 struct notifier_block disable_nb[WM899 75 struct notifier_block disable_nb[WM8996_NUM_SUPPLIES];
73 int bg_ena; 76 int bg_ena;
74 77
75 struct wm8996_pdata pdata; 78 struct wm8996_pdata pdata;
76 79
77 int rx_rate[WM8996_AIFS]; 80 int rx_rate[WM8996_AIFS];
78 int bclk_rate[WM8996_AIFS]; 81 int bclk_rate[WM8996_AIFS];
79 82
80 /* Platform dependant ReTune mobile co 83 /* Platform dependant ReTune mobile configuration */
81 int num_retune_mobile_texts; 84 int num_retune_mobile_texts;
82 const char **retune_mobile_texts; 85 const char **retune_mobile_texts;
83 int retune_mobile_cfg[2]; 86 int retune_mobile_cfg[2];
84 struct soc_enum retune_mobile_enum; 87 struct soc_enum retune_mobile_enum;
85 88
86 struct snd_soc_jack *jack; 89 struct snd_soc_jack *jack;
87 bool detecting; 90 bool detecting;
88 bool jack_mic; 91 bool jack_mic;
89 int jack_flips; 92 int jack_flips;
90 wm8996_polarity_fn polarity_cb; 93 wm8996_polarity_fn polarity_cb;
91 94
92 #ifdef CONFIG_GPIOLIB 95 #ifdef CONFIG_GPIOLIB
93 struct gpio_chip gpio_chip; 96 struct gpio_chip gpio_chip;
94 #endif 97 #endif
95 }; 98 };
96 99
97 /* We can't use the same notifier block for mo 100 /* We can't use the same notifier block for more than one supply and
98 * there's no way I can see to get from a call 101 * there's no way I can see to get from a callback to the caller
99 * except container_of(). 102 * except container_of().
100 */ 103 */
101 #define WM8996_REGULATOR_EVENT(n) \ 104 #define WM8996_REGULATOR_EVENT(n) \
102 static int wm8996_regulator_event_##n(struct n 105 static int wm8996_regulator_event_##n(struct notifier_block *nb, \
103 unsigned l 106 unsigned long event, void *data) \
104 { \ 107 { \
105 struct wm8996_priv *wm8996 = container 108 struct wm8996_priv *wm8996 = container_of(nb, struct wm8996_priv, \
106 109 disable_nb[n]); \
107 if (event & REGULATOR_EVENT_DISABLE) { 110 if (event & REGULATOR_EVENT_DISABLE) { \
108 regcache_mark_dirty(wm8996->re 111 regcache_mark_dirty(wm8996->regmap); \
109 } \ 112 } \
110 return 0; \ 113 return 0; \
111 } 114 }
112 115
113 WM8996_REGULATOR_EVENT(0) 116 WM8996_REGULATOR_EVENT(0)
114 WM8996_REGULATOR_EVENT(1) 117 WM8996_REGULATOR_EVENT(1)
115 WM8996_REGULATOR_EVENT(2) 118 WM8996_REGULATOR_EVENT(2)
116 119
117 static const struct reg_default wm8996_reg[] = 120 static const struct reg_default wm8996_reg[] = {
118 { WM8996_POWER_MANAGEMENT_1, 0x0 }, 121 { WM8996_POWER_MANAGEMENT_1, 0x0 },
119 { WM8996_POWER_MANAGEMENT_2, 0x0 }, 122 { WM8996_POWER_MANAGEMENT_2, 0x0 },
120 { WM8996_POWER_MANAGEMENT_3, 0x0 }, 123 { WM8996_POWER_MANAGEMENT_3, 0x0 },
121 { WM8996_POWER_MANAGEMENT_4, 0x0 }, 124 { WM8996_POWER_MANAGEMENT_4, 0x0 },
122 { WM8996_POWER_MANAGEMENT_5, 0x0 }, 125 { WM8996_POWER_MANAGEMENT_5, 0x0 },
123 { WM8996_POWER_MANAGEMENT_6, 0x0 }, 126 { WM8996_POWER_MANAGEMENT_6, 0x0 },
124 { WM8996_POWER_MANAGEMENT_7, 0x10 }, 127 { WM8996_POWER_MANAGEMENT_7, 0x10 },
125 { WM8996_POWER_MANAGEMENT_8, 0x0 }, 128 { WM8996_POWER_MANAGEMENT_8, 0x0 },
126 { WM8996_LEFT_LINE_INPUT_VOLUME, 0x0 } 129 { WM8996_LEFT_LINE_INPUT_VOLUME, 0x0 },
127 { WM8996_RIGHT_LINE_INPUT_VOLUME, 0x0 130 { WM8996_RIGHT_LINE_INPUT_VOLUME, 0x0 },
128 { WM8996_LINE_INPUT_CONTROL, 0x0 }, 131 { WM8996_LINE_INPUT_CONTROL, 0x0 },
129 { WM8996_DAC1_HPOUT1_VOLUME, 0x88 }, 132 { WM8996_DAC1_HPOUT1_VOLUME, 0x88 },
130 { WM8996_DAC2_HPOUT2_VOLUME, 0x88 }, 133 { WM8996_DAC2_HPOUT2_VOLUME, 0x88 },
131 { WM8996_DAC1_LEFT_VOLUME, 0x2c0 }, 134 { WM8996_DAC1_LEFT_VOLUME, 0x2c0 },
132 { WM8996_DAC1_RIGHT_VOLUME, 0x2c0 }, 135 { WM8996_DAC1_RIGHT_VOLUME, 0x2c0 },
133 { WM8996_DAC2_LEFT_VOLUME, 0x2c0 }, 136 { WM8996_DAC2_LEFT_VOLUME, 0x2c0 },
134 { WM8996_DAC2_RIGHT_VOLUME, 0x2c0 }, 137 { WM8996_DAC2_RIGHT_VOLUME, 0x2c0 },
135 { WM8996_OUTPUT1_LEFT_VOLUME, 0x80 }, 138 { WM8996_OUTPUT1_LEFT_VOLUME, 0x80 },
136 { WM8996_OUTPUT1_RIGHT_VOLUME, 0x80 }, 139 { WM8996_OUTPUT1_RIGHT_VOLUME, 0x80 },
137 { WM8996_OUTPUT2_LEFT_VOLUME, 0x80 }, 140 { WM8996_OUTPUT2_LEFT_VOLUME, 0x80 },
138 { WM8996_OUTPUT2_RIGHT_VOLUME, 0x80 }, 141 { WM8996_OUTPUT2_RIGHT_VOLUME, 0x80 },
139 { WM8996_MICBIAS_1, 0x39 }, 142 { WM8996_MICBIAS_1, 0x39 },
140 { WM8996_MICBIAS_2, 0x39 }, 143 { WM8996_MICBIAS_2, 0x39 },
141 { WM8996_LDO_1, 0x3 }, 144 { WM8996_LDO_1, 0x3 },
142 { WM8996_LDO_2, 0x13 }, 145 { WM8996_LDO_2, 0x13 },
143 { WM8996_ACCESSORY_DETECT_MODE_1, 0x4 146 { WM8996_ACCESSORY_DETECT_MODE_1, 0x4 },
144 { WM8996_ACCESSORY_DETECT_MODE_2, 0x0 147 { WM8996_ACCESSORY_DETECT_MODE_2, 0x0 },
145 { WM8996_HEADPHONE_DETECT_1, 0x20 }, 148 { WM8996_HEADPHONE_DETECT_1, 0x20 },
146 { WM8996_HEADPHONE_DETECT_2, 0x0 }, 149 { WM8996_HEADPHONE_DETECT_2, 0x0 },
147 { WM8996_MIC_DETECT_1, 0x7600 }, 150 { WM8996_MIC_DETECT_1, 0x7600 },
148 { WM8996_MIC_DETECT_2, 0xbf }, 151 { WM8996_MIC_DETECT_2, 0xbf },
149 { WM8996_CHARGE_PUMP_1, 0x1f25 }, 152 { WM8996_CHARGE_PUMP_1, 0x1f25 },
150 { WM8996_CHARGE_PUMP_2, 0xab19 }, 153 { WM8996_CHARGE_PUMP_2, 0xab19 },
151 { WM8996_DC_SERVO_1, 0x0 }, 154 { WM8996_DC_SERVO_1, 0x0 },
152 { WM8996_DC_SERVO_3, 0x0 }, 155 { WM8996_DC_SERVO_3, 0x0 },
153 { WM8996_DC_SERVO_5, 0x2a2a }, 156 { WM8996_DC_SERVO_5, 0x2a2a },
154 { WM8996_DC_SERVO_6, 0x0 }, 157 { WM8996_DC_SERVO_6, 0x0 },
155 { WM8996_DC_SERVO_7, 0x0 }, 158 { WM8996_DC_SERVO_7, 0x0 },
156 { WM8996_ANALOGUE_HP_1, 0x0 }, 159 { WM8996_ANALOGUE_HP_1, 0x0 },
157 { WM8996_ANALOGUE_HP_2, 0x0 }, 160 { WM8996_ANALOGUE_HP_2, 0x0 },
158 { WM8996_CONTROL_INTERFACE_1, 0x8004 } 161 { WM8996_CONTROL_INTERFACE_1, 0x8004 },
159 { WM8996_WRITE_SEQUENCER_CTRL_1, 0x0 } 162 { WM8996_WRITE_SEQUENCER_CTRL_1, 0x0 },
160 { WM8996_WRITE_SEQUENCER_CTRL_2, 0x0 } 163 { WM8996_WRITE_SEQUENCER_CTRL_2, 0x0 },
161 { WM8996_AIF_CLOCKING_1, 0x0 }, 164 { WM8996_AIF_CLOCKING_1, 0x0 },
162 { WM8996_AIF_CLOCKING_2, 0x0 }, 165 { WM8996_AIF_CLOCKING_2, 0x0 },
163 { WM8996_CLOCKING_1, 0x10 }, 166 { WM8996_CLOCKING_1, 0x10 },
164 { WM8996_CLOCKING_2, 0x0 }, 167 { WM8996_CLOCKING_2, 0x0 },
165 { WM8996_AIF_RATE, 0x83 }, 168 { WM8996_AIF_RATE, 0x83 },
166 { WM8996_FLL_CONTROL_1, 0x0 }, 169 { WM8996_FLL_CONTROL_1, 0x0 },
167 { WM8996_FLL_CONTROL_2, 0x0 }, 170 { WM8996_FLL_CONTROL_2, 0x0 },
168 { WM8996_FLL_CONTROL_3, 0x0 }, 171 { WM8996_FLL_CONTROL_3, 0x0 },
169 { WM8996_FLL_CONTROL_4, 0x5dc0 }, 172 { WM8996_FLL_CONTROL_4, 0x5dc0 },
170 { WM8996_FLL_CONTROL_5, 0xc84 }, 173 { WM8996_FLL_CONTROL_5, 0xc84 },
171 { WM8996_FLL_EFS_1, 0x0 }, 174 { WM8996_FLL_EFS_1, 0x0 },
172 { WM8996_FLL_EFS_2, 0x2 }, 175 { WM8996_FLL_EFS_2, 0x2 },
173 { WM8996_AIF1_CONTROL, 0x0 }, 176 { WM8996_AIF1_CONTROL, 0x0 },
174 { WM8996_AIF1_BCLK, 0x0 }, 177 { WM8996_AIF1_BCLK, 0x0 },
175 { WM8996_AIF1_TX_LRCLK_1, 0x80 }, 178 { WM8996_AIF1_TX_LRCLK_1, 0x80 },
176 { WM8996_AIF1_TX_LRCLK_2, 0x8 }, 179 { WM8996_AIF1_TX_LRCLK_2, 0x8 },
177 { WM8996_AIF1_RX_LRCLK_1, 0x80 }, 180 { WM8996_AIF1_RX_LRCLK_1, 0x80 },
178 { WM8996_AIF1_RX_LRCLK_2, 0x0 }, 181 { WM8996_AIF1_RX_LRCLK_2, 0x0 },
179 { WM8996_AIF1TX_DATA_CONFIGURATION_1, 182 { WM8996_AIF1TX_DATA_CONFIGURATION_1, 0x1818 },
180 { WM8996_AIF1TX_DATA_CONFIGURATION_2, 183 { WM8996_AIF1TX_DATA_CONFIGURATION_2, 0 },
181 { WM8996_AIF1RX_DATA_CONFIGURATION, 0x 184 { WM8996_AIF1RX_DATA_CONFIGURATION, 0x1818 },
182 { WM8996_AIF1TX_CHANNEL_0_CONFIGURATIO 185 { WM8996_AIF1TX_CHANNEL_0_CONFIGURATION, 0x0 },
183 { WM8996_AIF1TX_CHANNEL_1_CONFIGURATIO 186 { WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, 0x0 },
184 { WM8996_AIF1TX_CHANNEL_2_CONFIGURATIO 187 { WM8996_AIF1TX_CHANNEL_2_CONFIGURATION, 0x0 },
185 { WM8996_AIF1TX_CHANNEL_3_CONFIGURATIO 188 { WM8996_AIF1TX_CHANNEL_3_CONFIGURATION, 0x0 },
186 { WM8996_AIF1TX_CHANNEL_4_CONFIGURATIO 189 { WM8996_AIF1TX_CHANNEL_4_CONFIGURATION, 0x0 },
187 { WM8996_AIF1TX_CHANNEL_5_CONFIGURATIO 190 { WM8996_AIF1TX_CHANNEL_5_CONFIGURATION, 0x0 },
188 { WM8996_AIF1RX_CHANNEL_0_CONFIGURATIO 191 { WM8996_AIF1RX_CHANNEL_0_CONFIGURATION, 0x0 },
189 { WM8996_AIF1RX_CHANNEL_1_CONFIGURATIO 192 { WM8996_AIF1RX_CHANNEL_1_CONFIGURATION, 0x0 },
190 { WM8996_AIF1RX_CHANNEL_2_CONFIGURATIO 193 { WM8996_AIF1RX_CHANNEL_2_CONFIGURATION, 0x0 },
191 { WM8996_AIF1RX_CHANNEL_3_CONFIGURATIO 194 { WM8996_AIF1RX_CHANNEL_3_CONFIGURATION, 0x0 },
192 { WM8996_AIF1RX_CHANNEL_4_CONFIGURATIO 195 { WM8996_AIF1RX_CHANNEL_4_CONFIGURATION, 0x0 },
193 { WM8996_AIF1RX_CHANNEL_5_CONFIGURATIO 196 { WM8996_AIF1RX_CHANNEL_5_CONFIGURATION, 0x0 },
194 { WM8996_AIF1RX_MONO_CONFIGURATION, 0x 197 { WM8996_AIF1RX_MONO_CONFIGURATION, 0x0 },
195 { WM8996_AIF1TX_TEST, 0x7 }, 198 { WM8996_AIF1TX_TEST, 0x7 },
196 { WM8996_AIF2_CONTROL, 0x0 }, 199 { WM8996_AIF2_CONTROL, 0x0 },
197 { WM8996_AIF2_BCLK, 0x0 }, 200 { WM8996_AIF2_BCLK, 0x0 },
198 { WM8996_AIF2_TX_LRCLK_1, 0x80 }, 201 { WM8996_AIF2_TX_LRCLK_1, 0x80 },
199 { WM8996_AIF2_TX_LRCLK_2, 0x8 }, 202 { WM8996_AIF2_TX_LRCLK_2, 0x8 },
200 { WM8996_AIF2_RX_LRCLK_1, 0x80 }, 203 { WM8996_AIF2_RX_LRCLK_1, 0x80 },
201 { WM8996_AIF2_RX_LRCLK_2, 0x0 }, 204 { WM8996_AIF2_RX_LRCLK_2, 0x0 },
202 { WM8996_AIF2TX_DATA_CONFIGURATION_1, 205 { WM8996_AIF2TX_DATA_CONFIGURATION_1, 0x1818 },
203 { WM8996_AIF2RX_DATA_CONFIGURATION, 0x 206 { WM8996_AIF2RX_DATA_CONFIGURATION, 0x1818 },
204 { WM8996_AIF2RX_DATA_CONFIGURATION, 0x 207 { WM8996_AIF2RX_DATA_CONFIGURATION, 0x0 },
205 { WM8996_AIF2TX_CHANNEL_0_CONFIGURATIO 208 { WM8996_AIF2TX_CHANNEL_0_CONFIGURATION, 0x0 },
206 { WM8996_AIF2TX_CHANNEL_1_CONFIGURATIO 209 { WM8996_AIF2TX_CHANNEL_1_CONFIGURATION, 0x0 },
207 { WM8996_AIF2RX_CHANNEL_0_CONFIGURATIO 210 { WM8996_AIF2RX_CHANNEL_0_CONFIGURATION, 0x0 },
208 { WM8996_AIF2RX_CHANNEL_1_CONFIGURATIO 211 { WM8996_AIF2RX_CHANNEL_1_CONFIGURATION, 0x0 },
209 { WM8996_AIF2RX_MONO_CONFIGURATION, 0x 212 { WM8996_AIF2RX_MONO_CONFIGURATION, 0x0 },
210 { WM8996_AIF2TX_TEST, 0x1 }, 213 { WM8996_AIF2TX_TEST, 0x1 },
211 { WM8996_DSP1_TX_LEFT_VOLUME, 0xc0 }, 214 { WM8996_DSP1_TX_LEFT_VOLUME, 0xc0 },
212 { WM8996_DSP1_TX_RIGHT_VOLUME, 0xc0 }, 215 { WM8996_DSP1_TX_RIGHT_VOLUME, 0xc0 },
213 { WM8996_DSP1_RX_LEFT_VOLUME, 0xc0 }, 216 { WM8996_DSP1_RX_LEFT_VOLUME, 0xc0 },
214 { WM8996_DSP1_RX_RIGHT_VOLUME, 0xc0 }, 217 { WM8996_DSP1_RX_RIGHT_VOLUME, 0xc0 },
215 { WM8996_DSP1_TX_FILTERS, 0x2000 }, 218 { WM8996_DSP1_TX_FILTERS, 0x2000 },
216 { WM8996_DSP1_RX_FILTERS_1, 0x200 }, 219 { WM8996_DSP1_RX_FILTERS_1, 0x200 },
217 { WM8996_DSP1_RX_FILTERS_2, 0x10 }, 220 { WM8996_DSP1_RX_FILTERS_2, 0x10 },
218 { WM8996_DSP1_DRC_1, 0x98 }, 221 { WM8996_DSP1_DRC_1, 0x98 },
219 { WM8996_DSP1_DRC_2, 0x845 }, 222 { WM8996_DSP1_DRC_2, 0x845 },
220 { WM8996_DSP1_RX_EQ_GAINS_1, 0x6318 }, 223 { WM8996_DSP1_RX_EQ_GAINS_1, 0x6318 },
221 { WM8996_DSP1_RX_EQ_GAINS_2, 0x6300 }, 224 { WM8996_DSP1_RX_EQ_GAINS_2, 0x6300 },
222 { WM8996_DSP1_RX_EQ_BAND_1_A, 0xfca }, 225 { WM8996_DSP1_RX_EQ_BAND_1_A, 0xfca },
223 { WM8996_DSP1_RX_EQ_BAND_1_B, 0x400 }, 226 { WM8996_DSP1_RX_EQ_BAND_1_B, 0x400 },
224 { WM8996_DSP1_RX_EQ_BAND_1_PG, 0xd8 }, 227 { WM8996_DSP1_RX_EQ_BAND_1_PG, 0xd8 },
225 { WM8996_DSP1_RX_EQ_BAND_2_A, 0x1eb5 } 228 { WM8996_DSP1_RX_EQ_BAND_2_A, 0x1eb5 },
226 { WM8996_DSP1_RX_EQ_BAND_2_B, 0xf145 } 229 { WM8996_DSP1_RX_EQ_BAND_2_B, 0xf145 },
227 { WM8996_DSP1_RX_EQ_BAND_2_C, 0xb75 }, 230 { WM8996_DSP1_RX_EQ_BAND_2_C, 0xb75 },
228 { WM8996_DSP1_RX_EQ_BAND_2_PG, 0x1c5 } 231 { WM8996_DSP1_RX_EQ_BAND_2_PG, 0x1c5 },
229 { WM8996_DSP1_RX_EQ_BAND_3_A, 0x1c58 } 232 { WM8996_DSP1_RX_EQ_BAND_3_A, 0x1c58 },
230 { WM8996_DSP1_RX_EQ_BAND_3_B, 0xf373 } 233 { WM8996_DSP1_RX_EQ_BAND_3_B, 0xf373 },
231 { WM8996_DSP1_RX_EQ_BAND_3_C, 0xa54 }, 234 { WM8996_DSP1_RX_EQ_BAND_3_C, 0xa54 },
232 { WM8996_DSP1_RX_EQ_BAND_3_PG, 0x558 } 235 { WM8996_DSP1_RX_EQ_BAND_3_PG, 0x558 },
233 { WM8996_DSP1_RX_EQ_BAND_4_A, 0x168e } 236 { WM8996_DSP1_RX_EQ_BAND_4_A, 0x168e },
234 { WM8996_DSP1_RX_EQ_BAND_4_B, 0xf829 } 237 { WM8996_DSP1_RX_EQ_BAND_4_B, 0xf829 },
235 { WM8996_DSP1_RX_EQ_BAND_4_C, 0x7ad }, 238 { WM8996_DSP1_RX_EQ_BAND_4_C, 0x7ad },
236 { WM8996_DSP1_RX_EQ_BAND_4_PG, 0x1103 239 { WM8996_DSP1_RX_EQ_BAND_4_PG, 0x1103 },
237 { WM8996_DSP1_RX_EQ_BAND_5_A, 0x564 }, 240 { WM8996_DSP1_RX_EQ_BAND_5_A, 0x564 },
238 { WM8996_DSP1_RX_EQ_BAND_5_B, 0x559 }, 241 { WM8996_DSP1_RX_EQ_BAND_5_B, 0x559 },
239 { WM8996_DSP1_RX_EQ_BAND_5_PG, 0x4000 242 { WM8996_DSP1_RX_EQ_BAND_5_PG, 0x4000 },
240 { WM8996_DSP2_TX_LEFT_VOLUME, 0xc0 }, 243 { WM8996_DSP2_TX_LEFT_VOLUME, 0xc0 },
241 { WM8996_DSP2_TX_RIGHT_VOLUME, 0xc0 }, 244 { WM8996_DSP2_TX_RIGHT_VOLUME, 0xc0 },
242 { WM8996_DSP2_RX_LEFT_VOLUME, 0xc0 }, 245 { WM8996_DSP2_RX_LEFT_VOLUME, 0xc0 },
243 { WM8996_DSP2_RX_RIGHT_VOLUME, 0xc0 }, 246 { WM8996_DSP2_RX_RIGHT_VOLUME, 0xc0 },
244 { WM8996_DSP2_TX_FILTERS, 0x2000 }, 247 { WM8996_DSP2_TX_FILTERS, 0x2000 },
245 { WM8996_DSP2_RX_FILTERS_1, 0x200 }, 248 { WM8996_DSP2_RX_FILTERS_1, 0x200 },
246 { WM8996_DSP2_RX_FILTERS_2, 0x10 }, 249 { WM8996_DSP2_RX_FILTERS_2, 0x10 },
247 { WM8996_DSP2_DRC_1, 0x98 }, 250 { WM8996_DSP2_DRC_1, 0x98 },
248 { WM8996_DSP2_DRC_2, 0x845 }, 251 { WM8996_DSP2_DRC_2, 0x845 },
249 { WM8996_DSP2_RX_EQ_GAINS_1, 0x6318 }, 252 { WM8996_DSP2_RX_EQ_GAINS_1, 0x6318 },
250 { WM8996_DSP2_RX_EQ_GAINS_2, 0x6300 }, 253 { WM8996_DSP2_RX_EQ_GAINS_2, 0x6300 },
251 { WM8996_DSP2_RX_EQ_BAND_1_A, 0xfca }, 254 { WM8996_DSP2_RX_EQ_BAND_1_A, 0xfca },
252 { WM8996_DSP2_RX_EQ_BAND_1_B, 0x400 }, 255 { WM8996_DSP2_RX_EQ_BAND_1_B, 0x400 },
253 { WM8996_DSP2_RX_EQ_BAND_1_PG, 0xd8 }, 256 { WM8996_DSP2_RX_EQ_BAND_1_PG, 0xd8 },
254 { WM8996_DSP2_RX_EQ_BAND_2_A, 0x1eb5 } 257 { WM8996_DSP2_RX_EQ_BAND_2_A, 0x1eb5 },
255 { WM8996_DSP2_RX_EQ_BAND_2_B, 0xf145 } 258 { WM8996_DSP2_RX_EQ_BAND_2_B, 0xf145 },
256 { WM8996_DSP2_RX_EQ_BAND_2_C, 0xb75 }, 259 { WM8996_DSP2_RX_EQ_BAND_2_C, 0xb75 },
257 { WM8996_DSP2_RX_EQ_BAND_2_PG, 0x1c5 } 260 { WM8996_DSP2_RX_EQ_BAND_2_PG, 0x1c5 },
258 { WM8996_DSP2_RX_EQ_BAND_3_A, 0x1c58 } 261 { WM8996_DSP2_RX_EQ_BAND_3_A, 0x1c58 },
259 { WM8996_DSP2_RX_EQ_BAND_3_B, 0xf373 } 262 { WM8996_DSP2_RX_EQ_BAND_3_B, 0xf373 },
260 { WM8996_DSP2_RX_EQ_BAND_3_C, 0xa54 }, 263 { WM8996_DSP2_RX_EQ_BAND_3_C, 0xa54 },
261 { WM8996_DSP2_RX_EQ_BAND_3_PG, 0x558 } 264 { WM8996_DSP2_RX_EQ_BAND_3_PG, 0x558 },
262 { WM8996_DSP2_RX_EQ_BAND_4_A, 0x168e } 265 { WM8996_DSP2_RX_EQ_BAND_4_A, 0x168e },
263 { WM8996_DSP2_RX_EQ_BAND_4_B, 0xf829 } 266 { WM8996_DSP2_RX_EQ_BAND_4_B, 0xf829 },
264 { WM8996_DSP2_RX_EQ_BAND_4_C, 0x7ad }, 267 { WM8996_DSP2_RX_EQ_BAND_4_C, 0x7ad },
265 { WM8996_DSP2_RX_EQ_BAND_4_PG, 0x1103 268 { WM8996_DSP2_RX_EQ_BAND_4_PG, 0x1103 },
266 { WM8996_DSP2_RX_EQ_BAND_5_A, 0x564 }, 269 { WM8996_DSP2_RX_EQ_BAND_5_A, 0x564 },
267 { WM8996_DSP2_RX_EQ_BAND_5_B, 0x559 }, 270 { WM8996_DSP2_RX_EQ_BAND_5_B, 0x559 },
268 { WM8996_DSP2_RX_EQ_BAND_5_PG, 0x4000 271 { WM8996_DSP2_RX_EQ_BAND_5_PG, 0x4000 },
269 { WM8996_DAC1_MIXER_VOLUMES, 0x0 }, 272 { WM8996_DAC1_MIXER_VOLUMES, 0x0 },
270 { WM8996_DAC1_LEFT_MIXER_ROUTING, 0x0 273 { WM8996_DAC1_LEFT_MIXER_ROUTING, 0x0 },
271 { WM8996_DAC1_RIGHT_MIXER_ROUTING, 0x0 274 { WM8996_DAC1_RIGHT_MIXER_ROUTING, 0x0 },
272 { WM8996_DAC2_MIXER_VOLUMES, 0x0 }, 275 { WM8996_DAC2_MIXER_VOLUMES, 0x0 },
273 { WM8996_DAC2_LEFT_MIXER_ROUTING, 0x0 276 { WM8996_DAC2_LEFT_MIXER_ROUTING, 0x0 },
274 { WM8996_DAC2_RIGHT_MIXER_ROUTING, 0x0 277 { WM8996_DAC2_RIGHT_MIXER_ROUTING, 0x0 },
275 { WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 0 278 { WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 0x0 },
276 { WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, 279 { WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, 0x0 },
277 { WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 0 280 { WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 0x0 },
278 { WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, 281 { WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, 0x0 },
279 { WM8996_DSP_TX_MIXER_SELECT, 0x0 }, 282 { WM8996_DSP_TX_MIXER_SELECT, 0x0 },
280 { WM8996_DAC_SOFTMUTE, 0x0 }, 283 { WM8996_DAC_SOFTMUTE, 0x0 },
281 { WM8996_OVERSAMPLING, 0xd }, 284 { WM8996_OVERSAMPLING, 0xd },
282 { WM8996_SIDETONE, 0x1040 }, 285 { WM8996_SIDETONE, 0x1040 },
283 { WM8996_GPIO_1, 0xa101 }, 286 { WM8996_GPIO_1, 0xa101 },
284 { WM8996_GPIO_2, 0xa101 }, 287 { WM8996_GPIO_2, 0xa101 },
285 { WM8996_GPIO_3, 0xa101 }, 288 { WM8996_GPIO_3, 0xa101 },
286 { WM8996_GPIO_4, 0xa101 }, 289 { WM8996_GPIO_4, 0xa101 },
287 { WM8996_GPIO_5, 0xa101 }, 290 { WM8996_GPIO_5, 0xa101 },
288 { WM8996_PULL_CONTROL_1, 0x0 }, 291 { WM8996_PULL_CONTROL_1, 0x0 },
289 { WM8996_PULL_CONTROL_2, 0x140 }, 292 { WM8996_PULL_CONTROL_2, 0x140 },
290 { WM8996_INTERRUPT_STATUS_1_MASK, 0x1f 293 { WM8996_INTERRUPT_STATUS_1_MASK, 0x1f },
291 { WM8996_INTERRUPT_STATUS_2_MASK, 0x1e 294 { WM8996_INTERRUPT_STATUS_2_MASK, 0x1ecf },
292 { WM8996_LEFT_PDM_SPEAKER, 0x0 }, 295 { WM8996_LEFT_PDM_SPEAKER, 0x0 },
293 { WM8996_RIGHT_PDM_SPEAKER, 0x1 }, 296 { WM8996_RIGHT_PDM_SPEAKER, 0x1 },
294 { WM8996_PDM_SPEAKER_MUTE_SEQUENCE, 0x 297 { WM8996_PDM_SPEAKER_MUTE_SEQUENCE, 0x69 },
295 { WM8996_PDM_SPEAKER_VOLUME, 0x66 }, 298 { WM8996_PDM_SPEAKER_VOLUME, 0x66 },
296 }; 299 };
297 300
298 static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0 301 static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0);
299 static const DECLARE_TLV_DB_SCALE(sidetone_tlv 302 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
300 static const DECLARE_TLV_DB_SCALE(digital_tlv, 303 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
301 static const DECLARE_TLV_DB_SCALE(out_digital_ 304 static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0);
302 static const DECLARE_TLV_DB_SCALE(out_tlv, -90 305 static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0);
303 static const DECLARE_TLV_DB_SCALE(spk_tlv, -90 306 static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0);
304 static const DECLARE_TLV_DB_SCALE(eq_tlv, -120 307 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
305 static const DECLARE_TLV_DB_SCALE(threedstereo 308 static const DECLARE_TLV_DB_SCALE(threedstereo_tlv, -1600, 183, 1);
306 309
307 static const char *sidetone_hpf_text[] = { 310 static const char *sidetone_hpf_text[] = {
308 "2.9kHz", "1.5kHz", "735Hz", "403Hz", 311 "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz"
309 }; 312 };
310 313
311 static SOC_ENUM_SINGLE_DECL(sidetone_hpf, 314 static SOC_ENUM_SINGLE_DECL(sidetone_hpf,
312 WM8996_SIDETONE, 7 315 WM8996_SIDETONE, 7, sidetone_hpf_text);
313 316
314 static const char *hpf_mode_text[] = { 317 static const char *hpf_mode_text[] = {
315 "HiFi", "Custom", "Voice" 318 "HiFi", "Custom", "Voice"
316 }; 319 };
317 320
318 static SOC_ENUM_SINGLE_DECL(dsp1tx_hpf_mode, 321 static SOC_ENUM_SINGLE_DECL(dsp1tx_hpf_mode,
319 WM8996_DSP1_TX_FIL 322 WM8996_DSP1_TX_FILTERS, 3, hpf_mode_text);
320 323
321 static SOC_ENUM_SINGLE_DECL(dsp2tx_hpf_mode, 324 static SOC_ENUM_SINGLE_DECL(dsp2tx_hpf_mode,
322 WM8996_DSP2_TX_FIL 325 WM8996_DSP2_TX_FILTERS, 3, hpf_mode_text);
323 326
324 static const char *hpf_cutoff_text[] = { 327 static const char *hpf_cutoff_text[] = {
325 "50Hz", "75Hz", "100Hz", "150Hz", "200 328 "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
326 }; 329 };
327 330
328 static SOC_ENUM_SINGLE_DECL(dsp1tx_hpf_cutoff, 331 static SOC_ENUM_SINGLE_DECL(dsp1tx_hpf_cutoff,
329 WM8996_DSP1_TX_FIL 332 WM8996_DSP1_TX_FILTERS, 0, hpf_cutoff_text);
330 333
331 static SOC_ENUM_SINGLE_DECL(dsp2tx_hpf_cutoff, 334 static SOC_ENUM_SINGLE_DECL(dsp2tx_hpf_cutoff,
332 WM8996_DSP2_TX_FIL 335 WM8996_DSP2_TX_FILTERS, 0, hpf_cutoff_text);
333 336
334 static void wm8996_set_retune_mobile(struct sn !! 337 static void wm8996_set_retune_mobile(struct snd_soc_codec *codec, int block)
335 { 338 {
336 struct wm8996_priv *wm8996 = snd_soc_c !! 339 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
337 struct wm8996_pdata *pdata = &wm8996-> 340 struct wm8996_pdata *pdata = &wm8996->pdata;
338 int base, best, best_val, save, i, cfg 341 int base, best, best_val, save, i, cfg, iface;
339 342
340 if (!wm8996->num_retune_mobile_texts) 343 if (!wm8996->num_retune_mobile_texts)
341 return; 344 return;
342 345
343 switch (block) { 346 switch (block) {
344 case 0: 347 case 0:
345 base = WM8996_DSP1_RX_EQ_GAINS 348 base = WM8996_DSP1_RX_EQ_GAINS_1;
346 if (snd_soc_component_read(com !! 349 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) &
347 WM8996_DSP1RX_SRC) 350 WM8996_DSP1RX_SRC)
348 iface = 1; 351 iface = 1;
349 else 352 else
350 iface = 0; 353 iface = 0;
351 break; 354 break;
352 case 1: 355 case 1:
353 base = WM8996_DSP1_RX_EQ_GAINS 356 base = WM8996_DSP1_RX_EQ_GAINS_2;
354 if (snd_soc_component_read(com !! 357 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) &
355 WM8996_DSP2RX_SRC) 358 WM8996_DSP2RX_SRC)
356 iface = 1; 359 iface = 1;
357 else 360 else
358 iface = 0; 361 iface = 0;
359 break; 362 break;
360 default: 363 default:
361 return; 364 return;
362 } 365 }
363 366
364 /* Find the version of the currently s 367 /* Find the version of the currently selected configuration
365 * with the nearest sample rate. */ 368 * with the nearest sample rate. */
366 cfg = wm8996->retune_mobile_cfg[block] 369 cfg = wm8996->retune_mobile_cfg[block];
367 best = 0; 370 best = 0;
368 best_val = INT_MAX; 371 best_val = INT_MAX;
369 for (i = 0; i < pdata->num_retune_mobi 372 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
370 if (strcmp(pdata->retune_mobil 373 if (strcmp(pdata->retune_mobile_cfgs[i].name,
371 wm8996->retune_mobi 374 wm8996->retune_mobile_texts[cfg]) == 0 &&
372 abs(pdata->retune_mobile_c 375 abs(pdata->retune_mobile_cfgs[i].rate
373 - wm8996->rx_rate[ifac 376 - wm8996->rx_rate[iface]) < best_val) {
374 best = i; 377 best = i;
375 best_val = abs(pdata-> 378 best_val = abs(pdata->retune_mobile_cfgs[i].rate
376 - wm899 379 - wm8996->rx_rate[iface]);
377 } 380 }
378 } 381 }
379 382
380 dev_dbg(component->dev, "ReTune Mobile !! 383 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
381 block, 384 block,
382 pdata->retune_mobile_cfgs[best 385 pdata->retune_mobile_cfgs[best].name,
383 pdata->retune_mobile_cfgs[best 386 pdata->retune_mobile_cfgs[best].rate,
384 wm8996->rx_rate[iface]); 387 wm8996->rx_rate[iface]);
385 388
386 /* The EQ will be disabled while recon 389 /* The EQ will be disabled while reconfiguring it, remember the
387 * current configuration. 390 * current configuration.
388 */ 391 */
389 save = snd_soc_component_read(componen !! 392 save = snd_soc_read(codec, base);
390 save &= WM8996_DSP1RX_EQ_ENA; 393 save &= WM8996_DSP1RX_EQ_ENA;
391 394
392 for (i = 0; i < ARRAY_SIZE(pdata->retu 395 for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++)
393 snd_soc_component_update_bits( !! 396 snd_soc_update_bits(codec, base + i, 0xffff,
394 pdata->ret 397 pdata->retune_mobile_cfgs[best].regs[i]);
395 398
396 snd_soc_component_update_bits(componen !! 399 snd_soc_update_bits(codec, base, WM8996_DSP1RX_EQ_ENA, save);
397 } 400 }
398 401
399 /* Icky as hell but saves code duplication */ 402 /* Icky as hell but saves code duplication */
400 static int wm8996_get_retune_mobile_block(cons 403 static int wm8996_get_retune_mobile_block(const char *name)
401 { 404 {
402 if (strcmp(name, "DSP1 EQ Mode") == 0) 405 if (strcmp(name, "DSP1 EQ Mode") == 0)
403 return 0; 406 return 0;
404 if (strcmp(name, "DSP2 EQ Mode") == 0) 407 if (strcmp(name, "DSP2 EQ Mode") == 0)
405 return 1; 408 return 1;
406 return -EINVAL; 409 return -EINVAL;
407 } 410 }
408 411
409 static int wm8996_put_retune_mobile_enum(struc 412 static int wm8996_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
410 struc 413 struct snd_ctl_elem_value *ucontrol)
411 { 414 {
412 struct snd_soc_component *component = !! 415 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
413 struct wm8996_priv *wm8996 = snd_soc_c !! 416 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
414 struct wm8996_pdata *pdata = &wm8996-> 417 struct wm8996_pdata *pdata = &wm8996->pdata;
415 int block = wm8996_get_retune_mobile_b 418 int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
416 int value = ucontrol->value.enumerated !! 419 int value = ucontrol->value.integer.value[0];
417 420
418 if (block < 0) 421 if (block < 0)
419 return block; 422 return block;
420 423
421 if (value >= pdata->num_retune_mobile_ 424 if (value >= pdata->num_retune_mobile_cfgs)
422 return -EINVAL; 425 return -EINVAL;
423 426
424 wm8996->retune_mobile_cfg[block] = val 427 wm8996->retune_mobile_cfg[block] = value;
425 428
426 wm8996_set_retune_mobile(component, bl !! 429 wm8996_set_retune_mobile(codec, block);
427 430
428 return 0; 431 return 0;
429 } 432 }
430 433
431 static int wm8996_get_retune_mobile_enum(struc 434 static int wm8996_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
432 struc 435 struct snd_ctl_elem_value *ucontrol)
433 { 436 {
434 struct snd_soc_component *component = !! 437 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
435 struct wm8996_priv *wm8996 = snd_soc_c !! 438 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
436 int block = wm8996_get_retune_mobile_b 439 int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
437 440
438 if (block < 0) 441 if (block < 0)
439 return block; 442 return block;
440 ucontrol->value.enumerated.item[0] = w 443 ucontrol->value.enumerated.item[0] = wm8996->retune_mobile_cfg[block];
441 444
442 return 0; 445 return 0;
443 } 446 }
444 447
445 static const struct snd_kcontrol_new wm8996_sn 448 static const struct snd_kcontrol_new wm8996_snd_controls[] = {
446 SOC_DOUBLE_R_TLV("Capture Volume", WM8996_LEFT 449 SOC_DOUBLE_R_TLV("Capture Volume", WM8996_LEFT_LINE_INPUT_VOLUME,
447 WM8996_RIGHT_LINE_INPUT_VOLUM 450 WM8996_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv),
448 SOC_DOUBLE_R("Capture ZC Switch", WM8996_LEFT_ 451 SOC_DOUBLE_R("Capture ZC Switch", WM8996_LEFT_LINE_INPUT_VOLUME,
449 WM8996_RIGHT_LINE_INPUT_VOLUME, 5 452 WM8996_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0),
450 453
451 SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8996_ 454 SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8996_DAC1_MIXER_VOLUMES,
452 0, 5, 24, 0, sidetone_tlv), 455 0, 5, 24, 0, sidetone_tlv),
453 SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8996_ 456 SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8996_DAC2_MIXER_VOLUMES,
454 0, 5, 24, 0, sidetone_tlv), 457 0, 5, 24, 0, sidetone_tlv),
455 SOC_SINGLE("Sidetone LPF Switch", WM8996_SIDET 458 SOC_SINGLE("Sidetone LPF Switch", WM8996_SIDETONE, 12, 1, 0),
456 SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf) 459 SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf),
457 SOC_SINGLE("Sidetone HPF Switch", WM8996_SIDET 460 SOC_SINGLE("Sidetone HPF Switch", WM8996_SIDETONE, 6, 1, 0),
458 461
459 SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8996 462 SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8996_DSP1_TX_LEFT_VOLUME,
460 WM8996_DSP1_TX_RIGHT_VOLUME, 463 WM8996_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
461 SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8996 464 SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8996_DSP2_TX_LEFT_VOLUME,
462 WM8996_DSP2_TX_RIGHT_VOLUME, 465 WM8996_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
463 466
464 SOC_SINGLE("DSP1 Capture Notch Filter Switch", 467 SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8996_DSP1_TX_FILTERS,
465 13, 1, 0), 468 13, 1, 0),
466 SOC_DOUBLE("DSP1 Capture HPF Switch", WM8996_D 469 SOC_DOUBLE("DSP1 Capture HPF Switch", WM8996_DSP1_TX_FILTERS, 12, 11, 1, 0),
467 SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_m 470 SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode),
468 SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf 471 SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff),
469 472
470 SOC_SINGLE("DSP2 Capture Notch Filter Switch", 473 SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8996_DSP2_TX_FILTERS,
471 13, 1, 0), 474 13, 1, 0),
472 SOC_DOUBLE("DSP2 Capture HPF Switch", WM8996_D 475 SOC_DOUBLE("DSP2 Capture HPF Switch", WM8996_DSP2_TX_FILTERS, 12, 11, 1, 0),
473 SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_m 476 SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode),
474 SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf 477 SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff),
475 478
476 SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM899 479 SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8996_DSP1_RX_LEFT_VOLUME,
477 WM8996_DSP1_RX_RIGHT_VOLUME, 480 WM8996_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
478 SOC_SINGLE("DSP1 Playback Switch", WM8996_DSP1 481 SOC_SINGLE("DSP1 Playback Switch", WM8996_DSP1_RX_FILTERS_1, 9, 1, 1),
479 482
480 SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM899 483 SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8996_DSP2_RX_LEFT_VOLUME,
481 WM8996_DSP2_RX_RIGHT_VOLUME, 484 WM8996_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
482 SOC_SINGLE("DSP2 Playback Switch", WM8996_DSP2 485 SOC_SINGLE("DSP2 Playback Switch", WM8996_DSP2_RX_FILTERS_1, 9, 1, 1),
483 486
484 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8996_DAC1_LE 487 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8996_DAC1_LEFT_VOLUME,
485 WM8996_DAC1_RIGHT_VOLUME, 1, 488 WM8996_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
486 SOC_DOUBLE_R("DAC1 Switch", WM8996_DAC1_LEFT_V 489 SOC_DOUBLE_R("DAC1 Switch", WM8996_DAC1_LEFT_VOLUME,
487 WM8996_DAC1_RIGHT_VOLUME, 9, 1, 1 490 WM8996_DAC1_RIGHT_VOLUME, 9, 1, 1),
488 491
489 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8996_DAC2_LE 492 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8996_DAC2_LEFT_VOLUME,
490 WM8996_DAC2_RIGHT_VOLUME, 1, 493 WM8996_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
491 SOC_DOUBLE_R("DAC2 Switch", WM8996_DAC2_LEFT_V 494 SOC_DOUBLE_R("DAC2 Switch", WM8996_DAC2_LEFT_VOLUME,
492 WM8996_DAC2_RIGHT_VOLUME, 9, 1, 1 495 WM8996_DAC2_RIGHT_VOLUME, 9, 1, 1),
493 496
494 SOC_SINGLE("Speaker High Performance Switch", 497 SOC_SINGLE("Speaker High Performance Switch", WM8996_OVERSAMPLING, 3, 1, 0),
495 SOC_SINGLE("DMIC High Performance Switch", WM8 498 SOC_SINGLE("DMIC High Performance Switch", WM8996_OVERSAMPLING, 2, 1, 0),
496 SOC_SINGLE("ADC High Performance Switch", WM89 499 SOC_SINGLE("ADC High Performance Switch", WM8996_OVERSAMPLING, 1, 1, 0),
497 SOC_SINGLE("DAC High Performance Switch", WM89 500 SOC_SINGLE("DAC High Performance Switch", WM8996_OVERSAMPLING, 0, 1, 0),
498 501
499 SOC_SINGLE("DAC Soft Mute Switch", WM8996_DAC_ 502 SOC_SINGLE("DAC Soft Mute Switch", WM8996_DAC_SOFTMUTE, 1, 1, 0),
500 SOC_SINGLE("DAC Slow Soft Mute Switch", WM8996 503 SOC_SINGLE("DAC Slow Soft Mute Switch", WM8996_DAC_SOFTMUTE, 0, 1, 0),
501 504
502 SOC_SINGLE("DSP1 3D Stereo Switch", WM8996_DSP 505 SOC_SINGLE("DSP1 3D Stereo Switch", WM8996_DSP1_RX_FILTERS_2, 8, 1, 0),
503 SOC_SINGLE("DSP2 3D Stereo Switch", WM8996_DSP 506 SOC_SINGLE("DSP2 3D Stereo Switch", WM8996_DSP2_RX_FILTERS_2, 8, 1, 0),
504 507
505 SOC_SINGLE_TLV("DSP1 3D Stereo Volume", WM8996 508 SOC_SINGLE_TLV("DSP1 3D Stereo Volume", WM8996_DSP1_RX_FILTERS_2, 10, 15,
506 0, threedstereo_tlv), 509 0, threedstereo_tlv),
507 SOC_SINGLE_TLV("DSP2 3D Stereo Volume", WM8996 510 SOC_SINGLE_TLV("DSP2 3D Stereo Volume", WM8996_DSP2_RX_FILTERS_2, 10, 15,
508 0, threedstereo_tlv), 511 0, threedstereo_tlv),
509 512
510 SOC_DOUBLE_TLV("Digital Output 1 Volume", WM89 513 SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8996_DAC1_HPOUT1_VOLUME, 0, 4,
511 8, 0, out_digital_tlv), 514 8, 0, out_digital_tlv),
512 SOC_DOUBLE_TLV("Digital Output 2 Volume", WM89 515 SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8996_DAC2_HPOUT2_VOLUME, 0, 4,
513 8, 0, out_digital_tlv), 516 8, 0, out_digital_tlv),
514 517
515 SOC_DOUBLE_R_TLV("Output 1 Volume", WM8996_OUT 518 SOC_DOUBLE_R_TLV("Output 1 Volume", WM8996_OUTPUT1_LEFT_VOLUME,
516 WM8996_OUTPUT1_RIGHT_VOLUME, 519 WM8996_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv),
517 SOC_DOUBLE_R("Output 1 ZC Switch", WM8996_OUT 520 SOC_DOUBLE_R("Output 1 ZC Switch", WM8996_OUTPUT1_LEFT_VOLUME,
518 WM8996_OUTPUT1_RIGHT_VOLUME, 7, 1 521 WM8996_OUTPUT1_RIGHT_VOLUME, 7, 1, 0),
519 522
520 SOC_DOUBLE_R_TLV("Output 2 Volume", WM8996_OUT 523 SOC_DOUBLE_R_TLV("Output 2 Volume", WM8996_OUTPUT2_LEFT_VOLUME,
521 WM8996_OUTPUT2_RIGHT_VOLUME, 524 WM8996_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv),
522 SOC_DOUBLE_R("Output 2 ZC Switch", WM8996_OUT 525 SOC_DOUBLE_R("Output 2 ZC Switch", WM8996_OUTPUT2_LEFT_VOLUME,
523 WM8996_OUTPUT2_RIGHT_VOLUME, 7, 1 526 WM8996_OUTPUT2_RIGHT_VOLUME, 7, 1, 0),
524 527
525 SOC_DOUBLE_TLV("Speaker Volume", WM8996_PDM_SP 528 SOC_DOUBLE_TLV("Speaker Volume", WM8996_PDM_SPEAKER_VOLUME, 0, 4, 8, 0,
526 spk_tlv), 529 spk_tlv),
527 SOC_DOUBLE_R("Speaker Switch", WM8996_LEFT_PDM 530 SOC_DOUBLE_R("Speaker Switch", WM8996_LEFT_PDM_SPEAKER,
528 WM8996_RIGHT_PDM_SPEAKER, 3, 1, 1 531 WM8996_RIGHT_PDM_SPEAKER, 3, 1, 1),
529 SOC_DOUBLE_R("Speaker ZC Switch", WM8996_LEFT_ 532 SOC_DOUBLE_R("Speaker ZC Switch", WM8996_LEFT_PDM_SPEAKER,
530 WM8996_RIGHT_PDM_SPEAKER, 2, 1, 0 533 WM8996_RIGHT_PDM_SPEAKER, 2, 1, 0),
531 534
532 SOC_SINGLE("DSP1 EQ Switch", WM8996_DSP1_RX_EQ 535 SOC_SINGLE("DSP1 EQ Switch", WM8996_DSP1_RX_EQ_GAINS_1, 0, 1, 0),
533 SOC_SINGLE("DSP2 EQ Switch", WM8996_DSP2_RX_EQ 536 SOC_SINGLE("DSP2 EQ Switch", WM8996_DSP2_RX_EQ_GAINS_1, 0, 1, 0),
534 537
535 SOC_SINGLE("DSP1 DRC TXL Switch", WM8996_DSP1_ 538 SOC_SINGLE("DSP1 DRC TXL Switch", WM8996_DSP1_DRC_1, 0, 1, 0),
536 SOC_SINGLE("DSP1 DRC TXR Switch", WM8996_DSP1_ 539 SOC_SINGLE("DSP1 DRC TXR Switch", WM8996_DSP1_DRC_1, 1, 1, 0),
537 SOC_SINGLE("DSP1 DRC RX Switch", WM8996_DSP1_D 540 SOC_SINGLE("DSP1 DRC RX Switch", WM8996_DSP1_DRC_1, 2, 1, 0),
538 SND_SOC_BYTES_MASK("DSP1 DRC", WM8996_DSP1_DRC 541 SND_SOC_BYTES_MASK("DSP1 DRC", WM8996_DSP1_DRC_1, 5,
539 WM8996_DSP1RX_DRC_ENA | WM8 542 WM8996_DSP1RX_DRC_ENA | WM8996_DSP1TXL_DRC_ENA |
540 WM8996_DSP1TXR_DRC_ENA), 543 WM8996_DSP1TXR_DRC_ENA),
541 544
542 SOC_SINGLE("DSP2 DRC TXL Switch", WM8996_DSP2_ 545 SOC_SINGLE("DSP2 DRC TXL Switch", WM8996_DSP2_DRC_1, 0, 1, 0),
543 SOC_SINGLE("DSP2 DRC TXR Switch", WM8996_DSP2_ 546 SOC_SINGLE("DSP2 DRC TXR Switch", WM8996_DSP2_DRC_1, 1, 1, 0),
544 SOC_SINGLE("DSP2 DRC RX Switch", WM8996_DSP2_D 547 SOC_SINGLE("DSP2 DRC RX Switch", WM8996_DSP2_DRC_1, 2, 1, 0),
545 SND_SOC_BYTES_MASK("DSP2 DRC", WM8996_DSP2_DRC 548 SND_SOC_BYTES_MASK("DSP2 DRC", WM8996_DSP2_DRC_1, 5,
546 WM8996_DSP2RX_DRC_ENA | WM8 549 WM8996_DSP2RX_DRC_ENA | WM8996_DSP2TXL_DRC_ENA |
547 WM8996_DSP2TXR_DRC_ENA), 550 WM8996_DSP2TXR_DRC_ENA),
548 }; 551 };
549 552
550 static const struct snd_kcontrol_new wm8996_eq 553 static const struct snd_kcontrol_new wm8996_eq_controls[] = {
551 SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8996_DSP 554 SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 11, 31, 0,
552 eq_tlv), 555 eq_tlv),
553 SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8996_DSP 556 SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 6, 31, 0,
554 eq_tlv), 557 eq_tlv),
555 SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8996_DSP 558 SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 1, 31, 0,
556 eq_tlv), 559 eq_tlv),
557 SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8996_DSP 560 SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 11, 31, 0,
558 eq_tlv), 561 eq_tlv),
559 SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8996_DSP 562 SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 6, 31, 0,
560 eq_tlv), 563 eq_tlv),
561 564
562 SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8996_DSP 565 SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 11, 31, 0,
563 eq_tlv), 566 eq_tlv),
564 SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8996_DSP 567 SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 6, 31, 0,
565 eq_tlv), 568 eq_tlv),
566 SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8996_DSP 569 SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 1, 31, 0,
567 eq_tlv), 570 eq_tlv),
568 SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8996_DSP 571 SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 11, 31, 0,
569 eq_tlv), 572 eq_tlv),
570 SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8996_DSP 573 SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 6, 31, 0,
571 eq_tlv), 574 eq_tlv),
572 }; 575 };
573 576
574 static void wm8996_bg_enable(struct snd_soc_co !! 577 static void wm8996_bg_enable(struct snd_soc_codec *codec)
575 { 578 {
576 struct wm8996_priv *wm8996 = snd_soc_c !! 579 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
577 580
578 wm8996->bg_ena++; 581 wm8996->bg_ena++;
579 if (wm8996->bg_ena == 1) { 582 if (wm8996->bg_ena == 1) {
580 snd_soc_component_update_bits( !! 583 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1,
581 WM8996_BG_ 584 WM8996_BG_ENA, WM8996_BG_ENA);
582 msleep(2); 585 msleep(2);
583 } 586 }
584 } 587 }
585 588
586 static void wm8996_bg_disable(struct snd_soc_c !! 589 static void wm8996_bg_disable(struct snd_soc_codec *codec)
587 { 590 {
588 struct wm8996_priv *wm8996 = snd_soc_c !! 591 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
589 592
590 wm8996->bg_ena--; 593 wm8996->bg_ena--;
591 if (!wm8996->bg_ena) 594 if (!wm8996->bg_ena)
592 snd_soc_component_update_bits( !! 595 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1,
593 WM8996_BG_ 596 WM8996_BG_ENA, 0);
594 } 597 }
595 598
596 static int bg_event(struct snd_soc_dapm_widget 599 static int bg_event(struct snd_soc_dapm_widget *w,
597 struct snd_kcontrol *kcont 600 struct snd_kcontrol *kcontrol, int event)
598 { 601 {
599 struct snd_soc_component *component = !! 602 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
600 int ret = 0; 603 int ret = 0;
601 604
602 switch (event) { 605 switch (event) {
603 case SND_SOC_DAPM_PRE_PMU: 606 case SND_SOC_DAPM_PRE_PMU:
604 wm8996_bg_enable(component); !! 607 wm8996_bg_enable(codec);
605 break; 608 break;
606 case SND_SOC_DAPM_POST_PMD: 609 case SND_SOC_DAPM_POST_PMD:
607 wm8996_bg_disable(component); !! 610 wm8996_bg_disable(codec);
608 break; 611 break;
609 default: 612 default:
610 WARN(1, "Invalid event %d\n", 613 WARN(1, "Invalid event %d\n", event);
611 ret = -EINVAL; 614 ret = -EINVAL;
612 } 615 }
613 616
614 return ret; 617 return ret;
615 } 618 }
616 619
617 static int cp_event(struct snd_soc_dapm_widget 620 static int cp_event(struct snd_soc_dapm_widget *w,
618 struct snd_kcontrol *kcont 621 struct snd_kcontrol *kcontrol, int event)
619 { 622 {
620 switch (event) { 623 switch (event) {
621 case SND_SOC_DAPM_POST_PMU: 624 case SND_SOC_DAPM_POST_PMU:
622 msleep(5); 625 msleep(5);
623 break; 626 break;
624 default: 627 default:
625 WARN(1, "Invalid event %d\n", 628 WARN(1, "Invalid event %d\n", event);
626 } 629 }
627 630
628 return 0; 631 return 0;
629 } 632 }
630 633
631 static int rmv_short_event(struct snd_soc_dapm 634 static int rmv_short_event(struct snd_soc_dapm_widget *w,
632 struct snd_kcontrol 635 struct snd_kcontrol *kcontrol, int event)
633 { 636 {
634 struct snd_soc_component *component = !! 637 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
635 struct wm8996_priv *wm8996 = snd_soc_c !! 638 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
636 639
637 /* Record which outputs we enabled */ 640 /* Record which outputs we enabled */
638 switch (event) { 641 switch (event) {
639 case SND_SOC_DAPM_PRE_PMD: 642 case SND_SOC_DAPM_PRE_PMD:
640 wm8996->hpout_pending &= ~w->s 643 wm8996->hpout_pending &= ~w->shift;
641 break; 644 break;
642 case SND_SOC_DAPM_PRE_PMU: 645 case SND_SOC_DAPM_PRE_PMU:
643 wm8996->hpout_pending |= w->sh 646 wm8996->hpout_pending |= w->shift;
644 break; 647 break;
645 default: 648 default:
646 WARN(1, "Invalid event %d\n", 649 WARN(1, "Invalid event %d\n", event);
647 return -EINVAL; 650 return -EINVAL;
648 } 651 }
649 652
650 return 0; 653 return 0;
651 } 654 }
652 655
653 static void wait_for_dc_servo(struct snd_soc_c !! 656 static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask)
654 { 657 {
655 struct i2c_client *i2c = to_i2c_client !! 658 struct i2c_client *i2c = to_i2c_client(codec->dev);
656 struct wm8996_priv *wm8996 = snd_soc_c !! 659 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
657 int ret; 660 int ret;
658 unsigned long time_left = 200; !! 661 unsigned long timeout = 200;
659 662
660 snd_soc_component_write(component, WM8 !! 663 snd_soc_write(codec, WM8996_DC_SERVO_2, mask);
661 664
662 /* Use the interrupt if possible */ 665 /* Use the interrupt if possible */
663 do { 666 do {
664 if (i2c->irq) { 667 if (i2c->irq) {
665 time_left = wait_for_c !! 668 timeout = wait_for_completion_timeout(&wm8996->dcs_done,
666 !! 669 msecs_to_jiffies(200));
667 if (time_left == 0) !! 670 if (timeout == 0)
668 dev_err(compon !! 671 dev_err(codec->dev, "DC servo timed out\n");
669 672
670 } else { 673 } else {
671 msleep(1); 674 msleep(1);
672 time_left--; !! 675 timeout--;
673 } 676 }
674 677
675 ret = snd_soc_component_read(c !! 678 ret = snd_soc_read(codec, WM8996_DC_SERVO_2);
676 dev_dbg(component->dev, "DC se !! 679 dev_dbg(codec->dev, "DC servo state: %x\n", ret);
677 } while (time_left && ret & mask); !! 680 } while (timeout && ret & mask);
678 681
679 if (time_left == 0) !! 682 if (timeout == 0)
680 dev_err(component->dev, "DC se !! 683 dev_err(codec->dev, "DC servo timed out for %x\n", mask);
681 else 684 else
682 dev_dbg(component->dev, "DC se !! 685 dev_dbg(codec->dev, "DC servo complete for %x\n", mask);
683 } 686 }
684 687
685 static void wm8996_seq_notifier(struct snd_soc !! 688 static void wm8996_seq_notifier(struct snd_soc_dapm_context *dapm,
686 enum snd_soc_d 689 enum snd_soc_dapm_type event, int subseq)
687 { 690 {
688 struct wm8996_priv *wm8996 = snd_soc_c !! 691 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(dapm);
>> 692 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
689 u16 val, mask; 693 u16 val, mask;
690 694
691 /* Complete any pending DC servo start 695 /* Complete any pending DC servo starts */
692 if (wm8996->dcs_pending) { 696 if (wm8996->dcs_pending) {
693 dev_dbg(component->dev, "Start !! 697 dev_dbg(codec->dev, "Starting DC servo for %x\n",
694 wm8996->dcs_pending); 698 wm8996->dcs_pending);
695 699
696 /* Trigger a startup sequence 700 /* Trigger a startup sequence */
697 wait_for_dc_servo(component, w !! 701 wait_for_dc_servo(codec, wm8996->dcs_pending
698 << WM 702 << WM8996_DCS_TRIG_STARTUP_0_SHIFT);
699 703
700 wm8996->dcs_pending = 0; 704 wm8996->dcs_pending = 0;
701 } 705 }
702 706
703 if (wm8996->hpout_pending != wm8996->h 707 if (wm8996->hpout_pending != wm8996->hpout_ena) {
704 dev_dbg(component->dev, "Apply !! 708 dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n",
705 wm8996->hpout_ena, wm8 709 wm8996->hpout_ena, wm8996->hpout_pending);
706 710
707 val = 0; 711 val = 0;
708 mask = 0; 712 mask = 0;
709 if (wm8996->hpout_pending & HP 713 if (wm8996->hpout_pending & HPOUT1L) {
710 val |= WM8996_HPOUT1L_ 714 val |= WM8996_HPOUT1L_RMV_SHORT | WM8996_HPOUT1L_OUTP;
711 mask |= WM8996_HPOUT1L 715 mask |= WM8996_HPOUT1L_RMV_SHORT | WM8996_HPOUT1L_OUTP;
712 } else { 716 } else {
713 mask |= WM8996_HPOUT1L 717 mask |= WM8996_HPOUT1L_RMV_SHORT |
714 WM8996_HPOUT1L 718 WM8996_HPOUT1L_OUTP |
715 WM8996_HPOUT1L 719 WM8996_HPOUT1L_DLY;
716 } 720 }
717 721
718 if (wm8996->hpout_pending & HP 722 if (wm8996->hpout_pending & HPOUT1R) {
719 val |= WM8996_HPOUT1R_ 723 val |= WM8996_HPOUT1R_RMV_SHORT | WM8996_HPOUT1R_OUTP;
720 mask |= WM8996_HPOUT1R 724 mask |= WM8996_HPOUT1R_RMV_SHORT | WM8996_HPOUT1R_OUTP;
721 } else { 725 } else {
722 mask |= WM8996_HPOUT1R 726 mask |= WM8996_HPOUT1R_RMV_SHORT |
723 WM8996_HPOUT1R 727 WM8996_HPOUT1R_OUTP |
724 WM8996_HPOUT1R 728 WM8996_HPOUT1R_DLY;
725 } 729 }
726 730
727 snd_soc_component_update_bits( !! 731 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1, mask, val);
728 732
729 val = 0; 733 val = 0;
730 mask = 0; 734 mask = 0;
731 if (wm8996->hpout_pending & HP 735 if (wm8996->hpout_pending & HPOUT2L) {
732 val |= WM8996_HPOUT2L_ 736 val |= WM8996_HPOUT2L_RMV_SHORT | WM8996_HPOUT2L_OUTP;
733 mask |= WM8996_HPOUT2L 737 mask |= WM8996_HPOUT2L_RMV_SHORT | WM8996_HPOUT2L_OUTP;
734 } else { 738 } else {
735 mask |= WM8996_HPOUT2L 739 mask |= WM8996_HPOUT2L_RMV_SHORT |
736 WM8996_HPOUT2L 740 WM8996_HPOUT2L_OUTP |
737 WM8996_HPOUT2L 741 WM8996_HPOUT2L_DLY;
738 } 742 }
739 743
740 if (wm8996->hpout_pending & HP 744 if (wm8996->hpout_pending & HPOUT2R) {
741 val |= WM8996_HPOUT2R_ 745 val |= WM8996_HPOUT2R_RMV_SHORT | WM8996_HPOUT2R_OUTP;
742 mask |= WM8996_HPOUT2R 746 mask |= WM8996_HPOUT2R_RMV_SHORT | WM8996_HPOUT2R_OUTP;
743 } else { 747 } else {
744 mask |= WM8996_HPOUT2R 748 mask |= WM8996_HPOUT2R_RMV_SHORT |
745 WM8996_HPOUT2R 749 WM8996_HPOUT2R_OUTP |
746 WM8996_HPOUT2R 750 WM8996_HPOUT2R_DLY;
747 } 751 }
748 752
749 snd_soc_component_update_bits( !! 753 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_2, mask, val);
750 754
751 wm8996->hpout_ena = wm8996->hp 755 wm8996->hpout_ena = wm8996->hpout_pending;
752 } 756 }
753 } 757 }
754 758
755 static int dcs_start(struct snd_soc_dapm_widge 759 static int dcs_start(struct snd_soc_dapm_widget *w,
756 struct snd_kcontrol *kcon 760 struct snd_kcontrol *kcontrol, int event)
757 { 761 {
758 struct snd_soc_component *component = !! 762 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
759 struct wm8996_priv *wm8996 = snd_soc_c !! 763 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
760 764
761 switch (event) { 765 switch (event) {
762 case SND_SOC_DAPM_POST_PMU: 766 case SND_SOC_DAPM_POST_PMU:
763 wm8996->dcs_pending |= 1 << w- 767 wm8996->dcs_pending |= 1 << w->shift;
764 break; 768 break;
765 default: 769 default:
766 WARN(1, "Invalid event %d\n", 770 WARN(1, "Invalid event %d\n", event);
767 return -EINVAL; 771 return -EINVAL;
768 } 772 }
769 773
770 return 0; 774 return 0;
771 } 775 }
772 776
773 static const char *sidetone_text[] = { 777 static const char *sidetone_text[] = {
774 "IN1", "IN2", 778 "IN1", "IN2",
775 }; 779 };
776 780
777 static SOC_ENUM_SINGLE_DECL(left_sidetone_enum 781 static SOC_ENUM_SINGLE_DECL(left_sidetone_enum,
778 WM8996_SIDETONE, 0 782 WM8996_SIDETONE, 0, sidetone_text);
779 783
780 static const struct snd_kcontrol_new left_side 784 static const struct snd_kcontrol_new left_sidetone =
781 SOC_DAPM_ENUM("Left Sidetone", left_si 785 SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum);
782 786
783 static SOC_ENUM_SINGLE_DECL(right_sidetone_enu 787 static SOC_ENUM_SINGLE_DECL(right_sidetone_enum,
784 WM8996_SIDETONE, 1 788 WM8996_SIDETONE, 1, sidetone_text);
785 789
786 static const struct snd_kcontrol_new right_sid 790 static const struct snd_kcontrol_new right_sidetone =
787 SOC_DAPM_ENUM("Right Sidetone", right_ 791 SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum);
788 792
789 static const char *spk_text[] = { 793 static const char *spk_text[] = {
790 "DAC1L", "DAC1R", "DAC2L", "DAC2R" 794 "DAC1L", "DAC1R", "DAC2L", "DAC2R"
791 }; 795 };
792 796
793 static SOC_ENUM_SINGLE_DECL(spkl_enum, 797 static SOC_ENUM_SINGLE_DECL(spkl_enum,
794 WM8996_LEFT_PDM_SP 798 WM8996_LEFT_PDM_SPEAKER, 0, spk_text);
795 799
796 static const struct snd_kcontrol_new spkl_mux 800 static const struct snd_kcontrol_new spkl_mux =
797 SOC_DAPM_ENUM("SPKL", spkl_enum); 801 SOC_DAPM_ENUM("SPKL", spkl_enum);
798 802
799 static SOC_ENUM_SINGLE_DECL(spkr_enum, 803 static SOC_ENUM_SINGLE_DECL(spkr_enum,
800 WM8996_RIGHT_PDM_S 804 WM8996_RIGHT_PDM_SPEAKER, 0, spk_text);
801 805
802 static const struct snd_kcontrol_new spkr_mux 806 static const struct snd_kcontrol_new spkr_mux =
803 SOC_DAPM_ENUM("SPKR", spkr_enum); 807 SOC_DAPM_ENUM("SPKR", spkr_enum);
804 808
805 static const char *dsp1rx_text[] = { 809 static const char *dsp1rx_text[] = {
806 "AIF1", "AIF2" 810 "AIF1", "AIF2"
807 }; 811 };
808 812
809 static SOC_ENUM_SINGLE_DECL(dsp1rx_enum, 813 static SOC_ENUM_SINGLE_DECL(dsp1rx_enum,
810 WM8996_POWER_MANAG 814 WM8996_POWER_MANAGEMENT_8, 0, dsp1rx_text);
811 815
812 static const struct snd_kcontrol_new dsp1rx = 816 static const struct snd_kcontrol_new dsp1rx =
813 SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum); 817 SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum);
814 818
815 static const char *dsp2rx_text[] = { 819 static const char *dsp2rx_text[] = {
816 "AIF2", "AIF1" 820 "AIF2", "AIF1"
817 }; 821 };
818 822
819 static SOC_ENUM_SINGLE_DECL(dsp2rx_enum, 823 static SOC_ENUM_SINGLE_DECL(dsp2rx_enum,
820 WM8996_POWER_MANAG 824 WM8996_POWER_MANAGEMENT_8, 4, dsp2rx_text);
821 825
822 static const struct snd_kcontrol_new dsp2rx = 826 static const struct snd_kcontrol_new dsp2rx =
823 SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum); 827 SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum);
824 828
825 static const char *aif2tx_text[] = { 829 static const char *aif2tx_text[] = {
826 "DSP2", "DSP1", "AIF1" 830 "DSP2", "DSP1", "AIF1"
827 }; 831 };
828 832
829 static SOC_ENUM_SINGLE_DECL(aif2tx_enum, 833 static SOC_ENUM_SINGLE_DECL(aif2tx_enum,
830 WM8996_POWER_MANAG 834 WM8996_POWER_MANAGEMENT_8, 6, aif2tx_text);
831 835
832 static const struct snd_kcontrol_new aif2tx = 836 static const struct snd_kcontrol_new aif2tx =
833 SOC_DAPM_ENUM("AIF2TX", aif2tx_enum); 837 SOC_DAPM_ENUM("AIF2TX", aif2tx_enum);
834 838
835 static const char *inmux_text[] = { 839 static const char *inmux_text[] = {
836 "ADC", "DMIC1", "DMIC2" 840 "ADC", "DMIC1", "DMIC2"
837 }; 841 };
838 842
839 static SOC_ENUM_SINGLE_DECL(in1_enum, 843 static SOC_ENUM_SINGLE_DECL(in1_enum,
840 WM8996_POWER_MANAG 844 WM8996_POWER_MANAGEMENT_7, 0, inmux_text);
841 845
842 static const struct snd_kcontrol_new in1_mux = 846 static const struct snd_kcontrol_new in1_mux =
843 SOC_DAPM_ENUM("IN1 Mux", in1_enum); 847 SOC_DAPM_ENUM("IN1 Mux", in1_enum);
844 848
845 static SOC_ENUM_SINGLE_DECL(in2_enum, 849 static SOC_ENUM_SINGLE_DECL(in2_enum,
846 WM8996_POWER_MANAG 850 WM8996_POWER_MANAGEMENT_7, 4, inmux_text);
847 851
848 static const struct snd_kcontrol_new in2_mux = 852 static const struct snd_kcontrol_new in2_mux =
849 SOC_DAPM_ENUM("IN2 Mux", in2_enum); 853 SOC_DAPM_ENUM("IN2 Mux", in2_enum);
850 854
851 static const struct snd_kcontrol_new dac2r_mix 855 static const struct snd_kcontrol_new dac2r_mix[] = {
852 SOC_DAPM_SINGLE("Right Sidetone Switch", WM899 856 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
853 5, 1, 0), 857 5, 1, 0),
854 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996 858 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
855 4, 1, 0), 859 4, 1, 0),
856 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_RIG 860 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0),
857 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_RIG 861 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0),
858 }; 862 };
859 863
860 static const struct snd_kcontrol_new dac2l_mix 864 static const struct snd_kcontrol_new dac2l_mix[] = {
861 SOC_DAPM_SINGLE("Right Sidetone Switch", WM899 865 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
862 5, 1, 0), 866 5, 1, 0),
863 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996 867 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
864 4, 1, 0), 868 4, 1, 0),
865 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_LEF 869 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0),
866 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_LEF 870 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0),
867 }; 871 };
868 872
869 static const struct snd_kcontrol_new dac1r_mix 873 static const struct snd_kcontrol_new dac1r_mix[] = {
870 SOC_DAPM_SINGLE("Right Sidetone Switch", WM899 874 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
871 5, 1, 0), 875 5, 1, 0),
872 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996 876 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
873 4, 1, 0), 877 4, 1, 0),
874 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_RIG 878 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0),
875 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_RIG 879 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0),
876 }; 880 };
877 881
878 static const struct snd_kcontrol_new dac1l_mix 882 static const struct snd_kcontrol_new dac1l_mix[] = {
879 SOC_DAPM_SINGLE("Right Sidetone Switch", WM899 883 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
880 5, 1, 0), 884 5, 1, 0),
881 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996 885 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
882 4, 1, 0), 886 4, 1, 0),
883 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_LEF 887 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0),
884 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_LEF 888 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0),
885 }; 889 };
886 890
887 static const struct snd_kcontrol_new dsp1txl[] 891 static const struct snd_kcontrol_new dsp1txl[] = {
888 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_L 892 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
889 1, 1, 0), 893 1, 1, 0),
890 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_L 894 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
891 0, 1, 0), 895 0, 1, 0),
892 }; 896 };
893 897
894 static const struct snd_kcontrol_new dsp1txr[] 898 static const struct snd_kcontrol_new dsp1txr[] = {
895 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_R 899 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
896 1, 1, 0), 900 1, 1, 0),
897 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_R 901 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
898 0, 1, 0), 902 0, 1, 0),
899 }; 903 };
900 904
901 static const struct snd_kcontrol_new dsp2txl[] 905 static const struct snd_kcontrol_new dsp2txl[] = {
902 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_L 906 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
903 1, 1, 0), 907 1, 1, 0),
904 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_L 908 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
905 0, 1, 0), 909 0, 1, 0),
906 }; 910 };
907 911
908 static const struct snd_kcontrol_new dsp2txr[] 912 static const struct snd_kcontrol_new dsp2txr[] = {
909 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_R 913 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
910 1, 1, 0), 914 1, 1, 0),
911 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_R 915 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
912 0, 1, 0), 916 0, 1, 0),
913 }; 917 };
914 918
915 919
916 static const struct snd_soc_dapm_widget wm8996 920 static const struct snd_soc_dapm_widget wm8996_dapm_widgets[] = {
917 SND_SOC_DAPM_INPUT("IN1LN"), 921 SND_SOC_DAPM_INPUT("IN1LN"),
918 SND_SOC_DAPM_INPUT("IN1LP"), 922 SND_SOC_DAPM_INPUT("IN1LP"),
919 SND_SOC_DAPM_INPUT("IN1RN"), 923 SND_SOC_DAPM_INPUT("IN1RN"),
920 SND_SOC_DAPM_INPUT("IN1RP"), 924 SND_SOC_DAPM_INPUT("IN1RP"),
921 925
922 SND_SOC_DAPM_INPUT("IN2LN"), 926 SND_SOC_DAPM_INPUT("IN2LN"),
923 SND_SOC_DAPM_INPUT("IN2LP"), 927 SND_SOC_DAPM_INPUT("IN2LP"),
924 SND_SOC_DAPM_INPUT("IN2RN"), 928 SND_SOC_DAPM_INPUT("IN2RN"),
925 SND_SOC_DAPM_INPUT("IN2RP"), 929 SND_SOC_DAPM_INPUT("IN2RP"),
926 930
927 SND_SOC_DAPM_INPUT("DMIC1DAT"), 931 SND_SOC_DAPM_INPUT("DMIC1DAT"),
928 SND_SOC_DAPM_INPUT("DMIC2DAT"), 932 SND_SOC_DAPM_INPUT("DMIC2DAT"),
929 933
930 SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0), 934 SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0),
931 SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8996_AIF_ 935 SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8996_AIF_CLOCKING_1, 0, 0, NULL, 0),
932 SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8996_C 936 SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8996_CLOCKING_1, 1, 0, NULL, 0),
933 SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8996_CLOC 937 SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8996_CLOCKING_1, 2, 0, NULL, 0),
934 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8996 938 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8996_CHARGE_PUMP_1, 15, 0, cp_event,
935 SND_SOC_DAPM_POST_PMU), 939 SND_SOC_DAPM_POST_PMU),
936 SND_SOC_DAPM_SUPPLY("Bandgap", SND_SOC_NOPM, 0 940 SND_SOC_DAPM_SUPPLY("Bandgap", SND_SOC_NOPM, 0, 0, bg_event,
937 SND_SOC_DAPM_PRE_PMU | SND 941 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
938 SND_SOC_DAPM_SUPPLY("LDO2", WM8996_POWER_MANAG 942 SND_SOC_DAPM_SUPPLY("LDO2", WM8996_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
939 SND_SOC_DAPM_SUPPLY("MICB1 Audio", WM8996_MICB 943 SND_SOC_DAPM_SUPPLY("MICB1 Audio", WM8996_MICBIAS_1, 4, 1, NULL, 0),
940 SND_SOC_DAPM_SUPPLY("MICB2 Audio", WM8996_MICB 944 SND_SOC_DAPM_SUPPLY("MICB2 Audio", WM8996_MICBIAS_2, 4, 1, NULL, 0),
941 SND_SOC_DAPM_MICBIAS("MICB2", WM8996_POWER_MAN 945 SND_SOC_DAPM_MICBIAS("MICB2", WM8996_POWER_MANAGEMENT_1, 9, 0),
942 SND_SOC_DAPM_MICBIAS("MICB1", WM8996_POWER_MAN 946 SND_SOC_DAPM_MICBIAS("MICB1", WM8996_POWER_MANAGEMENT_1, 8, 0),
943 947
944 SND_SOC_DAPM_PGA("IN1L PGA", WM8996_POWER_MANA 948 SND_SOC_DAPM_PGA("IN1L PGA", WM8996_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
945 SND_SOC_DAPM_PGA("IN1R PGA", WM8996_POWER_MANA 949 SND_SOC_DAPM_PGA("IN1R PGA", WM8996_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
946 950
947 SND_SOC_DAPM_MUX("IN1L Mux", WM8996_POWER_MANA 951 SND_SOC_DAPM_MUX("IN1L Mux", WM8996_POWER_MANAGEMENT_7, 2, 0, &in1_mux),
948 SND_SOC_DAPM_MUX("IN1R Mux", WM8996_POWER_MANA 952 SND_SOC_DAPM_MUX("IN1R Mux", WM8996_POWER_MANAGEMENT_7, 3, 0, &in1_mux),
949 SND_SOC_DAPM_MUX("IN2L Mux", WM8996_POWER_MANA 953 SND_SOC_DAPM_MUX("IN2L Mux", WM8996_POWER_MANAGEMENT_7, 6, 0, &in2_mux),
950 SND_SOC_DAPM_MUX("IN2R Mux", WM8996_POWER_MANA 954 SND_SOC_DAPM_MUX("IN2R Mux", WM8996_POWER_MANAGEMENT_7, 7, 0, &in2_mux),
951 955
952 SND_SOC_DAPM_SUPPLY("DMIC2", WM8996_POWER_MANA 956 SND_SOC_DAPM_SUPPLY("DMIC2", WM8996_POWER_MANAGEMENT_7, 9, 0, NULL, 0),
953 SND_SOC_DAPM_SUPPLY("DMIC1", WM8996_POWER_MANA 957 SND_SOC_DAPM_SUPPLY("DMIC1", WM8996_POWER_MANAGEMENT_7, 8, 0, NULL, 0),
954 958
955 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8996_POWER_ 959 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8996_POWER_MANAGEMENT_3, 5, 0),
956 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8996_POWER_ 960 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8996_POWER_MANAGEMENT_3, 4, 0),
957 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8996_POWER_ 961 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8996_POWER_MANAGEMENT_3, 3, 0),
958 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8996_POWER_ 962 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8996_POWER_MANAGEMENT_3, 2, 0),
959 963
960 SND_SOC_DAPM_ADC("ADCL", NULL, WM8996_POWER_MA 964 SND_SOC_DAPM_ADC("ADCL", NULL, WM8996_POWER_MANAGEMENT_3, 1, 0),
961 SND_SOC_DAPM_ADC("ADCR", NULL, WM8996_POWER_MA 965 SND_SOC_DAPM_ADC("ADCR", NULL, WM8996_POWER_MANAGEMENT_3, 0, 0),
962 966
963 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM 967 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone),
964 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOP 968 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone),
965 969
966 SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8996 970 SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 11, 0),
967 SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8996 971 SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 10, 0),
968 SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8996 972 SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 9, 0),
969 SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8996 973 SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 8, 0),
970 974
971 SND_SOC_DAPM_MIXER("DSP2TXL", WM8996_POWER_MAN 975 SND_SOC_DAPM_MIXER("DSP2TXL", WM8996_POWER_MANAGEMENT_5, 11, 0,
972 dsp2txl, ARRAY_SIZE(dsp2txl 976 dsp2txl, ARRAY_SIZE(dsp2txl)),
973 SND_SOC_DAPM_MIXER("DSP2TXR", WM8996_POWER_MAN 977 SND_SOC_DAPM_MIXER("DSP2TXR", WM8996_POWER_MANAGEMENT_5, 10, 0,
974 dsp2txr, ARRAY_SIZE(dsp2txr 978 dsp2txr, ARRAY_SIZE(dsp2txr)),
975 SND_SOC_DAPM_MIXER("DSP1TXL", WM8996_POWER_MAN 979 SND_SOC_DAPM_MIXER("DSP1TXL", WM8996_POWER_MANAGEMENT_5, 9, 0,
976 dsp1txl, ARRAY_SIZE(dsp1txl 980 dsp1txl, ARRAY_SIZE(dsp1txl)),
977 SND_SOC_DAPM_MIXER("DSP1TXR", WM8996_POWER_MAN 981 SND_SOC_DAPM_MIXER("DSP1TXR", WM8996_POWER_MANAGEMENT_5, 8, 0,
978 dsp1txr, ARRAY_SIZE(dsp1txr 982 dsp1txr, ARRAY_SIZE(dsp1txr)),
979 983
980 SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM 984 SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0,
981 dac2l_mix, ARRAY_SIZE(dac2l 985 dac2l_mix, ARRAY_SIZE(dac2l_mix)),
982 SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM 986 SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0,
983 dac2r_mix, ARRAY_SIZE(dac2r 987 dac2r_mix, ARRAY_SIZE(dac2r_mix)),
984 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM 988 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
985 dac1l_mix, ARRAY_SIZE(dac1l 989 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
986 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM 990 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
987 dac1r_mix, ARRAY_SIZE(dac1r 991 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
988 992
989 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8996_POWER_M 993 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8996_POWER_MANAGEMENT_5, 3, 0),
990 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8996_POWER_M 994 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8996_POWER_MANAGEMENT_5, 2, 0),
991 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8996_POWER_M 995 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8996_POWER_MANAGEMENT_5, 1, 0),
992 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8996_POWER_M 996 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8996_POWER_MANAGEMENT_5, 0, 0),
993 997
994 SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0, WM8996 998 SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0, WM8996_POWER_MANAGEMENT_4, 9, 0),
995 SND_SOC_DAPM_AIF_IN("AIF2RX0", NULL, 1, WM8996 999 SND_SOC_DAPM_AIF_IN("AIF2RX0", NULL, 1, WM8996_POWER_MANAGEMENT_4, 8, 0),
996 1000
997 SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0, WM899 1001 SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0, WM8996_POWER_MANAGEMENT_6, 9, 0),
998 SND_SOC_DAPM_AIF_OUT("AIF2TX0", NULL, 1, WM899 1002 SND_SOC_DAPM_AIF_OUT("AIF2TX0", NULL, 1, WM8996_POWER_MANAGEMENT_6, 8, 0),
999 1003
1000 SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 5, WM899 1004 SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 5, WM8996_POWER_MANAGEMENT_4, 5, 0),
1001 SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 4, WM899 1005 SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 4, WM8996_POWER_MANAGEMENT_4, 4, 0),
1002 SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 3, WM899 1006 SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 3, WM8996_POWER_MANAGEMENT_4, 3, 0),
1003 SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 2, WM899 1007 SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 2, WM8996_POWER_MANAGEMENT_4, 2, 0),
1004 SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 1, WM899 1008 SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 1, WM8996_POWER_MANAGEMENT_4, 1, 0),
1005 SND_SOC_DAPM_AIF_IN("AIF1RX0", NULL, 0, WM899 1009 SND_SOC_DAPM_AIF_IN("AIF1RX0", NULL, 0, WM8996_POWER_MANAGEMENT_4, 0, 0),
1006 1010
1007 SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 5, WM89 1011 SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 5, WM8996_POWER_MANAGEMENT_6, 5, 0),
1008 SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 4, WM89 1012 SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 4, WM8996_POWER_MANAGEMENT_6, 4, 0),
1009 SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 3, WM89 1013 SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 3, WM8996_POWER_MANAGEMENT_6, 3, 0),
1010 SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 2, WM89 1014 SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 2, WM8996_POWER_MANAGEMENT_6, 2, 0),
1011 SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 1, WM89 1015 SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 1, WM8996_POWER_MANAGEMENT_6, 1, 0),
1012 SND_SOC_DAPM_AIF_OUT("AIF1TX0", NULL, 0, WM89 1016 SND_SOC_DAPM_AIF_OUT("AIF1TX0", NULL, 0, WM8996_POWER_MANAGEMENT_6, 0, 0),
1013 1017
1014 /* We route as stereo pairs so define some du 1018 /* We route as stereo pairs so define some dummy widgets to squash
1015 * things down for now. RXA = 0,1, RXB = 2,3 1019 * things down for now. RXA = 0,1, RXB = 2,3 and so on */
1016 SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 1020 SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0),
1017 SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 1021 SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0),
1018 SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 1022 SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0),
1019 SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0 1023 SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0),
1020 SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0 1024 SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0),
1021 1025
1022 SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0 1026 SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx),
1023 SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0 1027 SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx),
1024 SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0 1028 SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx),
1025 1029
1026 SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, 1030 SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux),
1027 SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, 1031 SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux),
1028 SND_SOC_DAPM_PGA("SPKL PGA", WM8996_LEFT_PDM_ 1032 SND_SOC_DAPM_PGA("SPKL PGA", WM8996_LEFT_PDM_SPEAKER, 4, 0, NULL, 0),
1029 SND_SOC_DAPM_PGA("SPKR PGA", WM8996_RIGHT_PDM 1033 SND_SOC_DAPM_PGA("SPKR PGA", WM8996_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0),
1030 1034
1031 SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8996_P 1035 SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8996_POWER_MANAGEMENT_1, 7, 0, NULL, 0),
1032 SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8996_A 1036 SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8996_ANALOGUE_HP_2, 5, 0, NULL, 0),
1033 SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8996_D 1037 SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8996_DC_SERVO_1, 2, 0, dcs_start,
1034 SND_SOC_DAPM_POST_PMU), 1038 SND_SOC_DAPM_POST_PMU),
1035 SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SN 1039 SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0,
1036 rmv_short_event, 1040 rmv_short_event,
1037 SND_SOC_DAPM_PRE_PMU | SND 1041 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1038 1042
1039 SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8996_P 1043 SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8996_POWER_MANAGEMENT_1, 6, 0,NULL, 0),
1040 SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8996_A 1044 SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8996_ANALOGUE_HP_2, 1, 0, NULL, 0),
1041 SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8996_D 1045 SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8996_DC_SERVO_1, 3, 0, dcs_start,
1042 SND_SOC_DAPM_POST_PMU), 1046 SND_SOC_DAPM_POST_PMU),
1043 SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SN 1047 SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0,
1044 rmv_short_event, 1048 rmv_short_event,
1045 SND_SOC_DAPM_PRE_PMU | SND 1049 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1046 1050
1047 SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8996_P 1051 SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8996_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
1048 SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8996_A 1052 SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8996_ANALOGUE_HP_1, 5, 0, NULL, 0),
1049 SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8996_D 1053 SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8996_DC_SERVO_1, 0, 0, dcs_start,
1050 SND_SOC_DAPM_POST_PMU), 1054 SND_SOC_DAPM_POST_PMU),
1051 SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SN 1055 SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0,
1052 rmv_short_event, 1056 rmv_short_event,
1053 SND_SOC_DAPM_PRE_PMU | SND 1057 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1054 1058
1055 SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8996_P 1059 SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8996_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
1056 SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8996_A 1060 SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8996_ANALOGUE_HP_1, 1, 0, NULL, 0),
1057 SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8996_D 1061 SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8996_DC_SERVO_1, 1, 0, dcs_start,
1058 SND_SOC_DAPM_POST_PMU), 1062 SND_SOC_DAPM_POST_PMU),
1059 SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SN 1063 SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0,
1060 rmv_short_event, 1064 rmv_short_event,
1061 SND_SOC_DAPM_PRE_PMU | SND 1065 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1062 1066
1063 SND_SOC_DAPM_OUTPUT("HPOUT1L"), 1067 SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1064 SND_SOC_DAPM_OUTPUT("HPOUT1R"), 1068 SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1065 SND_SOC_DAPM_OUTPUT("HPOUT2L"), 1069 SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1066 SND_SOC_DAPM_OUTPUT("HPOUT2R"), 1070 SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1067 SND_SOC_DAPM_OUTPUT("SPKDAT"), 1071 SND_SOC_DAPM_OUTPUT("SPKDAT"),
1068 }; 1072 };
1069 1073
1070 static const struct snd_soc_dapm_route wm8996 1074 static const struct snd_soc_dapm_route wm8996_dapm_routes[] = {
1071 { "AIFCLK", NULL, "SYSCLK" }, 1075 { "AIFCLK", NULL, "SYSCLK" },
1072 { "SYSDSPCLK", NULL, "SYSCLK" }, 1076 { "SYSDSPCLK", NULL, "SYSCLK" },
1073 { "Charge Pump", NULL, "SYSCLK" }, 1077 { "Charge Pump", NULL, "SYSCLK" },
1074 { "Charge Pump", NULL, "CPVDD" }, 1078 { "Charge Pump", NULL, "CPVDD" },
1075 1079
1076 { "MICB1", NULL, "LDO2" }, 1080 { "MICB1", NULL, "LDO2" },
1077 { "MICB1", NULL, "MICB1 Audio" }, 1081 { "MICB1", NULL, "MICB1 Audio" },
1078 { "MICB1", NULL, "Bandgap" }, 1082 { "MICB1", NULL, "Bandgap" },
1079 { "MICB2", NULL, "LDO2" }, 1083 { "MICB2", NULL, "LDO2" },
1080 { "MICB2", NULL, "MICB2 Audio" }, 1084 { "MICB2", NULL, "MICB2 Audio" },
1081 { "MICB2", NULL, "Bandgap" }, 1085 { "MICB2", NULL, "Bandgap" },
1082 1086
1083 { "AIF1RX0", NULL, "AIF1 Playback" }, 1087 { "AIF1RX0", NULL, "AIF1 Playback" },
1084 { "AIF1RX1", NULL, "AIF1 Playback" }, 1088 { "AIF1RX1", NULL, "AIF1 Playback" },
1085 { "AIF1RX2", NULL, "AIF1 Playback" }, 1089 { "AIF1RX2", NULL, "AIF1 Playback" },
1086 { "AIF1RX3", NULL, "AIF1 Playback" }, 1090 { "AIF1RX3", NULL, "AIF1 Playback" },
1087 { "AIF1RX4", NULL, "AIF1 Playback" }, 1091 { "AIF1RX4", NULL, "AIF1 Playback" },
1088 { "AIF1RX5", NULL, "AIF1 Playback" }, 1092 { "AIF1RX5", NULL, "AIF1 Playback" },
1089 1093
1090 { "AIF2RX0", NULL, "AIF2 Playback" }, 1094 { "AIF2RX0", NULL, "AIF2 Playback" },
1091 { "AIF2RX1", NULL, "AIF2 Playback" }, 1095 { "AIF2RX1", NULL, "AIF2 Playback" },
1092 1096
1093 { "AIF1 Capture", NULL, "AIF1TX0" }, 1097 { "AIF1 Capture", NULL, "AIF1TX0" },
1094 { "AIF1 Capture", NULL, "AIF1TX1" }, 1098 { "AIF1 Capture", NULL, "AIF1TX1" },
1095 { "AIF1 Capture", NULL, "AIF1TX2" }, 1099 { "AIF1 Capture", NULL, "AIF1TX2" },
1096 { "AIF1 Capture", NULL, "AIF1TX3" }, 1100 { "AIF1 Capture", NULL, "AIF1TX3" },
1097 { "AIF1 Capture", NULL, "AIF1TX4" }, 1101 { "AIF1 Capture", NULL, "AIF1TX4" },
1098 { "AIF1 Capture", NULL, "AIF1TX5" }, 1102 { "AIF1 Capture", NULL, "AIF1TX5" },
1099 1103
1100 { "AIF2 Capture", NULL, "AIF2TX0" }, 1104 { "AIF2 Capture", NULL, "AIF2TX0" },
1101 { "AIF2 Capture", NULL, "AIF2TX1" }, 1105 { "AIF2 Capture", NULL, "AIF2TX1" },
1102 1106
1103 { "IN1L PGA", NULL, "IN2LN" }, 1107 { "IN1L PGA", NULL, "IN2LN" },
1104 { "IN1L PGA", NULL, "IN2LP" }, 1108 { "IN1L PGA", NULL, "IN2LP" },
1105 { "IN1L PGA", NULL, "IN1LN" }, 1109 { "IN1L PGA", NULL, "IN1LN" },
1106 { "IN1L PGA", NULL, "IN1LP" }, 1110 { "IN1L PGA", NULL, "IN1LP" },
1107 { "IN1L PGA", NULL, "Bandgap" }, 1111 { "IN1L PGA", NULL, "Bandgap" },
1108 1112
1109 { "IN1R PGA", NULL, "IN2RN" }, 1113 { "IN1R PGA", NULL, "IN2RN" },
1110 { "IN1R PGA", NULL, "IN2RP" }, 1114 { "IN1R PGA", NULL, "IN2RP" },
1111 { "IN1R PGA", NULL, "IN1RN" }, 1115 { "IN1R PGA", NULL, "IN1RN" },
1112 { "IN1R PGA", NULL, "IN1RP" }, 1116 { "IN1R PGA", NULL, "IN1RP" },
1113 { "IN1R PGA", NULL, "Bandgap" }, 1117 { "IN1R PGA", NULL, "Bandgap" },
1114 1118
1115 { "ADCL", NULL, "IN1L PGA" }, 1119 { "ADCL", NULL, "IN1L PGA" },
1116 1120
1117 { "ADCR", NULL, "IN1R PGA" }, 1121 { "ADCR", NULL, "IN1R PGA" },
1118 1122
1119 { "DMIC1L", NULL, "DMIC1DAT" }, 1123 { "DMIC1L", NULL, "DMIC1DAT" },
1120 { "DMIC1R", NULL, "DMIC1DAT" }, 1124 { "DMIC1R", NULL, "DMIC1DAT" },
1121 { "DMIC2L", NULL, "DMIC2DAT" }, 1125 { "DMIC2L", NULL, "DMIC2DAT" },
1122 { "DMIC2R", NULL, "DMIC2DAT" }, 1126 { "DMIC2R", NULL, "DMIC2DAT" },
1123 1127
1124 { "DMIC2L", NULL, "DMIC2" }, 1128 { "DMIC2L", NULL, "DMIC2" },
1125 { "DMIC2R", NULL, "DMIC2" }, 1129 { "DMIC2R", NULL, "DMIC2" },
1126 { "DMIC1L", NULL, "DMIC1" }, 1130 { "DMIC1L", NULL, "DMIC1" },
1127 { "DMIC1R", NULL, "DMIC1" }, 1131 { "DMIC1R", NULL, "DMIC1" },
1128 1132
1129 { "IN1L Mux", "ADC", "ADCL" }, 1133 { "IN1L Mux", "ADC", "ADCL" },
1130 { "IN1L Mux", "DMIC1", "DMIC1L" }, 1134 { "IN1L Mux", "DMIC1", "DMIC1L" },
1131 { "IN1L Mux", "DMIC2", "DMIC2L" }, 1135 { "IN1L Mux", "DMIC2", "DMIC2L" },
1132 1136
1133 { "IN1R Mux", "ADC", "ADCR" }, 1137 { "IN1R Mux", "ADC", "ADCR" },
1134 { "IN1R Mux", "DMIC1", "DMIC1R" }, 1138 { "IN1R Mux", "DMIC1", "DMIC1R" },
1135 { "IN1R Mux", "DMIC2", "DMIC2R" }, 1139 { "IN1R Mux", "DMIC2", "DMIC2R" },
1136 1140
1137 { "IN2L Mux", "ADC", "ADCL" }, 1141 { "IN2L Mux", "ADC", "ADCL" },
1138 { "IN2L Mux", "DMIC1", "DMIC1L" }, 1142 { "IN2L Mux", "DMIC1", "DMIC1L" },
1139 { "IN2L Mux", "DMIC2", "DMIC2L" }, 1143 { "IN2L Mux", "DMIC2", "DMIC2L" },
1140 1144
1141 { "IN2R Mux", "ADC", "ADCR" }, 1145 { "IN2R Mux", "ADC", "ADCR" },
1142 { "IN2R Mux", "DMIC1", "DMIC1R" }, 1146 { "IN2R Mux", "DMIC1", "DMIC1R" },
1143 { "IN2R Mux", "DMIC2", "DMIC2R" }, 1147 { "IN2R Mux", "DMIC2", "DMIC2R" },
1144 1148
1145 { "Left Sidetone", "IN1", "IN1L Mux" 1149 { "Left Sidetone", "IN1", "IN1L Mux" },
1146 { "Left Sidetone", "IN2", "IN2L Mux" 1150 { "Left Sidetone", "IN2", "IN2L Mux" },
1147 1151
1148 { "Right Sidetone", "IN1", "IN1R Mux" 1152 { "Right Sidetone", "IN1", "IN1R Mux" },
1149 { "Right Sidetone", "IN2", "IN2R Mux" 1153 { "Right Sidetone", "IN2", "IN2R Mux" },
1150 1154
1151 { "DSP1TXL", "IN1 Switch", "IN1L Mux" 1155 { "DSP1TXL", "IN1 Switch", "IN1L Mux" },
1152 { "DSP1TXR", "IN1 Switch", "IN1R Mux" 1156 { "DSP1TXR", "IN1 Switch", "IN1R Mux" },
1153 1157
1154 { "DSP2TXL", "IN1 Switch", "IN2L Mux" 1158 { "DSP2TXL", "IN1 Switch", "IN2L Mux" },
1155 { "DSP2TXR", "IN1 Switch", "IN2R Mux" 1159 { "DSP2TXR", "IN1 Switch", "IN2R Mux" },
1156 1160
1157 { "AIF1TX0", NULL, "DSP1TXL" }, 1161 { "AIF1TX0", NULL, "DSP1TXL" },
1158 { "AIF1TX1", NULL, "DSP1TXR" }, 1162 { "AIF1TX1", NULL, "DSP1TXR" },
1159 { "AIF1TX2", NULL, "DSP2TXL" }, 1163 { "AIF1TX2", NULL, "DSP2TXL" },
1160 { "AIF1TX3", NULL, "DSP2TXR" }, 1164 { "AIF1TX3", NULL, "DSP2TXR" },
1161 { "AIF1TX4", NULL, "AIF2RX0" }, 1165 { "AIF1TX4", NULL, "AIF2RX0" },
1162 { "AIF1TX5", NULL, "AIF2RX1" }, 1166 { "AIF1TX5", NULL, "AIF2RX1" },
1163 1167
1164 { "AIF1RX0", NULL, "AIFCLK" }, 1168 { "AIF1RX0", NULL, "AIFCLK" },
1165 { "AIF1RX1", NULL, "AIFCLK" }, 1169 { "AIF1RX1", NULL, "AIFCLK" },
1166 { "AIF1RX2", NULL, "AIFCLK" }, 1170 { "AIF1RX2", NULL, "AIFCLK" },
1167 { "AIF1RX3", NULL, "AIFCLK" }, 1171 { "AIF1RX3", NULL, "AIFCLK" },
1168 { "AIF1RX4", NULL, "AIFCLK" }, 1172 { "AIF1RX4", NULL, "AIFCLK" },
1169 { "AIF1RX5", NULL, "AIFCLK" }, 1173 { "AIF1RX5", NULL, "AIFCLK" },
1170 1174
1171 { "AIF2RX0", NULL, "AIFCLK" }, 1175 { "AIF2RX0", NULL, "AIFCLK" },
1172 { "AIF2RX1", NULL, "AIFCLK" }, 1176 { "AIF2RX1", NULL, "AIFCLK" },
1173 1177
1174 { "AIF1TX0", NULL, "AIFCLK" }, 1178 { "AIF1TX0", NULL, "AIFCLK" },
1175 { "AIF1TX1", NULL, "AIFCLK" }, 1179 { "AIF1TX1", NULL, "AIFCLK" },
1176 { "AIF1TX2", NULL, "AIFCLK" }, 1180 { "AIF1TX2", NULL, "AIFCLK" },
1177 { "AIF1TX3", NULL, "AIFCLK" }, 1181 { "AIF1TX3", NULL, "AIFCLK" },
1178 { "AIF1TX4", NULL, "AIFCLK" }, 1182 { "AIF1TX4", NULL, "AIFCLK" },
1179 { "AIF1TX5", NULL, "AIFCLK" }, 1183 { "AIF1TX5", NULL, "AIFCLK" },
1180 1184
1181 { "AIF2TX0", NULL, "AIFCLK" }, 1185 { "AIF2TX0", NULL, "AIFCLK" },
1182 { "AIF2TX1", NULL, "AIFCLK" }, 1186 { "AIF2TX1", NULL, "AIFCLK" },
1183 1187
1184 { "DSP1RXL", NULL, "SYSDSPCLK" }, 1188 { "DSP1RXL", NULL, "SYSDSPCLK" },
1185 { "DSP1RXR", NULL, "SYSDSPCLK" }, 1189 { "DSP1RXR", NULL, "SYSDSPCLK" },
1186 { "DSP2RXL", NULL, "SYSDSPCLK" }, 1190 { "DSP2RXL", NULL, "SYSDSPCLK" },
1187 { "DSP2RXR", NULL, "SYSDSPCLK" }, 1191 { "DSP2RXR", NULL, "SYSDSPCLK" },
1188 { "DSP1TXL", NULL, "SYSDSPCLK" }, 1192 { "DSP1TXL", NULL, "SYSDSPCLK" },
1189 { "DSP1TXR", NULL, "SYSDSPCLK" }, 1193 { "DSP1TXR", NULL, "SYSDSPCLK" },
1190 { "DSP2TXL", NULL, "SYSDSPCLK" }, 1194 { "DSP2TXL", NULL, "SYSDSPCLK" },
1191 { "DSP2TXR", NULL, "SYSDSPCLK" }, 1195 { "DSP2TXR", NULL, "SYSDSPCLK" },
1192 1196
1193 { "AIF1RXA", NULL, "AIF1RX0" }, 1197 { "AIF1RXA", NULL, "AIF1RX0" },
1194 { "AIF1RXA", NULL, "AIF1RX1" }, 1198 { "AIF1RXA", NULL, "AIF1RX1" },
1195 { "AIF1RXB", NULL, "AIF1RX2" }, 1199 { "AIF1RXB", NULL, "AIF1RX2" },
1196 { "AIF1RXB", NULL, "AIF1RX3" }, 1200 { "AIF1RXB", NULL, "AIF1RX3" },
1197 { "AIF1RXC", NULL, "AIF1RX4" }, 1201 { "AIF1RXC", NULL, "AIF1RX4" },
1198 { "AIF1RXC", NULL, "AIF1RX5" }, 1202 { "AIF1RXC", NULL, "AIF1RX5" },
1199 1203
1200 { "AIF2RX", NULL, "AIF2RX0" }, 1204 { "AIF2RX", NULL, "AIF2RX0" },
1201 { "AIF2RX", NULL, "AIF2RX1" }, 1205 { "AIF2RX", NULL, "AIF2RX1" },
1202 1206
1203 { "AIF2TX", "DSP2", "DSP2TX" }, 1207 { "AIF2TX", "DSP2", "DSP2TX" },
1204 { "AIF2TX", "DSP1", "DSP1RX" }, 1208 { "AIF2TX", "DSP1", "DSP1RX" },
1205 { "AIF2TX", "AIF1", "AIF1RXC" }, 1209 { "AIF2TX", "AIF1", "AIF1RXC" },
1206 1210
1207 { "DSP1RXL", NULL, "DSP1RX" }, 1211 { "DSP1RXL", NULL, "DSP1RX" },
1208 { "DSP1RXR", NULL, "DSP1RX" }, 1212 { "DSP1RXR", NULL, "DSP1RX" },
1209 { "DSP2RXL", NULL, "DSP2RX" }, 1213 { "DSP2RXL", NULL, "DSP2RX" },
1210 { "DSP2RXR", NULL, "DSP2RX" }, 1214 { "DSP2RXR", NULL, "DSP2RX" },
1211 1215
1212 { "DSP2TX", NULL, "DSP2TXL" }, 1216 { "DSP2TX", NULL, "DSP2TXL" },
1213 { "DSP2TX", NULL, "DSP2TXR" }, 1217 { "DSP2TX", NULL, "DSP2TXR" },
1214 1218
1215 { "DSP1RX", "AIF1", "AIF1RXA" }, 1219 { "DSP1RX", "AIF1", "AIF1RXA" },
1216 { "DSP1RX", "AIF2", "AIF2RX" }, 1220 { "DSP1RX", "AIF2", "AIF2RX" },
1217 1221
1218 { "DSP2RX", "AIF1", "AIF1RXB" }, 1222 { "DSP2RX", "AIF1", "AIF1RXB" },
1219 { "DSP2RX", "AIF2", "AIF2RX" }, 1223 { "DSP2RX", "AIF2", "AIF2RX" },
1220 1224
1221 { "DAC2L Mixer", "DSP2 Switch", "DSP2 1225 { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" },
1222 { "DAC2L Mixer", "DSP1 Switch", "DSP1 1226 { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" },
1223 { "DAC2L Mixer", "Right Sidetone Swit 1227 { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1224 { "DAC2L Mixer", "Left Sidetone Switc 1228 { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1225 1229
1226 { "DAC2R Mixer", "DSP2 Switch", "DSP2 1230 { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" },
1227 { "DAC2R Mixer", "DSP1 Switch", "DSP1 1231 { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" },
1228 { "DAC2R Mixer", "Right Sidetone Swit 1232 { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1229 { "DAC2R Mixer", "Left Sidetone Switc 1233 { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1230 1234
1231 { "DAC1L Mixer", "DSP2 Switch", "DSP2 1235 { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" },
1232 { "DAC1L Mixer", "DSP1 Switch", "DSP1 1236 { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" },
1233 { "DAC1L Mixer", "Right Sidetone Swit 1237 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1234 { "DAC1L Mixer", "Left Sidetone Switc 1238 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1235 1239
1236 { "DAC1R Mixer", "DSP2 Switch", "DSP2 1240 { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" },
1237 { "DAC1R Mixer", "DSP1 Switch", "DSP1 1241 { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" },
1238 { "DAC1R Mixer", "Right Sidetone Swit 1242 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1239 { "DAC1R Mixer", "Left Sidetone Switc 1243 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1240 1244
1241 { "DAC1L", NULL, "DAC1L Mixer" }, 1245 { "DAC1L", NULL, "DAC1L Mixer" },
1242 { "DAC1R", NULL, "DAC1R Mixer" }, 1246 { "DAC1R", NULL, "DAC1R Mixer" },
1243 { "DAC2L", NULL, "DAC2L Mixer" }, 1247 { "DAC2L", NULL, "DAC2L Mixer" },
1244 { "DAC2R", NULL, "DAC2R Mixer" }, 1248 { "DAC2R", NULL, "DAC2R Mixer" },
1245 1249
1246 { "HPOUT2L PGA", NULL, "Charge Pump" 1250 { "HPOUT2L PGA", NULL, "Charge Pump" },
1247 { "HPOUT2L PGA", NULL, "Bandgap" }, 1251 { "HPOUT2L PGA", NULL, "Bandgap" },
1248 { "HPOUT2L PGA", NULL, "DAC2L" }, 1252 { "HPOUT2L PGA", NULL, "DAC2L" },
1249 { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" 1253 { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" },
1250 { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" 1254 { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" },
1251 { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L 1255 { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_DCS" },
1252 1256
1253 { "HPOUT2R PGA", NULL, "Charge Pump" 1257 { "HPOUT2R PGA", NULL, "Charge Pump" },
1254 { "HPOUT2R PGA", NULL, "Bandgap" }, 1258 { "HPOUT2R PGA", NULL, "Bandgap" },
1255 { "HPOUT2R PGA", NULL, "DAC2R" }, 1259 { "HPOUT2R PGA", NULL, "DAC2R" },
1256 { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" 1260 { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" },
1257 { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" 1261 { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" },
1258 { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R 1262 { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_DCS" },
1259 1263
1260 { "HPOUT1L PGA", NULL, "Charge Pump" 1264 { "HPOUT1L PGA", NULL, "Charge Pump" },
1261 { "HPOUT1L PGA", NULL, "Bandgap" }, 1265 { "HPOUT1L PGA", NULL, "Bandgap" },
1262 { "HPOUT1L PGA", NULL, "DAC1L" }, 1266 { "HPOUT1L PGA", NULL, "DAC1L" },
1263 { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" 1267 { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" },
1264 { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" 1268 { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" },
1265 { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L 1269 { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_DCS" },
1266 1270
1267 { "HPOUT1R PGA", NULL, "Charge Pump" 1271 { "HPOUT1R PGA", NULL, "Charge Pump" },
1268 { "HPOUT1R PGA", NULL, "Bandgap" }, 1272 { "HPOUT1R PGA", NULL, "Bandgap" },
1269 { "HPOUT1R PGA", NULL, "DAC1R" }, 1273 { "HPOUT1R PGA", NULL, "DAC1R" },
1270 { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" 1274 { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" },
1271 { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" 1275 { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" },
1272 { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R 1276 { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_DCS" },
1273 1277
1274 { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT 1278 { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" },
1275 { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT 1279 { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" },
1276 { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT 1280 { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" },
1277 { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT 1281 { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" },
1278 1282
1279 { "SPKL", "DAC1L", "DAC1L" }, 1283 { "SPKL", "DAC1L", "DAC1L" },
1280 { "SPKL", "DAC1R", "DAC1R" }, 1284 { "SPKL", "DAC1R", "DAC1R" },
1281 { "SPKL", "DAC2L", "DAC2L" }, 1285 { "SPKL", "DAC2L", "DAC2L" },
1282 { "SPKL", "DAC2R", "DAC2R" }, 1286 { "SPKL", "DAC2R", "DAC2R" },
1283 1287
1284 { "SPKR", "DAC1L", "DAC1L" }, 1288 { "SPKR", "DAC1L", "DAC1L" },
1285 { "SPKR", "DAC1R", "DAC1R" }, 1289 { "SPKR", "DAC1R", "DAC1R" },
1286 { "SPKR", "DAC2L", "DAC2L" }, 1290 { "SPKR", "DAC2L", "DAC2L" },
1287 { "SPKR", "DAC2R", "DAC2R" }, 1291 { "SPKR", "DAC2R", "DAC2R" },
1288 1292
1289 { "SPKL PGA", NULL, "SPKL" }, 1293 { "SPKL PGA", NULL, "SPKL" },
1290 { "SPKR PGA", NULL, "SPKR" }, 1294 { "SPKR PGA", NULL, "SPKR" },
1291 1295
1292 { "SPKDAT", NULL, "SPKL PGA" }, 1296 { "SPKDAT", NULL, "SPKL PGA" },
1293 { "SPKDAT", NULL, "SPKR PGA" }, 1297 { "SPKDAT", NULL, "SPKR PGA" },
1294 }; 1298 };
1295 1299
1296 static bool wm8996_readable_register(struct d 1300 static bool wm8996_readable_register(struct device *dev, unsigned int reg)
1297 { 1301 {
1298 /* Due to the sparseness of the regis 1302 /* Due to the sparseness of the register map the compiler
1299 * output from an explicit switch sta 1303 * output from an explicit switch statement ends up being much
1300 * more efficient than a table. 1304 * more efficient than a table.
1301 */ 1305 */
1302 switch (reg) { 1306 switch (reg) {
1303 case WM8996_SOFTWARE_RESET: 1307 case WM8996_SOFTWARE_RESET:
1304 case WM8996_POWER_MANAGEMENT_1: 1308 case WM8996_POWER_MANAGEMENT_1:
1305 case WM8996_POWER_MANAGEMENT_2: 1309 case WM8996_POWER_MANAGEMENT_2:
1306 case WM8996_POWER_MANAGEMENT_3: 1310 case WM8996_POWER_MANAGEMENT_3:
1307 case WM8996_POWER_MANAGEMENT_4: 1311 case WM8996_POWER_MANAGEMENT_4:
1308 case WM8996_POWER_MANAGEMENT_5: 1312 case WM8996_POWER_MANAGEMENT_5:
1309 case WM8996_POWER_MANAGEMENT_6: 1313 case WM8996_POWER_MANAGEMENT_6:
1310 case WM8996_POWER_MANAGEMENT_7: 1314 case WM8996_POWER_MANAGEMENT_7:
1311 case WM8996_POWER_MANAGEMENT_8: 1315 case WM8996_POWER_MANAGEMENT_8:
1312 case WM8996_LEFT_LINE_INPUT_VOLUME: 1316 case WM8996_LEFT_LINE_INPUT_VOLUME:
1313 case WM8996_RIGHT_LINE_INPUT_VOLUME: 1317 case WM8996_RIGHT_LINE_INPUT_VOLUME:
1314 case WM8996_LINE_INPUT_CONTROL: 1318 case WM8996_LINE_INPUT_CONTROL:
1315 case WM8996_DAC1_HPOUT1_VOLUME: 1319 case WM8996_DAC1_HPOUT1_VOLUME:
1316 case WM8996_DAC2_HPOUT2_VOLUME: 1320 case WM8996_DAC2_HPOUT2_VOLUME:
1317 case WM8996_DAC1_LEFT_VOLUME: 1321 case WM8996_DAC1_LEFT_VOLUME:
1318 case WM8996_DAC1_RIGHT_VOLUME: 1322 case WM8996_DAC1_RIGHT_VOLUME:
1319 case WM8996_DAC2_LEFT_VOLUME: 1323 case WM8996_DAC2_LEFT_VOLUME:
1320 case WM8996_DAC2_RIGHT_VOLUME: 1324 case WM8996_DAC2_RIGHT_VOLUME:
1321 case WM8996_OUTPUT1_LEFT_VOLUME: 1325 case WM8996_OUTPUT1_LEFT_VOLUME:
1322 case WM8996_OUTPUT1_RIGHT_VOLUME: 1326 case WM8996_OUTPUT1_RIGHT_VOLUME:
1323 case WM8996_OUTPUT2_LEFT_VOLUME: 1327 case WM8996_OUTPUT2_LEFT_VOLUME:
1324 case WM8996_OUTPUT2_RIGHT_VOLUME: 1328 case WM8996_OUTPUT2_RIGHT_VOLUME:
1325 case WM8996_MICBIAS_1: 1329 case WM8996_MICBIAS_1:
1326 case WM8996_MICBIAS_2: 1330 case WM8996_MICBIAS_2:
1327 case WM8996_LDO_1: 1331 case WM8996_LDO_1:
1328 case WM8996_LDO_2: 1332 case WM8996_LDO_2:
1329 case WM8996_ACCESSORY_DETECT_MODE_1: 1333 case WM8996_ACCESSORY_DETECT_MODE_1:
1330 case WM8996_ACCESSORY_DETECT_MODE_2: 1334 case WM8996_ACCESSORY_DETECT_MODE_2:
1331 case WM8996_HEADPHONE_DETECT_1: 1335 case WM8996_HEADPHONE_DETECT_1:
1332 case WM8996_HEADPHONE_DETECT_2: 1336 case WM8996_HEADPHONE_DETECT_2:
1333 case WM8996_MIC_DETECT_1: 1337 case WM8996_MIC_DETECT_1:
1334 case WM8996_MIC_DETECT_2: 1338 case WM8996_MIC_DETECT_2:
1335 case WM8996_MIC_DETECT_3: 1339 case WM8996_MIC_DETECT_3:
1336 case WM8996_CHARGE_PUMP_1: 1340 case WM8996_CHARGE_PUMP_1:
1337 case WM8996_CHARGE_PUMP_2: 1341 case WM8996_CHARGE_PUMP_2:
1338 case WM8996_DC_SERVO_1: 1342 case WM8996_DC_SERVO_1:
1339 case WM8996_DC_SERVO_2: 1343 case WM8996_DC_SERVO_2:
1340 case WM8996_DC_SERVO_3: 1344 case WM8996_DC_SERVO_3:
1341 case WM8996_DC_SERVO_5: 1345 case WM8996_DC_SERVO_5:
1342 case WM8996_DC_SERVO_6: 1346 case WM8996_DC_SERVO_6:
1343 case WM8996_DC_SERVO_7: 1347 case WM8996_DC_SERVO_7:
1344 case WM8996_DC_SERVO_READBACK_0: 1348 case WM8996_DC_SERVO_READBACK_0:
1345 case WM8996_ANALOGUE_HP_1: 1349 case WM8996_ANALOGUE_HP_1:
1346 case WM8996_ANALOGUE_HP_2: 1350 case WM8996_ANALOGUE_HP_2:
1347 case WM8996_CHIP_REVISION: 1351 case WM8996_CHIP_REVISION:
1348 case WM8996_CONTROL_INTERFACE_1: 1352 case WM8996_CONTROL_INTERFACE_1:
1349 case WM8996_WRITE_SEQUENCER_CTRL_1: 1353 case WM8996_WRITE_SEQUENCER_CTRL_1:
1350 case WM8996_WRITE_SEQUENCER_CTRL_2: 1354 case WM8996_WRITE_SEQUENCER_CTRL_2:
1351 case WM8996_AIF_CLOCKING_1: 1355 case WM8996_AIF_CLOCKING_1:
1352 case WM8996_AIF_CLOCKING_2: 1356 case WM8996_AIF_CLOCKING_2:
1353 case WM8996_CLOCKING_1: 1357 case WM8996_CLOCKING_1:
1354 case WM8996_CLOCKING_2: 1358 case WM8996_CLOCKING_2:
1355 case WM8996_AIF_RATE: 1359 case WM8996_AIF_RATE:
1356 case WM8996_FLL_CONTROL_1: 1360 case WM8996_FLL_CONTROL_1:
1357 case WM8996_FLL_CONTROL_2: 1361 case WM8996_FLL_CONTROL_2:
1358 case WM8996_FLL_CONTROL_3: 1362 case WM8996_FLL_CONTROL_3:
1359 case WM8996_FLL_CONTROL_4: 1363 case WM8996_FLL_CONTROL_4:
1360 case WM8996_FLL_CONTROL_5: 1364 case WM8996_FLL_CONTROL_5:
1361 case WM8996_FLL_CONTROL_6: 1365 case WM8996_FLL_CONTROL_6:
1362 case WM8996_FLL_EFS_1: 1366 case WM8996_FLL_EFS_1:
1363 case WM8996_FLL_EFS_2: 1367 case WM8996_FLL_EFS_2:
1364 case WM8996_AIF1_CONTROL: 1368 case WM8996_AIF1_CONTROL:
1365 case WM8996_AIF1_BCLK: 1369 case WM8996_AIF1_BCLK:
1366 case WM8996_AIF1_TX_LRCLK_1: 1370 case WM8996_AIF1_TX_LRCLK_1:
1367 case WM8996_AIF1_TX_LRCLK_2: 1371 case WM8996_AIF1_TX_LRCLK_2:
1368 case WM8996_AIF1_RX_LRCLK_1: 1372 case WM8996_AIF1_RX_LRCLK_1:
1369 case WM8996_AIF1_RX_LRCLK_2: 1373 case WM8996_AIF1_RX_LRCLK_2:
1370 case WM8996_AIF1TX_DATA_CONFIGURATION 1374 case WM8996_AIF1TX_DATA_CONFIGURATION_1:
1371 case WM8996_AIF1TX_DATA_CONFIGURATION 1375 case WM8996_AIF1TX_DATA_CONFIGURATION_2:
1372 case WM8996_AIF1RX_DATA_CONFIGURATION 1376 case WM8996_AIF1RX_DATA_CONFIGURATION:
1373 case WM8996_AIF1TX_CHANNEL_0_CONFIGUR 1377 case WM8996_AIF1TX_CHANNEL_0_CONFIGURATION:
1374 case WM8996_AIF1TX_CHANNEL_1_CONFIGUR 1378 case WM8996_AIF1TX_CHANNEL_1_CONFIGURATION:
1375 case WM8996_AIF1TX_CHANNEL_2_CONFIGUR 1379 case WM8996_AIF1TX_CHANNEL_2_CONFIGURATION:
1376 case WM8996_AIF1TX_CHANNEL_3_CONFIGUR 1380 case WM8996_AIF1TX_CHANNEL_3_CONFIGURATION:
1377 case WM8996_AIF1TX_CHANNEL_4_CONFIGUR 1381 case WM8996_AIF1TX_CHANNEL_4_CONFIGURATION:
1378 case WM8996_AIF1TX_CHANNEL_5_CONFIGUR 1382 case WM8996_AIF1TX_CHANNEL_5_CONFIGURATION:
1379 case WM8996_AIF1RX_CHANNEL_0_CONFIGUR 1383 case WM8996_AIF1RX_CHANNEL_0_CONFIGURATION:
1380 case WM8996_AIF1RX_CHANNEL_1_CONFIGUR 1384 case WM8996_AIF1RX_CHANNEL_1_CONFIGURATION:
1381 case WM8996_AIF1RX_CHANNEL_2_CONFIGUR 1385 case WM8996_AIF1RX_CHANNEL_2_CONFIGURATION:
1382 case WM8996_AIF1RX_CHANNEL_3_CONFIGUR 1386 case WM8996_AIF1RX_CHANNEL_3_CONFIGURATION:
1383 case WM8996_AIF1RX_CHANNEL_4_CONFIGUR 1387 case WM8996_AIF1RX_CHANNEL_4_CONFIGURATION:
1384 case WM8996_AIF1RX_CHANNEL_5_CONFIGUR 1388 case WM8996_AIF1RX_CHANNEL_5_CONFIGURATION:
1385 case WM8996_AIF1RX_MONO_CONFIGURATION 1389 case WM8996_AIF1RX_MONO_CONFIGURATION:
1386 case WM8996_AIF1TX_TEST: 1390 case WM8996_AIF1TX_TEST:
1387 case WM8996_AIF2_CONTROL: 1391 case WM8996_AIF2_CONTROL:
1388 case WM8996_AIF2_BCLK: 1392 case WM8996_AIF2_BCLK:
1389 case WM8996_AIF2_TX_LRCLK_1: 1393 case WM8996_AIF2_TX_LRCLK_1:
1390 case WM8996_AIF2_TX_LRCLK_2: 1394 case WM8996_AIF2_TX_LRCLK_2:
1391 case WM8996_AIF2_RX_LRCLK_1: 1395 case WM8996_AIF2_RX_LRCLK_1:
1392 case WM8996_AIF2_RX_LRCLK_2: 1396 case WM8996_AIF2_RX_LRCLK_2:
1393 case WM8996_AIF2TX_DATA_CONFIGURATION 1397 case WM8996_AIF2TX_DATA_CONFIGURATION_1:
1394 case WM8996_AIF2TX_DATA_CONFIGURATION 1398 case WM8996_AIF2TX_DATA_CONFIGURATION_2:
1395 case WM8996_AIF2RX_DATA_CONFIGURATION 1399 case WM8996_AIF2RX_DATA_CONFIGURATION:
1396 case WM8996_AIF2TX_CHANNEL_0_CONFIGUR 1400 case WM8996_AIF2TX_CHANNEL_0_CONFIGURATION:
1397 case WM8996_AIF2TX_CHANNEL_1_CONFIGUR 1401 case WM8996_AIF2TX_CHANNEL_1_CONFIGURATION:
1398 case WM8996_AIF2RX_CHANNEL_0_CONFIGUR 1402 case WM8996_AIF2RX_CHANNEL_0_CONFIGURATION:
1399 case WM8996_AIF2RX_CHANNEL_1_CONFIGUR 1403 case WM8996_AIF2RX_CHANNEL_1_CONFIGURATION:
1400 case WM8996_AIF2RX_MONO_CONFIGURATION 1404 case WM8996_AIF2RX_MONO_CONFIGURATION:
1401 case WM8996_AIF2TX_TEST: 1405 case WM8996_AIF2TX_TEST:
1402 case WM8996_DSP1_TX_LEFT_VOLUME: 1406 case WM8996_DSP1_TX_LEFT_VOLUME:
1403 case WM8996_DSP1_TX_RIGHT_VOLUME: 1407 case WM8996_DSP1_TX_RIGHT_VOLUME:
1404 case WM8996_DSP1_RX_LEFT_VOLUME: 1408 case WM8996_DSP1_RX_LEFT_VOLUME:
1405 case WM8996_DSP1_RX_RIGHT_VOLUME: 1409 case WM8996_DSP1_RX_RIGHT_VOLUME:
1406 case WM8996_DSP1_TX_FILTERS: 1410 case WM8996_DSP1_TX_FILTERS:
1407 case WM8996_DSP1_RX_FILTERS_1: 1411 case WM8996_DSP1_RX_FILTERS_1:
1408 case WM8996_DSP1_RX_FILTERS_2: 1412 case WM8996_DSP1_RX_FILTERS_2:
1409 case WM8996_DSP1_DRC_1: 1413 case WM8996_DSP1_DRC_1:
1410 case WM8996_DSP1_DRC_2: 1414 case WM8996_DSP1_DRC_2:
1411 case WM8996_DSP1_DRC_3: 1415 case WM8996_DSP1_DRC_3:
1412 case WM8996_DSP1_DRC_4: 1416 case WM8996_DSP1_DRC_4:
1413 case WM8996_DSP1_DRC_5: 1417 case WM8996_DSP1_DRC_5:
1414 case WM8996_DSP1_RX_EQ_GAINS_1: 1418 case WM8996_DSP1_RX_EQ_GAINS_1:
1415 case WM8996_DSP1_RX_EQ_GAINS_2: 1419 case WM8996_DSP1_RX_EQ_GAINS_2:
1416 case WM8996_DSP1_RX_EQ_BAND_1_A: 1420 case WM8996_DSP1_RX_EQ_BAND_1_A:
1417 case WM8996_DSP1_RX_EQ_BAND_1_B: 1421 case WM8996_DSP1_RX_EQ_BAND_1_B:
1418 case WM8996_DSP1_RX_EQ_BAND_1_PG: 1422 case WM8996_DSP1_RX_EQ_BAND_1_PG:
1419 case WM8996_DSP1_RX_EQ_BAND_2_A: 1423 case WM8996_DSP1_RX_EQ_BAND_2_A:
1420 case WM8996_DSP1_RX_EQ_BAND_2_B: 1424 case WM8996_DSP1_RX_EQ_BAND_2_B:
1421 case WM8996_DSP1_RX_EQ_BAND_2_C: 1425 case WM8996_DSP1_RX_EQ_BAND_2_C:
1422 case WM8996_DSP1_RX_EQ_BAND_2_PG: 1426 case WM8996_DSP1_RX_EQ_BAND_2_PG:
1423 case WM8996_DSP1_RX_EQ_BAND_3_A: 1427 case WM8996_DSP1_RX_EQ_BAND_3_A:
1424 case WM8996_DSP1_RX_EQ_BAND_3_B: 1428 case WM8996_DSP1_RX_EQ_BAND_3_B:
1425 case WM8996_DSP1_RX_EQ_BAND_3_C: 1429 case WM8996_DSP1_RX_EQ_BAND_3_C:
1426 case WM8996_DSP1_RX_EQ_BAND_3_PG: 1430 case WM8996_DSP1_RX_EQ_BAND_3_PG:
1427 case WM8996_DSP1_RX_EQ_BAND_4_A: 1431 case WM8996_DSP1_RX_EQ_BAND_4_A:
1428 case WM8996_DSP1_RX_EQ_BAND_4_B: 1432 case WM8996_DSP1_RX_EQ_BAND_4_B:
1429 case WM8996_DSP1_RX_EQ_BAND_4_C: 1433 case WM8996_DSP1_RX_EQ_BAND_4_C:
1430 case WM8996_DSP1_RX_EQ_BAND_4_PG: 1434 case WM8996_DSP1_RX_EQ_BAND_4_PG:
1431 case WM8996_DSP1_RX_EQ_BAND_5_A: 1435 case WM8996_DSP1_RX_EQ_BAND_5_A:
1432 case WM8996_DSP1_RX_EQ_BAND_5_B: 1436 case WM8996_DSP1_RX_EQ_BAND_5_B:
1433 case WM8996_DSP1_RX_EQ_BAND_5_PG: 1437 case WM8996_DSP1_RX_EQ_BAND_5_PG:
1434 case WM8996_DSP2_TX_LEFT_VOLUME: 1438 case WM8996_DSP2_TX_LEFT_VOLUME:
1435 case WM8996_DSP2_TX_RIGHT_VOLUME: 1439 case WM8996_DSP2_TX_RIGHT_VOLUME:
1436 case WM8996_DSP2_RX_LEFT_VOLUME: 1440 case WM8996_DSP2_RX_LEFT_VOLUME:
1437 case WM8996_DSP2_RX_RIGHT_VOLUME: 1441 case WM8996_DSP2_RX_RIGHT_VOLUME:
1438 case WM8996_DSP2_TX_FILTERS: 1442 case WM8996_DSP2_TX_FILTERS:
1439 case WM8996_DSP2_RX_FILTERS_1: 1443 case WM8996_DSP2_RX_FILTERS_1:
1440 case WM8996_DSP2_RX_FILTERS_2: 1444 case WM8996_DSP2_RX_FILTERS_2:
1441 case WM8996_DSP2_DRC_1: 1445 case WM8996_DSP2_DRC_1:
1442 case WM8996_DSP2_DRC_2: 1446 case WM8996_DSP2_DRC_2:
1443 case WM8996_DSP2_DRC_3: 1447 case WM8996_DSP2_DRC_3:
1444 case WM8996_DSP2_DRC_4: 1448 case WM8996_DSP2_DRC_4:
1445 case WM8996_DSP2_DRC_5: 1449 case WM8996_DSP2_DRC_5:
1446 case WM8996_DSP2_RX_EQ_GAINS_1: 1450 case WM8996_DSP2_RX_EQ_GAINS_1:
1447 case WM8996_DSP2_RX_EQ_GAINS_2: 1451 case WM8996_DSP2_RX_EQ_GAINS_2:
1448 case WM8996_DSP2_RX_EQ_BAND_1_A: 1452 case WM8996_DSP2_RX_EQ_BAND_1_A:
1449 case WM8996_DSP2_RX_EQ_BAND_1_B: 1453 case WM8996_DSP2_RX_EQ_BAND_1_B:
1450 case WM8996_DSP2_RX_EQ_BAND_1_PG: 1454 case WM8996_DSP2_RX_EQ_BAND_1_PG:
1451 case WM8996_DSP2_RX_EQ_BAND_2_A: 1455 case WM8996_DSP2_RX_EQ_BAND_2_A:
1452 case WM8996_DSP2_RX_EQ_BAND_2_B: 1456 case WM8996_DSP2_RX_EQ_BAND_2_B:
1453 case WM8996_DSP2_RX_EQ_BAND_2_C: 1457 case WM8996_DSP2_RX_EQ_BAND_2_C:
1454 case WM8996_DSP2_RX_EQ_BAND_2_PG: 1458 case WM8996_DSP2_RX_EQ_BAND_2_PG:
1455 case WM8996_DSP2_RX_EQ_BAND_3_A: 1459 case WM8996_DSP2_RX_EQ_BAND_3_A:
1456 case WM8996_DSP2_RX_EQ_BAND_3_B: 1460 case WM8996_DSP2_RX_EQ_BAND_3_B:
1457 case WM8996_DSP2_RX_EQ_BAND_3_C: 1461 case WM8996_DSP2_RX_EQ_BAND_3_C:
1458 case WM8996_DSP2_RX_EQ_BAND_3_PG: 1462 case WM8996_DSP2_RX_EQ_BAND_3_PG:
1459 case WM8996_DSP2_RX_EQ_BAND_4_A: 1463 case WM8996_DSP2_RX_EQ_BAND_4_A:
1460 case WM8996_DSP2_RX_EQ_BAND_4_B: 1464 case WM8996_DSP2_RX_EQ_BAND_4_B:
1461 case WM8996_DSP2_RX_EQ_BAND_4_C: 1465 case WM8996_DSP2_RX_EQ_BAND_4_C:
1462 case WM8996_DSP2_RX_EQ_BAND_4_PG: 1466 case WM8996_DSP2_RX_EQ_BAND_4_PG:
1463 case WM8996_DSP2_RX_EQ_BAND_5_A: 1467 case WM8996_DSP2_RX_EQ_BAND_5_A:
1464 case WM8996_DSP2_RX_EQ_BAND_5_B: 1468 case WM8996_DSP2_RX_EQ_BAND_5_B:
1465 case WM8996_DSP2_RX_EQ_BAND_5_PG: 1469 case WM8996_DSP2_RX_EQ_BAND_5_PG:
1466 case WM8996_DAC1_MIXER_VOLUMES: 1470 case WM8996_DAC1_MIXER_VOLUMES:
1467 case WM8996_DAC1_LEFT_MIXER_ROUTING: 1471 case WM8996_DAC1_LEFT_MIXER_ROUTING:
1468 case WM8996_DAC1_RIGHT_MIXER_ROUTING: 1472 case WM8996_DAC1_RIGHT_MIXER_ROUTING:
1469 case WM8996_DAC2_MIXER_VOLUMES: 1473 case WM8996_DAC2_MIXER_VOLUMES:
1470 case WM8996_DAC2_LEFT_MIXER_ROUTING: 1474 case WM8996_DAC2_LEFT_MIXER_ROUTING:
1471 case WM8996_DAC2_RIGHT_MIXER_ROUTING: 1475 case WM8996_DAC2_RIGHT_MIXER_ROUTING:
1472 case WM8996_DSP1_TX_LEFT_MIXER_ROUTIN 1476 case WM8996_DSP1_TX_LEFT_MIXER_ROUTING:
1473 case WM8996_DSP1_TX_RIGHT_MIXER_ROUTI 1477 case WM8996_DSP1_TX_RIGHT_MIXER_ROUTING:
1474 case WM8996_DSP2_TX_LEFT_MIXER_ROUTIN 1478 case WM8996_DSP2_TX_LEFT_MIXER_ROUTING:
1475 case WM8996_DSP2_TX_RIGHT_MIXER_ROUTI 1479 case WM8996_DSP2_TX_RIGHT_MIXER_ROUTING:
1476 case WM8996_DSP_TX_MIXER_SELECT: 1480 case WM8996_DSP_TX_MIXER_SELECT:
1477 case WM8996_DAC_SOFTMUTE: 1481 case WM8996_DAC_SOFTMUTE:
1478 case WM8996_OVERSAMPLING: 1482 case WM8996_OVERSAMPLING:
1479 case WM8996_SIDETONE: 1483 case WM8996_SIDETONE:
1480 case WM8996_GPIO_1: 1484 case WM8996_GPIO_1:
1481 case WM8996_GPIO_2: 1485 case WM8996_GPIO_2:
1482 case WM8996_GPIO_3: 1486 case WM8996_GPIO_3:
1483 case WM8996_GPIO_4: 1487 case WM8996_GPIO_4:
1484 case WM8996_GPIO_5: 1488 case WM8996_GPIO_5:
1485 case WM8996_PULL_CONTROL_1: 1489 case WM8996_PULL_CONTROL_1:
1486 case WM8996_PULL_CONTROL_2: 1490 case WM8996_PULL_CONTROL_2:
1487 case WM8996_INTERRUPT_STATUS_1: 1491 case WM8996_INTERRUPT_STATUS_1:
1488 case WM8996_INTERRUPT_STATUS_2: 1492 case WM8996_INTERRUPT_STATUS_2:
1489 case WM8996_INTERRUPT_RAW_STATUS_2: 1493 case WM8996_INTERRUPT_RAW_STATUS_2:
1490 case WM8996_INTERRUPT_STATUS_1_MASK: 1494 case WM8996_INTERRUPT_STATUS_1_MASK:
1491 case WM8996_INTERRUPT_STATUS_2_MASK: 1495 case WM8996_INTERRUPT_STATUS_2_MASK:
1492 case WM8996_INTERRUPT_CONTROL: 1496 case WM8996_INTERRUPT_CONTROL:
1493 case WM8996_LEFT_PDM_SPEAKER: 1497 case WM8996_LEFT_PDM_SPEAKER:
1494 case WM8996_RIGHT_PDM_SPEAKER: 1498 case WM8996_RIGHT_PDM_SPEAKER:
1495 case WM8996_PDM_SPEAKER_MUTE_SEQUENCE 1499 case WM8996_PDM_SPEAKER_MUTE_SEQUENCE:
1496 case WM8996_PDM_SPEAKER_VOLUME: 1500 case WM8996_PDM_SPEAKER_VOLUME:
1497 return true; !! 1501 return 1;
1498 default: 1502 default:
1499 return false; !! 1503 return 0;
1500 } 1504 }
1501 } 1505 }
1502 1506
1503 static bool wm8996_volatile_register(struct d 1507 static bool wm8996_volatile_register(struct device *dev, unsigned int reg)
1504 { 1508 {
1505 switch (reg) { 1509 switch (reg) {
1506 case WM8996_SOFTWARE_RESET: 1510 case WM8996_SOFTWARE_RESET:
1507 case WM8996_CHIP_REVISION: 1511 case WM8996_CHIP_REVISION:
1508 case WM8996_LDO_1: 1512 case WM8996_LDO_1:
1509 case WM8996_LDO_2: 1513 case WM8996_LDO_2:
1510 case WM8996_INTERRUPT_STATUS_1: 1514 case WM8996_INTERRUPT_STATUS_1:
1511 case WM8996_INTERRUPT_STATUS_2: 1515 case WM8996_INTERRUPT_STATUS_2:
1512 case WM8996_INTERRUPT_RAW_STATUS_2: 1516 case WM8996_INTERRUPT_RAW_STATUS_2:
1513 case WM8996_DC_SERVO_READBACK_0: 1517 case WM8996_DC_SERVO_READBACK_0:
1514 case WM8996_DC_SERVO_2: 1518 case WM8996_DC_SERVO_2:
1515 case WM8996_DC_SERVO_6: 1519 case WM8996_DC_SERVO_6:
1516 case WM8996_DC_SERVO_7: 1520 case WM8996_DC_SERVO_7:
1517 case WM8996_FLL_CONTROL_6: 1521 case WM8996_FLL_CONTROL_6:
1518 case WM8996_MIC_DETECT_3: 1522 case WM8996_MIC_DETECT_3:
1519 case WM8996_HEADPHONE_DETECT_1: 1523 case WM8996_HEADPHONE_DETECT_1:
1520 case WM8996_HEADPHONE_DETECT_2: 1524 case WM8996_HEADPHONE_DETECT_2:
1521 return true; !! 1525 return 1;
1522 default: 1526 default:
1523 return false; !! 1527 return 0;
1524 } 1528 }
1525 } 1529 }
1526 1530
1527 static const int bclk_divs[] = { 1531 static const int bclk_divs[] = {
1528 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 1532 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96
1529 }; 1533 };
1530 1534
1531 static void wm8996_update_bclk(struct snd_soc !! 1535 static void wm8996_update_bclk(struct snd_soc_codec *codec)
1532 { 1536 {
1533 struct wm8996_priv *wm8996 = snd_soc_ !! 1537 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1534 int aif, best, cur_val, bclk_rate, bc 1538 int aif, best, cur_val, bclk_rate, bclk_reg, i;
1535 1539
1536 /* Don't bother if we're in a low fre 1540 /* Don't bother if we're in a low frequency idle mode that
1537 * can't support audio. 1541 * can't support audio.
1538 */ 1542 */
1539 if (wm8996->sysclk < 64000) 1543 if (wm8996->sysclk < 64000)
1540 return; 1544 return;
1541 1545
1542 for (aif = 0; aif < WM8996_AIFS; aif+ 1546 for (aif = 0; aif < WM8996_AIFS; aif++) {
1543 switch (aif) { 1547 switch (aif) {
1544 case 0: 1548 case 0:
1545 bclk_reg = WM8996_AIF 1549 bclk_reg = WM8996_AIF1_BCLK;
1546 break; 1550 break;
1547 case 1: 1551 case 1:
1548 bclk_reg = WM8996_AIF 1552 bclk_reg = WM8996_AIF2_BCLK;
1549 break; 1553 break;
1550 } 1554 }
1551 1555
1552 bclk_rate = wm8996->bclk_rate 1556 bclk_rate = wm8996->bclk_rate[aif];
1553 1557
1554 /* Pick a divisor for BCLK as 1558 /* Pick a divisor for BCLK as close as we can get to ideal */
1555 best = 0; 1559 best = 0;
1556 for (i = 0; i < ARRAY_SIZE(bc 1560 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1557 cur_val = (wm8996->sy 1561 cur_val = (wm8996->sysclk / bclk_divs[i]) - bclk_rate;
1558 if (cur_val < 0) /* B 1562 if (cur_val < 0) /* BCLK table is sorted */
1559 break; 1563 break;
1560 best = i; 1564 best = i;
1561 } 1565 }
1562 bclk_rate = wm8996->sysclk / 1566 bclk_rate = wm8996->sysclk / bclk_divs[best];
1563 dev_dbg(component->dev, "Usin !! 1567 dev_dbg(codec->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1564 bclk_divs[best], bclk 1568 bclk_divs[best], bclk_rate);
1565 1569
1566 snd_soc_component_update_bits !! 1570 snd_soc_update_bits(codec, bclk_reg,
1567 WM8996_AI 1571 WM8996_AIF1_BCLK_DIV_MASK, best);
1568 } 1572 }
1569 } 1573 }
1570 1574
1571 static int wm8996_set_bias_level(struct snd_s !! 1575 static int wm8996_set_bias_level(struct snd_soc_codec *codec,
1572 enum snd_soc 1576 enum snd_soc_bias_level level)
1573 { 1577 {
1574 struct wm8996_priv *wm8996 = snd_soc_ !! 1578 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1575 int ret; 1579 int ret;
1576 1580
1577 switch (level) { 1581 switch (level) {
1578 case SND_SOC_BIAS_ON: 1582 case SND_SOC_BIAS_ON:
1579 break; 1583 break;
1580 case SND_SOC_BIAS_PREPARE: 1584 case SND_SOC_BIAS_PREPARE:
1581 /* Put the MICBIASes into reg 1585 /* Put the MICBIASes into regulating mode */
1582 snd_soc_component_update_bits !! 1586 snd_soc_update_bits(codec, WM8996_MICBIAS_1,
1583 WM8996_MI 1587 WM8996_MICB1_MODE, 0);
1584 snd_soc_component_update_bits !! 1588 snd_soc_update_bits(codec, WM8996_MICBIAS_2,
1585 WM8996_MI 1589 WM8996_MICB2_MODE, 0);
1586 break; 1590 break;
1587 1591
1588 case SND_SOC_BIAS_STANDBY: 1592 case SND_SOC_BIAS_STANDBY:
1589 if (snd_soc_component_get_bia !! 1593 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
1590 ret = regulator_bulk_ 1594 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
1591 1595 wm8996->supplies);
1592 if (ret != 0) { 1596 if (ret != 0) {
1593 dev_err(compo !! 1597 dev_err(codec->dev,
1594 "Fail 1598 "Failed to enable supplies: %d\n",
1595 ret); 1599 ret);
1596 return ret; 1600 return ret;
1597 } 1601 }
1598 1602
1599 if (wm8996->ldo_ena) !! 1603 if (wm8996->pdata.ldo_ena >= 0) {
1600 gpiod_set_val !! 1604 gpio_set_value_cansleep(wm8996->pdata.ldo_ena,
1601 !! 1605 1);
1602 msleep(5); 1606 msleep(5);
1603 } 1607 }
1604 1608
1605 regcache_cache_only(w 1609 regcache_cache_only(wm8996->regmap, false);
1606 regcache_sync(wm8996- 1610 regcache_sync(wm8996->regmap);
1607 } 1611 }
1608 1612
1609 /* Bypass the MICBIASes for l 1613 /* Bypass the MICBIASes for lowest power */
1610 snd_soc_component_update_bits !! 1614 snd_soc_update_bits(codec, WM8996_MICBIAS_1,
1611 WM8996_MI 1615 WM8996_MICB1_MODE, WM8996_MICB1_MODE);
1612 snd_soc_component_update_bits !! 1616 snd_soc_update_bits(codec, WM8996_MICBIAS_2,
1613 WM8996_MI 1617 WM8996_MICB2_MODE, WM8996_MICB2_MODE);
1614 break; 1618 break;
1615 1619
1616 case SND_SOC_BIAS_OFF: 1620 case SND_SOC_BIAS_OFF:
1617 regcache_cache_only(wm8996->r 1621 regcache_cache_only(wm8996->regmap, true);
1618 if (wm8996->ldo_ena) { !! 1622 if (wm8996->pdata.ldo_ena >= 0) {
1619 gpiod_set_value_cansl !! 1623 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
1620 regcache_cache_only(w 1624 regcache_cache_only(wm8996->regmap, true);
1621 } 1625 }
1622 regulator_bulk_disable(ARRAY_ 1626 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies),
1623 wm8996 1627 wm8996->supplies);
1624 break; 1628 break;
1625 } 1629 }
1626 1630
1627 return 0; 1631 return 0;
1628 } 1632 }
1629 1633
1630 static int wm8996_set_fmt(struct snd_soc_dai 1634 static int wm8996_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1631 { 1635 {
1632 struct snd_soc_component *component = !! 1636 struct snd_soc_codec *codec = dai->codec;
1633 int aifctrl = 0; 1637 int aifctrl = 0;
1634 int bclk = 0; 1638 int bclk = 0;
1635 int lrclk_tx = 0; 1639 int lrclk_tx = 0;
1636 int lrclk_rx = 0; 1640 int lrclk_rx = 0;
1637 int aifctrl_reg, bclk_reg, lrclk_tx_r 1641 int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg;
1638 1642
1639 switch (dai->id) { 1643 switch (dai->id) {
1640 case 0: 1644 case 0:
1641 aifctrl_reg = WM8996_AIF1_CON 1645 aifctrl_reg = WM8996_AIF1_CONTROL;
1642 bclk_reg = WM8996_AIF1_BCLK; 1646 bclk_reg = WM8996_AIF1_BCLK;
1643 lrclk_tx_reg = WM8996_AIF1_TX 1647 lrclk_tx_reg = WM8996_AIF1_TX_LRCLK_2;
1644 lrclk_rx_reg = WM8996_AIF1_RX 1648 lrclk_rx_reg = WM8996_AIF1_RX_LRCLK_2;
1645 break; 1649 break;
1646 case 1: 1650 case 1:
1647 aifctrl_reg = WM8996_AIF2_CON 1651 aifctrl_reg = WM8996_AIF2_CONTROL;
1648 bclk_reg = WM8996_AIF2_BCLK; 1652 bclk_reg = WM8996_AIF2_BCLK;
1649 lrclk_tx_reg = WM8996_AIF2_TX 1653 lrclk_tx_reg = WM8996_AIF2_TX_LRCLK_2;
1650 lrclk_rx_reg = WM8996_AIF2_RX 1654 lrclk_rx_reg = WM8996_AIF2_RX_LRCLK_2;
1651 break; 1655 break;
1652 default: 1656 default:
1653 WARN(1, "Invalid dai id %d\n" 1657 WARN(1, "Invalid dai id %d\n", dai->id);
1654 return -EINVAL; 1658 return -EINVAL;
1655 } 1659 }
1656 1660
1657 switch (fmt & SND_SOC_DAIFMT_INV_MASK 1661 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1658 case SND_SOC_DAIFMT_NB_NF: 1662 case SND_SOC_DAIFMT_NB_NF:
1659 break; 1663 break;
1660 case SND_SOC_DAIFMT_IB_NF: 1664 case SND_SOC_DAIFMT_IB_NF:
1661 bclk |= WM8996_AIF1_BCLK_INV; 1665 bclk |= WM8996_AIF1_BCLK_INV;
1662 break; 1666 break;
1663 case SND_SOC_DAIFMT_NB_IF: 1667 case SND_SOC_DAIFMT_NB_IF:
1664 lrclk_tx |= WM8996_AIF1TX_LRC 1668 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1665 lrclk_rx |= WM8996_AIF1RX_LRC 1669 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1666 break; 1670 break;
1667 case SND_SOC_DAIFMT_IB_IF: 1671 case SND_SOC_DAIFMT_IB_IF:
1668 bclk |= WM8996_AIF1_BCLK_INV; 1672 bclk |= WM8996_AIF1_BCLK_INV;
1669 lrclk_tx |= WM8996_AIF1TX_LRC 1673 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1670 lrclk_rx |= WM8996_AIF1RX_LRC 1674 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1671 break; 1675 break;
1672 } 1676 }
1673 1677
1674 switch (fmt & SND_SOC_DAIFMT_MASTER_M 1678 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1675 case SND_SOC_DAIFMT_CBS_CFS: 1679 case SND_SOC_DAIFMT_CBS_CFS:
1676 break; 1680 break;
1677 case SND_SOC_DAIFMT_CBS_CFM: 1681 case SND_SOC_DAIFMT_CBS_CFM:
1678 lrclk_tx |= WM8996_AIF1TX_LRC 1682 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1679 lrclk_rx |= WM8996_AIF1RX_LRC 1683 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1680 break; 1684 break;
1681 case SND_SOC_DAIFMT_CBM_CFS: 1685 case SND_SOC_DAIFMT_CBM_CFS:
1682 bclk |= WM8996_AIF1_BCLK_MSTR 1686 bclk |= WM8996_AIF1_BCLK_MSTR;
1683 break; 1687 break;
1684 case SND_SOC_DAIFMT_CBM_CFM: 1688 case SND_SOC_DAIFMT_CBM_CFM:
1685 bclk |= WM8996_AIF1_BCLK_MSTR 1689 bclk |= WM8996_AIF1_BCLK_MSTR;
1686 lrclk_tx |= WM8996_AIF1TX_LRC 1690 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1687 lrclk_rx |= WM8996_AIF1RX_LRC 1691 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1688 break; 1692 break;
1689 default: 1693 default:
1690 return -EINVAL; 1694 return -EINVAL;
1691 } 1695 }
1692 1696
1693 switch (fmt & SND_SOC_DAIFMT_FORMAT_M 1697 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1694 case SND_SOC_DAIFMT_DSP_A: 1698 case SND_SOC_DAIFMT_DSP_A:
1695 break; 1699 break;
1696 case SND_SOC_DAIFMT_DSP_B: 1700 case SND_SOC_DAIFMT_DSP_B:
1697 aifctrl |= 1; 1701 aifctrl |= 1;
1698 break; 1702 break;
1699 case SND_SOC_DAIFMT_I2S: 1703 case SND_SOC_DAIFMT_I2S:
1700 aifctrl |= 2; 1704 aifctrl |= 2;
1701 break; 1705 break;
1702 case SND_SOC_DAIFMT_LEFT_J: 1706 case SND_SOC_DAIFMT_LEFT_J:
1703 aifctrl |= 3; 1707 aifctrl |= 3;
1704 break; 1708 break;
1705 default: 1709 default:
1706 return -EINVAL; 1710 return -EINVAL;
1707 } 1711 }
1708 1712
1709 snd_soc_component_update_bits(compone !! 1713 snd_soc_update_bits(codec, aifctrl_reg, WM8996_AIF1_FMT_MASK, aifctrl);
1710 snd_soc_component_update_bits(compone !! 1714 snd_soc_update_bits(codec, bclk_reg,
1711 WM8996_AIF1_BCLK_ 1715 WM8996_AIF1_BCLK_INV | WM8996_AIF1_BCLK_MSTR,
1712 bclk); 1716 bclk);
1713 snd_soc_component_update_bits(compone !! 1717 snd_soc_update_bits(codec, lrclk_tx_reg,
1714 WM8996_AIF1TX_LRC 1718 WM8996_AIF1TX_LRCLK_INV |
1715 WM8996_AIF1TX_LRC 1719 WM8996_AIF1TX_LRCLK_MSTR,
1716 lrclk_tx); 1720 lrclk_tx);
1717 snd_soc_component_update_bits(compone !! 1721 snd_soc_update_bits(codec, lrclk_rx_reg,
1718 WM8996_AIF1RX_LRC 1722 WM8996_AIF1RX_LRCLK_INV |
1719 WM8996_AIF1RX_LRC 1723 WM8996_AIF1RX_LRCLK_MSTR,
1720 lrclk_rx); 1724 lrclk_rx);
1721 1725
1722 return 0; 1726 return 0;
1723 } 1727 }
1724 1728
1725 static const int dsp_divs[] = { 1729 static const int dsp_divs[] = {
1726 48000, 32000, 16000, 8000 1730 48000, 32000, 16000, 8000
1727 }; 1731 };
1728 1732
1729 static int wm8996_hw_params(struct snd_pcm_su 1733 static int wm8996_hw_params(struct snd_pcm_substream *substream,
1730 struct snd_pcm_hw 1734 struct snd_pcm_hw_params *params,
1731 struct snd_soc_da 1735 struct snd_soc_dai *dai)
1732 { 1736 {
1733 struct snd_soc_component *component = !! 1737 struct snd_soc_codec *codec = dai->codec;
1734 struct wm8996_priv *wm8996 = snd_soc_ !! 1738 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1735 int bits, i, bclk_rate, best; 1739 int bits, i, bclk_rate, best;
1736 int aifdata = 0; 1740 int aifdata = 0;
1737 int lrclk = 0; 1741 int lrclk = 0;
1738 int dsp = 0; 1742 int dsp = 0;
1739 int aifdata_reg, lrclk_reg, dsp_shift 1743 int aifdata_reg, lrclk_reg, dsp_shift;
1740 1744
1741 switch (dai->id) { 1745 switch (dai->id) {
1742 case 0: 1746 case 0:
1743 if (substream->stream == SNDR 1747 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1744 (snd_soc_component_read(c !! 1748 (snd_soc_read(codec, WM8996_GPIO_1)) & WM8996_GP1_FN_MASK) {
1745 aifdata_reg = WM8996_ 1749 aifdata_reg = WM8996_AIF1RX_DATA_CONFIGURATION;
1746 lrclk_reg = WM8996_AI 1750 lrclk_reg = WM8996_AIF1_RX_LRCLK_1;
1747 } else { 1751 } else {
1748 aifdata_reg = WM8996_ 1752 aifdata_reg = WM8996_AIF1TX_DATA_CONFIGURATION_1;
1749 lrclk_reg = WM8996_AI 1753 lrclk_reg = WM8996_AIF1_TX_LRCLK_1;
1750 } 1754 }
1751 dsp_shift = 0; 1755 dsp_shift = 0;
1752 break; 1756 break;
1753 case 1: 1757 case 1:
1754 if (substream->stream == SNDR 1758 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1755 (snd_soc_component_read(c !! 1759 (snd_soc_read(codec, WM8996_GPIO_2)) & WM8996_GP2_FN_MASK) {
1756 aifdata_reg = WM8996_ 1760 aifdata_reg = WM8996_AIF2RX_DATA_CONFIGURATION;
1757 lrclk_reg = WM8996_AI 1761 lrclk_reg = WM8996_AIF2_RX_LRCLK_1;
1758 } else { 1762 } else {
1759 aifdata_reg = WM8996_ 1763 aifdata_reg = WM8996_AIF2TX_DATA_CONFIGURATION_1;
1760 lrclk_reg = WM8996_AI 1764 lrclk_reg = WM8996_AIF2_TX_LRCLK_1;
1761 } 1765 }
1762 dsp_shift = WM8996_DSP2_DIV_S 1766 dsp_shift = WM8996_DSP2_DIV_SHIFT;
1763 break; 1767 break;
1764 default: 1768 default:
1765 WARN(1, "Invalid dai id %d\n" 1769 WARN(1, "Invalid dai id %d\n", dai->id);
1766 return -EINVAL; 1770 return -EINVAL;
1767 } 1771 }
1768 1772
1769 bclk_rate = snd_soc_params_to_bclk(pa 1773 bclk_rate = snd_soc_params_to_bclk(params);
1770 if (bclk_rate < 0) { 1774 if (bclk_rate < 0) {
1771 dev_err(component->dev, "Unsu !! 1775 dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate);
1772 return bclk_rate; 1776 return bclk_rate;
1773 } 1777 }
1774 1778
1775 wm8996->bclk_rate[dai->id] = bclk_rat 1779 wm8996->bclk_rate[dai->id] = bclk_rate;
1776 wm8996->rx_rate[dai->id] = params_rat 1780 wm8996->rx_rate[dai->id] = params_rate(params);
1777 1781
1778 /* Needs looking at for TDM */ 1782 /* Needs looking at for TDM */
1779 bits = params_width(params); 1783 bits = params_width(params);
1780 if (bits < 0) 1784 if (bits < 0)
1781 return bits; 1785 return bits;
1782 aifdata |= (bits << WM8996_AIF1TX_WL_ 1786 aifdata |= (bits << WM8996_AIF1TX_WL_SHIFT) | bits;
1783 1787
1784 best = 0; 1788 best = 0;
1785 for (i = 0; i < ARRAY_SIZE(dsp_divs); 1789 for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) {
1786 if (abs(dsp_divs[i] - params_ 1790 if (abs(dsp_divs[i] - params_rate(params)) <
1787 abs(dsp_divs[best] - para 1791 abs(dsp_divs[best] - params_rate(params)))
1788 best = i; 1792 best = i;
1789 } 1793 }
1790 dsp |= i << dsp_shift; 1794 dsp |= i << dsp_shift;
1791 1795
1792 wm8996_update_bclk(component); !! 1796 wm8996_update_bclk(codec);
1793 1797
1794 lrclk = bclk_rate / params_rate(param 1798 lrclk = bclk_rate / params_rate(params);
1795 dev_dbg(dai->dev, "Using LRCLK rate % 1799 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1796 lrclk, bclk_rate / lrclk); 1800 lrclk, bclk_rate / lrclk);
1797 1801
1798 snd_soc_component_update_bits(compone !! 1802 snd_soc_update_bits(codec, aifdata_reg,
1799 WM8996_AIF1TX_WL_ 1803 WM8996_AIF1TX_WL_MASK |
1800 WM8996_AIF1TX_SLO 1804 WM8996_AIF1TX_SLOT_LEN_MASK,
1801 aifdata); 1805 aifdata);
1802 snd_soc_component_update_bits(compone !! 1806 snd_soc_update_bits(codec, lrclk_reg, WM8996_AIF1RX_RATE_MASK,
1803 lrclk); 1807 lrclk);
1804 snd_soc_component_update_bits(compone !! 1808 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_2,
1805 WM8996_DSP1_DIV_M 1809 WM8996_DSP1_DIV_MASK << dsp_shift, dsp);
1806 1810
1807 return 0; 1811 return 0;
1808 } 1812 }
1809 1813
1810 static int wm8996_set_sysclk(struct snd_soc_d 1814 static int wm8996_set_sysclk(struct snd_soc_dai *dai,
1811 int clk_id, unsigned int freq 1815 int clk_id, unsigned int freq, int dir)
1812 { 1816 {
1813 struct snd_soc_component *component = !! 1817 struct snd_soc_codec *codec = dai->codec;
1814 struct wm8996_priv *wm8996 = snd_soc_ !! 1818 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1815 int lfclk = 0; 1819 int lfclk = 0;
1816 int ratediv = 0; 1820 int ratediv = 0;
1817 int sync = WM8996_REG_SYNC; 1821 int sync = WM8996_REG_SYNC;
1818 int src; 1822 int src;
1819 int old; 1823 int old;
1820 1824
1821 if (freq == wm8996->sysclk && clk_id 1825 if (freq == wm8996->sysclk && clk_id == wm8996->sysclk_src)
1822 return 0; 1826 return 0;
1823 1827
1824 /* Disable SYSCLK while we reconfigur 1828 /* Disable SYSCLK while we reconfigure */
1825 old = snd_soc_component_read(componen !! 1829 old = snd_soc_read(codec, WM8996_AIF_CLOCKING_1) & WM8996_SYSCLK_ENA;
1826 snd_soc_component_update_bits(compone !! 1830 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
1827 WM8996_SYSCLK_ENA 1831 WM8996_SYSCLK_ENA, 0);
1828 1832
1829 switch (clk_id) { 1833 switch (clk_id) {
1830 case WM8996_SYSCLK_MCLK1: 1834 case WM8996_SYSCLK_MCLK1:
1831 wm8996->sysclk = freq; 1835 wm8996->sysclk = freq;
1832 src = 0; 1836 src = 0;
1833 break; 1837 break;
1834 case WM8996_SYSCLK_MCLK2: 1838 case WM8996_SYSCLK_MCLK2:
1835 wm8996->sysclk = freq; 1839 wm8996->sysclk = freq;
1836 src = 1; 1840 src = 1;
1837 break; 1841 break;
1838 case WM8996_SYSCLK_FLL: 1842 case WM8996_SYSCLK_FLL:
1839 wm8996->sysclk = freq; 1843 wm8996->sysclk = freq;
1840 src = 2; 1844 src = 2;
1841 break; 1845 break;
1842 default: 1846 default:
1843 dev_err(component->dev, "Unsu !! 1847 dev_err(codec->dev, "Unsupported clock source %d\n", clk_id);
1844 return -EINVAL; 1848 return -EINVAL;
1845 } 1849 }
1846 1850
1847 switch (wm8996->sysclk) { 1851 switch (wm8996->sysclk) {
1848 case 5644800: 1852 case 5644800:
1849 case 6144000: 1853 case 6144000:
1850 snd_soc_component_update_bits !! 1854 snd_soc_update_bits(codec, WM8996_AIF_RATE,
1851 WM8996_SY 1855 WM8996_SYSCLK_RATE, 0);
1852 break; 1856 break;
1853 case 22579200: 1857 case 22579200:
1854 case 24576000: 1858 case 24576000:
1855 ratediv = WM8996_SYSCLK_DIV; 1859 ratediv = WM8996_SYSCLK_DIV;
1856 wm8996->sysclk /= 2; 1860 wm8996->sysclk /= 2;
1857 fallthrough; <<
1858 case 11289600: 1861 case 11289600:
1859 case 12288000: 1862 case 12288000:
1860 snd_soc_component_update_bits !! 1863 snd_soc_update_bits(codec, WM8996_AIF_RATE,
1861 WM8996_SY 1864 WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE);
1862 break; 1865 break;
1863 case 32000: 1866 case 32000:
1864 case 32768: 1867 case 32768:
1865 lfclk = WM8996_LFCLK_ENA; 1868 lfclk = WM8996_LFCLK_ENA;
1866 sync = 0; 1869 sync = 0;
1867 break; 1870 break;
1868 default: 1871 default:
1869 dev_warn(component->dev, "Uns !! 1872 dev_warn(codec->dev, "Unsupported clock rate %dHz\n",
1870 wm8996->sysclk); 1873 wm8996->sysclk);
1871 return -EINVAL; 1874 return -EINVAL;
1872 } 1875 }
1873 1876
1874 wm8996_update_bclk(component); !! 1877 wm8996_update_bclk(codec);
1875 1878
1876 snd_soc_component_update_bits(compone !! 1879 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
1877 WM8996_SYSCLK_SRC 1880 WM8996_SYSCLK_SRC_MASK | WM8996_SYSCLK_DIV_MASK,
1878 src << WM8996_SYS 1881 src << WM8996_SYSCLK_SRC_SHIFT | ratediv);
1879 snd_soc_component_update_bits(compone !! 1882 snd_soc_update_bits(codec, WM8996_CLOCKING_1, WM8996_LFCLK_ENA, lfclk);
1880 snd_soc_component_update_bits(compone !! 1883 snd_soc_update_bits(codec, WM8996_CONTROL_INTERFACE_1,
1881 WM8996_REG_SYNC, 1884 WM8996_REG_SYNC, sync);
1882 snd_soc_component_update_bits(compone !! 1885 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
1883 WM8996_SYSCLK_ENA 1886 WM8996_SYSCLK_ENA, old);
1884 1887
1885 wm8996->sysclk_src = clk_id; 1888 wm8996->sysclk_src = clk_id;
1886 1889
1887 return 0; 1890 return 0;
1888 } 1891 }
1889 1892
1890 struct _fll_div { 1893 struct _fll_div {
1891 u16 fll_fratio; 1894 u16 fll_fratio;
1892 u16 fll_outdiv; 1895 u16 fll_outdiv;
1893 u16 fll_refclk_div; 1896 u16 fll_refclk_div;
1894 u16 fll_loop_gain; 1897 u16 fll_loop_gain;
1895 u16 fll_ref_freq; 1898 u16 fll_ref_freq;
1896 u16 n; 1899 u16 n;
1897 u16 theta; 1900 u16 theta;
1898 u16 lambda; 1901 u16 lambda;
1899 }; 1902 };
1900 1903
1901 static struct { 1904 static struct {
1902 unsigned int min; 1905 unsigned int min;
1903 unsigned int max; 1906 unsigned int max;
1904 u16 fll_fratio; 1907 u16 fll_fratio;
1905 int ratio; 1908 int ratio;
1906 } fll_fratios[] = { 1909 } fll_fratios[] = {
1907 { 0, 64000, 4, 16 }, 1910 { 0, 64000, 4, 16 },
1908 { 64000, 128000, 3, 8 }, 1911 { 64000, 128000, 3, 8 },
1909 { 128000, 256000, 2, 4 }, 1912 { 128000, 256000, 2, 4 },
1910 { 256000, 1000000, 1, 2 }, 1913 { 256000, 1000000, 1, 2 },
1911 { 1000000, 13500000, 0, 1 }, 1914 { 1000000, 13500000, 0, 1 },
1912 }; 1915 };
1913 1916
1914 static int fll_factors(struct _fll_div *fll_d 1917 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1915 unsigned int Fout) 1918 unsigned int Fout)
1916 { 1919 {
1917 unsigned int target; 1920 unsigned int target;
1918 unsigned int div; 1921 unsigned int div;
1919 unsigned int fratio, gcd_fll; 1922 unsigned int fratio, gcd_fll;
1920 int i; 1923 int i;
1921 1924
1922 /* Fref must be <=13.5MHz */ 1925 /* Fref must be <=13.5MHz */
1923 div = 1; 1926 div = 1;
1924 fll_div->fll_refclk_div = 0; 1927 fll_div->fll_refclk_div = 0;
1925 while ((Fref / div) > 13500000) { 1928 while ((Fref / div) > 13500000) {
1926 div *= 2; 1929 div *= 2;
1927 fll_div->fll_refclk_div++; 1930 fll_div->fll_refclk_div++;
1928 1931
1929 if (div > 8) { 1932 if (div > 8) {
1930 pr_err("Can't scale % 1933 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1931 Fref); 1934 Fref);
1932 return -EINVAL; 1935 return -EINVAL;
1933 } 1936 }
1934 } 1937 }
1935 1938
1936 pr_debug("FLL Fref=%u Fout=%u\n", Fre 1939 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1937 1940
1938 /* Apply the division for our remaini 1941 /* Apply the division for our remaining calculations */
1939 Fref /= div; 1942 Fref /= div;
1940 1943
1941 if (Fref >= 3000000) 1944 if (Fref >= 3000000)
1942 fll_div->fll_loop_gain = 5; 1945 fll_div->fll_loop_gain = 5;
1943 else 1946 else
1944 fll_div->fll_loop_gain = 0; 1947 fll_div->fll_loop_gain = 0;
1945 1948
1946 if (Fref >= 48000) 1949 if (Fref >= 48000)
1947 fll_div->fll_ref_freq = 0; 1950 fll_div->fll_ref_freq = 0;
1948 else 1951 else
1949 fll_div->fll_ref_freq = 1; 1952 fll_div->fll_ref_freq = 1;
1950 1953
1951 /* Fvco should be 90-100MHz; don't ch 1954 /* Fvco should be 90-100MHz; don't check the upper bound */
1952 div = 2; 1955 div = 2;
1953 while (Fout * div < 90000000) { 1956 while (Fout * div < 90000000) {
1954 div++; 1957 div++;
1955 if (div > 64) { 1958 if (div > 64) {
1956 pr_err("Unable to fin 1959 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1957 Fout); 1960 Fout);
1958 return -EINVAL; 1961 return -EINVAL;
1959 } 1962 }
1960 } 1963 }
1961 target = Fout * div; 1964 target = Fout * div;
1962 fll_div->fll_outdiv = div - 1; 1965 fll_div->fll_outdiv = div - 1;
1963 1966
1964 pr_debug("FLL Fvco=%dHz\n", target); 1967 pr_debug("FLL Fvco=%dHz\n", target);
1965 1968
1966 /* Find an appropraite FLL_FRATIO and 1969 /* Find an appropraite FLL_FRATIO and factor it out of the target */
1967 for (i = 0; i < ARRAY_SIZE(fll_fratio 1970 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1968 if (fll_fratios[i].min <= Fre 1971 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1969 fll_div->fll_fratio = 1972 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1970 fratio = fll_fratios[ 1973 fratio = fll_fratios[i].ratio;
1971 break; 1974 break;
1972 } 1975 }
1973 } 1976 }
1974 if (i == ARRAY_SIZE(fll_fratios)) { 1977 if (i == ARRAY_SIZE(fll_fratios)) {
1975 pr_err("Unable to find FLL_FR 1978 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1976 return -EINVAL; 1979 return -EINVAL;
1977 } 1980 }
1978 1981
1979 fll_div->n = target / (fratio * Fref) 1982 fll_div->n = target / (fratio * Fref);
1980 1983
1981 if (target % Fref == 0) { 1984 if (target % Fref == 0) {
1982 fll_div->theta = 0; 1985 fll_div->theta = 0;
1983 fll_div->lambda = 0; 1986 fll_div->lambda = 0;
1984 } else { 1987 } else {
1985 gcd_fll = gcd(target, fratio 1988 gcd_fll = gcd(target, fratio * Fref);
1986 1989
1987 fll_div->theta = (target - (f 1990 fll_div->theta = (target - (fll_div->n * fratio * Fref))
1988 / gcd_fll; 1991 / gcd_fll;
1989 fll_div->lambda = (fratio * F 1992 fll_div->lambda = (fratio * Fref) / gcd_fll;
1990 } 1993 }
1991 1994
1992 pr_debug("FLL N=%x THETA=%x LAMBDA=%x 1995 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1993 fll_div->n, fll_div->theta, 1996 fll_div->n, fll_div->theta, fll_div->lambda);
1994 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x 1997 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
1995 fll_div->fll_fratio, fll_div 1998 fll_div->fll_fratio, fll_div->fll_outdiv,
1996 fll_div->fll_refclk_div); 1999 fll_div->fll_refclk_div);
1997 2000
1998 return 0; 2001 return 0;
1999 } 2002 }
2000 2003
2001 static int wm8996_set_fll(struct snd_soc_comp !! 2004 static int wm8996_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
2002 unsigned int Fref, 2005 unsigned int Fref, unsigned int Fout)
2003 { 2006 {
2004 struct wm8996_priv *wm8996 = snd_soc_ !! 2007 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2005 struct i2c_client *i2c = to_i2c_clien !! 2008 struct i2c_client *i2c = to_i2c_client(codec->dev);
2006 struct _fll_div fll_div; 2009 struct _fll_div fll_div;
2007 unsigned long timeout, time_left; 2010 unsigned long timeout, time_left;
2008 int ret, reg, retry; 2011 int ret, reg, retry;
2009 2012
2010 /* Any change? */ 2013 /* Any change? */
2011 if (source == wm8996->fll_src && Fref 2014 if (source == wm8996->fll_src && Fref == wm8996->fll_fref &&
2012 Fout == wm8996->fll_fout) 2015 Fout == wm8996->fll_fout)
2013 return 0; 2016 return 0;
2014 2017
2015 if (Fout == 0) { 2018 if (Fout == 0) {
2016 dev_dbg(component->dev, "FLL !! 2019 dev_dbg(codec->dev, "FLL disabled\n");
2017 2020
2018 wm8996->fll_fref = 0; 2021 wm8996->fll_fref = 0;
2019 wm8996->fll_fout = 0; 2022 wm8996->fll_fout = 0;
2020 2023
2021 snd_soc_component_update_bits !! 2024 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1,
2022 WM8996_FL 2025 WM8996_FLL_ENA, 0);
2023 2026
2024 wm8996_bg_disable(component); !! 2027 wm8996_bg_disable(codec);
2025 2028
2026 return 0; 2029 return 0;
2027 } 2030 }
2028 2031
2029 ret = fll_factors(&fll_div, Fref, Fou 2032 ret = fll_factors(&fll_div, Fref, Fout);
2030 if (ret != 0) 2033 if (ret != 0)
2031 return ret; 2034 return ret;
2032 2035
2033 switch (source) { 2036 switch (source) {
2034 case WM8996_FLL_MCLK1: 2037 case WM8996_FLL_MCLK1:
2035 reg = 0; 2038 reg = 0;
2036 break; 2039 break;
2037 case WM8996_FLL_MCLK2: 2040 case WM8996_FLL_MCLK2:
2038 reg = 1; 2041 reg = 1;
2039 break; 2042 break;
2040 case WM8996_FLL_DACLRCLK1: 2043 case WM8996_FLL_DACLRCLK1:
2041 reg = 2; 2044 reg = 2;
2042 break; 2045 break;
2043 case WM8996_FLL_BCLK1: 2046 case WM8996_FLL_BCLK1:
2044 reg = 3; 2047 reg = 3;
2045 break; 2048 break;
2046 default: 2049 default:
2047 dev_err(component->dev, "Unkn !! 2050 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2048 return -EINVAL; 2051 return -EINVAL;
2049 } 2052 }
2050 2053
2051 reg |= fll_div.fll_refclk_div << WM89 2054 reg |= fll_div.fll_refclk_div << WM8996_FLL_REFCLK_DIV_SHIFT;
2052 reg |= fll_div.fll_ref_freq << WM8996 2055 reg |= fll_div.fll_ref_freq << WM8996_FLL_REF_FREQ_SHIFT;
2053 2056
2054 snd_soc_component_update_bits(compone !! 2057 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_5,
2055 WM8996_FLL_REFCLK 2058 WM8996_FLL_REFCLK_DIV_MASK | WM8996_FLL_REF_FREQ |
2056 WM8996_FLL_REFCLK 2059 WM8996_FLL_REFCLK_SRC_MASK, reg);
2057 2060
2058 reg = 0; 2061 reg = 0;
2059 if (fll_div.theta || fll_div.lambda) 2062 if (fll_div.theta || fll_div.lambda)
2060 reg |= WM8996_FLL_EFS_ENA | ( 2063 reg |= WM8996_FLL_EFS_ENA | (3 << WM8996_FLL_LFSR_SEL_SHIFT);
2061 else 2064 else
2062 reg |= 1 << WM8996_FLL_LFSR_S 2065 reg |= 1 << WM8996_FLL_LFSR_SEL_SHIFT;
2063 snd_soc_component_write(component, WM !! 2066 snd_soc_write(codec, WM8996_FLL_EFS_2, reg);
2064 2067
2065 snd_soc_component_update_bits(compone !! 2068 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_2,
2066 WM8996_FLL_OUTDIV 2069 WM8996_FLL_OUTDIV_MASK |
2067 WM8996_FLL_FRATIO 2070 WM8996_FLL_FRATIO_MASK,
2068 (fll_div.fll_outd 2071 (fll_div.fll_outdiv << WM8996_FLL_OUTDIV_SHIFT) |
2069 (fll_div.fll_frat 2072 (fll_div.fll_fratio));
2070 2073
2071 snd_soc_component_write(component, WM !! 2074 snd_soc_write(codec, WM8996_FLL_CONTROL_3, fll_div.theta);
2072 2075
2073 snd_soc_component_update_bits(compone !! 2076 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_4,
2074 WM8996_FLL_N_MASK 2077 WM8996_FLL_N_MASK | WM8996_FLL_LOOP_GAIN_MASK,
2075 (fll_div.n << WM8 2078 (fll_div.n << WM8996_FLL_N_SHIFT) |
2076 fll_div.fll_loop_ 2079 fll_div.fll_loop_gain);
2077 2080
2078 snd_soc_component_write(component, WM !! 2081 snd_soc_write(codec, WM8996_FLL_EFS_1, fll_div.lambda);
2079 2082
2080 /* Enable the bandgap if it's not alr 2083 /* Enable the bandgap if it's not already enabled */
2081 ret = snd_soc_component_read(componen !! 2084 ret = snd_soc_read(codec, WM8996_FLL_CONTROL_1);
2082 if (!(ret & WM8996_FLL_ENA)) 2085 if (!(ret & WM8996_FLL_ENA))
2083 wm8996_bg_enable(component); !! 2086 wm8996_bg_enable(codec);
2084 2087
2085 /* Clear any pending completions (eg, 2088 /* Clear any pending completions (eg, from failed startups) */
2086 try_wait_for_completion(&wm8996->fll_ 2089 try_wait_for_completion(&wm8996->fll_lock);
2087 2090
2088 snd_soc_component_update_bits(compone !! 2091 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1,
2089 WM8996_FLL_ENA, W 2092 WM8996_FLL_ENA, WM8996_FLL_ENA);
2090 2093
2091 /* The FLL supports live reconfigurat 2094 /* The FLL supports live reconfiguration - kick that in case we were
2092 * already enabled. 2095 * already enabled.
2093 */ 2096 */
2094 snd_soc_component_write(component, WM !! 2097 snd_soc_write(codec, WM8996_FLL_CONTROL_6, WM8996_FLL_SWITCH_CLK);
2095 2098
2096 /* Wait for the FLL to lock, using th 2099 /* Wait for the FLL to lock, using the interrupt if possible */
2097 if (Fref > 1000000) 2100 if (Fref > 1000000)
2098 timeout = usecs_to_jiffies(30 2101 timeout = usecs_to_jiffies(300);
2099 else 2102 else
2100 timeout = msecs_to_jiffies(2) 2103 timeout = msecs_to_jiffies(2);
2101 2104
2102 /* Allow substantially longer if we'v 2105 /* Allow substantially longer if we've actually got the IRQ, poll
2103 * at a slightly higher rate if we do 2106 * at a slightly higher rate if we don't.
2104 */ 2107 */
2105 if (i2c->irq) 2108 if (i2c->irq)
2106 timeout *= 10; 2109 timeout *= 10;
2107 else 2110 else
2108 /* ensure timeout of atleast 2111 /* ensure timeout of atleast 1 jiffies */
2109 timeout = (timeout/2) ? : 1; !! 2112 timeout = timeout/2 ? : 1;
2110 2113
2111 for (retry = 0; retry < 10; retry++) 2114 for (retry = 0; retry < 10; retry++) {
2112 time_left = wait_for_completi 2115 time_left = wait_for_completion_timeout(&wm8996->fll_lock,
2113 2116 timeout);
2114 if (time_left != 0) { 2117 if (time_left != 0) {
2115 WARN_ON(!i2c->irq); 2118 WARN_ON(!i2c->irq);
2116 ret = 1; 2119 ret = 1;
2117 break; 2120 break;
2118 } 2121 }
2119 2122
2120 ret = snd_soc_component_read( !! 2123 ret = snd_soc_read(codec, WM8996_INTERRUPT_RAW_STATUS_2);
2121 if (ret & WM8996_FLL_LOCK_STS 2124 if (ret & WM8996_FLL_LOCK_STS)
2122 break; 2125 break;
2123 } 2126 }
2124 if (retry == 10) { 2127 if (retry == 10) {
2125 dev_err(component->dev, "Time !! 2128 dev_err(codec->dev, "Timed out waiting for FLL\n");
2126 ret = -ETIMEDOUT; 2129 ret = -ETIMEDOUT;
2127 } 2130 }
2128 2131
2129 dev_dbg(component->dev, "FLL configur !! 2132 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2130 2133
2131 wm8996->fll_fref = Fref; 2134 wm8996->fll_fref = Fref;
2132 wm8996->fll_fout = Fout; 2135 wm8996->fll_fout = Fout;
2133 wm8996->fll_src = source; 2136 wm8996->fll_src = source;
2134 2137
2135 return ret; 2138 return ret;
2136 } 2139 }
2137 2140
2138 #ifdef CONFIG_GPIOLIB 2141 #ifdef CONFIG_GPIOLIB
>> 2142 static inline struct wm8996_priv *gpio_to_wm8996(struct gpio_chip *chip)
>> 2143 {
>> 2144 return container_of(chip, struct wm8996_priv, gpio_chip);
>> 2145 }
>> 2146
2139 static void wm8996_gpio_set(struct gpio_chip 2147 static void wm8996_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2140 { 2148 {
2141 struct wm8996_priv *wm8996 = gpiochip !! 2149 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2142 2150
2143 regmap_update_bits(wm8996->regmap, WM 2151 regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2144 WM8996_GP1_LVL, !! 2152 WM8996_GP1_LVL, !!value << WM8996_GP1_LVL_SHIFT);
2145 } 2153 }
2146 2154
2147 static int wm8996_gpio_direction_out(struct g 2155 static int wm8996_gpio_direction_out(struct gpio_chip *chip,
2148 unsigned 2156 unsigned offset, int value)
2149 { 2157 {
2150 struct wm8996_priv *wm8996 = gpiochip !! 2158 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2151 int val; 2159 int val;
2152 2160
2153 val = (1 << WM8996_GP1_FN_SHIFT) | (! 2161 val = (1 << WM8996_GP1_FN_SHIFT) | (!!value << WM8996_GP1_LVL_SHIFT);
2154 2162
2155 return regmap_update_bits(wm8996->reg 2163 return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2156 WM8996_GP1_ 2164 WM8996_GP1_FN_MASK | WM8996_GP1_DIR |
2157 WM8996_GP1_ 2165 WM8996_GP1_LVL, val);
2158 } 2166 }
2159 2167
2160 static int wm8996_gpio_get(struct gpio_chip * 2168 static int wm8996_gpio_get(struct gpio_chip *chip, unsigned offset)
2161 { 2169 {
2162 struct wm8996_priv *wm8996 = gpiochip !! 2170 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2163 unsigned int reg; 2171 unsigned int reg;
2164 int ret; 2172 int ret;
2165 2173
2166 ret = regmap_read(wm8996->regmap, WM8 2174 ret = regmap_read(wm8996->regmap, WM8996_GPIO_1 + offset, ®);
2167 if (ret < 0) 2175 if (ret < 0)
2168 return ret; 2176 return ret;
2169 2177
2170 return (reg & WM8996_GP1_LVL) != 0; 2178 return (reg & WM8996_GP1_LVL) != 0;
2171 } 2179 }
2172 2180
2173 static int wm8996_gpio_direction_in(struct gp 2181 static int wm8996_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2174 { 2182 {
2175 struct wm8996_priv *wm8996 = gpiochip !! 2183 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2176 2184
2177 return regmap_update_bits(wm8996->reg 2185 return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2178 WM8996_GP1_ 2186 WM8996_GP1_FN_MASK | WM8996_GP1_DIR,
2179 (1 << WM899 2187 (1 << WM8996_GP1_FN_SHIFT) |
2180 (1 << WM899 2188 (1 << WM8996_GP1_DIR_SHIFT));
2181 } 2189 }
2182 2190
2183 static const struct gpio_chip wm8996_template !! 2191 static struct gpio_chip wm8996_template_chip = {
2184 .label = "wm8996", 2192 .label = "wm8996",
2185 .owner = THIS_MODULE 2193 .owner = THIS_MODULE,
2186 .direction_output = wm8996_gpio 2194 .direction_output = wm8996_gpio_direction_out,
2187 .set = wm8996_gpio 2195 .set = wm8996_gpio_set,
2188 .direction_input = wm8996_gpio 2196 .direction_input = wm8996_gpio_direction_in,
2189 .get = wm8996_gpio 2197 .get = wm8996_gpio_get,
2190 .can_sleep = 1, 2198 .can_sleep = 1,
2191 .ngpio = 5, <<
2192 .base = -1, <<
2193 }; 2199 };
2194 2200
2195 static void wm8996_init_gpio(struct wm8996_pr 2201 static void wm8996_init_gpio(struct wm8996_priv *wm8996)
2196 { 2202 {
2197 int ret; 2203 int ret;
2198 2204
2199 wm8996->gpio_chip = wm8996_template_c 2205 wm8996->gpio_chip = wm8996_template_chip;
2200 wm8996->gpio_chip.parent = wm8996->de !! 2206 wm8996->gpio_chip.ngpio = 5;
>> 2207 wm8996->gpio_chip.dev = wm8996->dev;
>> 2208
>> 2209 if (wm8996->pdata.gpio_base)
>> 2210 wm8996->gpio_chip.base = wm8996->pdata.gpio_base;
>> 2211 else
>> 2212 wm8996->gpio_chip.base = -1;
2201 2213
2202 ret = gpiochip_add_data(&wm8996->gpio !! 2214 ret = gpiochip_add(&wm8996->gpio_chip);
2203 if (ret != 0) 2215 if (ret != 0)
2204 dev_err(wm8996->dev, "Failed 2216 dev_err(wm8996->dev, "Failed to add GPIOs: %d\n", ret);
2205 } 2217 }
2206 2218
2207 static void wm8996_free_gpio(struct wm8996_pr 2219 static void wm8996_free_gpio(struct wm8996_priv *wm8996)
2208 { 2220 {
2209 gpiochip_remove(&wm8996->gpio_chip); 2221 gpiochip_remove(&wm8996->gpio_chip);
2210 } 2222 }
2211 #else 2223 #else
2212 static void wm8996_init_gpio(struct wm8996_pr 2224 static void wm8996_init_gpio(struct wm8996_priv *wm8996)
2213 { 2225 {
2214 } 2226 }
2215 2227
2216 static void wm8996_free_gpio(struct wm8996_pr 2228 static void wm8996_free_gpio(struct wm8996_priv *wm8996)
2217 { 2229 {
2218 } 2230 }
2219 #endif 2231 #endif
2220 2232
2221 /** 2233 /**
2222 * wm8996_detect - Enable default WM8996 jack 2234 * wm8996_detect - Enable default WM8996 jack detection
2223 * @component: ASoC component <<
2224 * @jack: jack pointer <<
2225 * @polarity_cb: polarity callback <<
2226 * 2235 *
2227 * The WM8996 has advanced accessory detectio 2236 * The WM8996 has advanced accessory detection support for headsets.
2228 * This function provides a default implement 2237 * This function provides a default implementation which integrates
2229 * the majority of this functionality with mi 2238 * the majority of this functionality with minimal user configuration.
2230 * 2239 *
2231 * This will detect headset, headphone and sh 2240 * This will detect headset, headphone and short circuit button and
2232 * will also detect inverted microphone groun 2241 * will also detect inverted microphone ground connections and update
2233 * the polarity of the connections. 2242 * the polarity of the connections.
2234 */ 2243 */
2235 int wm8996_detect(struct snd_soc_component *c !! 2244 int wm8996_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2236 wm8996_polarity_fn polarity 2245 wm8996_polarity_fn polarity_cb)
2237 { 2246 {
2238 struct wm8996_priv *wm8996 = snd_soc_ !! 2247 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2239 struct snd_soc_dapm_context *dapm = s !! 2248 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
2240 2249
2241 wm8996->jack = jack; 2250 wm8996->jack = jack;
2242 wm8996->detecting = true; 2251 wm8996->detecting = true;
2243 wm8996->polarity_cb = polarity_cb; 2252 wm8996->polarity_cb = polarity_cb;
2244 wm8996->jack_flips = 0; 2253 wm8996->jack_flips = 0;
2245 2254
2246 if (wm8996->polarity_cb) 2255 if (wm8996->polarity_cb)
2247 wm8996->polarity_cb(component !! 2256 wm8996->polarity_cb(codec, 0);
2248 2257
2249 /* Clear discarge to avoid noise duri 2258 /* Clear discarge to avoid noise during detection */
2250 snd_soc_component_update_bits(compone !! 2259 snd_soc_update_bits(codec, WM8996_MICBIAS_1,
2251 WM8996_MICB1_DISC 2260 WM8996_MICB1_DISCH, 0);
2252 snd_soc_component_update_bits(compone !! 2261 snd_soc_update_bits(codec, WM8996_MICBIAS_2,
2253 WM8996_MICB2_DISC 2262 WM8996_MICB2_DISCH, 0);
2254 2263
2255 /* LDO2 powers the microphones, SYSCL 2264 /* LDO2 powers the microphones, SYSCLK clocks detection */
2256 snd_soc_dapm_mutex_lock(dapm); 2265 snd_soc_dapm_mutex_lock(dapm);
2257 2266
2258 snd_soc_dapm_force_enable_pin_unlocke 2267 snd_soc_dapm_force_enable_pin_unlocked(dapm, "LDO2");
2259 snd_soc_dapm_force_enable_pin_unlocke 2268 snd_soc_dapm_force_enable_pin_unlocked(dapm, "SYSCLK");
2260 2269
2261 snd_soc_dapm_mutex_unlock(dapm); 2270 snd_soc_dapm_mutex_unlock(dapm);
2262 2271
2263 /* We start off just enabling microph 2272 /* We start off just enabling microphone detection - even a
2264 * plain headphone will trigger detec 2273 * plain headphone will trigger detection.
2265 */ 2274 */
2266 snd_soc_component_update_bits(compone !! 2275 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2267 WM8996_MICD_ENA, 2276 WM8996_MICD_ENA, WM8996_MICD_ENA);
2268 2277
2269 /* Slowest detection rate, gives debo 2278 /* Slowest detection rate, gives debounce for initial detection */
2270 snd_soc_component_update_bits(compone !! 2279 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2271 WM8996_MICD_RATE_ 2280 WM8996_MICD_RATE_MASK,
2272 WM8996_MICD_RATE_ 2281 WM8996_MICD_RATE_MASK);
2273 2282
2274 /* Enable interrupts and we're off */ 2283 /* Enable interrupts and we're off */
2275 snd_soc_component_update_bits(compone !! 2284 snd_soc_update_bits(codec, WM8996_INTERRUPT_STATUS_2_MASK,
2276 WM8996_IM_MICD_EI 2285 WM8996_IM_MICD_EINT | WM8996_HP_DONE_EINT, 0);
2277 2286
2278 return 0; 2287 return 0;
2279 } 2288 }
2280 EXPORT_SYMBOL_GPL(wm8996_detect); 2289 EXPORT_SYMBOL_GPL(wm8996_detect);
2281 2290
2282 static void wm8996_hpdet_irq(struct snd_soc_c !! 2291 static void wm8996_hpdet_irq(struct snd_soc_codec *codec)
2283 { 2292 {
2284 struct snd_soc_dapm_context *dapm = s !! 2293 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
2285 struct wm8996_priv *wm8996 = snd_soc_ !! 2294 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2286 int val, reg, report; 2295 int val, reg, report;
2287 2296
2288 /* Assume headphone in error conditio 2297 /* Assume headphone in error conditions; we need to report
2289 * something or we stall our state ma 2298 * something or we stall our state machine.
2290 */ 2299 */
2291 report = SND_JACK_HEADPHONE; 2300 report = SND_JACK_HEADPHONE;
2292 2301
2293 reg = snd_soc_component_read(componen !! 2302 reg = snd_soc_read(codec, WM8996_HEADPHONE_DETECT_2);
2294 if (reg < 0) { 2303 if (reg < 0) {
2295 dev_err(component->dev, "Fail !! 2304 dev_err(codec->dev, "Failed to read HPDET status\n");
2296 goto out; 2305 goto out;
2297 } 2306 }
2298 2307
2299 if (!(reg & WM8996_HP_DONE)) { 2308 if (!(reg & WM8996_HP_DONE)) {
2300 dev_err(component->dev, "Got !! 2309 dev_err(codec->dev, "Got HPDET IRQ but HPDET is busy\n");
2301 goto out; 2310 goto out;
2302 } 2311 }
2303 2312
2304 val = reg & WM8996_HP_LVL_MASK; 2313 val = reg & WM8996_HP_LVL_MASK;
2305 2314
2306 dev_dbg(component->dev, "HPDET measur !! 2315 dev_dbg(codec->dev, "HPDET measured %d ohms\n", val);
2307 2316
2308 /* If we've got high enough impedence 2317 /* If we've got high enough impedence then report as line,
2309 * otherwise assume headphone. 2318 * otherwise assume headphone.
2310 */ 2319 */
2311 if (val >= 126) 2320 if (val >= 126)
2312 report = SND_JACK_LINEOUT; 2321 report = SND_JACK_LINEOUT;
2313 else 2322 else
2314 report = SND_JACK_HEADPHONE; 2323 report = SND_JACK_HEADPHONE;
2315 2324
2316 out: 2325 out:
2317 if (wm8996->jack_mic) 2326 if (wm8996->jack_mic)
2318 report |= SND_JACK_MICROPHONE 2327 report |= SND_JACK_MICROPHONE;
2319 2328
2320 snd_soc_jack_report(wm8996->jack, rep 2329 snd_soc_jack_report(wm8996->jack, report,
2321 SND_JACK_LINEOUT 2330 SND_JACK_LINEOUT | SND_JACK_HEADSET);
2322 2331
2323 wm8996->detecting = false; 2332 wm8996->detecting = false;
2324 2333
2325 /* If the output isn't running re-cla 2334 /* If the output isn't running re-clamp it */
2326 if (!(snd_soc_component_read(componen !! 2335 if (!(snd_soc_read(codec, WM8996_POWER_MANAGEMENT_1) &
2327 (WM8996_HPOUT1L_ENA | WM8996_HP 2336 (WM8996_HPOUT1L_ENA | WM8996_HPOUT1R_RMV_SHORT)))
2328 snd_soc_component_update_bits !! 2337 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1,
2329 WM8996_HP 2338 WM8996_HPOUT1L_RMV_SHORT |
2330 WM8996_HP 2339 WM8996_HPOUT1R_RMV_SHORT, 0);
2331 2340
2332 /* Go back to looking at the micropho 2341 /* Go back to looking at the microphone */
2333 snd_soc_component_update_bits(compone !! 2342 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1,
2334 WM8996_JD_MODE_MA 2343 WM8996_JD_MODE_MASK, 0);
2335 snd_soc_component_update_bits(compone !! 2344 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA,
2336 WM8996_MICD_ENA); 2345 WM8996_MICD_ENA);
2337 2346
2338 snd_soc_dapm_disable_pin(dapm, "Bandg 2347 snd_soc_dapm_disable_pin(dapm, "Bandgap");
2339 snd_soc_dapm_sync(dapm); 2348 snd_soc_dapm_sync(dapm);
2340 } 2349 }
2341 2350
2342 static void wm8996_hpdet_start(struct snd_soc !! 2351 static void wm8996_hpdet_start(struct snd_soc_codec *codec)
2343 { 2352 {
2344 struct snd_soc_dapm_context *dapm = s !! 2353 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
2345 2354
2346 /* Unclamp the output, we can't measu 2355 /* Unclamp the output, we can't measure while we're shorting it */
2347 snd_soc_component_update_bits(compone !! 2356 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1,
2348 WM8996_HPOUT1L_RM 2357 WM8996_HPOUT1L_RMV_SHORT |
2349 WM8996_HPOUT1R_RM 2358 WM8996_HPOUT1R_RMV_SHORT,
2350 WM8996_HPOUT1L_RM 2359 WM8996_HPOUT1L_RMV_SHORT |
2351 WM8996_HPOUT1R_RM 2360 WM8996_HPOUT1R_RMV_SHORT);
2352 2361
2353 /* We need bandgap for HPDET */ 2362 /* We need bandgap for HPDET */
2354 snd_soc_dapm_force_enable_pin(dapm, " 2363 snd_soc_dapm_force_enable_pin(dapm, "Bandgap");
2355 snd_soc_dapm_sync(dapm); 2364 snd_soc_dapm_sync(dapm);
2356 2365
2357 /* Go into headphone detect left mode 2366 /* Go into headphone detect left mode */
2358 snd_soc_component_update_bits(compone !! 2367 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA, 0);
2359 snd_soc_component_update_bits(compone !! 2368 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1,
2360 WM8996_JD_MODE_MA 2369 WM8996_JD_MODE_MASK, 1);
2361 2370
2362 /* Trigger a measurement */ 2371 /* Trigger a measurement */
2363 snd_soc_component_update_bits(compone !! 2372 snd_soc_update_bits(codec, WM8996_HEADPHONE_DETECT_1,
2364 WM8996_HP_POLL, W 2373 WM8996_HP_POLL, WM8996_HP_POLL);
2365 } 2374 }
2366 2375
2367 static void wm8996_report_headphone(struct sn !! 2376 static void wm8996_report_headphone(struct snd_soc_codec *codec)
2368 { 2377 {
2369 dev_dbg(component->dev, "Headphone de !! 2378 dev_dbg(codec->dev, "Headphone detected\n");
2370 wm8996_hpdet_start(component); !! 2379 wm8996_hpdet_start(codec);
2371 2380
2372 /* Increase the detection rate a bit 2381 /* Increase the detection rate a bit for responsiveness. */
2373 snd_soc_component_update_bits(compone !! 2382 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2374 WM8996_MICD_RATE_ 2383 WM8996_MICD_RATE_MASK |
2375 WM8996_MICD_BIAS_ 2384 WM8996_MICD_BIAS_STARTTIME_MASK,
2376 7 << WM8996_MICD_ 2385 7 << WM8996_MICD_RATE_SHIFT |
2377 7 << WM8996_MICD_ 2386 7 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
2378 } 2387 }
2379 2388
2380 static void wm8996_micd(struct snd_soc_compon !! 2389 static void wm8996_micd(struct snd_soc_codec *codec)
2381 { 2390 {
2382 struct wm8996_priv *wm8996 = snd_soc_ !! 2391 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2383 int val, reg; 2392 int val, reg;
2384 2393
2385 val = snd_soc_component_read(componen !! 2394 val = snd_soc_read(codec, WM8996_MIC_DETECT_3);
2386 2395
2387 dev_dbg(component->dev, "Microphone e !! 2396 dev_dbg(codec->dev, "Microphone event: %x\n", val);
2388 2397
2389 if (!(val & WM8996_MICD_VALID)) { 2398 if (!(val & WM8996_MICD_VALID)) {
2390 dev_warn(component->dev, "Mic !! 2399 dev_warn(codec->dev, "Microphone detection state invalid\n");
2391 return; 2400 return;
2392 } 2401 }
2393 2402
2394 /* No accessory, reset everything and 2403 /* No accessory, reset everything and report removal */
2395 if (!(val & WM8996_MICD_STS)) { 2404 if (!(val & WM8996_MICD_STS)) {
2396 dev_dbg(component->dev, "Jack !! 2405 dev_dbg(codec->dev, "Jack removal detected\n");
2397 wm8996->jack_mic = false; 2406 wm8996->jack_mic = false;
2398 wm8996->detecting = true; 2407 wm8996->detecting = true;
2399 wm8996->jack_flips = 0; 2408 wm8996->jack_flips = 0;
2400 snd_soc_jack_report(wm8996->j 2409 snd_soc_jack_report(wm8996->jack, 0,
2401 SND_JACK_ 2410 SND_JACK_LINEOUT | SND_JACK_HEADSET |
2402 SND_JACK_ 2411 SND_JACK_BTN_0);
2403 2412
2404 snd_soc_component_update_bits !! 2413 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2405 WM8996_MI 2414 WM8996_MICD_RATE_MASK |
2406 WM8996_MI 2415 WM8996_MICD_BIAS_STARTTIME_MASK,
2407 WM8996_MI 2416 WM8996_MICD_RATE_MASK |
2408 9 << WM89 2417 9 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
2409 return; 2418 return;
2410 } 2419 }
2411 2420
2412 /* If the measurement is very high we 2421 /* If the measurement is very high we've got a microphone,
2413 * either we just detected one or if 2422 * either we just detected one or if we already reported then
2414 * we've got a button release event. 2423 * we've got a button release event.
2415 */ 2424 */
2416 if (val & 0x400) { 2425 if (val & 0x400) {
2417 if (wm8996->detecting) { 2426 if (wm8996->detecting) {
2418 dev_dbg(component->de !! 2427 dev_dbg(codec->dev, "Microphone detected\n");
2419 wm8996->jack_mic = tr 2428 wm8996->jack_mic = true;
2420 wm8996_hpdet_start(co !! 2429 wm8996_hpdet_start(codec);
2421 2430
2422 /* Increase poll rate 2431 /* Increase poll rate to give better responsiveness
2423 * for buttons */ 2432 * for buttons */
2424 snd_soc_component_upd !! 2433 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2425 W 2434 WM8996_MICD_RATE_MASK |
2426 W 2435 WM8996_MICD_BIAS_STARTTIME_MASK,
2427 5 2436 5 << WM8996_MICD_RATE_SHIFT |
2428 7 2437 7 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
2429 } else { 2438 } else {
2430 dev_dbg(component->de !! 2439 dev_dbg(codec->dev, "Mic button up\n");
2431 snd_soc_jack_report(w 2440 snd_soc_jack_report(wm8996->jack, 0, SND_JACK_BTN_0);
2432 } 2441 }
2433 2442
2434 return; 2443 return;
2435 } 2444 }
2436 2445
2437 /* If we detected a lower impedence d 2446 /* If we detected a lower impedence during initial startup
2438 * then we probably have the wrong po 2447 * then we probably have the wrong polarity, flip it. Don't
2439 * do this for the lowest impedences 2448 * do this for the lowest impedences to speed up detection of
2440 * plain headphones. If both polarit 2449 * plain headphones. If both polarities report a low
2441 * impedence then give up and report 2450 * impedence then give up and report headphones.
2442 */ 2451 */
2443 if (wm8996->detecting && (val & 0x3f0 2452 if (wm8996->detecting && (val & 0x3f0)) {
2444 wm8996->jack_flips++; 2453 wm8996->jack_flips++;
2445 2454
2446 if (wm8996->jack_flips > 1) { 2455 if (wm8996->jack_flips > 1) {
2447 wm8996_report_headpho !! 2456 wm8996_report_headphone(codec);
2448 return; 2457 return;
2449 } 2458 }
2450 2459
2451 reg = snd_soc_component_read( !! 2460 reg = snd_soc_read(codec, WM8996_ACCESSORY_DETECT_MODE_2);
2452 reg ^= WM8996_HPOUT1FB_SRC | 2461 reg ^= WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2453 WM8996_MICD_BIAS_SRC; 2462 WM8996_MICD_BIAS_SRC;
2454 snd_soc_component_update_bits !! 2463 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2,
2455 WM8996_HP 2464 WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2456 WM8996_MI 2465 WM8996_MICD_BIAS_SRC, reg);
2457 2466
2458 if (wm8996->polarity_cb) 2467 if (wm8996->polarity_cb)
2459 wm8996->polarity_cb(c !! 2468 wm8996->polarity_cb(codec,
2460 ( 2469 (reg & WM8996_MICD_SRC) != 0);
2461 2470
2462 dev_dbg(component->dev, "Set !! 2471 dev_dbg(codec->dev, "Set microphone polarity to %d\n",
2463 (reg & WM8996_MICD_SR 2472 (reg & WM8996_MICD_SRC) != 0);
2464 2473
2465 return; 2474 return;
2466 } 2475 }
2467 2476
2468 /* Don't distinguish between buttons, 2477 /* Don't distinguish between buttons, just report any low
2469 * impedence as BTN_0. 2478 * impedence as BTN_0.
2470 */ 2479 */
2471 if (val & 0x3fc) { 2480 if (val & 0x3fc) {
2472 if (wm8996->jack_mic) { 2481 if (wm8996->jack_mic) {
2473 dev_dbg(component->de !! 2482 dev_dbg(codec->dev, "Mic button detected\n");
2474 snd_soc_jack_report(w 2483 snd_soc_jack_report(wm8996->jack, SND_JACK_BTN_0,
2475 S 2484 SND_JACK_BTN_0);
2476 } else if (wm8996->detecting) 2485 } else if (wm8996->detecting) {
2477 wm8996_report_headpho !! 2486 wm8996_report_headphone(codec);
2478 } 2487 }
2479 } 2488 }
2480 } 2489 }
2481 2490
2482 static irqreturn_t wm8996_irq(int irq, void * 2491 static irqreturn_t wm8996_irq(int irq, void *data)
2483 { 2492 {
2484 struct snd_soc_component *component = !! 2493 struct snd_soc_codec *codec = data;
2485 struct wm8996_priv *wm8996 = snd_soc_ !! 2494 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2486 int irq_val; 2495 int irq_val;
2487 2496
2488 irq_val = snd_soc_component_read(comp !! 2497 irq_val = snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2);
2489 if (irq_val < 0) { 2498 if (irq_val < 0) {
2490 dev_err(component->dev, "Fail !! 2499 dev_err(codec->dev, "Failed to read IRQ status: %d\n",
2491 irq_val); 2500 irq_val);
2492 return IRQ_NONE; 2501 return IRQ_NONE;
2493 } 2502 }
2494 irq_val &= ~snd_soc_component_read(co !! 2503 irq_val &= ~snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2_MASK);
2495 2504
2496 if (!irq_val) 2505 if (!irq_val)
2497 return IRQ_NONE; 2506 return IRQ_NONE;
2498 2507
2499 snd_soc_component_write(component, WM !! 2508 snd_soc_write(codec, WM8996_INTERRUPT_STATUS_2, irq_val);
2500 2509
2501 if (irq_val & (WM8996_DCS_DONE_01_EIN 2510 if (irq_val & (WM8996_DCS_DONE_01_EINT | WM8996_DCS_DONE_23_EINT)) {
2502 dev_dbg(component->dev, "DC s !! 2511 dev_dbg(codec->dev, "DC servo IRQ\n");
2503 complete(&wm8996->dcs_done); 2512 complete(&wm8996->dcs_done);
2504 } 2513 }
2505 2514
2506 if (irq_val & WM8996_FIFOS_ERR_EINT) 2515 if (irq_val & WM8996_FIFOS_ERR_EINT)
2507 dev_err(component->dev, "Digi !! 2516 dev_err(codec->dev, "Digital core FIFO error\n");
2508 2517
2509 if (irq_val & WM8996_FLL_LOCK_EINT) { 2518 if (irq_val & WM8996_FLL_LOCK_EINT) {
2510 dev_dbg(component->dev, "FLL !! 2519 dev_dbg(codec->dev, "FLL locked\n");
2511 complete(&wm8996->fll_lock); 2520 complete(&wm8996->fll_lock);
2512 } 2521 }
2513 2522
2514 if (irq_val & WM8996_MICD_EINT) 2523 if (irq_val & WM8996_MICD_EINT)
2515 wm8996_micd(component); !! 2524 wm8996_micd(codec);
2516 2525
2517 if (irq_val & WM8996_HP_DONE_EINT) 2526 if (irq_val & WM8996_HP_DONE_EINT)
2518 wm8996_hpdet_irq(component); !! 2527 wm8996_hpdet_irq(codec);
2519 2528
2520 return IRQ_HANDLED; 2529 return IRQ_HANDLED;
2521 } 2530 }
2522 2531
2523 static irqreturn_t wm8996_edge_irq(int irq, v 2532 static irqreturn_t wm8996_edge_irq(int irq, void *data)
2524 { 2533 {
2525 irqreturn_t ret = IRQ_NONE; 2534 irqreturn_t ret = IRQ_NONE;
2526 irqreturn_t val; 2535 irqreturn_t val;
2527 2536
2528 do { 2537 do {
2529 val = wm8996_irq(irq, data); 2538 val = wm8996_irq(irq, data);
2530 if (val != IRQ_NONE) 2539 if (val != IRQ_NONE)
2531 ret = val; 2540 ret = val;
2532 } while (val != IRQ_NONE); 2541 } while (val != IRQ_NONE);
2533 2542
2534 return ret; 2543 return ret;
2535 } 2544 }
2536 2545
2537 static void wm8996_retune_mobile_pdata(struct !! 2546 static void wm8996_retune_mobile_pdata(struct snd_soc_codec *codec)
2538 { 2547 {
2539 struct wm8996_priv *wm8996 = snd_soc_ !! 2548 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2540 struct wm8996_pdata *pdata = &wm8996- 2549 struct wm8996_pdata *pdata = &wm8996->pdata;
2541 2550
2542 struct snd_kcontrol_new controls[] = 2551 struct snd_kcontrol_new controls[] = {
2543 SOC_ENUM_EXT("DSP1 EQ Mode", 2552 SOC_ENUM_EXT("DSP1 EQ Mode",
2544 wm8996->retune_m 2553 wm8996->retune_mobile_enum,
2545 wm8996_get_retun 2554 wm8996_get_retune_mobile_enum,
2546 wm8996_put_retun 2555 wm8996_put_retune_mobile_enum),
2547 SOC_ENUM_EXT("DSP2 EQ Mode", 2556 SOC_ENUM_EXT("DSP2 EQ Mode",
2548 wm8996->retune_m 2557 wm8996->retune_mobile_enum,
2549 wm8996_get_retun 2558 wm8996_get_retune_mobile_enum,
2550 wm8996_put_retun 2559 wm8996_put_retune_mobile_enum),
2551 }; 2560 };
2552 int ret, i, j; 2561 int ret, i, j;
2553 const char **t; 2562 const char **t;
2554 2563
2555 /* We need an array of texts for the 2564 /* We need an array of texts for the enum API but the number
2556 * of texts is likely to be less than 2565 * of texts is likely to be less than the number of
2557 * configurations due to the sample r 2566 * configurations due to the sample rate dependency of the
2558 * configurations. */ 2567 * configurations. */
2559 wm8996->num_retune_mobile_texts = 0; 2568 wm8996->num_retune_mobile_texts = 0;
2560 wm8996->retune_mobile_texts = NULL; 2569 wm8996->retune_mobile_texts = NULL;
2561 for (i = 0; i < pdata->num_retune_mob 2570 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2562 for (j = 0; j < wm8996->num_r 2571 for (j = 0; j < wm8996->num_retune_mobile_texts; j++) {
2563 if (strcmp(pdata->ret 2572 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2564 wm8996->re 2573 wm8996->retune_mobile_texts[j]) == 0)
2565 break; 2574 break;
2566 } 2575 }
2567 2576
2568 if (j != wm8996->num_retune_m 2577 if (j != wm8996->num_retune_mobile_texts)
2569 continue; 2578 continue;
2570 2579
2571 /* Expand the array... */ 2580 /* Expand the array... */
2572 t = krealloc(wm8996->retune_m 2581 t = krealloc(wm8996->retune_mobile_texts,
2573 sizeof(char *) * 2582 sizeof(char *) *
2574 (wm8996->num_ret 2583 (wm8996->num_retune_mobile_texts + 1),
2575 GFP_KERNEL); 2584 GFP_KERNEL);
2576 if (t == NULL) 2585 if (t == NULL)
2577 continue; 2586 continue;
2578 2587
2579 /* ...store the new entry... 2588 /* ...store the new entry... */
2580 t[wm8996->num_retune_mobile_t 2589 t[wm8996->num_retune_mobile_texts] =
2581 pdata->retune_mobile_ 2590 pdata->retune_mobile_cfgs[i].name;
2582 2591
2583 /* ...and remember the new ve 2592 /* ...and remember the new version. */
2584 wm8996->num_retune_mobile_tex 2593 wm8996->num_retune_mobile_texts++;
2585 wm8996->retune_mobile_texts = 2594 wm8996->retune_mobile_texts = t;
2586 } 2595 }
2587 2596
2588 dev_dbg(component->dev, "Allocated %d !! 2597 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2589 wm8996->num_retune_mobile_tex 2598 wm8996->num_retune_mobile_texts);
2590 2599
2591 wm8996->retune_mobile_enum.items = wm 2600 wm8996->retune_mobile_enum.items = wm8996->num_retune_mobile_texts;
2592 wm8996->retune_mobile_enum.texts = wm 2601 wm8996->retune_mobile_enum.texts = wm8996->retune_mobile_texts;
2593 2602
2594 ret = snd_soc_add_component_controls( !! 2603 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls));
2595 if (ret != 0) 2604 if (ret != 0)
2596 dev_err(component->dev, !! 2605 dev_err(codec->dev,
2597 "Failed to add ReTune 2606 "Failed to add ReTune Mobile controls: %d\n", ret);
2598 } 2607 }
2599 2608
2600 static const struct regmap_config wm8996_regm 2609 static const struct regmap_config wm8996_regmap = {
2601 .reg_bits = 16, 2610 .reg_bits = 16,
2602 .val_bits = 16, 2611 .val_bits = 16,
2603 2612
2604 .max_register = WM8996_MAX_REGISTER, 2613 .max_register = WM8996_MAX_REGISTER,
2605 .reg_defaults = wm8996_reg, 2614 .reg_defaults = wm8996_reg,
2606 .num_reg_defaults = ARRAY_SIZE(wm8996 2615 .num_reg_defaults = ARRAY_SIZE(wm8996_reg),
2607 .volatile_reg = wm8996_volatile_regis 2616 .volatile_reg = wm8996_volatile_register,
2608 .readable_reg = wm8996_readable_regis 2617 .readable_reg = wm8996_readable_register,
2609 .cache_type = REGCACHE_MAPLE, !! 2618 .cache_type = REGCACHE_RBTREE,
2610 }; 2619 };
2611 2620
2612 static int wm8996_probe(struct snd_soc_compon !! 2621 static int wm8996_probe(struct snd_soc_codec *codec)
2613 { 2622 {
2614 int ret; 2623 int ret;
2615 struct wm8996_priv *wm8996 = snd_soc_ !! 2624 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2616 struct i2c_client *i2c = to_i2c_clien !! 2625 struct i2c_client *i2c = to_i2c_client(codec->dev);
2617 int irq_flags; 2626 int irq_flags;
2618 2627
2619 wm8996->component = component; !! 2628 wm8996->codec = codec;
2620 2629
2621 init_completion(&wm8996->dcs_done); 2630 init_completion(&wm8996->dcs_done);
2622 init_completion(&wm8996->fll_lock); 2631 init_completion(&wm8996->fll_lock);
2623 2632
2624 if (wm8996->pdata.num_retune_mobile_c 2633 if (wm8996->pdata.num_retune_mobile_cfgs)
2625 wm8996_retune_mobile_pdata(co !! 2634 wm8996_retune_mobile_pdata(codec);
2626 else 2635 else
2627 snd_soc_add_component_control !! 2636 snd_soc_add_codec_controls(codec, wm8996_eq_controls,
2628 ARRAY_SI 2637 ARRAY_SIZE(wm8996_eq_controls));
2629 2638
2630 if (i2c->irq) { 2639 if (i2c->irq) {
2631 if (wm8996->pdata.irq_flags) 2640 if (wm8996->pdata.irq_flags)
2632 irq_flags = wm8996->p 2641 irq_flags = wm8996->pdata.irq_flags;
2633 else 2642 else
2634 irq_flags = IRQF_TRIG 2643 irq_flags = IRQF_TRIGGER_LOW;
2635 2644
2636 irq_flags |= IRQF_ONESHOT; 2645 irq_flags |= IRQF_ONESHOT;
2637 2646
2638 if (irq_flags & (IRQF_TRIGGER 2647 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
2639 ret = request_threade 2648 ret = request_threaded_irq(i2c->irq, NULL,
2640 2649 wm8996_edge_irq,
2641 !! 2650 irq_flags, "wm8996", codec);
2642 else 2651 else
2643 ret = request_threade 2652 ret = request_threaded_irq(i2c->irq, NULL, wm8996_irq,
2644 !! 2653 irq_flags, "wm8996", codec);
2645 2654
2646 if (ret == 0) { 2655 if (ret == 0) {
2647 /* Unmask the interru 2656 /* Unmask the interrupt */
2648 snd_soc_component_upd !! 2657 snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL,
2649 W 2658 WM8996_IM_IRQ, 0);
2650 2659
2651 /* Enable error repor 2660 /* Enable error reporting and DC servo status */
2652 snd_soc_component_upd !! 2661 snd_soc_update_bits(codec,
2653 W 2662 WM8996_INTERRUPT_STATUS_2_MASK,
2654 W 2663 WM8996_IM_DCS_DONE_23_EINT |
2655 W 2664 WM8996_IM_DCS_DONE_01_EINT |
2656 W 2665 WM8996_IM_FLL_LOCK_EINT |
2657 W 2666 WM8996_IM_FIFOS_ERR_EINT,
2658 0 2667 0);
2659 } else { 2668 } else {
2660 dev_err(component->de !! 2669 dev_err(codec->dev, "Failed to request IRQ: %d\n",
2661 ret); 2670 ret);
2662 return ret; 2671 return ret;
2663 } 2672 }
2664 } 2673 }
2665 2674
2666 return 0; 2675 return 0;
2667 } 2676 }
2668 2677
2669 static void wm8996_remove(struct snd_soc_comp !! 2678 static int wm8996_remove(struct snd_soc_codec *codec)
2670 { 2679 {
2671 struct i2c_client *i2c = to_i2c_clien !! 2680 struct i2c_client *i2c = to_i2c_client(codec->dev);
2672 2681
2673 snd_soc_component_update_bits(compone !! 2682 snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL,
2674 WM8996_IM_IRQ, WM 2683 WM8996_IM_IRQ, WM8996_IM_IRQ);
2675 2684
2676 if (i2c->irq) 2685 if (i2c->irq)
2677 free_irq(i2c->irq, component) !! 2686 free_irq(i2c->irq, codec);
>> 2687
>> 2688 return 0;
2678 } 2689 }
2679 2690
2680 static const struct snd_soc_component_driver !! 2691 static struct snd_soc_codec_driver soc_codec_dev_wm8996 = {
2681 .probe = wm8996_prob !! 2692 .probe = wm8996_probe,
2682 .remove = wm8996_remo !! 2693 .remove = wm8996_remove,
2683 .set_bias_level = wm8996_set_ !! 2694 .set_bias_level = wm8996_set_bias_level,
2684 .seq_notifier = wm8996_seq_ !! 2695 .idle_bias_off = true,
2685 .controls = wm8996_snd_ !! 2696 .seq_notifier = wm8996_seq_notifier,
2686 .num_controls = ARRAY_SIZE( !! 2697 .controls = wm8996_snd_controls,
2687 .dapm_widgets = wm8996_dapm !! 2698 .num_controls = ARRAY_SIZE(wm8996_snd_controls),
2688 .num_dapm_widgets = ARRAY_SIZE( !! 2699 .dapm_widgets = wm8996_dapm_widgets,
2689 .dapm_routes = wm8996_dapm !! 2700 .num_dapm_widgets = ARRAY_SIZE(wm8996_dapm_widgets),
2690 .num_dapm_routes = ARRAY_SIZE( !! 2701 .dapm_routes = wm8996_dapm_routes,
2691 .set_pll = wm8996_set_ !! 2702 .num_dapm_routes = ARRAY_SIZE(wm8996_dapm_routes),
2692 .use_pmdown_time = 1, !! 2703 .set_pll = wm8996_set_fll,
2693 .endianness = 1, <<
2694 }; 2704 };
2695 2705
2696 #define WM8996_RATES (SNDRV_PCM_RATE_8000 | S 2706 #define WM8996_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
2697 SNDRV_PCM_RATE_32000 | 2707 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
2698 SNDRV_PCM_RATE_48000) 2708 SNDRV_PCM_RATE_48000)
2699 #define WM8996_FORMATS (SNDRV_PCM_FMTBIT_S8 | 2709 #define WM8996_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
2700 SNDRV_PCM_FMTBIT_S20_ 2710 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
2701 SNDRV_PCM_FMTBIT_S32_ 2711 SNDRV_PCM_FMTBIT_S32_LE)
2702 2712
2703 static const struct snd_soc_dai_ops wm8996_da 2713 static const struct snd_soc_dai_ops wm8996_dai_ops = {
2704 .set_fmt = wm8996_set_fmt, 2714 .set_fmt = wm8996_set_fmt,
2705 .hw_params = wm8996_hw_params, 2715 .hw_params = wm8996_hw_params,
2706 .set_sysclk = wm8996_set_sysclk, 2716 .set_sysclk = wm8996_set_sysclk,
2707 }; 2717 };
2708 2718
2709 static struct snd_soc_dai_driver wm8996_dai[] 2719 static struct snd_soc_dai_driver wm8996_dai[] = {
2710 { 2720 {
2711 .name = "wm8996-aif1", 2721 .name = "wm8996-aif1",
2712 .playback = { 2722 .playback = {
2713 .stream_name = "AIF1 2723 .stream_name = "AIF1 Playback",
2714 .channels_min = 1, 2724 .channels_min = 1,
2715 .channels_max = 6, 2725 .channels_max = 6,
2716 .rates = WM8996_RATES 2726 .rates = WM8996_RATES,
2717 .formats = WM8996_FOR 2727 .formats = WM8996_FORMATS,
2718 .sig_bits = 24, 2728 .sig_bits = 24,
2719 }, 2729 },
2720 .capture = { 2730 .capture = {
2721 .stream_name = "AIF1 2731 .stream_name = "AIF1 Capture",
2722 .channels_min = 1, 2732 .channels_min = 1,
2723 .channels_max = 6, 2733 .channels_max = 6,
2724 .rates = WM8996_RATE 2734 .rates = WM8996_RATES,
2725 .formats = WM8996_FO 2735 .formats = WM8996_FORMATS,
2726 .sig_bits = 24, 2736 .sig_bits = 24,
2727 }, 2737 },
2728 .ops = &wm8996_dai_ops, 2738 .ops = &wm8996_dai_ops,
2729 }, 2739 },
2730 { 2740 {
2731 .name = "wm8996-aif2", 2741 .name = "wm8996-aif2",
2732 .playback = { 2742 .playback = {
2733 .stream_name = "AIF2 2743 .stream_name = "AIF2 Playback",
2734 .channels_min = 1, 2744 .channels_min = 1,
2735 .channels_max = 2, 2745 .channels_max = 2,
2736 .rates = WM8996_RATES 2746 .rates = WM8996_RATES,
2737 .formats = WM8996_FOR 2747 .formats = WM8996_FORMATS,
2738 .sig_bits = 24, 2748 .sig_bits = 24,
2739 }, 2749 },
2740 .capture = { 2750 .capture = {
2741 .stream_name = "AIF2 2751 .stream_name = "AIF2 Capture",
2742 .channels_min = 1, 2752 .channels_min = 1,
2743 .channels_max = 2, 2753 .channels_max = 2,
2744 .rates = WM8996_RATE 2754 .rates = WM8996_RATES,
2745 .formats = WM8996_FO 2755 .formats = WM8996_FORMATS,
2746 .sig_bits = 24, 2756 .sig_bits = 24,
2747 }, 2757 },
2748 .ops = &wm8996_dai_ops, 2758 .ops = &wm8996_dai_ops,
2749 }, 2759 },
2750 }; 2760 };
2751 2761
2752 static int wm8996_i2c_probe(struct i2c_client !! 2762 static int wm8996_i2c_probe(struct i2c_client *i2c,
>> 2763 const struct i2c_device_id *id)
2753 { 2764 {
2754 struct wm8996_priv *wm8996; 2765 struct wm8996_priv *wm8996;
2755 int ret, i; 2766 int ret, i;
2756 unsigned int reg; 2767 unsigned int reg;
2757 2768
2758 wm8996 = devm_kzalloc(&i2c->dev, size 2769 wm8996 = devm_kzalloc(&i2c->dev, sizeof(struct wm8996_priv),
2759 GFP_KERNEL); 2770 GFP_KERNEL);
2760 if (wm8996 == NULL) 2771 if (wm8996 == NULL)
2761 return -ENOMEM; 2772 return -ENOMEM;
2762 2773
2763 i2c_set_clientdata(i2c, wm8996); 2774 i2c_set_clientdata(i2c, wm8996);
2764 wm8996->dev = &i2c->dev; 2775 wm8996->dev = &i2c->dev;
2765 2776
2766 if (dev_get_platdata(&i2c->dev)) 2777 if (dev_get_platdata(&i2c->dev))
2767 memcpy(&wm8996->pdata, dev_ge 2778 memcpy(&wm8996->pdata, dev_get_platdata(&i2c->dev),
2768 sizeof(wm8996->pdata)) 2779 sizeof(wm8996->pdata));
2769 2780
2770 wm8996->ldo_ena = devm_gpiod_get_opti !! 2781 if (wm8996->pdata.ldo_ena > 0) {
2771 !! 2782 ret = gpio_request_one(wm8996->pdata.ldo_ena,
2772 if (IS_ERR(wm8996->ldo_ena)) { !! 2783 GPIOF_OUT_INIT_LOW, "WM8996 ENA");
2773 ret = PTR_ERR(wm8996->ldo_ena !! 2784 if (ret < 0) {
2774 dev_err(&i2c->dev, "Failed to !! 2785 dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n",
2775 ret); !! 2786 wm8996->pdata.ldo_ena, ret);
2776 goto err; !! 2787 goto err;
>> 2788 }
2777 } 2789 }
2778 gpiod_set_consumer_name(wm8996->ldo_e <<
2779 2790
2780 for (i = 0; i < ARRAY_SIZE(wm8996->su 2791 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
2781 wm8996->supplies[i].supply = 2792 wm8996->supplies[i].supply = wm8996_supply_names[i];
2782 2793
2783 ret = devm_regulator_bulk_get(&i2c->d 2794 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8996->supplies),
2784 wm8996- 2795 wm8996->supplies);
2785 if (ret != 0) { 2796 if (ret != 0) {
2786 dev_err(&i2c->dev, "Failed to 2797 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
2787 goto err_gpio; 2798 goto err_gpio;
2788 } 2799 }
2789 2800
2790 wm8996->disable_nb[0].notifier_call = 2801 wm8996->disable_nb[0].notifier_call = wm8996_regulator_event_0;
2791 wm8996->disable_nb[1].notifier_call = 2802 wm8996->disable_nb[1].notifier_call = wm8996_regulator_event_1;
2792 wm8996->disable_nb[2].notifier_call = 2803 wm8996->disable_nb[2].notifier_call = wm8996_regulator_event_2;
2793 2804
2794 /* This should really be moved into t 2805 /* This should really be moved into the regulator core */
2795 for (i = 0; i < ARRAY_SIZE(wm8996->su 2806 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) {
2796 ret = devm_regulator_register !! 2807 ret = regulator_register_notifier(wm8996->supplies[i].consumer,
2797 !! 2808 &wm8996->disable_nb[i]);
2798 <<
2799 if (ret != 0) { 2809 if (ret != 0) {
2800 dev_err(&i2c->dev, 2810 dev_err(&i2c->dev,
2801 "Failed to re 2811 "Failed to register regulator notifier: %d\n",
2802 ret); 2812 ret);
2803 } 2813 }
2804 } 2814 }
2805 2815
2806 ret = regulator_bulk_enable(ARRAY_SIZ 2816 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
2807 wm8996->s 2817 wm8996->supplies);
2808 if (ret != 0) { 2818 if (ret != 0) {
2809 dev_err(&i2c->dev, "Failed to 2819 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
2810 goto err_gpio; 2820 goto err_gpio;
2811 } 2821 }
2812 2822
2813 if (wm8996->ldo_ena) { !! 2823 if (wm8996->pdata.ldo_ena > 0) {
2814 gpiod_set_value_cansleep(wm89 !! 2824 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1);
2815 msleep(5); 2825 msleep(5);
2816 } 2826 }
2817 2827
2818 wm8996->regmap = devm_regmap_init_i2c 2828 wm8996->regmap = devm_regmap_init_i2c(i2c, &wm8996_regmap);
2819 if (IS_ERR(wm8996->regmap)) { 2829 if (IS_ERR(wm8996->regmap)) {
2820 ret = PTR_ERR(wm8996->regmap) 2830 ret = PTR_ERR(wm8996->regmap);
2821 dev_err(&i2c->dev, "regmap_in 2831 dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
2822 goto err_enable; 2832 goto err_enable;
2823 } 2833 }
2824 2834
2825 ret = regmap_read(wm8996->regmap, WM8 2835 ret = regmap_read(wm8996->regmap, WM8996_SOFTWARE_RESET, ®);
2826 if (ret < 0) { 2836 if (ret < 0) {
2827 dev_err(&i2c->dev, "Failed to 2837 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
2828 goto err_regmap; 2838 goto err_regmap;
2829 } 2839 }
2830 if (reg != 0x8915) { 2840 if (reg != 0x8915) {
2831 dev_err(&i2c->dev, "Device is 2841 dev_err(&i2c->dev, "Device is not a WM8996, ID %x\n", reg);
2832 ret = -EINVAL; 2842 ret = -EINVAL;
2833 goto err_regmap; 2843 goto err_regmap;
2834 } 2844 }
2835 2845
2836 ret = regmap_read(wm8996->regmap, WM8 2846 ret = regmap_read(wm8996->regmap, WM8996_CHIP_REVISION, ®);
2837 if (ret < 0) { 2847 if (ret < 0) {
2838 dev_err(&i2c->dev, "Failed to 2848 dev_err(&i2c->dev, "Failed to read device revision: %d\n",
2839 ret); 2849 ret);
2840 goto err_regmap; 2850 goto err_regmap;
2841 } 2851 }
2842 2852
2843 dev_info(&i2c->dev, "revision %c\n", 2853 dev_info(&i2c->dev, "revision %c\n",
2844 (reg & WM8996_CHIP_REV_MASK) 2854 (reg & WM8996_CHIP_REV_MASK) + 'A');
2845 2855
2846 if (wm8996->ldo_ena) { !! 2856 if (wm8996->pdata.ldo_ena > 0) {
2847 gpiod_set_value_cansleep(wm89 !! 2857 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
2848 regcache_cache_only(wm8996->r 2858 regcache_cache_only(wm8996->regmap, true);
2849 } else { 2859 } else {
2850 ret = regmap_write(wm8996->re 2860 ret = regmap_write(wm8996->regmap, WM8996_SOFTWARE_RESET,
2851 0x8915); 2861 0x8915);
2852 if (ret != 0) { 2862 if (ret != 0) {
2853 dev_err(&i2c->dev, "F 2863 dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
2854 goto err_regmap; 2864 goto err_regmap;
2855 } 2865 }
2856 } 2866 }
2857 2867
2858 regulator_bulk_disable(ARRAY_SIZE(wm8 2868 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
2859 2869
2860 /* Apply platform data settings */ 2870 /* Apply platform data settings */
2861 regmap_update_bits(wm8996->regmap, WM 2871 regmap_update_bits(wm8996->regmap, WM8996_LINE_INPUT_CONTROL,
2862 WM8996_INL_MODE_MA 2872 WM8996_INL_MODE_MASK | WM8996_INR_MODE_MASK,
2863 wm8996->pdata.inl_ 2873 wm8996->pdata.inl_mode << WM8996_INL_MODE_SHIFT |
2864 wm8996->pdata.inr_ 2874 wm8996->pdata.inr_mode);
2865 2875
2866 for (i = 0; i < ARRAY_SIZE(wm8996->pd 2876 for (i = 0; i < ARRAY_SIZE(wm8996->pdata.gpio_default); i++) {
2867 if (!wm8996->pdata.gpio_defau 2877 if (!wm8996->pdata.gpio_default[i])
2868 continue; 2878 continue;
2869 2879
2870 regmap_write(wm8996->regmap, 2880 regmap_write(wm8996->regmap, WM8996_GPIO_1 + i,
2871 wm8996->pdata.gp 2881 wm8996->pdata.gpio_default[i] & 0xffff);
2872 } 2882 }
2873 2883
2874 if (wm8996->pdata.spkmute_seq) 2884 if (wm8996->pdata.spkmute_seq)
2875 regmap_update_bits(wm8996->re 2885 regmap_update_bits(wm8996->regmap,
2876 WM8996_PDM 2886 WM8996_PDM_SPEAKER_MUTE_SEQUENCE,
2877 WM8996_SPK 2887 WM8996_SPK_MUTE_ENDIAN |
2878 WM8996_SPK 2888 WM8996_SPK_MUTE_SEQ1_MASK,
2879 wm8996->pd 2889 wm8996->pdata.spkmute_seq);
2880 2890
2881 regmap_update_bits(wm8996->regmap, WM 2891 regmap_update_bits(wm8996->regmap, WM8996_ACCESSORY_DETECT_MODE_2,
2882 WM8996_MICD_BIAS_S 2892 WM8996_MICD_BIAS_SRC | WM8996_HPOUT1FB_SRC |
2883 WM8996_MICD_SRC, w 2893 WM8996_MICD_SRC, wm8996->pdata.micdet_def);
2884 2894
2885 /* Latch volume update bits */ 2895 /* Latch volume update bits */
2886 regmap_update_bits(wm8996->regmap, WM 2896 regmap_update_bits(wm8996->regmap, WM8996_LEFT_LINE_INPUT_VOLUME,
2887 WM8996_IN1_VU, WM8 2897 WM8996_IN1_VU, WM8996_IN1_VU);
2888 regmap_update_bits(wm8996->regmap, WM 2898 regmap_update_bits(wm8996->regmap, WM8996_RIGHT_LINE_INPUT_VOLUME,
2889 WM8996_IN1_VU, WM8 2899 WM8996_IN1_VU, WM8996_IN1_VU);
2890 2900
2891 regmap_update_bits(wm8996->regmap, WM 2901 regmap_update_bits(wm8996->regmap, WM8996_DAC1_LEFT_VOLUME,
2892 WM8996_DAC1_VU, WM 2902 WM8996_DAC1_VU, WM8996_DAC1_VU);
2893 regmap_update_bits(wm8996->regmap, WM 2903 regmap_update_bits(wm8996->regmap, WM8996_DAC1_RIGHT_VOLUME,
2894 WM8996_DAC1_VU, WM 2904 WM8996_DAC1_VU, WM8996_DAC1_VU);
2895 regmap_update_bits(wm8996->regmap, WM 2905 regmap_update_bits(wm8996->regmap, WM8996_DAC2_LEFT_VOLUME,
2896 WM8996_DAC2_VU, WM 2906 WM8996_DAC2_VU, WM8996_DAC2_VU);
2897 regmap_update_bits(wm8996->regmap, WM 2907 regmap_update_bits(wm8996->regmap, WM8996_DAC2_RIGHT_VOLUME,
2898 WM8996_DAC2_VU, WM 2908 WM8996_DAC2_VU, WM8996_DAC2_VU);
2899 2909
2900 regmap_update_bits(wm8996->regmap, WM 2910 regmap_update_bits(wm8996->regmap, WM8996_OUTPUT1_LEFT_VOLUME,
2901 WM8996_DAC1_VU, WM 2911 WM8996_DAC1_VU, WM8996_DAC1_VU);
2902 regmap_update_bits(wm8996->regmap, WM 2912 regmap_update_bits(wm8996->regmap, WM8996_OUTPUT1_RIGHT_VOLUME,
2903 WM8996_DAC1_VU, WM 2913 WM8996_DAC1_VU, WM8996_DAC1_VU);
2904 regmap_update_bits(wm8996->regmap, WM 2914 regmap_update_bits(wm8996->regmap, WM8996_OUTPUT2_LEFT_VOLUME,
2905 WM8996_DAC2_VU, WM 2915 WM8996_DAC2_VU, WM8996_DAC2_VU);
2906 regmap_update_bits(wm8996->regmap, WM 2916 regmap_update_bits(wm8996->regmap, WM8996_OUTPUT2_RIGHT_VOLUME,
2907 WM8996_DAC2_VU, WM 2917 WM8996_DAC2_VU, WM8996_DAC2_VU);
2908 2918
2909 regmap_update_bits(wm8996->regmap, WM 2919 regmap_update_bits(wm8996->regmap, WM8996_DSP1_TX_LEFT_VOLUME,
2910 WM8996_DSP1TX_VU, 2920 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2911 regmap_update_bits(wm8996->regmap, WM 2921 regmap_update_bits(wm8996->regmap, WM8996_DSP1_TX_RIGHT_VOLUME,
2912 WM8996_DSP1TX_VU, 2922 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2913 regmap_update_bits(wm8996->regmap, WM 2923 regmap_update_bits(wm8996->regmap, WM8996_DSP2_TX_LEFT_VOLUME,
2914 WM8996_DSP2TX_VU, 2924 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2915 regmap_update_bits(wm8996->regmap, WM 2925 regmap_update_bits(wm8996->regmap, WM8996_DSP2_TX_RIGHT_VOLUME,
2916 WM8996_DSP2TX_VU, 2926 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2917 2927
2918 regmap_update_bits(wm8996->regmap, WM 2928 regmap_update_bits(wm8996->regmap, WM8996_DSP1_RX_LEFT_VOLUME,
2919 WM8996_DSP1RX_VU, 2929 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2920 regmap_update_bits(wm8996->regmap, WM 2930 regmap_update_bits(wm8996->regmap, WM8996_DSP1_RX_RIGHT_VOLUME,
2921 WM8996_DSP1RX_VU, 2931 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2922 regmap_update_bits(wm8996->regmap, WM 2932 regmap_update_bits(wm8996->regmap, WM8996_DSP2_RX_LEFT_VOLUME,
2923 WM8996_DSP2RX_VU, 2933 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2924 regmap_update_bits(wm8996->regmap, WM 2934 regmap_update_bits(wm8996->regmap, WM8996_DSP2_RX_RIGHT_VOLUME,
2925 WM8996_DSP2RX_VU, 2935 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2926 2936
2927 /* No support currently for the under 2937 /* No support currently for the underclocked TDM modes and
2928 * pick a default TDM layout with eac 2938 * pick a default TDM layout with each channel pair working with
2929 * slots 0 and 1. */ 2939 * slots 0 and 1. */
2930 regmap_update_bits(wm8996->regmap, 2940 regmap_update_bits(wm8996->regmap,
2931 WM8996_AIF1RX_CHAN 2941 WM8996_AIF1RX_CHANNEL_0_CONFIGURATION,
2932 WM8996_AIF1RX_CHAN 2942 WM8996_AIF1RX_CHAN0_SLOTS_MASK |
2933 WM8996_AIF1RX_CHAN 2943 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2934 1 << WM8996_AIF1RX 2944 1 << WM8996_AIF1RX_CHAN0_SLOTS_SHIFT | 0);
2935 regmap_update_bits(wm8996->regmap, 2945 regmap_update_bits(wm8996->regmap,
2936 WM8996_AIF1RX_CHAN 2946 WM8996_AIF1RX_CHANNEL_1_CONFIGURATION,
2937 WM8996_AIF1RX_CHAN 2947 WM8996_AIF1RX_CHAN1_SLOTS_MASK |
2938 WM8996_AIF1RX_CHAN 2948 WM8996_AIF1RX_CHAN1_START_SLOT_MASK,
2939 1 << WM8996_AIF1RX 2949 1 << WM8996_AIF1RX_CHAN1_SLOTS_SHIFT | 1);
2940 regmap_update_bits(wm8996->regmap, 2950 regmap_update_bits(wm8996->regmap,
2941 WM8996_AIF1RX_CHAN 2951 WM8996_AIF1RX_CHANNEL_2_CONFIGURATION,
2942 WM8996_AIF1RX_CHAN 2952 WM8996_AIF1RX_CHAN2_SLOTS_MASK |
2943 WM8996_AIF1RX_CHAN 2953 WM8996_AIF1RX_CHAN2_START_SLOT_MASK,
2944 1 << WM8996_AIF1RX 2954 1 << WM8996_AIF1RX_CHAN2_SLOTS_SHIFT | 0);
2945 regmap_update_bits(wm8996->regmap, 2955 regmap_update_bits(wm8996->regmap,
2946 WM8996_AIF1RX_CHAN 2956 WM8996_AIF1RX_CHANNEL_3_CONFIGURATION,
2947 WM8996_AIF1RX_CHAN 2957 WM8996_AIF1RX_CHAN3_SLOTS_MASK |
2948 WM8996_AIF1RX_CHAN 2958 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2949 1 << WM8996_AIF1RX 2959 1 << WM8996_AIF1RX_CHAN3_SLOTS_SHIFT | 1);
2950 regmap_update_bits(wm8996->regmap, 2960 regmap_update_bits(wm8996->regmap,
2951 WM8996_AIF1RX_CHAN 2961 WM8996_AIF1RX_CHANNEL_4_CONFIGURATION,
2952 WM8996_AIF1RX_CHAN 2962 WM8996_AIF1RX_CHAN4_SLOTS_MASK |
2953 WM8996_AIF1RX_CHAN 2963 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2954 1 << WM8996_AIF1RX 2964 1 << WM8996_AIF1RX_CHAN4_SLOTS_SHIFT | 0);
2955 regmap_update_bits(wm8996->regmap, 2965 regmap_update_bits(wm8996->regmap,
2956 WM8996_AIF1RX_CHAN 2966 WM8996_AIF1RX_CHANNEL_5_CONFIGURATION,
2957 WM8996_AIF1RX_CHAN 2967 WM8996_AIF1RX_CHAN5_SLOTS_MASK |
2958 WM8996_AIF1RX_CHAN 2968 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2959 1 << WM8996_AIF1RX 2969 1 << WM8996_AIF1RX_CHAN5_SLOTS_SHIFT | 1);
2960 2970
2961 regmap_update_bits(wm8996->regmap, 2971 regmap_update_bits(wm8996->regmap,
2962 WM8996_AIF2RX_CHAN 2972 WM8996_AIF2RX_CHANNEL_0_CONFIGURATION,
2963 WM8996_AIF2RX_CHAN 2973 WM8996_AIF2RX_CHAN0_SLOTS_MASK |
2964 WM8996_AIF2RX_CHAN 2974 WM8996_AIF2RX_CHAN0_START_SLOT_MASK,
2965 1 << WM8996_AIF2RX 2975 1 << WM8996_AIF2RX_CHAN0_SLOTS_SHIFT | 0);
2966 regmap_update_bits(wm8996->regmap, 2976 regmap_update_bits(wm8996->regmap,
2967 WM8996_AIF2RX_CHAN 2977 WM8996_AIF2RX_CHANNEL_1_CONFIGURATION,
2968 WM8996_AIF2RX_CHAN 2978 WM8996_AIF2RX_CHAN1_SLOTS_MASK |
2969 WM8996_AIF2RX_CHAN 2979 WM8996_AIF2RX_CHAN1_START_SLOT_MASK,
2970 1 << WM8996_AIF2RX 2980 1 << WM8996_AIF2RX_CHAN1_SLOTS_SHIFT | 1);
2971 2981
2972 regmap_update_bits(wm8996->regmap, 2982 regmap_update_bits(wm8996->regmap,
2973 WM8996_AIF1TX_CHAN 2983 WM8996_AIF1TX_CHANNEL_0_CONFIGURATION,
2974 WM8996_AIF1TX_CHAN 2984 WM8996_AIF1TX_CHAN0_SLOTS_MASK |
2975 WM8996_AIF1TX_CHAN 2985 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2976 1 << WM8996_AIF1TX 2986 1 << WM8996_AIF1TX_CHAN0_SLOTS_SHIFT | 0);
2977 regmap_update_bits(wm8996->regmap, 2987 regmap_update_bits(wm8996->regmap,
2978 WM8996_AIF1TX_CHAN 2988 WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
2979 WM8996_AIF1TX_CHAN 2989 WM8996_AIF1TX_CHAN1_SLOTS_MASK |
2980 WM8996_AIF1TX_CHAN 2990 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2981 1 << WM8996_AIF1TX 2991 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2982 regmap_update_bits(wm8996->regmap, 2992 regmap_update_bits(wm8996->regmap,
2983 WM8996_AIF1TX_CHAN 2993 WM8996_AIF1TX_CHANNEL_2_CONFIGURATION,
2984 WM8996_AIF1TX_CHAN 2994 WM8996_AIF1TX_CHAN2_SLOTS_MASK |
2985 WM8996_AIF1TX_CHAN 2995 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2986 1 << WM8996_AIF1TX 2996 1 << WM8996_AIF1TX_CHAN2_SLOTS_SHIFT | 0);
2987 regmap_update_bits(wm8996->regmap, 2997 regmap_update_bits(wm8996->regmap,
2988 WM8996_AIF1TX_CHAN 2998 WM8996_AIF1TX_CHANNEL_3_CONFIGURATION,
2989 WM8996_AIF1TX_CHAN 2999 WM8996_AIF1TX_CHAN3_SLOTS_MASK |
2990 WM8996_AIF1TX_CHAN 3000 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2991 1 << WM8996_AIF1TX 3001 1 << WM8996_AIF1TX_CHAN3_SLOTS_SHIFT | 1);
2992 regmap_update_bits(wm8996->regmap, 3002 regmap_update_bits(wm8996->regmap,
2993 WM8996_AIF1TX_CHAN 3003 WM8996_AIF1TX_CHANNEL_4_CONFIGURATION,
2994 WM8996_AIF1TX_CHAN 3004 WM8996_AIF1TX_CHAN4_SLOTS_MASK |
2995 WM8996_AIF1TX_CHAN 3005 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2996 1 << WM8996_AIF1TX 3006 1 << WM8996_AIF1TX_CHAN4_SLOTS_SHIFT | 0);
2997 regmap_update_bits(wm8996->regmap, 3007 regmap_update_bits(wm8996->regmap,
2998 WM8996_AIF1TX_CHAN 3008 WM8996_AIF1TX_CHANNEL_5_CONFIGURATION,
2999 WM8996_AIF1TX_CHAN 3009 WM8996_AIF1TX_CHAN5_SLOTS_MASK |
3000 WM8996_AIF1TX_CHAN 3010 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
3001 1 << WM8996_AIF1TX 3011 1 << WM8996_AIF1TX_CHAN5_SLOTS_SHIFT | 1);
3002 3012
3003 regmap_update_bits(wm8996->regmap, 3013 regmap_update_bits(wm8996->regmap,
3004 WM8996_AIF2TX_CHAN 3014 WM8996_AIF2TX_CHANNEL_0_CONFIGURATION,
3005 WM8996_AIF2TX_CHAN 3015 WM8996_AIF2TX_CHAN0_SLOTS_MASK |
3006 WM8996_AIF2TX_CHAN 3016 WM8996_AIF2TX_CHAN0_START_SLOT_MASK,
3007 1 << WM8996_AIF2TX 3017 1 << WM8996_AIF2TX_CHAN0_SLOTS_SHIFT | 0);
3008 regmap_update_bits(wm8996->regmap, 3018 regmap_update_bits(wm8996->regmap,
3009 WM8996_AIF1TX_CHAN 3019 WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
3010 WM8996_AIF2TX_CHAN 3020 WM8996_AIF2TX_CHAN1_SLOTS_MASK |
3011 WM8996_AIF2TX_CHAN 3021 WM8996_AIF2TX_CHAN1_START_SLOT_MASK,
3012 1 << WM8996_AIF1TX 3022 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
3013 3023
3014 /* If the TX LRCLK pins are not in LR 3024 /* If the TX LRCLK pins are not in LRCLK mode configure the
3015 * AIFs to source their clocks from t 3025 * AIFs to source their clocks from the RX LRCLKs.
3016 */ 3026 */
3017 ret = regmap_read(wm8996->regmap, WM8 3027 ret = regmap_read(wm8996->regmap, WM8996_GPIO_1, ®);
3018 if (ret != 0) { 3028 if (ret != 0) {
3019 dev_err(&i2c->dev, "Failed to 3029 dev_err(&i2c->dev, "Failed to read GPIO1: %d\n", ret);
3020 goto err_regmap; 3030 goto err_regmap;
3021 } 3031 }
3022 3032
3023 if (reg & WM8996_GP1_FN_MASK) 3033 if (reg & WM8996_GP1_FN_MASK)
3024 regmap_update_bits(wm8996->re 3034 regmap_update_bits(wm8996->regmap, WM8996_AIF1_TX_LRCLK_2,
3025 WM8996_AIF 3035 WM8996_AIF1TX_LRCLK_MODE,
3026 WM8996_AIF 3036 WM8996_AIF1TX_LRCLK_MODE);
3027 3037
3028 ret = regmap_read(wm8996->regmap, WM8 3038 ret = regmap_read(wm8996->regmap, WM8996_GPIO_2, ®);
3029 if (ret != 0) { 3039 if (ret != 0) {
3030 dev_err(&i2c->dev, "Failed to 3040 dev_err(&i2c->dev, "Failed to read GPIO2: %d\n", ret);
3031 goto err_regmap; 3041 goto err_regmap;
3032 } 3042 }
3033 3043
3034 if (reg & WM8996_GP2_FN_MASK) 3044 if (reg & WM8996_GP2_FN_MASK)
3035 regmap_update_bits(wm8996->re 3045 regmap_update_bits(wm8996->regmap, WM8996_AIF2_TX_LRCLK_2,
3036 WM8996_AIF 3046 WM8996_AIF2TX_LRCLK_MODE,
3037 WM8996_AIF 3047 WM8996_AIF2TX_LRCLK_MODE);
3038 3048
3039 wm8996_init_gpio(wm8996); 3049 wm8996_init_gpio(wm8996);
3040 3050
3041 ret = devm_snd_soc_register_component !! 3051 ret = snd_soc_register_codec(&i2c->dev,
3042 &soc_com !! 3052 &soc_codec_dev_wm8996, wm8996_dai,
3043 ARRAY_SI 3053 ARRAY_SIZE(wm8996_dai));
3044 if (ret < 0) 3054 if (ret < 0)
3045 goto err_gpiolib; 3055 goto err_gpiolib;
3046 3056
3047 return ret; 3057 return ret;
3048 3058
3049 err_gpiolib: 3059 err_gpiolib:
3050 wm8996_free_gpio(wm8996); 3060 wm8996_free_gpio(wm8996);
3051 err_regmap: 3061 err_regmap:
3052 err_enable: 3062 err_enable:
3053 if (wm8996->ldo_ena) !! 3063 if (wm8996->pdata.ldo_ena > 0)
3054 gpiod_set_value_cansleep(wm89 !! 3064 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
3055 regulator_bulk_disable(ARRAY_SIZE(wm8 3065 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
3056 err_gpio: 3066 err_gpio:
>> 3067 if (wm8996->pdata.ldo_ena > 0)
>> 3068 gpio_free(wm8996->pdata.ldo_ena);
3057 err: 3069 err:
3058 3070
3059 return ret; 3071 return ret;
3060 } 3072 }
3061 3073
3062 static void wm8996_i2c_remove(struct i2c_clie !! 3074 static int wm8996_i2c_remove(struct i2c_client *client)
3063 { 3075 {
3064 struct wm8996_priv *wm8996 = i2c_get_ 3076 struct wm8996_priv *wm8996 = i2c_get_clientdata(client);
>> 3077 int i;
3065 3078
>> 3079 snd_soc_unregister_codec(&client->dev);
3066 wm8996_free_gpio(wm8996); 3080 wm8996_free_gpio(wm8996);
3067 if (wm8996->ldo_ena) !! 3081 if (wm8996->pdata.ldo_ena > 0) {
3068 gpiod_set_value_cansleep(wm89 !! 3082 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
>> 3083 gpio_free(wm8996->pdata.ldo_ena);
>> 3084 }
>> 3085 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
>> 3086 regulator_unregister_notifier(wm8996->supplies[i].consumer,
>> 3087 &wm8996->disable_nb[i]);
>> 3088
>> 3089 return 0;
3069 } 3090 }
3070 3091
3071 static const struct i2c_device_id wm8996_i2c_ 3092 static const struct i2c_device_id wm8996_i2c_id[] = {
3072 { "wm8996" }, !! 3093 { "wm8996", 0 },
3073 { } 3094 { }
3074 }; 3095 };
3075 MODULE_DEVICE_TABLE(i2c, wm8996_i2c_id); 3096 MODULE_DEVICE_TABLE(i2c, wm8996_i2c_id);
3076 3097
3077 static struct i2c_driver wm8996_i2c_driver = 3098 static struct i2c_driver wm8996_i2c_driver = {
3078 .driver = { 3099 .driver = {
3079 .name = "wm8996", 3100 .name = "wm8996",
3080 }, 3101 },
3081 .probe = wm8996_i2c_probe, 3102 .probe = wm8996_i2c_probe,
3082 .remove = wm8996_i2c_remove, 3103 .remove = wm8996_i2c_remove,
3083 .id_table = wm8996_i2c_id, 3104 .id_table = wm8996_i2c_id,
3084 }; 3105 };
3085 3106
3086 module_i2c_driver(wm8996_i2c_driver); 3107 module_i2c_driver(wm8996_i2c_driver);
3087 3108
3088 MODULE_DESCRIPTION("ASoC WM8996 driver"); 3109 MODULE_DESCRIPTION("ASoC WM8996 driver");
3089 MODULE_AUTHOR("Mark Brown <broonie@opensource 3110 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3090 MODULE_LICENSE("GPL"); 3111 MODULE_LICENSE("GPL");
3091 3112
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