1 // SPDX-License-Identifier: GPL-2.0-or-later 1
2 /*
3 * wm8996.c - WM8996 audio codec interface
4 *
5 * Copyright 2011-2 Wolfson Microelectronics P
6 * Author: Mark Brown <broonie@opensource.wolf
7 */
8
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/completion.h>
13 #include <linux/delay.h>
14 #include <linux/pm.h>
15 #include <linux/gcd.h>
16 #include <linux/gpio/driver.h>
17 #include <linux/gpio/consumer.h>
18 #include <linux/i2c.h>
19 #include <linux/regmap.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/slab.h>
22 #include <linux/workqueue.h>
23 #include <sound/core.h>
24 #include <sound/jack.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/soc.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
30 #include <trace/events/asoc.h>
31
32 #include <sound/wm8996.h>
33 #include "wm8996.h"
34
35 #define WM8996_AIFS 2
36
37 #define HPOUT1L 1
38 #define HPOUT1R 2
39 #define HPOUT2L 4
40 #define HPOUT2R 8
41
42 #define WM8996_NUM_SUPPLIES 3
43 static const char *wm8996_supply_names[WM8996_
44 "DBVDD",
45 "AVDD1",
46 "AVDD2",
47 };
48
49 struct wm8996_priv {
50 struct device *dev;
51 struct regmap *regmap;
52 struct snd_soc_component *component;
53
54 struct gpio_desc *ldo_ena;
55
56 int sysclk;
57 int sysclk_src;
58
59 int fll_src;
60 int fll_fref;
61 int fll_fout;
62
63 struct completion fll_lock;
64
65 u16 dcs_pending;
66 struct completion dcs_done;
67
68 u16 hpout_ena;
69 u16 hpout_pending;
70
71 struct regulator_bulk_data supplies[WM
72 struct notifier_block disable_nb[WM899
73 int bg_ena;
74
75 struct wm8996_pdata pdata;
76
77 int rx_rate[WM8996_AIFS];
78 int bclk_rate[WM8996_AIFS];
79
80 /* Platform dependant ReTune mobile co
81 int num_retune_mobile_texts;
82 const char **retune_mobile_texts;
83 int retune_mobile_cfg[2];
84 struct soc_enum retune_mobile_enum;
85
86 struct snd_soc_jack *jack;
87 bool detecting;
88 bool jack_mic;
89 int jack_flips;
90 wm8996_polarity_fn polarity_cb;
91
92 #ifdef CONFIG_GPIOLIB
93 struct gpio_chip gpio_chip;
94 #endif
95 };
96
97 /* We can't use the same notifier block for mo
98 * there's no way I can see to get from a call
99 * except container_of().
100 */
101 #define WM8996_REGULATOR_EVENT(n) \
102 static int wm8996_regulator_event_##n(struct n
103 unsigned l
104 { \
105 struct wm8996_priv *wm8996 = container
106
107 if (event & REGULATOR_EVENT_DISABLE) {
108 regcache_mark_dirty(wm8996->re
109 } \
110 return 0; \
111 }
112
113 WM8996_REGULATOR_EVENT(0)
114 WM8996_REGULATOR_EVENT(1)
115 WM8996_REGULATOR_EVENT(2)
116
117 static const struct reg_default wm8996_reg[] =
118 { WM8996_POWER_MANAGEMENT_1, 0x0 },
119 { WM8996_POWER_MANAGEMENT_2, 0x0 },
120 { WM8996_POWER_MANAGEMENT_3, 0x0 },
121 { WM8996_POWER_MANAGEMENT_4, 0x0 },
122 { WM8996_POWER_MANAGEMENT_5, 0x0 },
123 { WM8996_POWER_MANAGEMENT_6, 0x0 },
124 { WM8996_POWER_MANAGEMENT_7, 0x10 },
125 { WM8996_POWER_MANAGEMENT_8, 0x0 },
126 { WM8996_LEFT_LINE_INPUT_VOLUME, 0x0 }
127 { WM8996_RIGHT_LINE_INPUT_VOLUME, 0x0
128 { WM8996_LINE_INPUT_CONTROL, 0x0 },
129 { WM8996_DAC1_HPOUT1_VOLUME, 0x88 },
130 { WM8996_DAC2_HPOUT2_VOLUME, 0x88 },
131 { WM8996_DAC1_LEFT_VOLUME, 0x2c0 },
132 { WM8996_DAC1_RIGHT_VOLUME, 0x2c0 },
133 { WM8996_DAC2_LEFT_VOLUME, 0x2c0 },
134 { WM8996_DAC2_RIGHT_VOLUME, 0x2c0 },
135 { WM8996_OUTPUT1_LEFT_VOLUME, 0x80 },
136 { WM8996_OUTPUT1_RIGHT_VOLUME, 0x80 },
137 { WM8996_OUTPUT2_LEFT_VOLUME, 0x80 },
138 { WM8996_OUTPUT2_RIGHT_VOLUME, 0x80 },
139 { WM8996_MICBIAS_1, 0x39 },
140 { WM8996_MICBIAS_2, 0x39 },
141 { WM8996_LDO_1, 0x3 },
142 { WM8996_LDO_2, 0x13 },
143 { WM8996_ACCESSORY_DETECT_MODE_1, 0x4
144 { WM8996_ACCESSORY_DETECT_MODE_2, 0x0
145 { WM8996_HEADPHONE_DETECT_1, 0x20 },
146 { WM8996_HEADPHONE_DETECT_2, 0x0 },
147 { WM8996_MIC_DETECT_1, 0x7600 },
148 { WM8996_MIC_DETECT_2, 0xbf },
149 { WM8996_CHARGE_PUMP_1, 0x1f25 },
150 { WM8996_CHARGE_PUMP_2, 0xab19 },
151 { WM8996_DC_SERVO_1, 0x0 },
152 { WM8996_DC_SERVO_3, 0x0 },
153 { WM8996_DC_SERVO_5, 0x2a2a },
154 { WM8996_DC_SERVO_6, 0x0 },
155 { WM8996_DC_SERVO_7, 0x0 },
156 { WM8996_ANALOGUE_HP_1, 0x0 },
157 { WM8996_ANALOGUE_HP_2, 0x0 },
158 { WM8996_CONTROL_INTERFACE_1, 0x8004 }
159 { WM8996_WRITE_SEQUENCER_CTRL_1, 0x0 }
160 { WM8996_WRITE_SEQUENCER_CTRL_2, 0x0 }
161 { WM8996_AIF_CLOCKING_1, 0x0 },
162 { WM8996_AIF_CLOCKING_2, 0x0 },
163 { WM8996_CLOCKING_1, 0x10 },
164 { WM8996_CLOCKING_2, 0x0 },
165 { WM8996_AIF_RATE, 0x83 },
166 { WM8996_FLL_CONTROL_1, 0x0 },
167 { WM8996_FLL_CONTROL_2, 0x0 },
168 { WM8996_FLL_CONTROL_3, 0x0 },
169 { WM8996_FLL_CONTROL_4, 0x5dc0 },
170 { WM8996_FLL_CONTROL_5, 0xc84 },
171 { WM8996_FLL_EFS_1, 0x0 },
172 { WM8996_FLL_EFS_2, 0x2 },
173 { WM8996_AIF1_CONTROL, 0x0 },
174 { WM8996_AIF1_BCLK, 0x0 },
175 { WM8996_AIF1_TX_LRCLK_1, 0x80 },
176 { WM8996_AIF1_TX_LRCLK_2, 0x8 },
177 { WM8996_AIF1_RX_LRCLK_1, 0x80 },
178 { WM8996_AIF1_RX_LRCLK_2, 0x0 },
179 { WM8996_AIF1TX_DATA_CONFIGURATION_1,
180 { WM8996_AIF1TX_DATA_CONFIGURATION_2,
181 { WM8996_AIF1RX_DATA_CONFIGURATION, 0x
182 { WM8996_AIF1TX_CHANNEL_0_CONFIGURATIO
183 { WM8996_AIF1TX_CHANNEL_1_CONFIGURATIO
184 { WM8996_AIF1TX_CHANNEL_2_CONFIGURATIO
185 { WM8996_AIF1TX_CHANNEL_3_CONFIGURATIO
186 { WM8996_AIF1TX_CHANNEL_4_CONFIGURATIO
187 { WM8996_AIF1TX_CHANNEL_5_CONFIGURATIO
188 { WM8996_AIF1RX_CHANNEL_0_CONFIGURATIO
189 { WM8996_AIF1RX_CHANNEL_1_CONFIGURATIO
190 { WM8996_AIF1RX_CHANNEL_2_CONFIGURATIO
191 { WM8996_AIF1RX_CHANNEL_3_CONFIGURATIO
192 { WM8996_AIF1RX_CHANNEL_4_CONFIGURATIO
193 { WM8996_AIF1RX_CHANNEL_5_CONFIGURATIO
194 { WM8996_AIF1RX_MONO_CONFIGURATION, 0x
195 { WM8996_AIF1TX_TEST, 0x7 },
196 { WM8996_AIF2_CONTROL, 0x0 },
197 { WM8996_AIF2_BCLK, 0x0 },
198 { WM8996_AIF2_TX_LRCLK_1, 0x80 },
199 { WM8996_AIF2_TX_LRCLK_2, 0x8 },
200 { WM8996_AIF2_RX_LRCLK_1, 0x80 },
201 { WM8996_AIF2_RX_LRCLK_2, 0x0 },
202 { WM8996_AIF2TX_DATA_CONFIGURATION_1,
203 { WM8996_AIF2RX_DATA_CONFIGURATION, 0x
204 { WM8996_AIF2RX_DATA_CONFIGURATION, 0x
205 { WM8996_AIF2TX_CHANNEL_0_CONFIGURATIO
206 { WM8996_AIF2TX_CHANNEL_1_CONFIGURATIO
207 { WM8996_AIF2RX_CHANNEL_0_CONFIGURATIO
208 { WM8996_AIF2RX_CHANNEL_1_CONFIGURATIO
209 { WM8996_AIF2RX_MONO_CONFIGURATION, 0x
210 { WM8996_AIF2TX_TEST, 0x1 },
211 { WM8996_DSP1_TX_LEFT_VOLUME, 0xc0 },
212 { WM8996_DSP1_TX_RIGHT_VOLUME, 0xc0 },
213 { WM8996_DSP1_RX_LEFT_VOLUME, 0xc0 },
214 { WM8996_DSP1_RX_RIGHT_VOLUME, 0xc0 },
215 { WM8996_DSP1_TX_FILTERS, 0x2000 },
216 { WM8996_DSP1_RX_FILTERS_1, 0x200 },
217 { WM8996_DSP1_RX_FILTERS_2, 0x10 },
218 { WM8996_DSP1_DRC_1, 0x98 },
219 { WM8996_DSP1_DRC_2, 0x845 },
220 { WM8996_DSP1_RX_EQ_GAINS_1, 0x6318 },
221 { WM8996_DSP1_RX_EQ_GAINS_2, 0x6300 },
222 { WM8996_DSP1_RX_EQ_BAND_1_A, 0xfca },
223 { WM8996_DSP1_RX_EQ_BAND_1_B, 0x400 },
224 { WM8996_DSP1_RX_EQ_BAND_1_PG, 0xd8 },
225 { WM8996_DSP1_RX_EQ_BAND_2_A, 0x1eb5 }
226 { WM8996_DSP1_RX_EQ_BAND_2_B, 0xf145 }
227 { WM8996_DSP1_RX_EQ_BAND_2_C, 0xb75 },
228 { WM8996_DSP1_RX_EQ_BAND_2_PG, 0x1c5 }
229 { WM8996_DSP1_RX_EQ_BAND_3_A, 0x1c58 }
230 { WM8996_DSP1_RX_EQ_BAND_3_B, 0xf373 }
231 { WM8996_DSP1_RX_EQ_BAND_3_C, 0xa54 },
232 { WM8996_DSP1_RX_EQ_BAND_3_PG, 0x558 }
233 { WM8996_DSP1_RX_EQ_BAND_4_A, 0x168e }
234 { WM8996_DSP1_RX_EQ_BAND_4_B, 0xf829 }
235 { WM8996_DSP1_RX_EQ_BAND_4_C, 0x7ad },
236 { WM8996_DSP1_RX_EQ_BAND_4_PG, 0x1103
237 { WM8996_DSP1_RX_EQ_BAND_5_A, 0x564 },
238 { WM8996_DSP1_RX_EQ_BAND_5_B, 0x559 },
239 { WM8996_DSP1_RX_EQ_BAND_5_PG, 0x4000
240 { WM8996_DSP2_TX_LEFT_VOLUME, 0xc0 },
241 { WM8996_DSP2_TX_RIGHT_VOLUME, 0xc0 },
242 { WM8996_DSP2_RX_LEFT_VOLUME, 0xc0 },
243 { WM8996_DSP2_RX_RIGHT_VOLUME, 0xc0 },
244 { WM8996_DSP2_TX_FILTERS, 0x2000 },
245 { WM8996_DSP2_RX_FILTERS_1, 0x200 },
246 { WM8996_DSP2_RX_FILTERS_2, 0x10 },
247 { WM8996_DSP2_DRC_1, 0x98 },
248 { WM8996_DSP2_DRC_2, 0x845 },
249 { WM8996_DSP2_RX_EQ_GAINS_1, 0x6318 },
250 { WM8996_DSP2_RX_EQ_GAINS_2, 0x6300 },
251 { WM8996_DSP2_RX_EQ_BAND_1_A, 0xfca },
252 { WM8996_DSP2_RX_EQ_BAND_1_B, 0x400 },
253 { WM8996_DSP2_RX_EQ_BAND_1_PG, 0xd8 },
254 { WM8996_DSP2_RX_EQ_BAND_2_A, 0x1eb5 }
255 { WM8996_DSP2_RX_EQ_BAND_2_B, 0xf145 }
256 { WM8996_DSP2_RX_EQ_BAND_2_C, 0xb75 },
257 { WM8996_DSP2_RX_EQ_BAND_2_PG, 0x1c5 }
258 { WM8996_DSP2_RX_EQ_BAND_3_A, 0x1c58 }
259 { WM8996_DSP2_RX_EQ_BAND_3_B, 0xf373 }
260 { WM8996_DSP2_RX_EQ_BAND_3_C, 0xa54 },
261 { WM8996_DSP2_RX_EQ_BAND_3_PG, 0x558 }
262 { WM8996_DSP2_RX_EQ_BAND_4_A, 0x168e }
263 { WM8996_DSP2_RX_EQ_BAND_4_B, 0xf829 }
264 { WM8996_DSP2_RX_EQ_BAND_4_C, 0x7ad },
265 { WM8996_DSP2_RX_EQ_BAND_4_PG, 0x1103
266 { WM8996_DSP2_RX_EQ_BAND_5_A, 0x564 },
267 { WM8996_DSP2_RX_EQ_BAND_5_B, 0x559 },
268 { WM8996_DSP2_RX_EQ_BAND_5_PG, 0x4000
269 { WM8996_DAC1_MIXER_VOLUMES, 0x0 },
270 { WM8996_DAC1_LEFT_MIXER_ROUTING, 0x0
271 { WM8996_DAC1_RIGHT_MIXER_ROUTING, 0x0
272 { WM8996_DAC2_MIXER_VOLUMES, 0x0 },
273 { WM8996_DAC2_LEFT_MIXER_ROUTING, 0x0
274 { WM8996_DAC2_RIGHT_MIXER_ROUTING, 0x0
275 { WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 0
276 { WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
277 { WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 0
278 { WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
279 { WM8996_DSP_TX_MIXER_SELECT, 0x0 },
280 { WM8996_DAC_SOFTMUTE, 0x0 },
281 { WM8996_OVERSAMPLING, 0xd },
282 { WM8996_SIDETONE, 0x1040 },
283 { WM8996_GPIO_1, 0xa101 },
284 { WM8996_GPIO_2, 0xa101 },
285 { WM8996_GPIO_3, 0xa101 },
286 { WM8996_GPIO_4, 0xa101 },
287 { WM8996_GPIO_5, 0xa101 },
288 { WM8996_PULL_CONTROL_1, 0x0 },
289 { WM8996_PULL_CONTROL_2, 0x140 },
290 { WM8996_INTERRUPT_STATUS_1_MASK, 0x1f
291 { WM8996_INTERRUPT_STATUS_2_MASK, 0x1e
292 { WM8996_LEFT_PDM_SPEAKER, 0x0 },
293 { WM8996_RIGHT_PDM_SPEAKER, 0x1 },
294 { WM8996_PDM_SPEAKER_MUTE_SEQUENCE, 0x
295 { WM8996_PDM_SPEAKER_VOLUME, 0x66 },
296 };
297
298 static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0
299 static const DECLARE_TLV_DB_SCALE(sidetone_tlv
300 static const DECLARE_TLV_DB_SCALE(digital_tlv,
301 static const DECLARE_TLV_DB_SCALE(out_digital_
302 static const DECLARE_TLV_DB_SCALE(out_tlv, -90
303 static const DECLARE_TLV_DB_SCALE(spk_tlv, -90
304 static const DECLARE_TLV_DB_SCALE(eq_tlv, -120
305 static const DECLARE_TLV_DB_SCALE(threedstereo
306
307 static const char *sidetone_hpf_text[] = {
308 "2.9kHz", "1.5kHz", "735Hz", "403Hz",
309 };
310
311 static SOC_ENUM_SINGLE_DECL(sidetone_hpf,
312 WM8996_SIDETONE, 7
313
314 static const char *hpf_mode_text[] = {
315 "HiFi", "Custom", "Voice"
316 };
317
318 static SOC_ENUM_SINGLE_DECL(dsp1tx_hpf_mode,
319 WM8996_DSP1_TX_FIL
320
321 static SOC_ENUM_SINGLE_DECL(dsp2tx_hpf_mode,
322 WM8996_DSP2_TX_FIL
323
324 static const char *hpf_cutoff_text[] = {
325 "50Hz", "75Hz", "100Hz", "150Hz", "200
326 };
327
328 static SOC_ENUM_SINGLE_DECL(dsp1tx_hpf_cutoff,
329 WM8996_DSP1_TX_FIL
330
331 static SOC_ENUM_SINGLE_DECL(dsp2tx_hpf_cutoff,
332 WM8996_DSP2_TX_FIL
333
334 static void wm8996_set_retune_mobile(struct sn
335 {
336 struct wm8996_priv *wm8996 = snd_soc_c
337 struct wm8996_pdata *pdata = &wm8996->
338 int base, best, best_val, save, i, cfg
339
340 if (!wm8996->num_retune_mobile_texts)
341 return;
342
343 switch (block) {
344 case 0:
345 base = WM8996_DSP1_RX_EQ_GAINS
346 if (snd_soc_component_read(com
347 WM8996_DSP1RX_SRC)
348 iface = 1;
349 else
350 iface = 0;
351 break;
352 case 1:
353 base = WM8996_DSP1_RX_EQ_GAINS
354 if (snd_soc_component_read(com
355 WM8996_DSP2RX_SRC)
356 iface = 1;
357 else
358 iface = 0;
359 break;
360 default:
361 return;
362 }
363
364 /* Find the version of the currently s
365 * with the nearest sample rate. */
366 cfg = wm8996->retune_mobile_cfg[block]
367 best = 0;
368 best_val = INT_MAX;
369 for (i = 0; i < pdata->num_retune_mobi
370 if (strcmp(pdata->retune_mobil
371 wm8996->retune_mobi
372 abs(pdata->retune_mobile_c
373 - wm8996->rx_rate[ifac
374 best = i;
375 best_val = abs(pdata->
376 - wm899
377 }
378 }
379
380 dev_dbg(component->dev, "ReTune Mobile
381 block,
382 pdata->retune_mobile_cfgs[best
383 pdata->retune_mobile_cfgs[best
384 wm8996->rx_rate[iface]);
385
386 /* The EQ will be disabled while recon
387 * current configuration.
388 */
389 save = snd_soc_component_read(componen
390 save &= WM8996_DSP1RX_EQ_ENA;
391
392 for (i = 0; i < ARRAY_SIZE(pdata->retu
393 snd_soc_component_update_bits(
394 pdata->ret
395
396 snd_soc_component_update_bits(componen
397 }
398
399 /* Icky as hell but saves code duplication */
400 static int wm8996_get_retune_mobile_block(cons
401 {
402 if (strcmp(name, "DSP1 EQ Mode") == 0)
403 return 0;
404 if (strcmp(name, "DSP2 EQ Mode") == 0)
405 return 1;
406 return -EINVAL;
407 }
408
409 static int wm8996_put_retune_mobile_enum(struc
410 struc
411 {
412 struct snd_soc_component *component =
413 struct wm8996_priv *wm8996 = snd_soc_c
414 struct wm8996_pdata *pdata = &wm8996->
415 int block = wm8996_get_retune_mobile_b
416 int value = ucontrol->value.enumerated
417
418 if (block < 0)
419 return block;
420
421 if (value >= pdata->num_retune_mobile_
422 return -EINVAL;
423
424 wm8996->retune_mobile_cfg[block] = val
425
426 wm8996_set_retune_mobile(component, bl
427
428 return 0;
429 }
430
431 static int wm8996_get_retune_mobile_enum(struc
432 struc
433 {
434 struct snd_soc_component *component =
435 struct wm8996_priv *wm8996 = snd_soc_c
436 int block = wm8996_get_retune_mobile_b
437
438 if (block < 0)
439 return block;
440 ucontrol->value.enumerated.item[0] = w
441
442 return 0;
443 }
444
445 static const struct snd_kcontrol_new wm8996_sn
446 SOC_DOUBLE_R_TLV("Capture Volume", WM8996_LEFT
447 WM8996_RIGHT_LINE_INPUT_VOLUM
448 SOC_DOUBLE_R("Capture ZC Switch", WM8996_LEFT_
449 WM8996_RIGHT_LINE_INPUT_VOLUME, 5
450
451 SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8996_
452 0, 5, 24, 0, sidetone_tlv),
453 SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8996_
454 0, 5, 24, 0, sidetone_tlv),
455 SOC_SINGLE("Sidetone LPF Switch", WM8996_SIDET
456 SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf)
457 SOC_SINGLE("Sidetone HPF Switch", WM8996_SIDET
458
459 SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8996
460 WM8996_DSP1_TX_RIGHT_VOLUME,
461 SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8996
462 WM8996_DSP2_TX_RIGHT_VOLUME,
463
464 SOC_SINGLE("DSP1 Capture Notch Filter Switch",
465 13, 1, 0),
466 SOC_DOUBLE("DSP1 Capture HPF Switch", WM8996_D
467 SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_m
468 SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf
469
470 SOC_SINGLE("DSP2 Capture Notch Filter Switch",
471 13, 1, 0),
472 SOC_DOUBLE("DSP2 Capture HPF Switch", WM8996_D
473 SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_m
474 SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf
475
476 SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM899
477 WM8996_DSP1_RX_RIGHT_VOLUME,
478 SOC_SINGLE("DSP1 Playback Switch", WM8996_DSP1
479
480 SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM899
481 WM8996_DSP2_RX_RIGHT_VOLUME,
482 SOC_SINGLE("DSP2 Playback Switch", WM8996_DSP2
483
484 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8996_DAC1_LE
485 WM8996_DAC1_RIGHT_VOLUME, 1,
486 SOC_DOUBLE_R("DAC1 Switch", WM8996_DAC1_LEFT_V
487 WM8996_DAC1_RIGHT_VOLUME, 9, 1, 1
488
489 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8996_DAC2_LE
490 WM8996_DAC2_RIGHT_VOLUME, 1,
491 SOC_DOUBLE_R("DAC2 Switch", WM8996_DAC2_LEFT_V
492 WM8996_DAC2_RIGHT_VOLUME, 9, 1, 1
493
494 SOC_SINGLE("Speaker High Performance Switch",
495 SOC_SINGLE("DMIC High Performance Switch", WM8
496 SOC_SINGLE("ADC High Performance Switch", WM89
497 SOC_SINGLE("DAC High Performance Switch", WM89
498
499 SOC_SINGLE("DAC Soft Mute Switch", WM8996_DAC_
500 SOC_SINGLE("DAC Slow Soft Mute Switch", WM8996
501
502 SOC_SINGLE("DSP1 3D Stereo Switch", WM8996_DSP
503 SOC_SINGLE("DSP2 3D Stereo Switch", WM8996_DSP
504
505 SOC_SINGLE_TLV("DSP1 3D Stereo Volume", WM8996
506 0, threedstereo_tlv),
507 SOC_SINGLE_TLV("DSP2 3D Stereo Volume", WM8996
508 0, threedstereo_tlv),
509
510 SOC_DOUBLE_TLV("Digital Output 1 Volume", WM89
511 8, 0, out_digital_tlv),
512 SOC_DOUBLE_TLV("Digital Output 2 Volume", WM89
513 8, 0, out_digital_tlv),
514
515 SOC_DOUBLE_R_TLV("Output 1 Volume", WM8996_OUT
516 WM8996_OUTPUT1_RIGHT_VOLUME,
517 SOC_DOUBLE_R("Output 1 ZC Switch", WM8996_OUT
518 WM8996_OUTPUT1_RIGHT_VOLUME, 7, 1
519
520 SOC_DOUBLE_R_TLV("Output 2 Volume", WM8996_OUT
521 WM8996_OUTPUT2_RIGHT_VOLUME,
522 SOC_DOUBLE_R("Output 2 ZC Switch", WM8996_OUT
523 WM8996_OUTPUT2_RIGHT_VOLUME, 7, 1
524
525 SOC_DOUBLE_TLV("Speaker Volume", WM8996_PDM_SP
526 spk_tlv),
527 SOC_DOUBLE_R("Speaker Switch", WM8996_LEFT_PDM
528 WM8996_RIGHT_PDM_SPEAKER, 3, 1, 1
529 SOC_DOUBLE_R("Speaker ZC Switch", WM8996_LEFT_
530 WM8996_RIGHT_PDM_SPEAKER, 2, 1, 0
531
532 SOC_SINGLE("DSP1 EQ Switch", WM8996_DSP1_RX_EQ
533 SOC_SINGLE("DSP2 EQ Switch", WM8996_DSP2_RX_EQ
534
535 SOC_SINGLE("DSP1 DRC TXL Switch", WM8996_DSP1_
536 SOC_SINGLE("DSP1 DRC TXR Switch", WM8996_DSP1_
537 SOC_SINGLE("DSP1 DRC RX Switch", WM8996_DSP1_D
538 SND_SOC_BYTES_MASK("DSP1 DRC", WM8996_DSP1_DRC
539 WM8996_DSP1RX_DRC_ENA | WM8
540 WM8996_DSP1TXR_DRC_ENA),
541
542 SOC_SINGLE("DSP2 DRC TXL Switch", WM8996_DSP2_
543 SOC_SINGLE("DSP2 DRC TXR Switch", WM8996_DSP2_
544 SOC_SINGLE("DSP2 DRC RX Switch", WM8996_DSP2_D
545 SND_SOC_BYTES_MASK("DSP2 DRC", WM8996_DSP2_DRC
546 WM8996_DSP2RX_DRC_ENA | WM8
547 WM8996_DSP2TXR_DRC_ENA),
548 };
549
550 static const struct snd_kcontrol_new wm8996_eq
551 SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8996_DSP
552 eq_tlv),
553 SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8996_DSP
554 eq_tlv),
555 SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8996_DSP
556 eq_tlv),
557 SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8996_DSP
558 eq_tlv),
559 SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8996_DSP
560 eq_tlv),
561
562 SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8996_DSP
563 eq_tlv),
564 SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8996_DSP
565 eq_tlv),
566 SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8996_DSP
567 eq_tlv),
568 SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8996_DSP
569 eq_tlv),
570 SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8996_DSP
571 eq_tlv),
572 };
573
574 static void wm8996_bg_enable(struct snd_soc_co
575 {
576 struct wm8996_priv *wm8996 = snd_soc_c
577
578 wm8996->bg_ena++;
579 if (wm8996->bg_ena == 1) {
580 snd_soc_component_update_bits(
581 WM8996_BG_
582 msleep(2);
583 }
584 }
585
586 static void wm8996_bg_disable(struct snd_soc_c
587 {
588 struct wm8996_priv *wm8996 = snd_soc_c
589
590 wm8996->bg_ena--;
591 if (!wm8996->bg_ena)
592 snd_soc_component_update_bits(
593 WM8996_BG_
594 }
595
596 static int bg_event(struct snd_soc_dapm_widget
597 struct snd_kcontrol *kcont
598 {
599 struct snd_soc_component *component =
600 int ret = 0;
601
602 switch (event) {
603 case SND_SOC_DAPM_PRE_PMU:
604 wm8996_bg_enable(component);
605 break;
606 case SND_SOC_DAPM_POST_PMD:
607 wm8996_bg_disable(component);
608 break;
609 default:
610 WARN(1, "Invalid event %d\n",
611 ret = -EINVAL;
612 }
613
614 return ret;
615 }
616
617 static int cp_event(struct snd_soc_dapm_widget
618 struct snd_kcontrol *kcont
619 {
620 switch (event) {
621 case SND_SOC_DAPM_POST_PMU:
622 msleep(5);
623 break;
624 default:
625 WARN(1, "Invalid event %d\n",
626 }
627
628 return 0;
629 }
630
631 static int rmv_short_event(struct snd_soc_dapm
632 struct snd_kcontrol
633 {
634 struct snd_soc_component *component =
635 struct wm8996_priv *wm8996 = snd_soc_c
636
637 /* Record which outputs we enabled */
638 switch (event) {
639 case SND_SOC_DAPM_PRE_PMD:
640 wm8996->hpout_pending &= ~w->s
641 break;
642 case SND_SOC_DAPM_PRE_PMU:
643 wm8996->hpout_pending |= w->sh
644 break;
645 default:
646 WARN(1, "Invalid event %d\n",
647 return -EINVAL;
648 }
649
650 return 0;
651 }
652
653 static void wait_for_dc_servo(struct snd_soc_c
654 {
655 struct i2c_client *i2c = to_i2c_client
656 struct wm8996_priv *wm8996 = snd_soc_c
657 int ret;
658 unsigned long time_left = 200;
659
660 snd_soc_component_write(component, WM8
661
662 /* Use the interrupt if possible */
663 do {
664 if (i2c->irq) {
665 time_left = wait_for_c
666
667 if (time_left == 0)
668 dev_err(compon
669
670 } else {
671 msleep(1);
672 time_left--;
673 }
674
675 ret = snd_soc_component_read(c
676 dev_dbg(component->dev, "DC se
677 } while (time_left && ret & mask);
678
679 if (time_left == 0)
680 dev_err(component->dev, "DC se
681 else
682 dev_dbg(component->dev, "DC se
683 }
684
685 static void wm8996_seq_notifier(struct snd_soc
686 enum snd_soc_d
687 {
688 struct wm8996_priv *wm8996 = snd_soc_c
689 u16 val, mask;
690
691 /* Complete any pending DC servo start
692 if (wm8996->dcs_pending) {
693 dev_dbg(component->dev, "Start
694 wm8996->dcs_pending);
695
696 /* Trigger a startup sequence
697 wait_for_dc_servo(component, w
698 << WM
699
700 wm8996->dcs_pending = 0;
701 }
702
703 if (wm8996->hpout_pending != wm8996->h
704 dev_dbg(component->dev, "Apply
705 wm8996->hpout_ena, wm8
706
707 val = 0;
708 mask = 0;
709 if (wm8996->hpout_pending & HP
710 val |= WM8996_HPOUT1L_
711 mask |= WM8996_HPOUT1L
712 } else {
713 mask |= WM8996_HPOUT1L
714 WM8996_HPOUT1L
715 WM8996_HPOUT1L
716 }
717
718 if (wm8996->hpout_pending & HP
719 val |= WM8996_HPOUT1R_
720 mask |= WM8996_HPOUT1R
721 } else {
722 mask |= WM8996_HPOUT1R
723 WM8996_HPOUT1R
724 WM8996_HPOUT1R
725 }
726
727 snd_soc_component_update_bits(
728
729 val = 0;
730 mask = 0;
731 if (wm8996->hpout_pending & HP
732 val |= WM8996_HPOUT2L_
733 mask |= WM8996_HPOUT2L
734 } else {
735 mask |= WM8996_HPOUT2L
736 WM8996_HPOUT2L
737 WM8996_HPOUT2L
738 }
739
740 if (wm8996->hpout_pending & HP
741 val |= WM8996_HPOUT2R_
742 mask |= WM8996_HPOUT2R
743 } else {
744 mask |= WM8996_HPOUT2R
745 WM8996_HPOUT2R
746 WM8996_HPOUT2R
747 }
748
749 snd_soc_component_update_bits(
750
751 wm8996->hpout_ena = wm8996->hp
752 }
753 }
754
755 static int dcs_start(struct snd_soc_dapm_widge
756 struct snd_kcontrol *kcon
757 {
758 struct snd_soc_component *component =
759 struct wm8996_priv *wm8996 = snd_soc_c
760
761 switch (event) {
762 case SND_SOC_DAPM_POST_PMU:
763 wm8996->dcs_pending |= 1 << w-
764 break;
765 default:
766 WARN(1, "Invalid event %d\n",
767 return -EINVAL;
768 }
769
770 return 0;
771 }
772
773 static const char *sidetone_text[] = {
774 "IN1", "IN2",
775 };
776
777 static SOC_ENUM_SINGLE_DECL(left_sidetone_enum
778 WM8996_SIDETONE, 0
779
780 static const struct snd_kcontrol_new left_side
781 SOC_DAPM_ENUM("Left Sidetone", left_si
782
783 static SOC_ENUM_SINGLE_DECL(right_sidetone_enu
784 WM8996_SIDETONE, 1
785
786 static const struct snd_kcontrol_new right_sid
787 SOC_DAPM_ENUM("Right Sidetone", right_
788
789 static const char *spk_text[] = {
790 "DAC1L", "DAC1R", "DAC2L", "DAC2R"
791 };
792
793 static SOC_ENUM_SINGLE_DECL(spkl_enum,
794 WM8996_LEFT_PDM_SP
795
796 static const struct snd_kcontrol_new spkl_mux
797 SOC_DAPM_ENUM("SPKL", spkl_enum);
798
799 static SOC_ENUM_SINGLE_DECL(spkr_enum,
800 WM8996_RIGHT_PDM_S
801
802 static const struct snd_kcontrol_new spkr_mux
803 SOC_DAPM_ENUM("SPKR", spkr_enum);
804
805 static const char *dsp1rx_text[] = {
806 "AIF1", "AIF2"
807 };
808
809 static SOC_ENUM_SINGLE_DECL(dsp1rx_enum,
810 WM8996_POWER_MANAG
811
812 static const struct snd_kcontrol_new dsp1rx =
813 SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum);
814
815 static const char *dsp2rx_text[] = {
816 "AIF2", "AIF1"
817 };
818
819 static SOC_ENUM_SINGLE_DECL(dsp2rx_enum,
820 WM8996_POWER_MANAG
821
822 static const struct snd_kcontrol_new dsp2rx =
823 SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum);
824
825 static const char *aif2tx_text[] = {
826 "DSP2", "DSP1", "AIF1"
827 };
828
829 static SOC_ENUM_SINGLE_DECL(aif2tx_enum,
830 WM8996_POWER_MANAG
831
832 static const struct snd_kcontrol_new aif2tx =
833 SOC_DAPM_ENUM("AIF2TX", aif2tx_enum);
834
835 static const char *inmux_text[] = {
836 "ADC", "DMIC1", "DMIC2"
837 };
838
839 static SOC_ENUM_SINGLE_DECL(in1_enum,
840 WM8996_POWER_MANAG
841
842 static const struct snd_kcontrol_new in1_mux =
843 SOC_DAPM_ENUM("IN1 Mux", in1_enum);
844
845 static SOC_ENUM_SINGLE_DECL(in2_enum,
846 WM8996_POWER_MANAG
847
848 static const struct snd_kcontrol_new in2_mux =
849 SOC_DAPM_ENUM("IN2 Mux", in2_enum);
850
851 static const struct snd_kcontrol_new dac2r_mix
852 SOC_DAPM_SINGLE("Right Sidetone Switch", WM899
853 5, 1, 0),
854 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996
855 4, 1, 0),
856 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_RIG
857 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_RIG
858 };
859
860 static const struct snd_kcontrol_new dac2l_mix
861 SOC_DAPM_SINGLE("Right Sidetone Switch", WM899
862 5, 1, 0),
863 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996
864 4, 1, 0),
865 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_LEF
866 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_LEF
867 };
868
869 static const struct snd_kcontrol_new dac1r_mix
870 SOC_DAPM_SINGLE("Right Sidetone Switch", WM899
871 5, 1, 0),
872 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996
873 4, 1, 0),
874 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_RIG
875 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_RIG
876 };
877
878 static const struct snd_kcontrol_new dac1l_mix
879 SOC_DAPM_SINGLE("Right Sidetone Switch", WM899
880 5, 1, 0),
881 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996
882 4, 1, 0),
883 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_LEF
884 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_LEF
885 };
886
887 static const struct snd_kcontrol_new dsp1txl[]
888 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_L
889 1, 1, 0),
890 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_L
891 0, 1, 0),
892 };
893
894 static const struct snd_kcontrol_new dsp1txr[]
895 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_R
896 1, 1, 0),
897 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_R
898 0, 1, 0),
899 };
900
901 static const struct snd_kcontrol_new dsp2txl[]
902 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_L
903 1, 1, 0),
904 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_L
905 0, 1, 0),
906 };
907
908 static const struct snd_kcontrol_new dsp2txr[]
909 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_R
910 1, 1, 0),
911 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_R
912 0, 1, 0),
913 };
914
915
916 static const struct snd_soc_dapm_widget wm8996
917 SND_SOC_DAPM_INPUT("IN1LN"),
918 SND_SOC_DAPM_INPUT("IN1LP"),
919 SND_SOC_DAPM_INPUT("IN1RN"),
920 SND_SOC_DAPM_INPUT("IN1RP"),
921
922 SND_SOC_DAPM_INPUT("IN2LN"),
923 SND_SOC_DAPM_INPUT("IN2LP"),
924 SND_SOC_DAPM_INPUT("IN2RN"),
925 SND_SOC_DAPM_INPUT("IN2RP"),
926
927 SND_SOC_DAPM_INPUT("DMIC1DAT"),
928 SND_SOC_DAPM_INPUT("DMIC2DAT"),
929
930 SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0),
931 SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8996_AIF_
932 SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8996_C
933 SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8996_CLOC
934 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8996
935 SND_SOC_DAPM_POST_PMU),
936 SND_SOC_DAPM_SUPPLY("Bandgap", SND_SOC_NOPM, 0
937 SND_SOC_DAPM_PRE_PMU | SND
938 SND_SOC_DAPM_SUPPLY("LDO2", WM8996_POWER_MANAG
939 SND_SOC_DAPM_SUPPLY("MICB1 Audio", WM8996_MICB
940 SND_SOC_DAPM_SUPPLY("MICB2 Audio", WM8996_MICB
941 SND_SOC_DAPM_MICBIAS("MICB2", WM8996_POWER_MAN
942 SND_SOC_DAPM_MICBIAS("MICB1", WM8996_POWER_MAN
943
944 SND_SOC_DAPM_PGA("IN1L PGA", WM8996_POWER_MANA
945 SND_SOC_DAPM_PGA("IN1R PGA", WM8996_POWER_MANA
946
947 SND_SOC_DAPM_MUX("IN1L Mux", WM8996_POWER_MANA
948 SND_SOC_DAPM_MUX("IN1R Mux", WM8996_POWER_MANA
949 SND_SOC_DAPM_MUX("IN2L Mux", WM8996_POWER_MANA
950 SND_SOC_DAPM_MUX("IN2R Mux", WM8996_POWER_MANA
951
952 SND_SOC_DAPM_SUPPLY("DMIC2", WM8996_POWER_MANA
953 SND_SOC_DAPM_SUPPLY("DMIC1", WM8996_POWER_MANA
954
955 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8996_POWER_
956 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8996_POWER_
957 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8996_POWER_
958 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8996_POWER_
959
960 SND_SOC_DAPM_ADC("ADCL", NULL, WM8996_POWER_MA
961 SND_SOC_DAPM_ADC("ADCR", NULL, WM8996_POWER_MA
962
963 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM
964 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOP
965
966 SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8996
967 SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8996
968 SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8996
969 SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8996
970
971 SND_SOC_DAPM_MIXER("DSP2TXL", WM8996_POWER_MAN
972 dsp2txl, ARRAY_SIZE(dsp2txl
973 SND_SOC_DAPM_MIXER("DSP2TXR", WM8996_POWER_MAN
974 dsp2txr, ARRAY_SIZE(dsp2txr
975 SND_SOC_DAPM_MIXER("DSP1TXL", WM8996_POWER_MAN
976 dsp1txl, ARRAY_SIZE(dsp1txl
977 SND_SOC_DAPM_MIXER("DSP1TXR", WM8996_POWER_MAN
978 dsp1txr, ARRAY_SIZE(dsp1txr
979
980 SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM
981 dac2l_mix, ARRAY_SIZE(dac2l
982 SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM
983 dac2r_mix, ARRAY_SIZE(dac2r
984 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM
985 dac1l_mix, ARRAY_SIZE(dac1l
986 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM
987 dac1r_mix, ARRAY_SIZE(dac1r
988
989 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8996_POWER_M
990 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8996_POWER_M
991 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8996_POWER_M
992 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8996_POWER_M
993
994 SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0, WM8996
995 SND_SOC_DAPM_AIF_IN("AIF2RX0", NULL, 1, WM8996
996
997 SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0, WM899
998 SND_SOC_DAPM_AIF_OUT("AIF2TX0", NULL, 1, WM899
999
1000 SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 5, WM899
1001 SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 4, WM899
1002 SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 3, WM899
1003 SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 2, WM899
1004 SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 1, WM899
1005 SND_SOC_DAPM_AIF_IN("AIF1RX0", NULL, 0, WM899
1006
1007 SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 5, WM89
1008 SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 4, WM89
1009 SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 3, WM89
1010 SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 2, WM89
1011 SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 1, WM89
1012 SND_SOC_DAPM_AIF_OUT("AIF1TX0", NULL, 0, WM89
1013
1014 /* We route as stereo pairs so define some du
1015 * things down for now. RXA = 0,1, RXB = 2,3
1016 SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0,
1017 SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0,
1018 SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0,
1019 SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0
1020 SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0
1021
1022 SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0
1023 SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0
1024 SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0
1025
1026 SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0,
1027 SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0,
1028 SND_SOC_DAPM_PGA("SPKL PGA", WM8996_LEFT_PDM_
1029 SND_SOC_DAPM_PGA("SPKR PGA", WM8996_RIGHT_PDM
1030
1031 SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8996_P
1032 SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8996_A
1033 SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8996_D
1034 SND_SOC_DAPM_POST_PMU),
1035 SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SN
1036 rmv_short_event,
1037 SND_SOC_DAPM_PRE_PMU | SND
1038
1039 SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8996_P
1040 SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8996_A
1041 SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8996_D
1042 SND_SOC_DAPM_POST_PMU),
1043 SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SN
1044 rmv_short_event,
1045 SND_SOC_DAPM_PRE_PMU | SND
1046
1047 SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8996_P
1048 SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8996_A
1049 SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8996_D
1050 SND_SOC_DAPM_POST_PMU),
1051 SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SN
1052 rmv_short_event,
1053 SND_SOC_DAPM_PRE_PMU | SND
1054
1055 SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8996_P
1056 SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8996_A
1057 SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8996_D
1058 SND_SOC_DAPM_POST_PMU),
1059 SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SN
1060 rmv_short_event,
1061 SND_SOC_DAPM_PRE_PMU | SND
1062
1063 SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1064 SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1065 SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1066 SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1067 SND_SOC_DAPM_OUTPUT("SPKDAT"),
1068 };
1069
1070 static const struct snd_soc_dapm_route wm8996
1071 { "AIFCLK", NULL, "SYSCLK" },
1072 { "SYSDSPCLK", NULL, "SYSCLK" },
1073 { "Charge Pump", NULL, "SYSCLK" },
1074 { "Charge Pump", NULL, "CPVDD" },
1075
1076 { "MICB1", NULL, "LDO2" },
1077 { "MICB1", NULL, "MICB1 Audio" },
1078 { "MICB1", NULL, "Bandgap" },
1079 { "MICB2", NULL, "LDO2" },
1080 { "MICB2", NULL, "MICB2 Audio" },
1081 { "MICB2", NULL, "Bandgap" },
1082
1083 { "AIF1RX0", NULL, "AIF1 Playback" },
1084 { "AIF1RX1", NULL, "AIF1 Playback" },
1085 { "AIF1RX2", NULL, "AIF1 Playback" },
1086 { "AIF1RX3", NULL, "AIF1 Playback" },
1087 { "AIF1RX4", NULL, "AIF1 Playback" },
1088 { "AIF1RX5", NULL, "AIF1 Playback" },
1089
1090 { "AIF2RX0", NULL, "AIF2 Playback" },
1091 { "AIF2RX1", NULL, "AIF2 Playback" },
1092
1093 { "AIF1 Capture", NULL, "AIF1TX0" },
1094 { "AIF1 Capture", NULL, "AIF1TX1" },
1095 { "AIF1 Capture", NULL, "AIF1TX2" },
1096 { "AIF1 Capture", NULL, "AIF1TX3" },
1097 { "AIF1 Capture", NULL, "AIF1TX4" },
1098 { "AIF1 Capture", NULL, "AIF1TX5" },
1099
1100 { "AIF2 Capture", NULL, "AIF2TX0" },
1101 { "AIF2 Capture", NULL, "AIF2TX1" },
1102
1103 { "IN1L PGA", NULL, "IN2LN" },
1104 { "IN1L PGA", NULL, "IN2LP" },
1105 { "IN1L PGA", NULL, "IN1LN" },
1106 { "IN1L PGA", NULL, "IN1LP" },
1107 { "IN1L PGA", NULL, "Bandgap" },
1108
1109 { "IN1R PGA", NULL, "IN2RN" },
1110 { "IN1R PGA", NULL, "IN2RP" },
1111 { "IN1R PGA", NULL, "IN1RN" },
1112 { "IN1R PGA", NULL, "IN1RP" },
1113 { "IN1R PGA", NULL, "Bandgap" },
1114
1115 { "ADCL", NULL, "IN1L PGA" },
1116
1117 { "ADCR", NULL, "IN1R PGA" },
1118
1119 { "DMIC1L", NULL, "DMIC1DAT" },
1120 { "DMIC1R", NULL, "DMIC1DAT" },
1121 { "DMIC2L", NULL, "DMIC2DAT" },
1122 { "DMIC2R", NULL, "DMIC2DAT" },
1123
1124 { "DMIC2L", NULL, "DMIC2" },
1125 { "DMIC2R", NULL, "DMIC2" },
1126 { "DMIC1L", NULL, "DMIC1" },
1127 { "DMIC1R", NULL, "DMIC1" },
1128
1129 { "IN1L Mux", "ADC", "ADCL" },
1130 { "IN1L Mux", "DMIC1", "DMIC1L" },
1131 { "IN1L Mux", "DMIC2", "DMIC2L" },
1132
1133 { "IN1R Mux", "ADC", "ADCR" },
1134 { "IN1R Mux", "DMIC1", "DMIC1R" },
1135 { "IN1R Mux", "DMIC2", "DMIC2R" },
1136
1137 { "IN2L Mux", "ADC", "ADCL" },
1138 { "IN2L Mux", "DMIC1", "DMIC1L" },
1139 { "IN2L Mux", "DMIC2", "DMIC2L" },
1140
1141 { "IN2R Mux", "ADC", "ADCR" },
1142 { "IN2R Mux", "DMIC1", "DMIC1R" },
1143 { "IN2R Mux", "DMIC2", "DMIC2R" },
1144
1145 { "Left Sidetone", "IN1", "IN1L Mux"
1146 { "Left Sidetone", "IN2", "IN2L Mux"
1147
1148 { "Right Sidetone", "IN1", "IN1R Mux"
1149 { "Right Sidetone", "IN2", "IN2R Mux"
1150
1151 { "DSP1TXL", "IN1 Switch", "IN1L Mux"
1152 { "DSP1TXR", "IN1 Switch", "IN1R Mux"
1153
1154 { "DSP2TXL", "IN1 Switch", "IN2L Mux"
1155 { "DSP2TXR", "IN1 Switch", "IN2R Mux"
1156
1157 { "AIF1TX0", NULL, "DSP1TXL" },
1158 { "AIF1TX1", NULL, "DSP1TXR" },
1159 { "AIF1TX2", NULL, "DSP2TXL" },
1160 { "AIF1TX3", NULL, "DSP2TXR" },
1161 { "AIF1TX4", NULL, "AIF2RX0" },
1162 { "AIF1TX5", NULL, "AIF2RX1" },
1163
1164 { "AIF1RX0", NULL, "AIFCLK" },
1165 { "AIF1RX1", NULL, "AIFCLK" },
1166 { "AIF1RX2", NULL, "AIFCLK" },
1167 { "AIF1RX3", NULL, "AIFCLK" },
1168 { "AIF1RX4", NULL, "AIFCLK" },
1169 { "AIF1RX5", NULL, "AIFCLK" },
1170
1171 { "AIF2RX0", NULL, "AIFCLK" },
1172 { "AIF2RX1", NULL, "AIFCLK" },
1173
1174 { "AIF1TX0", NULL, "AIFCLK" },
1175 { "AIF1TX1", NULL, "AIFCLK" },
1176 { "AIF1TX2", NULL, "AIFCLK" },
1177 { "AIF1TX3", NULL, "AIFCLK" },
1178 { "AIF1TX4", NULL, "AIFCLK" },
1179 { "AIF1TX5", NULL, "AIFCLK" },
1180
1181 { "AIF2TX0", NULL, "AIFCLK" },
1182 { "AIF2TX1", NULL, "AIFCLK" },
1183
1184 { "DSP1RXL", NULL, "SYSDSPCLK" },
1185 { "DSP1RXR", NULL, "SYSDSPCLK" },
1186 { "DSP2RXL", NULL, "SYSDSPCLK" },
1187 { "DSP2RXR", NULL, "SYSDSPCLK" },
1188 { "DSP1TXL", NULL, "SYSDSPCLK" },
1189 { "DSP1TXR", NULL, "SYSDSPCLK" },
1190 { "DSP2TXL", NULL, "SYSDSPCLK" },
1191 { "DSP2TXR", NULL, "SYSDSPCLK" },
1192
1193 { "AIF1RXA", NULL, "AIF1RX0" },
1194 { "AIF1RXA", NULL, "AIF1RX1" },
1195 { "AIF1RXB", NULL, "AIF1RX2" },
1196 { "AIF1RXB", NULL, "AIF1RX3" },
1197 { "AIF1RXC", NULL, "AIF1RX4" },
1198 { "AIF1RXC", NULL, "AIF1RX5" },
1199
1200 { "AIF2RX", NULL, "AIF2RX0" },
1201 { "AIF2RX", NULL, "AIF2RX1" },
1202
1203 { "AIF2TX", "DSP2", "DSP2TX" },
1204 { "AIF2TX", "DSP1", "DSP1RX" },
1205 { "AIF2TX", "AIF1", "AIF1RXC" },
1206
1207 { "DSP1RXL", NULL, "DSP1RX" },
1208 { "DSP1RXR", NULL, "DSP1RX" },
1209 { "DSP2RXL", NULL, "DSP2RX" },
1210 { "DSP2RXR", NULL, "DSP2RX" },
1211
1212 { "DSP2TX", NULL, "DSP2TXL" },
1213 { "DSP2TX", NULL, "DSP2TXR" },
1214
1215 { "DSP1RX", "AIF1", "AIF1RXA" },
1216 { "DSP1RX", "AIF2", "AIF2RX" },
1217
1218 { "DSP2RX", "AIF1", "AIF1RXB" },
1219 { "DSP2RX", "AIF2", "AIF2RX" },
1220
1221 { "DAC2L Mixer", "DSP2 Switch", "DSP2
1222 { "DAC2L Mixer", "DSP1 Switch", "DSP1
1223 { "DAC2L Mixer", "Right Sidetone Swit
1224 { "DAC2L Mixer", "Left Sidetone Switc
1225
1226 { "DAC2R Mixer", "DSP2 Switch", "DSP2
1227 { "DAC2R Mixer", "DSP1 Switch", "DSP1
1228 { "DAC2R Mixer", "Right Sidetone Swit
1229 { "DAC2R Mixer", "Left Sidetone Switc
1230
1231 { "DAC1L Mixer", "DSP2 Switch", "DSP2
1232 { "DAC1L Mixer", "DSP1 Switch", "DSP1
1233 { "DAC1L Mixer", "Right Sidetone Swit
1234 { "DAC1L Mixer", "Left Sidetone Switc
1235
1236 { "DAC1R Mixer", "DSP2 Switch", "DSP2
1237 { "DAC1R Mixer", "DSP1 Switch", "DSP1
1238 { "DAC1R Mixer", "Right Sidetone Swit
1239 { "DAC1R Mixer", "Left Sidetone Switc
1240
1241 { "DAC1L", NULL, "DAC1L Mixer" },
1242 { "DAC1R", NULL, "DAC1R Mixer" },
1243 { "DAC2L", NULL, "DAC2L Mixer" },
1244 { "DAC2R", NULL, "DAC2R Mixer" },
1245
1246 { "HPOUT2L PGA", NULL, "Charge Pump"
1247 { "HPOUT2L PGA", NULL, "Bandgap" },
1248 { "HPOUT2L PGA", NULL, "DAC2L" },
1249 { "HPOUT2L_DLY", NULL, "HPOUT2L PGA"
1250 { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY"
1251 { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L
1252
1253 { "HPOUT2R PGA", NULL, "Charge Pump"
1254 { "HPOUT2R PGA", NULL, "Bandgap" },
1255 { "HPOUT2R PGA", NULL, "DAC2R" },
1256 { "HPOUT2R_DLY", NULL, "HPOUT2R PGA"
1257 { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY"
1258 { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R
1259
1260 { "HPOUT1L PGA", NULL, "Charge Pump"
1261 { "HPOUT1L PGA", NULL, "Bandgap" },
1262 { "HPOUT1L PGA", NULL, "DAC1L" },
1263 { "HPOUT1L_DLY", NULL, "HPOUT1L PGA"
1264 { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY"
1265 { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L
1266
1267 { "HPOUT1R PGA", NULL, "Charge Pump"
1268 { "HPOUT1R PGA", NULL, "Bandgap" },
1269 { "HPOUT1R PGA", NULL, "DAC1R" },
1270 { "HPOUT1R_DLY", NULL, "HPOUT1R PGA"
1271 { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY"
1272 { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R
1273
1274 { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT
1275 { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT
1276 { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT
1277 { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT
1278
1279 { "SPKL", "DAC1L", "DAC1L" },
1280 { "SPKL", "DAC1R", "DAC1R" },
1281 { "SPKL", "DAC2L", "DAC2L" },
1282 { "SPKL", "DAC2R", "DAC2R" },
1283
1284 { "SPKR", "DAC1L", "DAC1L" },
1285 { "SPKR", "DAC1R", "DAC1R" },
1286 { "SPKR", "DAC2L", "DAC2L" },
1287 { "SPKR", "DAC2R", "DAC2R" },
1288
1289 { "SPKL PGA", NULL, "SPKL" },
1290 { "SPKR PGA", NULL, "SPKR" },
1291
1292 { "SPKDAT", NULL, "SPKL PGA" },
1293 { "SPKDAT", NULL, "SPKR PGA" },
1294 };
1295
1296 static bool wm8996_readable_register(struct d
1297 {
1298 /* Due to the sparseness of the regis
1299 * output from an explicit switch sta
1300 * more efficient than a table.
1301 */
1302 switch (reg) {
1303 case WM8996_SOFTWARE_RESET:
1304 case WM8996_POWER_MANAGEMENT_1:
1305 case WM8996_POWER_MANAGEMENT_2:
1306 case WM8996_POWER_MANAGEMENT_3:
1307 case WM8996_POWER_MANAGEMENT_4:
1308 case WM8996_POWER_MANAGEMENT_5:
1309 case WM8996_POWER_MANAGEMENT_6:
1310 case WM8996_POWER_MANAGEMENT_7:
1311 case WM8996_POWER_MANAGEMENT_8:
1312 case WM8996_LEFT_LINE_INPUT_VOLUME:
1313 case WM8996_RIGHT_LINE_INPUT_VOLUME:
1314 case WM8996_LINE_INPUT_CONTROL:
1315 case WM8996_DAC1_HPOUT1_VOLUME:
1316 case WM8996_DAC2_HPOUT2_VOLUME:
1317 case WM8996_DAC1_LEFT_VOLUME:
1318 case WM8996_DAC1_RIGHT_VOLUME:
1319 case WM8996_DAC2_LEFT_VOLUME:
1320 case WM8996_DAC2_RIGHT_VOLUME:
1321 case WM8996_OUTPUT1_LEFT_VOLUME:
1322 case WM8996_OUTPUT1_RIGHT_VOLUME:
1323 case WM8996_OUTPUT2_LEFT_VOLUME:
1324 case WM8996_OUTPUT2_RIGHT_VOLUME:
1325 case WM8996_MICBIAS_1:
1326 case WM8996_MICBIAS_2:
1327 case WM8996_LDO_1:
1328 case WM8996_LDO_2:
1329 case WM8996_ACCESSORY_DETECT_MODE_1:
1330 case WM8996_ACCESSORY_DETECT_MODE_2:
1331 case WM8996_HEADPHONE_DETECT_1:
1332 case WM8996_HEADPHONE_DETECT_2:
1333 case WM8996_MIC_DETECT_1:
1334 case WM8996_MIC_DETECT_2:
1335 case WM8996_MIC_DETECT_3:
1336 case WM8996_CHARGE_PUMP_1:
1337 case WM8996_CHARGE_PUMP_2:
1338 case WM8996_DC_SERVO_1:
1339 case WM8996_DC_SERVO_2:
1340 case WM8996_DC_SERVO_3:
1341 case WM8996_DC_SERVO_5:
1342 case WM8996_DC_SERVO_6:
1343 case WM8996_DC_SERVO_7:
1344 case WM8996_DC_SERVO_READBACK_0:
1345 case WM8996_ANALOGUE_HP_1:
1346 case WM8996_ANALOGUE_HP_2:
1347 case WM8996_CHIP_REVISION:
1348 case WM8996_CONTROL_INTERFACE_1:
1349 case WM8996_WRITE_SEQUENCER_CTRL_1:
1350 case WM8996_WRITE_SEQUENCER_CTRL_2:
1351 case WM8996_AIF_CLOCKING_1:
1352 case WM8996_AIF_CLOCKING_2:
1353 case WM8996_CLOCKING_1:
1354 case WM8996_CLOCKING_2:
1355 case WM8996_AIF_RATE:
1356 case WM8996_FLL_CONTROL_1:
1357 case WM8996_FLL_CONTROL_2:
1358 case WM8996_FLL_CONTROL_3:
1359 case WM8996_FLL_CONTROL_4:
1360 case WM8996_FLL_CONTROL_5:
1361 case WM8996_FLL_CONTROL_6:
1362 case WM8996_FLL_EFS_1:
1363 case WM8996_FLL_EFS_2:
1364 case WM8996_AIF1_CONTROL:
1365 case WM8996_AIF1_BCLK:
1366 case WM8996_AIF1_TX_LRCLK_1:
1367 case WM8996_AIF1_TX_LRCLK_2:
1368 case WM8996_AIF1_RX_LRCLK_1:
1369 case WM8996_AIF1_RX_LRCLK_2:
1370 case WM8996_AIF1TX_DATA_CONFIGURATION
1371 case WM8996_AIF1TX_DATA_CONFIGURATION
1372 case WM8996_AIF1RX_DATA_CONFIGURATION
1373 case WM8996_AIF1TX_CHANNEL_0_CONFIGUR
1374 case WM8996_AIF1TX_CHANNEL_1_CONFIGUR
1375 case WM8996_AIF1TX_CHANNEL_2_CONFIGUR
1376 case WM8996_AIF1TX_CHANNEL_3_CONFIGUR
1377 case WM8996_AIF1TX_CHANNEL_4_CONFIGUR
1378 case WM8996_AIF1TX_CHANNEL_5_CONFIGUR
1379 case WM8996_AIF1RX_CHANNEL_0_CONFIGUR
1380 case WM8996_AIF1RX_CHANNEL_1_CONFIGUR
1381 case WM8996_AIF1RX_CHANNEL_2_CONFIGUR
1382 case WM8996_AIF1RX_CHANNEL_3_CONFIGUR
1383 case WM8996_AIF1RX_CHANNEL_4_CONFIGUR
1384 case WM8996_AIF1RX_CHANNEL_5_CONFIGUR
1385 case WM8996_AIF1RX_MONO_CONFIGURATION
1386 case WM8996_AIF1TX_TEST:
1387 case WM8996_AIF2_CONTROL:
1388 case WM8996_AIF2_BCLK:
1389 case WM8996_AIF2_TX_LRCLK_1:
1390 case WM8996_AIF2_TX_LRCLK_2:
1391 case WM8996_AIF2_RX_LRCLK_1:
1392 case WM8996_AIF2_RX_LRCLK_2:
1393 case WM8996_AIF2TX_DATA_CONFIGURATION
1394 case WM8996_AIF2TX_DATA_CONFIGURATION
1395 case WM8996_AIF2RX_DATA_CONFIGURATION
1396 case WM8996_AIF2TX_CHANNEL_0_CONFIGUR
1397 case WM8996_AIF2TX_CHANNEL_1_CONFIGUR
1398 case WM8996_AIF2RX_CHANNEL_0_CONFIGUR
1399 case WM8996_AIF2RX_CHANNEL_1_CONFIGUR
1400 case WM8996_AIF2RX_MONO_CONFIGURATION
1401 case WM8996_AIF2TX_TEST:
1402 case WM8996_DSP1_TX_LEFT_VOLUME:
1403 case WM8996_DSP1_TX_RIGHT_VOLUME:
1404 case WM8996_DSP1_RX_LEFT_VOLUME:
1405 case WM8996_DSP1_RX_RIGHT_VOLUME:
1406 case WM8996_DSP1_TX_FILTERS:
1407 case WM8996_DSP1_RX_FILTERS_1:
1408 case WM8996_DSP1_RX_FILTERS_2:
1409 case WM8996_DSP1_DRC_1:
1410 case WM8996_DSP1_DRC_2:
1411 case WM8996_DSP1_DRC_3:
1412 case WM8996_DSP1_DRC_4:
1413 case WM8996_DSP1_DRC_5:
1414 case WM8996_DSP1_RX_EQ_GAINS_1:
1415 case WM8996_DSP1_RX_EQ_GAINS_2:
1416 case WM8996_DSP1_RX_EQ_BAND_1_A:
1417 case WM8996_DSP1_RX_EQ_BAND_1_B:
1418 case WM8996_DSP1_RX_EQ_BAND_1_PG:
1419 case WM8996_DSP1_RX_EQ_BAND_2_A:
1420 case WM8996_DSP1_RX_EQ_BAND_2_B:
1421 case WM8996_DSP1_RX_EQ_BAND_2_C:
1422 case WM8996_DSP1_RX_EQ_BAND_2_PG:
1423 case WM8996_DSP1_RX_EQ_BAND_3_A:
1424 case WM8996_DSP1_RX_EQ_BAND_3_B:
1425 case WM8996_DSP1_RX_EQ_BAND_3_C:
1426 case WM8996_DSP1_RX_EQ_BAND_3_PG:
1427 case WM8996_DSP1_RX_EQ_BAND_4_A:
1428 case WM8996_DSP1_RX_EQ_BAND_4_B:
1429 case WM8996_DSP1_RX_EQ_BAND_4_C:
1430 case WM8996_DSP1_RX_EQ_BAND_4_PG:
1431 case WM8996_DSP1_RX_EQ_BAND_5_A:
1432 case WM8996_DSP1_RX_EQ_BAND_5_B:
1433 case WM8996_DSP1_RX_EQ_BAND_5_PG:
1434 case WM8996_DSP2_TX_LEFT_VOLUME:
1435 case WM8996_DSP2_TX_RIGHT_VOLUME:
1436 case WM8996_DSP2_RX_LEFT_VOLUME:
1437 case WM8996_DSP2_RX_RIGHT_VOLUME:
1438 case WM8996_DSP2_TX_FILTERS:
1439 case WM8996_DSP2_RX_FILTERS_1:
1440 case WM8996_DSP2_RX_FILTERS_2:
1441 case WM8996_DSP2_DRC_1:
1442 case WM8996_DSP2_DRC_2:
1443 case WM8996_DSP2_DRC_3:
1444 case WM8996_DSP2_DRC_4:
1445 case WM8996_DSP2_DRC_5:
1446 case WM8996_DSP2_RX_EQ_GAINS_1:
1447 case WM8996_DSP2_RX_EQ_GAINS_2:
1448 case WM8996_DSP2_RX_EQ_BAND_1_A:
1449 case WM8996_DSP2_RX_EQ_BAND_1_B:
1450 case WM8996_DSP2_RX_EQ_BAND_1_PG:
1451 case WM8996_DSP2_RX_EQ_BAND_2_A:
1452 case WM8996_DSP2_RX_EQ_BAND_2_B:
1453 case WM8996_DSP2_RX_EQ_BAND_2_C:
1454 case WM8996_DSP2_RX_EQ_BAND_2_PG:
1455 case WM8996_DSP2_RX_EQ_BAND_3_A:
1456 case WM8996_DSP2_RX_EQ_BAND_3_B:
1457 case WM8996_DSP2_RX_EQ_BAND_3_C:
1458 case WM8996_DSP2_RX_EQ_BAND_3_PG:
1459 case WM8996_DSP2_RX_EQ_BAND_4_A:
1460 case WM8996_DSP2_RX_EQ_BAND_4_B:
1461 case WM8996_DSP2_RX_EQ_BAND_4_C:
1462 case WM8996_DSP2_RX_EQ_BAND_4_PG:
1463 case WM8996_DSP2_RX_EQ_BAND_5_A:
1464 case WM8996_DSP2_RX_EQ_BAND_5_B:
1465 case WM8996_DSP2_RX_EQ_BAND_5_PG:
1466 case WM8996_DAC1_MIXER_VOLUMES:
1467 case WM8996_DAC1_LEFT_MIXER_ROUTING:
1468 case WM8996_DAC1_RIGHT_MIXER_ROUTING:
1469 case WM8996_DAC2_MIXER_VOLUMES:
1470 case WM8996_DAC2_LEFT_MIXER_ROUTING:
1471 case WM8996_DAC2_RIGHT_MIXER_ROUTING:
1472 case WM8996_DSP1_TX_LEFT_MIXER_ROUTIN
1473 case WM8996_DSP1_TX_RIGHT_MIXER_ROUTI
1474 case WM8996_DSP2_TX_LEFT_MIXER_ROUTIN
1475 case WM8996_DSP2_TX_RIGHT_MIXER_ROUTI
1476 case WM8996_DSP_TX_MIXER_SELECT:
1477 case WM8996_DAC_SOFTMUTE:
1478 case WM8996_OVERSAMPLING:
1479 case WM8996_SIDETONE:
1480 case WM8996_GPIO_1:
1481 case WM8996_GPIO_2:
1482 case WM8996_GPIO_3:
1483 case WM8996_GPIO_4:
1484 case WM8996_GPIO_5:
1485 case WM8996_PULL_CONTROL_1:
1486 case WM8996_PULL_CONTROL_2:
1487 case WM8996_INTERRUPT_STATUS_1:
1488 case WM8996_INTERRUPT_STATUS_2:
1489 case WM8996_INTERRUPT_RAW_STATUS_2:
1490 case WM8996_INTERRUPT_STATUS_1_MASK:
1491 case WM8996_INTERRUPT_STATUS_2_MASK:
1492 case WM8996_INTERRUPT_CONTROL:
1493 case WM8996_LEFT_PDM_SPEAKER:
1494 case WM8996_RIGHT_PDM_SPEAKER:
1495 case WM8996_PDM_SPEAKER_MUTE_SEQUENCE
1496 case WM8996_PDM_SPEAKER_VOLUME:
1497 return true;
1498 default:
1499 return false;
1500 }
1501 }
1502
1503 static bool wm8996_volatile_register(struct d
1504 {
1505 switch (reg) {
1506 case WM8996_SOFTWARE_RESET:
1507 case WM8996_CHIP_REVISION:
1508 case WM8996_LDO_1:
1509 case WM8996_LDO_2:
1510 case WM8996_INTERRUPT_STATUS_1:
1511 case WM8996_INTERRUPT_STATUS_2:
1512 case WM8996_INTERRUPT_RAW_STATUS_2:
1513 case WM8996_DC_SERVO_READBACK_0:
1514 case WM8996_DC_SERVO_2:
1515 case WM8996_DC_SERVO_6:
1516 case WM8996_DC_SERVO_7:
1517 case WM8996_FLL_CONTROL_6:
1518 case WM8996_MIC_DETECT_3:
1519 case WM8996_HEADPHONE_DETECT_1:
1520 case WM8996_HEADPHONE_DETECT_2:
1521 return true;
1522 default:
1523 return false;
1524 }
1525 }
1526
1527 static const int bclk_divs[] = {
1528 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48,
1529 };
1530
1531 static void wm8996_update_bclk(struct snd_soc
1532 {
1533 struct wm8996_priv *wm8996 = snd_soc_
1534 int aif, best, cur_val, bclk_rate, bc
1535
1536 /* Don't bother if we're in a low fre
1537 * can't support audio.
1538 */
1539 if (wm8996->sysclk < 64000)
1540 return;
1541
1542 for (aif = 0; aif < WM8996_AIFS; aif+
1543 switch (aif) {
1544 case 0:
1545 bclk_reg = WM8996_AIF
1546 break;
1547 case 1:
1548 bclk_reg = WM8996_AIF
1549 break;
1550 }
1551
1552 bclk_rate = wm8996->bclk_rate
1553
1554 /* Pick a divisor for BCLK as
1555 best = 0;
1556 for (i = 0; i < ARRAY_SIZE(bc
1557 cur_val = (wm8996->sy
1558 if (cur_val < 0) /* B
1559 break;
1560 best = i;
1561 }
1562 bclk_rate = wm8996->sysclk /
1563 dev_dbg(component->dev, "Usin
1564 bclk_divs[best], bclk
1565
1566 snd_soc_component_update_bits
1567 WM8996_AI
1568 }
1569 }
1570
1571 static int wm8996_set_bias_level(struct snd_s
1572 enum snd_soc
1573 {
1574 struct wm8996_priv *wm8996 = snd_soc_
1575 int ret;
1576
1577 switch (level) {
1578 case SND_SOC_BIAS_ON:
1579 break;
1580 case SND_SOC_BIAS_PREPARE:
1581 /* Put the MICBIASes into reg
1582 snd_soc_component_update_bits
1583 WM8996_MI
1584 snd_soc_component_update_bits
1585 WM8996_MI
1586 break;
1587
1588 case SND_SOC_BIAS_STANDBY:
1589 if (snd_soc_component_get_bia
1590 ret = regulator_bulk_
1591
1592 if (ret != 0) {
1593 dev_err(compo
1594 "Fail
1595 ret);
1596 return ret;
1597 }
1598
1599 if (wm8996->ldo_ena)
1600 gpiod_set_val
1601
1602 msleep(5);
1603 }
1604
1605 regcache_cache_only(w
1606 regcache_sync(wm8996-
1607 }
1608
1609 /* Bypass the MICBIASes for l
1610 snd_soc_component_update_bits
1611 WM8996_MI
1612 snd_soc_component_update_bits
1613 WM8996_MI
1614 break;
1615
1616 case SND_SOC_BIAS_OFF:
1617 regcache_cache_only(wm8996->r
1618 if (wm8996->ldo_ena) {
1619 gpiod_set_value_cansl
1620 regcache_cache_only(w
1621 }
1622 regulator_bulk_disable(ARRAY_
1623 wm8996
1624 break;
1625 }
1626
1627 return 0;
1628 }
1629
1630 static int wm8996_set_fmt(struct snd_soc_dai
1631 {
1632 struct snd_soc_component *component =
1633 int aifctrl = 0;
1634 int bclk = 0;
1635 int lrclk_tx = 0;
1636 int lrclk_rx = 0;
1637 int aifctrl_reg, bclk_reg, lrclk_tx_r
1638
1639 switch (dai->id) {
1640 case 0:
1641 aifctrl_reg = WM8996_AIF1_CON
1642 bclk_reg = WM8996_AIF1_BCLK;
1643 lrclk_tx_reg = WM8996_AIF1_TX
1644 lrclk_rx_reg = WM8996_AIF1_RX
1645 break;
1646 case 1:
1647 aifctrl_reg = WM8996_AIF2_CON
1648 bclk_reg = WM8996_AIF2_BCLK;
1649 lrclk_tx_reg = WM8996_AIF2_TX
1650 lrclk_rx_reg = WM8996_AIF2_RX
1651 break;
1652 default:
1653 WARN(1, "Invalid dai id %d\n"
1654 return -EINVAL;
1655 }
1656
1657 switch (fmt & SND_SOC_DAIFMT_INV_MASK
1658 case SND_SOC_DAIFMT_NB_NF:
1659 break;
1660 case SND_SOC_DAIFMT_IB_NF:
1661 bclk |= WM8996_AIF1_BCLK_INV;
1662 break;
1663 case SND_SOC_DAIFMT_NB_IF:
1664 lrclk_tx |= WM8996_AIF1TX_LRC
1665 lrclk_rx |= WM8996_AIF1RX_LRC
1666 break;
1667 case SND_SOC_DAIFMT_IB_IF:
1668 bclk |= WM8996_AIF1_BCLK_INV;
1669 lrclk_tx |= WM8996_AIF1TX_LRC
1670 lrclk_rx |= WM8996_AIF1RX_LRC
1671 break;
1672 }
1673
1674 switch (fmt & SND_SOC_DAIFMT_MASTER_M
1675 case SND_SOC_DAIFMT_CBS_CFS:
1676 break;
1677 case SND_SOC_DAIFMT_CBS_CFM:
1678 lrclk_tx |= WM8996_AIF1TX_LRC
1679 lrclk_rx |= WM8996_AIF1RX_LRC
1680 break;
1681 case SND_SOC_DAIFMT_CBM_CFS:
1682 bclk |= WM8996_AIF1_BCLK_MSTR
1683 break;
1684 case SND_SOC_DAIFMT_CBM_CFM:
1685 bclk |= WM8996_AIF1_BCLK_MSTR
1686 lrclk_tx |= WM8996_AIF1TX_LRC
1687 lrclk_rx |= WM8996_AIF1RX_LRC
1688 break;
1689 default:
1690 return -EINVAL;
1691 }
1692
1693 switch (fmt & SND_SOC_DAIFMT_FORMAT_M
1694 case SND_SOC_DAIFMT_DSP_A:
1695 break;
1696 case SND_SOC_DAIFMT_DSP_B:
1697 aifctrl |= 1;
1698 break;
1699 case SND_SOC_DAIFMT_I2S:
1700 aifctrl |= 2;
1701 break;
1702 case SND_SOC_DAIFMT_LEFT_J:
1703 aifctrl |= 3;
1704 break;
1705 default:
1706 return -EINVAL;
1707 }
1708
1709 snd_soc_component_update_bits(compone
1710 snd_soc_component_update_bits(compone
1711 WM8996_AIF1_BCLK_
1712 bclk);
1713 snd_soc_component_update_bits(compone
1714 WM8996_AIF1TX_LRC
1715 WM8996_AIF1TX_LRC
1716 lrclk_tx);
1717 snd_soc_component_update_bits(compone
1718 WM8996_AIF1RX_LRC
1719 WM8996_AIF1RX_LRC
1720 lrclk_rx);
1721
1722 return 0;
1723 }
1724
1725 static const int dsp_divs[] = {
1726 48000, 32000, 16000, 8000
1727 };
1728
1729 static int wm8996_hw_params(struct snd_pcm_su
1730 struct snd_pcm_hw
1731 struct snd_soc_da
1732 {
1733 struct snd_soc_component *component =
1734 struct wm8996_priv *wm8996 = snd_soc_
1735 int bits, i, bclk_rate, best;
1736 int aifdata = 0;
1737 int lrclk = 0;
1738 int dsp = 0;
1739 int aifdata_reg, lrclk_reg, dsp_shift
1740
1741 switch (dai->id) {
1742 case 0:
1743 if (substream->stream == SNDR
1744 (snd_soc_component_read(c
1745 aifdata_reg = WM8996_
1746 lrclk_reg = WM8996_AI
1747 } else {
1748 aifdata_reg = WM8996_
1749 lrclk_reg = WM8996_AI
1750 }
1751 dsp_shift = 0;
1752 break;
1753 case 1:
1754 if (substream->stream == SNDR
1755 (snd_soc_component_read(c
1756 aifdata_reg = WM8996_
1757 lrclk_reg = WM8996_AI
1758 } else {
1759 aifdata_reg = WM8996_
1760 lrclk_reg = WM8996_AI
1761 }
1762 dsp_shift = WM8996_DSP2_DIV_S
1763 break;
1764 default:
1765 WARN(1, "Invalid dai id %d\n"
1766 return -EINVAL;
1767 }
1768
1769 bclk_rate = snd_soc_params_to_bclk(pa
1770 if (bclk_rate < 0) {
1771 dev_err(component->dev, "Unsu
1772 return bclk_rate;
1773 }
1774
1775 wm8996->bclk_rate[dai->id] = bclk_rat
1776 wm8996->rx_rate[dai->id] = params_rat
1777
1778 /* Needs looking at for TDM */
1779 bits = params_width(params);
1780 if (bits < 0)
1781 return bits;
1782 aifdata |= (bits << WM8996_AIF1TX_WL_
1783
1784 best = 0;
1785 for (i = 0; i < ARRAY_SIZE(dsp_divs);
1786 if (abs(dsp_divs[i] - params_
1787 abs(dsp_divs[best] - para
1788 best = i;
1789 }
1790 dsp |= i << dsp_shift;
1791
1792 wm8996_update_bclk(component);
1793
1794 lrclk = bclk_rate / params_rate(param
1795 dev_dbg(dai->dev, "Using LRCLK rate %
1796 lrclk, bclk_rate / lrclk);
1797
1798 snd_soc_component_update_bits(compone
1799 WM8996_AIF1TX_WL_
1800 WM8996_AIF1TX_SLO
1801 aifdata);
1802 snd_soc_component_update_bits(compone
1803 lrclk);
1804 snd_soc_component_update_bits(compone
1805 WM8996_DSP1_DIV_M
1806
1807 return 0;
1808 }
1809
1810 static int wm8996_set_sysclk(struct snd_soc_d
1811 int clk_id, unsigned int freq
1812 {
1813 struct snd_soc_component *component =
1814 struct wm8996_priv *wm8996 = snd_soc_
1815 int lfclk = 0;
1816 int ratediv = 0;
1817 int sync = WM8996_REG_SYNC;
1818 int src;
1819 int old;
1820
1821 if (freq == wm8996->sysclk && clk_id
1822 return 0;
1823
1824 /* Disable SYSCLK while we reconfigur
1825 old = snd_soc_component_read(componen
1826 snd_soc_component_update_bits(compone
1827 WM8996_SYSCLK_ENA
1828
1829 switch (clk_id) {
1830 case WM8996_SYSCLK_MCLK1:
1831 wm8996->sysclk = freq;
1832 src = 0;
1833 break;
1834 case WM8996_SYSCLK_MCLK2:
1835 wm8996->sysclk = freq;
1836 src = 1;
1837 break;
1838 case WM8996_SYSCLK_FLL:
1839 wm8996->sysclk = freq;
1840 src = 2;
1841 break;
1842 default:
1843 dev_err(component->dev, "Unsu
1844 return -EINVAL;
1845 }
1846
1847 switch (wm8996->sysclk) {
1848 case 5644800:
1849 case 6144000:
1850 snd_soc_component_update_bits
1851 WM8996_SY
1852 break;
1853 case 22579200:
1854 case 24576000:
1855 ratediv = WM8996_SYSCLK_DIV;
1856 wm8996->sysclk /= 2;
1857 fallthrough;
1858 case 11289600:
1859 case 12288000:
1860 snd_soc_component_update_bits
1861 WM8996_SY
1862 break;
1863 case 32000:
1864 case 32768:
1865 lfclk = WM8996_LFCLK_ENA;
1866 sync = 0;
1867 break;
1868 default:
1869 dev_warn(component->dev, "Uns
1870 wm8996->sysclk);
1871 return -EINVAL;
1872 }
1873
1874 wm8996_update_bclk(component);
1875
1876 snd_soc_component_update_bits(compone
1877 WM8996_SYSCLK_SRC
1878 src << WM8996_SYS
1879 snd_soc_component_update_bits(compone
1880 snd_soc_component_update_bits(compone
1881 WM8996_REG_SYNC,
1882 snd_soc_component_update_bits(compone
1883 WM8996_SYSCLK_ENA
1884
1885 wm8996->sysclk_src = clk_id;
1886
1887 return 0;
1888 }
1889
1890 struct _fll_div {
1891 u16 fll_fratio;
1892 u16 fll_outdiv;
1893 u16 fll_refclk_div;
1894 u16 fll_loop_gain;
1895 u16 fll_ref_freq;
1896 u16 n;
1897 u16 theta;
1898 u16 lambda;
1899 };
1900
1901 static struct {
1902 unsigned int min;
1903 unsigned int max;
1904 u16 fll_fratio;
1905 int ratio;
1906 } fll_fratios[] = {
1907 { 0, 64000, 4, 16 },
1908 { 64000, 128000, 3, 8 },
1909 { 128000, 256000, 2, 4 },
1910 { 256000, 1000000, 1, 2 },
1911 { 1000000, 13500000, 0, 1 },
1912 };
1913
1914 static int fll_factors(struct _fll_div *fll_d
1915 unsigned int Fout)
1916 {
1917 unsigned int target;
1918 unsigned int div;
1919 unsigned int fratio, gcd_fll;
1920 int i;
1921
1922 /* Fref must be <=13.5MHz */
1923 div = 1;
1924 fll_div->fll_refclk_div = 0;
1925 while ((Fref / div) > 13500000) {
1926 div *= 2;
1927 fll_div->fll_refclk_div++;
1928
1929 if (div > 8) {
1930 pr_err("Can't scale %
1931 Fref);
1932 return -EINVAL;
1933 }
1934 }
1935
1936 pr_debug("FLL Fref=%u Fout=%u\n", Fre
1937
1938 /* Apply the division for our remaini
1939 Fref /= div;
1940
1941 if (Fref >= 3000000)
1942 fll_div->fll_loop_gain = 5;
1943 else
1944 fll_div->fll_loop_gain = 0;
1945
1946 if (Fref >= 48000)
1947 fll_div->fll_ref_freq = 0;
1948 else
1949 fll_div->fll_ref_freq = 1;
1950
1951 /* Fvco should be 90-100MHz; don't ch
1952 div = 2;
1953 while (Fout * div < 90000000) {
1954 div++;
1955 if (div > 64) {
1956 pr_err("Unable to fin
1957 Fout);
1958 return -EINVAL;
1959 }
1960 }
1961 target = Fout * div;
1962 fll_div->fll_outdiv = div - 1;
1963
1964 pr_debug("FLL Fvco=%dHz\n", target);
1965
1966 /* Find an appropraite FLL_FRATIO and
1967 for (i = 0; i < ARRAY_SIZE(fll_fratio
1968 if (fll_fratios[i].min <= Fre
1969 fll_div->fll_fratio =
1970 fratio = fll_fratios[
1971 break;
1972 }
1973 }
1974 if (i == ARRAY_SIZE(fll_fratios)) {
1975 pr_err("Unable to find FLL_FR
1976 return -EINVAL;
1977 }
1978
1979 fll_div->n = target / (fratio * Fref)
1980
1981 if (target % Fref == 0) {
1982 fll_div->theta = 0;
1983 fll_div->lambda = 0;
1984 } else {
1985 gcd_fll = gcd(target, fratio
1986
1987 fll_div->theta = (target - (f
1988 / gcd_fll;
1989 fll_div->lambda = (fratio * F
1990 }
1991
1992 pr_debug("FLL N=%x THETA=%x LAMBDA=%x
1993 fll_div->n, fll_div->theta,
1994 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x
1995 fll_div->fll_fratio, fll_div
1996 fll_div->fll_refclk_div);
1997
1998 return 0;
1999 }
2000
2001 static int wm8996_set_fll(struct snd_soc_comp
2002 unsigned int Fref,
2003 {
2004 struct wm8996_priv *wm8996 = snd_soc_
2005 struct i2c_client *i2c = to_i2c_clien
2006 struct _fll_div fll_div;
2007 unsigned long timeout, time_left;
2008 int ret, reg, retry;
2009
2010 /* Any change? */
2011 if (source == wm8996->fll_src && Fref
2012 Fout == wm8996->fll_fout)
2013 return 0;
2014
2015 if (Fout == 0) {
2016 dev_dbg(component->dev, "FLL
2017
2018 wm8996->fll_fref = 0;
2019 wm8996->fll_fout = 0;
2020
2021 snd_soc_component_update_bits
2022 WM8996_FL
2023
2024 wm8996_bg_disable(component);
2025
2026 return 0;
2027 }
2028
2029 ret = fll_factors(&fll_div, Fref, Fou
2030 if (ret != 0)
2031 return ret;
2032
2033 switch (source) {
2034 case WM8996_FLL_MCLK1:
2035 reg = 0;
2036 break;
2037 case WM8996_FLL_MCLK2:
2038 reg = 1;
2039 break;
2040 case WM8996_FLL_DACLRCLK1:
2041 reg = 2;
2042 break;
2043 case WM8996_FLL_BCLK1:
2044 reg = 3;
2045 break;
2046 default:
2047 dev_err(component->dev, "Unkn
2048 return -EINVAL;
2049 }
2050
2051 reg |= fll_div.fll_refclk_div << WM89
2052 reg |= fll_div.fll_ref_freq << WM8996
2053
2054 snd_soc_component_update_bits(compone
2055 WM8996_FLL_REFCLK
2056 WM8996_FLL_REFCLK
2057
2058 reg = 0;
2059 if (fll_div.theta || fll_div.lambda)
2060 reg |= WM8996_FLL_EFS_ENA | (
2061 else
2062 reg |= 1 << WM8996_FLL_LFSR_S
2063 snd_soc_component_write(component, WM
2064
2065 snd_soc_component_update_bits(compone
2066 WM8996_FLL_OUTDIV
2067 WM8996_FLL_FRATIO
2068 (fll_div.fll_outd
2069 (fll_div.fll_frat
2070
2071 snd_soc_component_write(component, WM
2072
2073 snd_soc_component_update_bits(compone
2074 WM8996_FLL_N_MASK
2075 (fll_div.n << WM8
2076 fll_div.fll_loop_
2077
2078 snd_soc_component_write(component, WM
2079
2080 /* Enable the bandgap if it's not alr
2081 ret = snd_soc_component_read(componen
2082 if (!(ret & WM8996_FLL_ENA))
2083 wm8996_bg_enable(component);
2084
2085 /* Clear any pending completions (eg,
2086 try_wait_for_completion(&wm8996->fll_
2087
2088 snd_soc_component_update_bits(compone
2089 WM8996_FLL_ENA, W
2090
2091 /* The FLL supports live reconfigurat
2092 * already enabled.
2093 */
2094 snd_soc_component_write(component, WM
2095
2096 /* Wait for the FLL to lock, using th
2097 if (Fref > 1000000)
2098 timeout = usecs_to_jiffies(30
2099 else
2100 timeout = msecs_to_jiffies(2)
2101
2102 /* Allow substantially longer if we'v
2103 * at a slightly higher rate if we do
2104 */
2105 if (i2c->irq)
2106 timeout *= 10;
2107 else
2108 /* ensure timeout of atleast
2109 timeout = (timeout/2) ? : 1;
2110
2111 for (retry = 0; retry < 10; retry++)
2112 time_left = wait_for_completi
2113
2114 if (time_left != 0) {
2115 WARN_ON(!i2c->irq);
2116 ret = 1;
2117 break;
2118 }
2119
2120 ret = snd_soc_component_read(
2121 if (ret & WM8996_FLL_LOCK_STS
2122 break;
2123 }
2124 if (retry == 10) {
2125 dev_err(component->dev, "Time
2126 ret = -ETIMEDOUT;
2127 }
2128
2129 dev_dbg(component->dev, "FLL configur
2130
2131 wm8996->fll_fref = Fref;
2132 wm8996->fll_fout = Fout;
2133 wm8996->fll_src = source;
2134
2135 return ret;
2136 }
2137
2138 #ifdef CONFIG_GPIOLIB
2139 static void wm8996_gpio_set(struct gpio_chip
2140 {
2141 struct wm8996_priv *wm8996 = gpiochip
2142
2143 regmap_update_bits(wm8996->regmap, WM
2144 WM8996_GP1_LVL, !!
2145 }
2146
2147 static int wm8996_gpio_direction_out(struct g
2148 unsigned
2149 {
2150 struct wm8996_priv *wm8996 = gpiochip
2151 int val;
2152
2153 val = (1 << WM8996_GP1_FN_SHIFT) | (!
2154
2155 return regmap_update_bits(wm8996->reg
2156 WM8996_GP1_
2157 WM8996_GP1_
2158 }
2159
2160 static int wm8996_gpio_get(struct gpio_chip *
2161 {
2162 struct wm8996_priv *wm8996 = gpiochip
2163 unsigned int reg;
2164 int ret;
2165
2166 ret = regmap_read(wm8996->regmap, WM8
2167 if (ret < 0)
2168 return ret;
2169
2170 return (reg & WM8996_GP1_LVL) != 0;
2171 }
2172
2173 static int wm8996_gpio_direction_in(struct gp
2174 {
2175 struct wm8996_priv *wm8996 = gpiochip
2176
2177 return regmap_update_bits(wm8996->reg
2178 WM8996_GP1_
2179 (1 << WM899
2180 (1 << WM899
2181 }
2182
2183 static const struct gpio_chip wm8996_template
2184 .label = "wm8996",
2185 .owner = THIS_MODULE
2186 .direction_output = wm8996_gpio
2187 .set = wm8996_gpio
2188 .direction_input = wm8996_gpio
2189 .get = wm8996_gpio
2190 .can_sleep = 1,
2191 .ngpio = 5,
2192 .base = -1,
2193 };
2194
2195 static void wm8996_init_gpio(struct wm8996_pr
2196 {
2197 int ret;
2198
2199 wm8996->gpio_chip = wm8996_template_c
2200 wm8996->gpio_chip.parent = wm8996->de
2201
2202 ret = gpiochip_add_data(&wm8996->gpio
2203 if (ret != 0)
2204 dev_err(wm8996->dev, "Failed
2205 }
2206
2207 static void wm8996_free_gpio(struct wm8996_pr
2208 {
2209 gpiochip_remove(&wm8996->gpio_chip);
2210 }
2211 #else
2212 static void wm8996_init_gpio(struct wm8996_pr
2213 {
2214 }
2215
2216 static void wm8996_free_gpio(struct wm8996_pr
2217 {
2218 }
2219 #endif
2220
2221 /**
2222 * wm8996_detect - Enable default WM8996 jack
2223 * @component: ASoC component
2224 * @jack: jack pointer
2225 * @polarity_cb: polarity callback
2226 *
2227 * The WM8996 has advanced accessory detectio
2228 * This function provides a default implement
2229 * the majority of this functionality with mi
2230 *
2231 * This will detect headset, headphone and sh
2232 * will also detect inverted microphone groun
2233 * the polarity of the connections.
2234 */
2235 int wm8996_detect(struct snd_soc_component *c
2236 wm8996_polarity_fn polarity
2237 {
2238 struct wm8996_priv *wm8996 = snd_soc_
2239 struct snd_soc_dapm_context *dapm = s
2240
2241 wm8996->jack = jack;
2242 wm8996->detecting = true;
2243 wm8996->polarity_cb = polarity_cb;
2244 wm8996->jack_flips = 0;
2245
2246 if (wm8996->polarity_cb)
2247 wm8996->polarity_cb(component
2248
2249 /* Clear discarge to avoid noise duri
2250 snd_soc_component_update_bits(compone
2251 WM8996_MICB1_DISC
2252 snd_soc_component_update_bits(compone
2253 WM8996_MICB2_DISC
2254
2255 /* LDO2 powers the microphones, SYSCL
2256 snd_soc_dapm_mutex_lock(dapm);
2257
2258 snd_soc_dapm_force_enable_pin_unlocke
2259 snd_soc_dapm_force_enable_pin_unlocke
2260
2261 snd_soc_dapm_mutex_unlock(dapm);
2262
2263 /* We start off just enabling microph
2264 * plain headphone will trigger detec
2265 */
2266 snd_soc_component_update_bits(compone
2267 WM8996_MICD_ENA,
2268
2269 /* Slowest detection rate, gives debo
2270 snd_soc_component_update_bits(compone
2271 WM8996_MICD_RATE_
2272 WM8996_MICD_RATE_
2273
2274 /* Enable interrupts and we're off */
2275 snd_soc_component_update_bits(compone
2276 WM8996_IM_MICD_EI
2277
2278 return 0;
2279 }
2280 EXPORT_SYMBOL_GPL(wm8996_detect);
2281
2282 static void wm8996_hpdet_irq(struct snd_soc_c
2283 {
2284 struct snd_soc_dapm_context *dapm = s
2285 struct wm8996_priv *wm8996 = snd_soc_
2286 int val, reg, report;
2287
2288 /* Assume headphone in error conditio
2289 * something or we stall our state ma
2290 */
2291 report = SND_JACK_HEADPHONE;
2292
2293 reg = snd_soc_component_read(componen
2294 if (reg < 0) {
2295 dev_err(component->dev, "Fail
2296 goto out;
2297 }
2298
2299 if (!(reg & WM8996_HP_DONE)) {
2300 dev_err(component->dev, "Got
2301 goto out;
2302 }
2303
2304 val = reg & WM8996_HP_LVL_MASK;
2305
2306 dev_dbg(component->dev, "HPDET measur
2307
2308 /* If we've got high enough impedence
2309 * otherwise assume headphone.
2310 */
2311 if (val >= 126)
2312 report = SND_JACK_LINEOUT;
2313 else
2314 report = SND_JACK_HEADPHONE;
2315
2316 out:
2317 if (wm8996->jack_mic)
2318 report |= SND_JACK_MICROPHONE
2319
2320 snd_soc_jack_report(wm8996->jack, rep
2321 SND_JACK_LINEOUT
2322
2323 wm8996->detecting = false;
2324
2325 /* If the output isn't running re-cla
2326 if (!(snd_soc_component_read(componen
2327 (WM8996_HPOUT1L_ENA | WM8996_HP
2328 snd_soc_component_update_bits
2329 WM8996_HP
2330 WM8996_HP
2331
2332 /* Go back to looking at the micropho
2333 snd_soc_component_update_bits(compone
2334 WM8996_JD_MODE_MA
2335 snd_soc_component_update_bits(compone
2336 WM8996_MICD_ENA);
2337
2338 snd_soc_dapm_disable_pin(dapm, "Bandg
2339 snd_soc_dapm_sync(dapm);
2340 }
2341
2342 static void wm8996_hpdet_start(struct snd_soc
2343 {
2344 struct snd_soc_dapm_context *dapm = s
2345
2346 /* Unclamp the output, we can't measu
2347 snd_soc_component_update_bits(compone
2348 WM8996_HPOUT1L_RM
2349 WM8996_HPOUT1R_RM
2350 WM8996_HPOUT1L_RM
2351 WM8996_HPOUT1R_RM
2352
2353 /* We need bandgap for HPDET */
2354 snd_soc_dapm_force_enable_pin(dapm, "
2355 snd_soc_dapm_sync(dapm);
2356
2357 /* Go into headphone detect left mode
2358 snd_soc_component_update_bits(compone
2359 snd_soc_component_update_bits(compone
2360 WM8996_JD_MODE_MA
2361
2362 /* Trigger a measurement */
2363 snd_soc_component_update_bits(compone
2364 WM8996_HP_POLL, W
2365 }
2366
2367 static void wm8996_report_headphone(struct sn
2368 {
2369 dev_dbg(component->dev, "Headphone de
2370 wm8996_hpdet_start(component);
2371
2372 /* Increase the detection rate a bit
2373 snd_soc_component_update_bits(compone
2374 WM8996_MICD_RATE_
2375 WM8996_MICD_BIAS_
2376 7 << WM8996_MICD_
2377 7 << WM8996_MICD_
2378 }
2379
2380 static void wm8996_micd(struct snd_soc_compon
2381 {
2382 struct wm8996_priv *wm8996 = snd_soc_
2383 int val, reg;
2384
2385 val = snd_soc_component_read(componen
2386
2387 dev_dbg(component->dev, "Microphone e
2388
2389 if (!(val & WM8996_MICD_VALID)) {
2390 dev_warn(component->dev, "Mic
2391 return;
2392 }
2393
2394 /* No accessory, reset everything and
2395 if (!(val & WM8996_MICD_STS)) {
2396 dev_dbg(component->dev, "Jack
2397 wm8996->jack_mic = false;
2398 wm8996->detecting = true;
2399 wm8996->jack_flips = 0;
2400 snd_soc_jack_report(wm8996->j
2401 SND_JACK_
2402 SND_JACK_
2403
2404 snd_soc_component_update_bits
2405 WM8996_MI
2406 WM8996_MI
2407 WM8996_MI
2408 9 << WM89
2409 return;
2410 }
2411
2412 /* If the measurement is very high we
2413 * either we just detected one or if
2414 * we've got a button release event.
2415 */
2416 if (val & 0x400) {
2417 if (wm8996->detecting) {
2418 dev_dbg(component->de
2419 wm8996->jack_mic = tr
2420 wm8996_hpdet_start(co
2421
2422 /* Increase poll rate
2423 * for buttons */
2424 snd_soc_component_upd
2425 W
2426 W
2427 5
2428 7
2429 } else {
2430 dev_dbg(component->de
2431 snd_soc_jack_report(w
2432 }
2433
2434 return;
2435 }
2436
2437 /* If we detected a lower impedence d
2438 * then we probably have the wrong po
2439 * do this for the lowest impedences
2440 * plain headphones. If both polarit
2441 * impedence then give up and report
2442 */
2443 if (wm8996->detecting && (val & 0x3f0
2444 wm8996->jack_flips++;
2445
2446 if (wm8996->jack_flips > 1) {
2447 wm8996_report_headpho
2448 return;
2449 }
2450
2451 reg = snd_soc_component_read(
2452 reg ^= WM8996_HPOUT1FB_SRC |
2453 WM8996_MICD_BIAS_SRC;
2454 snd_soc_component_update_bits
2455 WM8996_HP
2456 WM8996_MI
2457
2458 if (wm8996->polarity_cb)
2459 wm8996->polarity_cb(c
2460 (
2461
2462 dev_dbg(component->dev, "Set
2463 (reg & WM8996_MICD_SR
2464
2465 return;
2466 }
2467
2468 /* Don't distinguish between buttons,
2469 * impedence as BTN_0.
2470 */
2471 if (val & 0x3fc) {
2472 if (wm8996->jack_mic) {
2473 dev_dbg(component->de
2474 snd_soc_jack_report(w
2475 S
2476 } else if (wm8996->detecting)
2477 wm8996_report_headpho
2478 }
2479 }
2480 }
2481
2482 static irqreturn_t wm8996_irq(int irq, void *
2483 {
2484 struct snd_soc_component *component =
2485 struct wm8996_priv *wm8996 = snd_soc_
2486 int irq_val;
2487
2488 irq_val = snd_soc_component_read(comp
2489 if (irq_val < 0) {
2490 dev_err(component->dev, "Fail
2491 irq_val);
2492 return IRQ_NONE;
2493 }
2494 irq_val &= ~snd_soc_component_read(co
2495
2496 if (!irq_val)
2497 return IRQ_NONE;
2498
2499 snd_soc_component_write(component, WM
2500
2501 if (irq_val & (WM8996_DCS_DONE_01_EIN
2502 dev_dbg(component->dev, "DC s
2503 complete(&wm8996->dcs_done);
2504 }
2505
2506 if (irq_val & WM8996_FIFOS_ERR_EINT)
2507 dev_err(component->dev, "Digi
2508
2509 if (irq_val & WM8996_FLL_LOCK_EINT) {
2510 dev_dbg(component->dev, "FLL
2511 complete(&wm8996->fll_lock);
2512 }
2513
2514 if (irq_val & WM8996_MICD_EINT)
2515 wm8996_micd(component);
2516
2517 if (irq_val & WM8996_HP_DONE_EINT)
2518 wm8996_hpdet_irq(component);
2519
2520 return IRQ_HANDLED;
2521 }
2522
2523 static irqreturn_t wm8996_edge_irq(int irq, v
2524 {
2525 irqreturn_t ret = IRQ_NONE;
2526 irqreturn_t val;
2527
2528 do {
2529 val = wm8996_irq(irq, data);
2530 if (val != IRQ_NONE)
2531 ret = val;
2532 } while (val != IRQ_NONE);
2533
2534 return ret;
2535 }
2536
2537 static void wm8996_retune_mobile_pdata(struct
2538 {
2539 struct wm8996_priv *wm8996 = snd_soc_
2540 struct wm8996_pdata *pdata = &wm8996-
2541
2542 struct snd_kcontrol_new controls[] =
2543 SOC_ENUM_EXT("DSP1 EQ Mode",
2544 wm8996->retune_m
2545 wm8996_get_retun
2546 wm8996_put_retun
2547 SOC_ENUM_EXT("DSP2 EQ Mode",
2548 wm8996->retune_m
2549 wm8996_get_retun
2550 wm8996_put_retun
2551 };
2552 int ret, i, j;
2553 const char **t;
2554
2555 /* We need an array of texts for the
2556 * of texts is likely to be less than
2557 * configurations due to the sample r
2558 * configurations. */
2559 wm8996->num_retune_mobile_texts = 0;
2560 wm8996->retune_mobile_texts = NULL;
2561 for (i = 0; i < pdata->num_retune_mob
2562 for (j = 0; j < wm8996->num_r
2563 if (strcmp(pdata->ret
2564 wm8996->re
2565 break;
2566 }
2567
2568 if (j != wm8996->num_retune_m
2569 continue;
2570
2571 /* Expand the array... */
2572 t = krealloc(wm8996->retune_m
2573 sizeof(char *) *
2574 (wm8996->num_ret
2575 GFP_KERNEL);
2576 if (t == NULL)
2577 continue;
2578
2579 /* ...store the new entry...
2580 t[wm8996->num_retune_mobile_t
2581 pdata->retune_mobile_
2582
2583 /* ...and remember the new ve
2584 wm8996->num_retune_mobile_tex
2585 wm8996->retune_mobile_texts =
2586 }
2587
2588 dev_dbg(component->dev, "Allocated %d
2589 wm8996->num_retune_mobile_tex
2590
2591 wm8996->retune_mobile_enum.items = wm
2592 wm8996->retune_mobile_enum.texts = wm
2593
2594 ret = snd_soc_add_component_controls(
2595 if (ret != 0)
2596 dev_err(component->dev,
2597 "Failed to add ReTune
2598 }
2599
2600 static const struct regmap_config wm8996_regm
2601 .reg_bits = 16,
2602 .val_bits = 16,
2603
2604 .max_register = WM8996_MAX_REGISTER,
2605 .reg_defaults = wm8996_reg,
2606 .num_reg_defaults = ARRAY_SIZE(wm8996
2607 .volatile_reg = wm8996_volatile_regis
2608 .readable_reg = wm8996_readable_regis
2609 .cache_type = REGCACHE_MAPLE,
2610 };
2611
2612 static int wm8996_probe(struct snd_soc_compon
2613 {
2614 int ret;
2615 struct wm8996_priv *wm8996 = snd_soc_
2616 struct i2c_client *i2c = to_i2c_clien
2617 int irq_flags;
2618
2619 wm8996->component = component;
2620
2621 init_completion(&wm8996->dcs_done);
2622 init_completion(&wm8996->fll_lock);
2623
2624 if (wm8996->pdata.num_retune_mobile_c
2625 wm8996_retune_mobile_pdata(co
2626 else
2627 snd_soc_add_component_control
2628 ARRAY_SI
2629
2630 if (i2c->irq) {
2631 if (wm8996->pdata.irq_flags)
2632 irq_flags = wm8996->p
2633 else
2634 irq_flags = IRQF_TRIG
2635
2636 irq_flags |= IRQF_ONESHOT;
2637
2638 if (irq_flags & (IRQF_TRIGGER
2639 ret = request_threade
2640
2641
2642 else
2643 ret = request_threade
2644
2645
2646 if (ret == 0) {
2647 /* Unmask the interru
2648 snd_soc_component_upd
2649 W
2650
2651 /* Enable error repor
2652 snd_soc_component_upd
2653 W
2654 W
2655 W
2656 W
2657 W
2658 0
2659 } else {
2660 dev_err(component->de
2661 ret);
2662 return ret;
2663 }
2664 }
2665
2666 return 0;
2667 }
2668
2669 static void wm8996_remove(struct snd_soc_comp
2670 {
2671 struct i2c_client *i2c = to_i2c_clien
2672
2673 snd_soc_component_update_bits(compone
2674 WM8996_IM_IRQ, WM
2675
2676 if (i2c->irq)
2677 free_irq(i2c->irq, component)
2678 }
2679
2680 static const struct snd_soc_component_driver
2681 .probe = wm8996_prob
2682 .remove = wm8996_remo
2683 .set_bias_level = wm8996_set_
2684 .seq_notifier = wm8996_seq_
2685 .controls = wm8996_snd_
2686 .num_controls = ARRAY_SIZE(
2687 .dapm_widgets = wm8996_dapm
2688 .num_dapm_widgets = ARRAY_SIZE(
2689 .dapm_routes = wm8996_dapm
2690 .num_dapm_routes = ARRAY_SIZE(
2691 .set_pll = wm8996_set_
2692 .use_pmdown_time = 1,
2693 .endianness = 1,
2694 };
2695
2696 #define WM8996_RATES (SNDRV_PCM_RATE_8000 | S
2697 SNDRV_PCM_RATE_32000 |
2698 SNDRV_PCM_RATE_48000)
2699 #define WM8996_FORMATS (SNDRV_PCM_FMTBIT_S8 |
2700 SNDRV_PCM_FMTBIT_S20_
2701 SNDRV_PCM_FMTBIT_S32_
2702
2703 static const struct snd_soc_dai_ops wm8996_da
2704 .set_fmt = wm8996_set_fmt,
2705 .hw_params = wm8996_hw_params,
2706 .set_sysclk = wm8996_set_sysclk,
2707 };
2708
2709 static struct snd_soc_dai_driver wm8996_dai[]
2710 {
2711 .name = "wm8996-aif1",
2712 .playback = {
2713 .stream_name = "AIF1
2714 .channels_min = 1,
2715 .channels_max = 6,
2716 .rates = WM8996_RATES
2717 .formats = WM8996_FOR
2718 .sig_bits = 24,
2719 },
2720 .capture = {
2721 .stream_name = "AIF1
2722 .channels_min = 1,
2723 .channels_max = 6,
2724 .rates = WM8996_RATE
2725 .formats = WM8996_FO
2726 .sig_bits = 24,
2727 },
2728 .ops = &wm8996_dai_ops,
2729 },
2730 {
2731 .name = "wm8996-aif2",
2732 .playback = {
2733 .stream_name = "AIF2
2734 .channels_min = 1,
2735 .channels_max = 2,
2736 .rates = WM8996_RATES
2737 .formats = WM8996_FOR
2738 .sig_bits = 24,
2739 },
2740 .capture = {
2741 .stream_name = "AIF2
2742 .channels_min = 1,
2743 .channels_max = 2,
2744 .rates = WM8996_RATE
2745 .formats = WM8996_FO
2746 .sig_bits = 24,
2747 },
2748 .ops = &wm8996_dai_ops,
2749 },
2750 };
2751
2752 static int wm8996_i2c_probe(struct i2c_client
2753 {
2754 struct wm8996_priv *wm8996;
2755 int ret, i;
2756 unsigned int reg;
2757
2758 wm8996 = devm_kzalloc(&i2c->dev, size
2759 GFP_KERNEL);
2760 if (wm8996 == NULL)
2761 return -ENOMEM;
2762
2763 i2c_set_clientdata(i2c, wm8996);
2764 wm8996->dev = &i2c->dev;
2765
2766 if (dev_get_platdata(&i2c->dev))
2767 memcpy(&wm8996->pdata, dev_ge
2768 sizeof(wm8996->pdata))
2769
2770 wm8996->ldo_ena = devm_gpiod_get_opti
2771
2772 if (IS_ERR(wm8996->ldo_ena)) {
2773 ret = PTR_ERR(wm8996->ldo_ena
2774 dev_err(&i2c->dev, "Failed to
2775 ret);
2776 goto err;
2777 }
2778 gpiod_set_consumer_name(wm8996->ldo_e
2779
2780 for (i = 0; i < ARRAY_SIZE(wm8996->su
2781 wm8996->supplies[i].supply =
2782
2783 ret = devm_regulator_bulk_get(&i2c->d
2784 wm8996-
2785 if (ret != 0) {
2786 dev_err(&i2c->dev, "Failed to
2787 goto err_gpio;
2788 }
2789
2790 wm8996->disable_nb[0].notifier_call =
2791 wm8996->disable_nb[1].notifier_call =
2792 wm8996->disable_nb[2].notifier_call =
2793
2794 /* This should really be moved into t
2795 for (i = 0; i < ARRAY_SIZE(wm8996->su
2796 ret = devm_regulator_register
2797
2798
2799 if (ret != 0) {
2800 dev_err(&i2c->dev,
2801 "Failed to re
2802 ret);
2803 }
2804 }
2805
2806 ret = regulator_bulk_enable(ARRAY_SIZ
2807 wm8996->s
2808 if (ret != 0) {
2809 dev_err(&i2c->dev, "Failed to
2810 goto err_gpio;
2811 }
2812
2813 if (wm8996->ldo_ena) {
2814 gpiod_set_value_cansleep(wm89
2815 msleep(5);
2816 }
2817
2818 wm8996->regmap = devm_regmap_init_i2c
2819 if (IS_ERR(wm8996->regmap)) {
2820 ret = PTR_ERR(wm8996->regmap)
2821 dev_err(&i2c->dev, "regmap_in
2822 goto err_enable;
2823 }
2824
2825 ret = regmap_read(wm8996->regmap, WM8
2826 if (ret < 0) {
2827 dev_err(&i2c->dev, "Failed to
2828 goto err_regmap;
2829 }
2830 if (reg != 0x8915) {
2831 dev_err(&i2c->dev, "Device is
2832 ret = -EINVAL;
2833 goto err_regmap;
2834 }
2835
2836 ret = regmap_read(wm8996->regmap, WM8
2837 if (ret < 0) {
2838 dev_err(&i2c->dev, "Failed to
2839 ret);
2840 goto err_regmap;
2841 }
2842
2843 dev_info(&i2c->dev, "revision %c\n",
2844 (reg & WM8996_CHIP_REV_MASK)
2845
2846 if (wm8996->ldo_ena) {
2847 gpiod_set_value_cansleep(wm89
2848 regcache_cache_only(wm8996->r
2849 } else {
2850 ret = regmap_write(wm8996->re
2851 0x8915);
2852 if (ret != 0) {
2853 dev_err(&i2c->dev, "F
2854 goto err_regmap;
2855 }
2856 }
2857
2858 regulator_bulk_disable(ARRAY_SIZE(wm8
2859
2860 /* Apply platform data settings */
2861 regmap_update_bits(wm8996->regmap, WM
2862 WM8996_INL_MODE_MA
2863 wm8996->pdata.inl_
2864 wm8996->pdata.inr_
2865
2866 for (i = 0; i < ARRAY_SIZE(wm8996->pd
2867 if (!wm8996->pdata.gpio_defau
2868 continue;
2869
2870 regmap_write(wm8996->regmap,
2871 wm8996->pdata.gp
2872 }
2873
2874 if (wm8996->pdata.spkmute_seq)
2875 regmap_update_bits(wm8996->re
2876 WM8996_PDM
2877 WM8996_SPK
2878 WM8996_SPK
2879 wm8996->pd
2880
2881 regmap_update_bits(wm8996->regmap, WM
2882 WM8996_MICD_BIAS_S
2883 WM8996_MICD_SRC, w
2884
2885 /* Latch volume update bits */
2886 regmap_update_bits(wm8996->regmap, WM
2887 WM8996_IN1_VU, WM8
2888 regmap_update_bits(wm8996->regmap, WM
2889 WM8996_IN1_VU, WM8
2890
2891 regmap_update_bits(wm8996->regmap, WM
2892 WM8996_DAC1_VU, WM
2893 regmap_update_bits(wm8996->regmap, WM
2894 WM8996_DAC1_VU, WM
2895 regmap_update_bits(wm8996->regmap, WM
2896 WM8996_DAC2_VU, WM
2897 regmap_update_bits(wm8996->regmap, WM
2898 WM8996_DAC2_VU, WM
2899
2900 regmap_update_bits(wm8996->regmap, WM
2901 WM8996_DAC1_VU, WM
2902 regmap_update_bits(wm8996->regmap, WM
2903 WM8996_DAC1_VU, WM
2904 regmap_update_bits(wm8996->regmap, WM
2905 WM8996_DAC2_VU, WM
2906 regmap_update_bits(wm8996->regmap, WM
2907 WM8996_DAC2_VU, WM
2908
2909 regmap_update_bits(wm8996->regmap, WM
2910 WM8996_DSP1TX_VU,
2911 regmap_update_bits(wm8996->regmap, WM
2912 WM8996_DSP1TX_VU,
2913 regmap_update_bits(wm8996->regmap, WM
2914 WM8996_DSP2TX_VU,
2915 regmap_update_bits(wm8996->regmap, WM
2916 WM8996_DSP2TX_VU,
2917
2918 regmap_update_bits(wm8996->regmap, WM
2919 WM8996_DSP1RX_VU,
2920 regmap_update_bits(wm8996->regmap, WM
2921 WM8996_DSP1RX_VU,
2922 regmap_update_bits(wm8996->regmap, WM
2923 WM8996_DSP2RX_VU,
2924 regmap_update_bits(wm8996->regmap, WM
2925 WM8996_DSP2RX_VU,
2926
2927 /* No support currently for the under
2928 * pick a default TDM layout with eac
2929 * slots 0 and 1. */
2930 regmap_update_bits(wm8996->regmap,
2931 WM8996_AIF1RX_CHAN
2932 WM8996_AIF1RX_CHAN
2933 WM8996_AIF1RX_CHAN
2934 1 << WM8996_AIF1RX
2935 regmap_update_bits(wm8996->regmap,
2936 WM8996_AIF1RX_CHAN
2937 WM8996_AIF1RX_CHAN
2938 WM8996_AIF1RX_CHAN
2939 1 << WM8996_AIF1RX
2940 regmap_update_bits(wm8996->regmap,
2941 WM8996_AIF1RX_CHAN
2942 WM8996_AIF1RX_CHAN
2943 WM8996_AIF1RX_CHAN
2944 1 << WM8996_AIF1RX
2945 regmap_update_bits(wm8996->regmap,
2946 WM8996_AIF1RX_CHAN
2947 WM8996_AIF1RX_CHAN
2948 WM8996_AIF1RX_CHAN
2949 1 << WM8996_AIF1RX
2950 regmap_update_bits(wm8996->regmap,
2951 WM8996_AIF1RX_CHAN
2952 WM8996_AIF1RX_CHAN
2953 WM8996_AIF1RX_CHAN
2954 1 << WM8996_AIF1RX
2955 regmap_update_bits(wm8996->regmap,
2956 WM8996_AIF1RX_CHAN
2957 WM8996_AIF1RX_CHAN
2958 WM8996_AIF1RX_CHAN
2959 1 << WM8996_AIF1RX
2960
2961 regmap_update_bits(wm8996->regmap,
2962 WM8996_AIF2RX_CHAN
2963 WM8996_AIF2RX_CHAN
2964 WM8996_AIF2RX_CHAN
2965 1 << WM8996_AIF2RX
2966 regmap_update_bits(wm8996->regmap,
2967 WM8996_AIF2RX_CHAN
2968 WM8996_AIF2RX_CHAN
2969 WM8996_AIF2RX_CHAN
2970 1 << WM8996_AIF2RX
2971
2972 regmap_update_bits(wm8996->regmap,
2973 WM8996_AIF1TX_CHAN
2974 WM8996_AIF1TX_CHAN
2975 WM8996_AIF1TX_CHAN
2976 1 << WM8996_AIF1TX
2977 regmap_update_bits(wm8996->regmap,
2978 WM8996_AIF1TX_CHAN
2979 WM8996_AIF1TX_CHAN
2980 WM8996_AIF1TX_CHAN
2981 1 << WM8996_AIF1TX
2982 regmap_update_bits(wm8996->regmap,
2983 WM8996_AIF1TX_CHAN
2984 WM8996_AIF1TX_CHAN
2985 WM8996_AIF1TX_CHAN
2986 1 << WM8996_AIF1TX
2987 regmap_update_bits(wm8996->regmap,
2988 WM8996_AIF1TX_CHAN
2989 WM8996_AIF1TX_CHAN
2990 WM8996_AIF1TX_CHAN
2991 1 << WM8996_AIF1TX
2992 regmap_update_bits(wm8996->regmap,
2993 WM8996_AIF1TX_CHAN
2994 WM8996_AIF1TX_CHAN
2995 WM8996_AIF1TX_CHAN
2996 1 << WM8996_AIF1TX
2997 regmap_update_bits(wm8996->regmap,
2998 WM8996_AIF1TX_CHAN
2999 WM8996_AIF1TX_CHAN
3000 WM8996_AIF1TX_CHAN
3001 1 << WM8996_AIF1TX
3002
3003 regmap_update_bits(wm8996->regmap,
3004 WM8996_AIF2TX_CHAN
3005 WM8996_AIF2TX_CHAN
3006 WM8996_AIF2TX_CHAN
3007 1 << WM8996_AIF2TX
3008 regmap_update_bits(wm8996->regmap,
3009 WM8996_AIF1TX_CHAN
3010 WM8996_AIF2TX_CHAN
3011 WM8996_AIF2TX_CHAN
3012 1 << WM8996_AIF1TX
3013
3014 /* If the TX LRCLK pins are not in LR
3015 * AIFs to source their clocks from t
3016 */
3017 ret = regmap_read(wm8996->regmap, WM8
3018 if (ret != 0) {
3019 dev_err(&i2c->dev, "Failed to
3020 goto err_regmap;
3021 }
3022
3023 if (reg & WM8996_GP1_FN_MASK)
3024 regmap_update_bits(wm8996->re
3025 WM8996_AIF
3026 WM8996_AIF
3027
3028 ret = regmap_read(wm8996->regmap, WM8
3029 if (ret != 0) {
3030 dev_err(&i2c->dev, "Failed to
3031 goto err_regmap;
3032 }
3033
3034 if (reg & WM8996_GP2_FN_MASK)
3035 regmap_update_bits(wm8996->re
3036 WM8996_AIF
3037 WM8996_AIF
3038
3039 wm8996_init_gpio(wm8996);
3040
3041 ret = devm_snd_soc_register_component
3042 &soc_com
3043 ARRAY_SI
3044 if (ret < 0)
3045 goto err_gpiolib;
3046
3047 return ret;
3048
3049 err_gpiolib:
3050 wm8996_free_gpio(wm8996);
3051 err_regmap:
3052 err_enable:
3053 if (wm8996->ldo_ena)
3054 gpiod_set_value_cansleep(wm89
3055 regulator_bulk_disable(ARRAY_SIZE(wm8
3056 err_gpio:
3057 err:
3058
3059 return ret;
3060 }
3061
3062 static void wm8996_i2c_remove(struct i2c_clie
3063 {
3064 struct wm8996_priv *wm8996 = i2c_get_
3065
3066 wm8996_free_gpio(wm8996);
3067 if (wm8996->ldo_ena)
3068 gpiod_set_value_cansleep(wm89
3069 }
3070
3071 static const struct i2c_device_id wm8996_i2c_
3072 { "wm8996" },
3073 { }
3074 };
3075 MODULE_DEVICE_TABLE(i2c, wm8996_i2c_id);
3076
3077 static struct i2c_driver wm8996_i2c_driver =
3078 .driver = {
3079 .name = "wm8996",
3080 },
3081 .probe = wm8996_i2c_probe,
3082 .remove = wm8996_i2c_remove,
3083 .id_table = wm8996_i2c_id,
3084 };
3085
3086 module_i2c_driver(wm8996_i2c_driver);
3087
3088 MODULE_DESCRIPTION("ASoC WM8996 driver");
3089 MODULE_AUTHOR("Mark Brown <broonie@opensource
3090 MODULE_LICENSE("GPL");
3091
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