1 /* SPDX-License-Identifier: GPL-2.0-only */ <<
2 #ifndef WM9081_H 1 #ifndef WM9081_H
3 #define WM9081_H 2 #define WM9081_H
4 3
5 /* 4 /*
6 * wm9081.c -- WM9081 ALSA SoC Audio driver 5 * wm9081.c -- WM9081 ALSA SoC Audio driver
7 * 6 *
8 * Author: Mark Brown 7 * Author: Mark Brown
9 * 8 *
10 * Copyright 2009 Wolfson Microelectronics plc 9 * Copyright 2009 Wolfson Microelectronics plc
>> 10 *
>> 11 * This program is free software; you can redistribute it and/or modify
>> 12 * it under the terms of the GNU General Public License version 2 as
>> 13 * published by the Free Software Foundation.
11 */ 14 */
12 15
13 #include <sound/soc.h> 16 #include <sound/soc.h>
14 17
15 /* 18 /*
16 * SYSCLK sources 19 * SYSCLK sources
17 */ 20 */
18 #define WM9081_SYSCLK_MCLK 1 /* Use MCL 21 #define WM9081_SYSCLK_MCLK 1 /* Use MCLK without FLL */
19 #define WM9081_SYSCLK_FLL_MCLK 2 /* Use MCL 22 #define WM9081_SYSCLK_FLL_MCLK 2 /* Use MCLK, enabling FLL if required */
20 23
21 /* 24 /*
22 * Register values. 25 * Register values.
23 */ 26 */
24 #define WM9081_SOFTWARE_RESET 27 #define WM9081_SOFTWARE_RESET 0x00
25 #define WM9081_ANALOGUE_LINEOUT 28 #define WM9081_ANALOGUE_LINEOUT 0x02
26 #define WM9081_ANALOGUE_SPEAKER_PGA 29 #define WM9081_ANALOGUE_SPEAKER_PGA 0x03
27 #define WM9081_VMID_CONTROL 30 #define WM9081_VMID_CONTROL 0x04
28 #define WM9081_BIAS_CONTROL_1 31 #define WM9081_BIAS_CONTROL_1 0x05
29 #define WM9081_ANALOGUE_MIXER 32 #define WM9081_ANALOGUE_MIXER 0x07
30 #define WM9081_ANTI_POP_CONTROL 33 #define WM9081_ANTI_POP_CONTROL 0x08
31 #define WM9081_ANALOGUE_SPEAKER_1 34 #define WM9081_ANALOGUE_SPEAKER_1 0x09
32 #define WM9081_ANALOGUE_SPEAKER_2 35 #define WM9081_ANALOGUE_SPEAKER_2 0x0A
33 #define WM9081_POWER_MANAGEMENT 36 #define WM9081_POWER_MANAGEMENT 0x0B
34 #define WM9081_CLOCK_CONTROL_1 37 #define WM9081_CLOCK_CONTROL_1 0x0C
35 #define WM9081_CLOCK_CONTROL_2 38 #define WM9081_CLOCK_CONTROL_2 0x0D
36 #define WM9081_CLOCK_CONTROL_3 39 #define WM9081_CLOCK_CONTROL_3 0x0E
37 #define WM9081_FLL_CONTROL_1 40 #define WM9081_FLL_CONTROL_1 0x10
38 #define WM9081_FLL_CONTROL_2 41 #define WM9081_FLL_CONTROL_2 0x11
39 #define WM9081_FLL_CONTROL_3 42 #define WM9081_FLL_CONTROL_3 0x12
40 #define WM9081_FLL_CONTROL_4 43 #define WM9081_FLL_CONTROL_4 0x13
41 #define WM9081_FLL_CONTROL_5 44 #define WM9081_FLL_CONTROL_5 0x14
42 #define WM9081_AUDIO_INTERFACE_1 45 #define WM9081_AUDIO_INTERFACE_1 0x16
43 #define WM9081_AUDIO_INTERFACE_2 46 #define WM9081_AUDIO_INTERFACE_2 0x17
44 #define WM9081_AUDIO_INTERFACE_3 47 #define WM9081_AUDIO_INTERFACE_3 0x18
45 #define WM9081_AUDIO_INTERFACE_4 48 #define WM9081_AUDIO_INTERFACE_4 0x19
46 #define WM9081_INTERRUPT_STATUS 49 #define WM9081_INTERRUPT_STATUS 0x1A
47 #define WM9081_INTERRUPT_STATUS_MASK 50 #define WM9081_INTERRUPT_STATUS_MASK 0x1B
48 #define WM9081_INTERRUPT_POLARITY 51 #define WM9081_INTERRUPT_POLARITY 0x1C
49 #define WM9081_INTERRUPT_CONTROL 52 #define WM9081_INTERRUPT_CONTROL 0x1D
50 #define WM9081_DAC_DIGITAL_1 53 #define WM9081_DAC_DIGITAL_1 0x1E
51 #define WM9081_DAC_DIGITAL_2 54 #define WM9081_DAC_DIGITAL_2 0x1F
52 #define WM9081_DRC_1 55 #define WM9081_DRC_1 0x20
53 #define WM9081_DRC_2 56 #define WM9081_DRC_2 0x21
54 #define WM9081_DRC_3 57 #define WM9081_DRC_3 0x22
55 #define WM9081_DRC_4 58 #define WM9081_DRC_4 0x23
56 #define WM9081_WRITE_SEQUENCER_1 59 #define WM9081_WRITE_SEQUENCER_1 0x26
57 #define WM9081_WRITE_SEQUENCER_2 60 #define WM9081_WRITE_SEQUENCER_2 0x27
58 #define WM9081_MW_SLAVE_1 61 #define WM9081_MW_SLAVE_1 0x28
59 #define WM9081_EQ_1 62 #define WM9081_EQ_1 0x2A
60 #define WM9081_EQ_2 63 #define WM9081_EQ_2 0x2B
61 #define WM9081_EQ_3 64 #define WM9081_EQ_3 0x2C
62 #define WM9081_EQ_4 65 #define WM9081_EQ_4 0x2D
63 #define WM9081_EQ_5 66 #define WM9081_EQ_5 0x2E
64 #define WM9081_EQ_6 67 #define WM9081_EQ_6 0x2F
65 #define WM9081_EQ_7 68 #define WM9081_EQ_7 0x30
66 #define WM9081_EQ_8 69 #define WM9081_EQ_8 0x31
67 #define WM9081_EQ_9 70 #define WM9081_EQ_9 0x32
68 #define WM9081_EQ_10 71 #define WM9081_EQ_10 0x33
69 #define WM9081_EQ_11 72 #define WM9081_EQ_11 0x34
70 #define WM9081_EQ_12 73 #define WM9081_EQ_12 0x35
71 #define WM9081_EQ_13 74 #define WM9081_EQ_13 0x36
72 #define WM9081_EQ_14 75 #define WM9081_EQ_14 0x37
73 #define WM9081_EQ_15 76 #define WM9081_EQ_15 0x38
74 #define WM9081_EQ_16 77 #define WM9081_EQ_16 0x39
75 #define WM9081_EQ_17 78 #define WM9081_EQ_17 0x3A
76 #define WM9081_EQ_18 79 #define WM9081_EQ_18 0x3B
77 #define WM9081_EQ_19 80 #define WM9081_EQ_19 0x3C
78 #define WM9081_EQ_20 81 #define WM9081_EQ_20 0x3D
79 82
80 #define WM9081_REGISTER_COUNT 83 #define WM9081_REGISTER_COUNT 55
81 #define WM9081_MAX_REGISTER 84 #define WM9081_MAX_REGISTER 0x3D
82 85
83 /* 86 /*
84 * Field Definitions. 87 * Field Definitions.
85 */ 88 */
86 89
87 /* 90 /*
88 * R0 (0x00) - Software Reset 91 * R0 (0x00) - Software Reset
89 */ 92 */
90 #define WM9081_SW_RST_DEV_ID1_MASK 93 #define WM9081_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */
91 #define WM9081_SW_RST_DEV_ID1_SHIFT 94 #define WM9081_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */
92 #define WM9081_SW_RST_DEV_ID1_WIDTH 95 #define WM9081_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */
93 96
94 /* 97 /*
95 * R2 (0x02) - Analogue Lineout 98 * R2 (0x02) - Analogue Lineout
96 */ 99 */
97 #define WM9081_LINEOUT_MUTE 100 #define WM9081_LINEOUT_MUTE 0x0080 /* LINEOUT_MUTE */
98 #define WM9081_LINEOUT_MUTE_MASK 101 #define WM9081_LINEOUT_MUTE_MASK 0x0080 /* LINEOUT_MUTE */
99 #define WM9081_LINEOUT_MUTE_SHIFT 102 #define WM9081_LINEOUT_MUTE_SHIFT 7 /* LINEOUT_MUTE */
100 #define WM9081_LINEOUT_MUTE_WIDTH 103 #define WM9081_LINEOUT_MUTE_WIDTH 1 /* LINEOUT_MUTE */
101 #define WM9081_LINEOUTZC 104 #define WM9081_LINEOUTZC 0x0040 /* LINEOUTZC */
102 #define WM9081_LINEOUTZC_MASK 105 #define WM9081_LINEOUTZC_MASK 0x0040 /* LINEOUTZC */
103 #define WM9081_LINEOUTZC_SHIFT 106 #define WM9081_LINEOUTZC_SHIFT 6 /* LINEOUTZC */
104 #define WM9081_LINEOUTZC_WIDTH 107 #define WM9081_LINEOUTZC_WIDTH 1 /* LINEOUTZC */
105 #define WM9081_LINEOUT_VOL_MASK 108 #define WM9081_LINEOUT_VOL_MASK 0x003F /* LINEOUT_VOL - [5:0] */
106 #define WM9081_LINEOUT_VOL_SHIFT 109 #define WM9081_LINEOUT_VOL_SHIFT 0 /* LINEOUT_VOL - [5:0] */
107 #define WM9081_LINEOUT_VOL_WIDTH 110 #define WM9081_LINEOUT_VOL_WIDTH 6 /* LINEOUT_VOL - [5:0] */
108 111
109 /* 112 /*
110 * R3 (0x03) - Analogue Speaker PGA 113 * R3 (0x03) - Analogue Speaker PGA
111 */ 114 */
112 #define WM9081_SPKPGA_MUTE 115 #define WM9081_SPKPGA_MUTE 0x0080 /* SPKPGA_MUTE */
113 #define WM9081_SPKPGA_MUTE_MASK 116 #define WM9081_SPKPGA_MUTE_MASK 0x0080 /* SPKPGA_MUTE */
114 #define WM9081_SPKPGA_MUTE_SHIFT 117 #define WM9081_SPKPGA_MUTE_SHIFT 7 /* SPKPGA_MUTE */
115 #define WM9081_SPKPGA_MUTE_WIDTH 118 #define WM9081_SPKPGA_MUTE_WIDTH 1 /* SPKPGA_MUTE */
116 #define WM9081_SPKPGAZC 119 #define WM9081_SPKPGAZC 0x0040 /* SPKPGAZC */
117 #define WM9081_SPKPGAZC_MASK 120 #define WM9081_SPKPGAZC_MASK 0x0040 /* SPKPGAZC */
118 #define WM9081_SPKPGAZC_SHIFT 121 #define WM9081_SPKPGAZC_SHIFT 6 /* SPKPGAZC */
119 #define WM9081_SPKPGAZC_WIDTH 122 #define WM9081_SPKPGAZC_WIDTH 1 /* SPKPGAZC */
120 #define WM9081_SPKPGA_VOL_MASK 123 #define WM9081_SPKPGA_VOL_MASK 0x003F /* SPKPGA_VOL - [5:0] */
121 #define WM9081_SPKPGA_VOL_SHIFT 124 #define WM9081_SPKPGA_VOL_SHIFT 0 /* SPKPGA_VOL - [5:0] */
122 #define WM9081_SPKPGA_VOL_WIDTH 125 #define WM9081_SPKPGA_VOL_WIDTH 6 /* SPKPGA_VOL - [5:0] */
123 126
124 /* 127 /*
125 * R4 (0x04) - VMID Control 128 * R4 (0x04) - VMID Control
126 */ 129 */
127 #define WM9081_VMID_BUF_ENA 130 #define WM9081_VMID_BUF_ENA 0x0020 /* VMID_BUF_ENA */
128 #define WM9081_VMID_BUF_ENA_MASK 131 #define WM9081_VMID_BUF_ENA_MASK 0x0020 /* VMID_BUF_ENA */
129 #define WM9081_VMID_BUF_ENA_SHIFT 132 #define WM9081_VMID_BUF_ENA_SHIFT 5 /* VMID_BUF_ENA */
130 #define WM9081_VMID_BUF_ENA_WIDTH 133 #define WM9081_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */
131 #define WM9081_VMID_RAMP 134 #define WM9081_VMID_RAMP 0x0008 /* VMID_RAMP */
132 #define WM9081_VMID_RAMP_MASK 135 #define WM9081_VMID_RAMP_MASK 0x0008 /* VMID_RAMP */
133 #define WM9081_VMID_RAMP_SHIFT 136 #define WM9081_VMID_RAMP_SHIFT 3 /* VMID_RAMP */
134 #define WM9081_VMID_RAMP_WIDTH 137 #define WM9081_VMID_RAMP_WIDTH 1 /* VMID_RAMP */
135 #define WM9081_VMID_SEL_MASK 138 #define WM9081_VMID_SEL_MASK 0x0006 /* VMID_SEL - [2:1] */
136 #define WM9081_VMID_SEL_SHIFT 139 #define WM9081_VMID_SEL_SHIFT 1 /* VMID_SEL - [2:1] */
137 #define WM9081_VMID_SEL_WIDTH 140 #define WM9081_VMID_SEL_WIDTH 2 /* VMID_SEL - [2:1] */
138 #define WM9081_VMID_FAST_ST 141 #define WM9081_VMID_FAST_ST 0x0001 /* VMID_FAST_ST */
139 #define WM9081_VMID_FAST_ST_MASK 142 #define WM9081_VMID_FAST_ST_MASK 0x0001 /* VMID_FAST_ST */
140 #define WM9081_VMID_FAST_ST_SHIFT 143 #define WM9081_VMID_FAST_ST_SHIFT 0 /* VMID_FAST_ST */
141 #define WM9081_VMID_FAST_ST_WIDTH 144 #define WM9081_VMID_FAST_ST_WIDTH 1 /* VMID_FAST_ST */
142 145
143 /* 146 /*
144 * R5 (0x05) - Bias Control 1 147 * R5 (0x05) - Bias Control 1
145 */ 148 */
146 #define WM9081_BIAS_SRC 149 #define WM9081_BIAS_SRC 0x0040 /* BIAS_SRC */
147 #define WM9081_BIAS_SRC_MASK 150 #define WM9081_BIAS_SRC_MASK 0x0040 /* BIAS_SRC */
148 #define WM9081_BIAS_SRC_SHIFT 151 #define WM9081_BIAS_SRC_SHIFT 6 /* BIAS_SRC */
149 #define WM9081_BIAS_SRC_WIDTH 152 #define WM9081_BIAS_SRC_WIDTH 1 /* BIAS_SRC */
150 #define WM9081_STBY_BIAS_LVL 153 #define WM9081_STBY_BIAS_LVL 0x0020 /* STBY_BIAS_LVL */
151 #define WM9081_STBY_BIAS_LVL_MASK 154 #define WM9081_STBY_BIAS_LVL_MASK 0x0020 /* STBY_BIAS_LVL */
152 #define WM9081_STBY_BIAS_LVL_SHIFT 155 #define WM9081_STBY_BIAS_LVL_SHIFT 5 /* STBY_BIAS_LVL */
153 #define WM9081_STBY_BIAS_LVL_WIDTH 156 #define WM9081_STBY_BIAS_LVL_WIDTH 1 /* STBY_BIAS_LVL */
154 #define WM9081_STBY_BIAS_ENA 157 #define WM9081_STBY_BIAS_ENA 0x0010 /* STBY_BIAS_ENA */
155 #define WM9081_STBY_BIAS_ENA_MASK 158 #define WM9081_STBY_BIAS_ENA_MASK 0x0010 /* STBY_BIAS_ENA */
156 #define WM9081_STBY_BIAS_ENA_SHIFT 159 #define WM9081_STBY_BIAS_ENA_SHIFT 4 /* STBY_BIAS_ENA */
157 #define WM9081_STBY_BIAS_ENA_WIDTH 160 #define WM9081_STBY_BIAS_ENA_WIDTH 1 /* STBY_BIAS_ENA */
158 #define WM9081_BIAS_LVL_MASK 161 #define WM9081_BIAS_LVL_MASK 0x000C /* BIAS_LVL - [3:2] */
159 #define WM9081_BIAS_LVL_SHIFT 162 #define WM9081_BIAS_LVL_SHIFT 2 /* BIAS_LVL - [3:2] */
160 #define WM9081_BIAS_LVL_WIDTH 163 #define WM9081_BIAS_LVL_WIDTH 2 /* BIAS_LVL - [3:2] */
161 #define WM9081_BIAS_ENA 164 #define WM9081_BIAS_ENA 0x0002 /* BIAS_ENA */
162 #define WM9081_BIAS_ENA_MASK 165 #define WM9081_BIAS_ENA_MASK 0x0002 /* BIAS_ENA */
163 #define WM9081_BIAS_ENA_SHIFT 166 #define WM9081_BIAS_ENA_SHIFT 1 /* BIAS_ENA */
164 #define WM9081_BIAS_ENA_WIDTH 167 #define WM9081_BIAS_ENA_WIDTH 1 /* BIAS_ENA */
165 #define WM9081_STARTUP_BIAS_ENA 168 #define WM9081_STARTUP_BIAS_ENA 0x0001 /* STARTUP_BIAS_ENA */
166 #define WM9081_STARTUP_BIAS_ENA_MASK 169 #define WM9081_STARTUP_BIAS_ENA_MASK 0x0001 /* STARTUP_BIAS_ENA */
167 #define WM9081_STARTUP_BIAS_ENA_SHIFT 170 #define WM9081_STARTUP_BIAS_ENA_SHIFT 0 /* STARTUP_BIAS_ENA */
168 #define WM9081_STARTUP_BIAS_ENA_WIDTH 171 #define WM9081_STARTUP_BIAS_ENA_WIDTH 1 /* STARTUP_BIAS_ENA */
169 172
170 /* 173 /*
171 * R7 (0x07) - Analogue Mixer 174 * R7 (0x07) - Analogue Mixer
172 */ 175 */
173 #define WM9081_DAC_SEL 176 #define WM9081_DAC_SEL 0x0010 /* DAC_SEL */
174 #define WM9081_DAC_SEL_MASK 177 #define WM9081_DAC_SEL_MASK 0x0010 /* DAC_SEL */
175 #define WM9081_DAC_SEL_SHIFT 178 #define WM9081_DAC_SEL_SHIFT 4 /* DAC_SEL */
176 #define WM9081_DAC_SEL_WIDTH 179 #define WM9081_DAC_SEL_WIDTH 1 /* DAC_SEL */
177 #define WM9081_IN2_VOL 180 #define WM9081_IN2_VOL 0x0008 /* IN2_VOL */
178 #define WM9081_IN2_VOL_MASK 181 #define WM9081_IN2_VOL_MASK 0x0008 /* IN2_VOL */
179 #define WM9081_IN2_VOL_SHIFT 182 #define WM9081_IN2_VOL_SHIFT 3 /* IN2_VOL */
180 #define WM9081_IN2_VOL_WIDTH 183 #define WM9081_IN2_VOL_WIDTH 1 /* IN2_VOL */
181 #define WM9081_IN2_ENA 184 #define WM9081_IN2_ENA 0x0004 /* IN2_ENA */
182 #define WM9081_IN2_ENA_MASK 185 #define WM9081_IN2_ENA_MASK 0x0004 /* IN2_ENA */
183 #define WM9081_IN2_ENA_SHIFT 186 #define WM9081_IN2_ENA_SHIFT 2 /* IN2_ENA */
184 #define WM9081_IN2_ENA_WIDTH 187 #define WM9081_IN2_ENA_WIDTH 1 /* IN2_ENA */
185 #define WM9081_IN1_VOL 188 #define WM9081_IN1_VOL 0x0002 /* IN1_VOL */
186 #define WM9081_IN1_VOL_MASK 189 #define WM9081_IN1_VOL_MASK 0x0002 /* IN1_VOL */
187 #define WM9081_IN1_VOL_SHIFT 190 #define WM9081_IN1_VOL_SHIFT 1 /* IN1_VOL */
188 #define WM9081_IN1_VOL_WIDTH 191 #define WM9081_IN1_VOL_WIDTH 1 /* IN1_VOL */
189 #define WM9081_IN1_ENA 192 #define WM9081_IN1_ENA 0x0001 /* IN1_ENA */
190 #define WM9081_IN1_ENA_MASK 193 #define WM9081_IN1_ENA_MASK 0x0001 /* IN1_ENA */
191 #define WM9081_IN1_ENA_SHIFT 194 #define WM9081_IN1_ENA_SHIFT 0 /* IN1_ENA */
192 #define WM9081_IN1_ENA_WIDTH 195 #define WM9081_IN1_ENA_WIDTH 1 /* IN1_ENA */
193 196
194 /* 197 /*
195 * R8 (0x08) - Anti Pop Control 198 * R8 (0x08) - Anti Pop Control
196 */ 199 */
197 #define WM9081_LINEOUT_DISCH 200 #define WM9081_LINEOUT_DISCH 0x0004 /* LINEOUT_DISCH */
198 #define WM9081_LINEOUT_DISCH_MASK 201 #define WM9081_LINEOUT_DISCH_MASK 0x0004 /* LINEOUT_DISCH */
199 #define WM9081_LINEOUT_DISCH_SHIFT 202 #define WM9081_LINEOUT_DISCH_SHIFT 2 /* LINEOUT_DISCH */
200 #define WM9081_LINEOUT_DISCH_WIDTH 203 #define WM9081_LINEOUT_DISCH_WIDTH 1 /* LINEOUT_DISCH */
201 #define WM9081_LINEOUT_VROI 204 #define WM9081_LINEOUT_VROI 0x0002 /* LINEOUT_VROI */
202 #define WM9081_LINEOUT_VROI_MASK 205 #define WM9081_LINEOUT_VROI_MASK 0x0002 /* LINEOUT_VROI */
203 #define WM9081_LINEOUT_VROI_SHIFT 206 #define WM9081_LINEOUT_VROI_SHIFT 1 /* LINEOUT_VROI */
204 #define WM9081_LINEOUT_VROI_WIDTH 207 #define WM9081_LINEOUT_VROI_WIDTH 1 /* LINEOUT_VROI */
205 #define WM9081_LINEOUT_CLAMP 208 #define WM9081_LINEOUT_CLAMP 0x0001 /* LINEOUT_CLAMP */
206 #define WM9081_LINEOUT_CLAMP_MASK 209 #define WM9081_LINEOUT_CLAMP_MASK 0x0001 /* LINEOUT_CLAMP */
207 #define WM9081_LINEOUT_CLAMP_SHIFT 210 #define WM9081_LINEOUT_CLAMP_SHIFT 0 /* LINEOUT_CLAMP */
208 #define WM9081_LINEOUT_CLAMP_WIDTH 211 #define WM9081_LINEOUT_CLAMP_WIDTH 1 /* LINEOUT_CLAMP */
209 212
210 /* 213 /*
211 * R9 (0x09) - Analogue Speaker 1 214 * R9 (0x09) - Analogue Speaker 1
212 */ 215 */
213 #define WM9081_SPK_DCGAIN_MASK 216 #define WM9081_SPK_DCGAIN_MASK 0x0038 /* SPK_DCGAIN - [5:3] */
214 #define WM9081_SPK_DCGAIN_SHIFT 217 #define WM9081_SPK_DCGAIN_SHIFT 3 /* SPK_DCGAIN - [5:3] */
215 #define WM9081_SPK_DCGAIN_WIDTH 218 #define WM9081_SPK_DCGAIN_WIDTH 3 /* SPK_DCGAIN - [5:3] */
216 #define WM9081_SPK_ACGAIN_MASK 219 #define WM9081_SPK_ACGAIN_MASK 0x0007 /* SPK_ACGAIN - [2:0] */
217 #define WM9081_SPK_ACGAIN_SHIFT 220 #define WM9081_SPK_ACGAIN_SHIFT 0 /* SPK_ACGAIN - [2:0] */
218 #define WM9081_SPK_ACGAIN_WIDTH 221 #define WM9081_SPK_ACGAIN_WIDTH 3 /* SPK_ACGAIN - [2:0] */
219 222
220 /* 223 /*
221 * R10 (0x0A) - Analogue Speaker 2 224 * R10 (0x0A) - Analogue Speaker 2
222 */ 225 */
223 #define WM9081_SPK_MODE 226 #define WM9081_SPK_MODE 0x0040 /* SPK_MODE */
224 #define WM9081_SPK_MODE_MASK 227 #define WM9081_SPK_MODE_MASK 0x0040 /* SPK_MODE */
225 #define WM9081_SPK_MODE_SHIFT 228 #define WM9081_SPK_MODE_SHIFT 6 /* SPK_MODE */
226 #define WM9081_SPK_MODE_WIDTH 229 #define WM9081_SPK_MODE_WIDTH 1 /* SPK_MODE */
227 #define WM9081_SPK_INV_MUTE 230 #define WM9081_SPK_INV_MUTE 0x0010 /* SPK_INV_MUTE */
228 #define WM9081_SPK_INV_MUTE_MASK 231 #define WM9081_SPK_INV_MUTE_MASK 0x0010 /* SPK_INV_MUTE */
229 #define WM9081_SPK_INV_MUTE_SHIFT 232 #define WM9081_SPK_INV_MUTE_SHIFT 4 /* SPK_INV_MUTE */
230 #define WM9081_SPK_INV_MUTE_WIDTH 233 #define WM9081_SPK_INV_MUTE_WIDTH 1 /* SPK_INV_MUTE */
231 #define WM9081_OUT_SPK_CTRL 234 #define WM9081_OUT_SPK_CTRL 0x0008 /* OUT_SPK_CTRL */
232 #define WM9081_OUT_SPK_CTRL_MASK 235 #define WM9081_OUT_SPK_CTRL_MASK 0x0008 /* OUT_SPK_CTRL */
233 #define WM9081_OUT_SPK_CTRL_SHIFT 236 #define WM9081_OUT_SPK_CTRL_SHIFT 3 /* OUT_SPK_CTRL */
234 #define WM9081_OUT_SPK_CTRL_WIDTH 237 #define WM9081_OUT_SPK_CTRL_WIDTH 1 /* OUT_SPK_CTRL */
235 238
236 /* 239 /*
237 * R11 (0x0B) - Power Management 240 * R11 (0x0B) - Power Management
238 */ 241 */
239 #define WM9081_TSHUT_ENA 242 #define WM9081_TSHUT_ENA 0x0100 /* TSHUT_ENA */
240 #define WM9081_TSHUT_ENA_MASK 243 #define WM9081_TSHUT_ENA_MASK 0x0100 /* TSHUT_ENA */
241 #define WM9081_TSHUT_ENA_SHIFT 244 #define WM9081_TSHUT_ENA_SHIFT 8 /* TSHUT_ENA */
242 #define WM9081_TSHUT_ENA_WIDTH 245 #define WM9081_TSHUT_ENA_WIDTH 1 /* TSHUT_ENA */
243 #define WM9081_TSENSE_ENA 246 #define WM9081_TSENSE_ENA 0x0080 /* TSENSE_ENA */
244 #define WM9081_TSENSE_ENA_MASK 247 #define WM9081_TSENSE_ENA_MASK 0x0080 /* TSENSE_ENA */
245 #define WM9081_TSENSE_ENA_SHIFT 248 #define WM9081_TSENSE_ENA_SHIFT 7 /* TSENSE_ENA */
246 #define WM9081_TSENSE_ENA_WIDTH 249 #define WM9081_TSENSE_ENA_WIDTH 1 /* TSENSE_ENA */
247 #define WM9081_TEMP_SHUT 250 #define WM9081_TEMP_SHUT 0x0040 /* TEMP_SHUT */
248 #define WM9081_TEMP_SHUT_MASK 251 #define WM9081_TEMP_SHUT_MASK 0x0040 /* TEMP_SHUT */
249 #define WM9081_TEMP_SHUT_SHIFT 252 #define WM9081_TEMP_SHUT_SHIFT 6 /* TEMP_SHUT */
250 #define WM9081_TEMP_SHUT_WIDTH 253 #define WM9081_TEMP_SHUT_WIDTH 1 /* TEMP_SHUT */
251 #define WM9081_LINEOUT_ENA 254 #define WM9081_LINEOUT_ENA 0x0010 /* LINEOUT_ENA */
252 #define WM9081_LINEOUT_ENA_MASK 255 #define WM9081_LINEOUT_ENA_MASK 0x0010 /* LINEOUT_ENA */
253 #define WM9081_LINEOUT_ENA_SHIFT 256 #define WM9081_LINEOUT_ENA_SHIFT 4 /* LINEOUT_ENA */
254 #define WM9081_LINEOUT_ENA_WIDTH 257 #define WM9081_LINEOUT_ENA_WIDTH 1 /* LINEOUT_ENA */
255 #define WM9081_SPKPGA_ENA 258 #define WM9081_SPKPGA_ENA 0x0004 /* SPKPGA_ENA */
256 #define WM9081_SPKPGA_ENA_MASK 259 #define WM9081_SPKPGA_ENA_MASK 0x0004 /* SPKPGA_ENA */
257 #define WM9081_SPKPGA_ENA_SHIFT 260 #define WM9081_SPKPGA_ENA_SHIFT 2 /* SPKPGA_ENA */
258 #define WM9081_SPKPGA_ENA_WIDTH 261 #define WM9081_SPKPGA_ENA_WIDTH 1 /* SPKPGA_ENA */
259 #define WM9081_SPK_ENA 262 #define WM9081_SPK_ENA 0x0002 /* SPK_ENA */
260 #define WM9081_SPK_ENA_MASK 263 #define WM9081_SPK_ENA_MASK 0x0002 /* SPK_ENA */
261 #define WM9081_SPK_ENA_SHIFT 264 #define WM9081_SPK_ENA_SHIFT 1 /* SPK_ENA */
262 #define WM9081_SPK_ENA_WIDTH 265 #define WM9081_SPK_ENA_WIDTH 1 /* SPK_ENA */
263 #define WM9081_DAC_ENA 266 #define WM9081_DAC_ENA 0x0001 /* DAC_ENA */
264 #define WM9081_DAC_ENA_MASK 267 #define WM9081_DAC_ENA_MASK 0x0001 /* DAC_ENA */
265 #define WM9081_DAC_ENA_SHIFT 268 #define WM9081_DAC_ENA_SHIFT 0 /* DAC_ENA */
266 #define WM9081_DAC_ENA_WIDTH 269 #define WM9081_DAC_ENA_WIDTH 1 /* DAC_ENA */
267 270
268 /* 271 /*
269 * R12 (0x0C) - Clock Control 1 272 * R12 (0x0C) - Clock Control 1
270 */ 273 */
271 #define WM9081_CLK_OP_DIV_MASK 274 #define WM9081_CLK_OP_DIV_MASK 0x1C00 /* CLK_OP_DIV - [12:10] */
272 #define WM9081_CLK_OP_DIV_SHIFT 275 #define WM9081_CLK_OP_DIV_SHIFT 10 /* CLK_OP_DIV - [12:10] */
273 #define WM9081_CLK_OP_DIV_WIDTH 276 #define WM9081_CLK_OP_DIV_WIDTH 3 /* CLK_OP_DIV - [12:10] */
274 #define WM9081_CLK_TO_DIV_MASK 277 #define WM9081_CLK_TO_DIV_MASK 0x0300 /* CLK_TO_DIV - [9:8] */
275 #define WM9081_CLK_TO_DIV_SHIFT 278 #define WM9081_CLK_TO_DIV_SHIFT 8 /* CLK_TO_DIV - [9:8] */
276 #define WM9081_CLK_TO_DIV_WIDTH 279 #define WM9081_CLK_TO_DIV_WIDTH 2 /* CLK_TO_DIV - [9:8] */
277 #define WM9081_MCLKDIV2 280 #define WM9081_MCLKDIV2 0x0080 /* MCLKDIV2 */
278 #define WM9081_MCLKDIV2_MASK 281 #define WM9081_MCLKDIV2_MASK 0x0080 /* MCLKDIV2 */
279 #define WM9081_MCLKDIV2_SHIFT 282 #define WM9081_MCLKDIV2_SHIFT 7 /* MCLKDIV2 */
280 #define WM9081_MCLKDIV2_WIDTH 283 #define WM9081_MCLKDIV2_WIDTH 1 /* MCLKDIV2 */
281 284
282 /* 285 /*
283 * R13 (0x0D) - Clock Control 2 286 * R13 (0x0D) - Clock Control 2
284 */ 287 */
285 #define WM9081_CLK_SYS_RATE_MASK 288 #define WM9081_CLK_SYS_RATE_MASK 0x00F0 /* CLK_SYS_RATE - [7:4] */
286 #define WM9081_CLK_SYS_RATE_SHIFT 289 #define WM9081_CLK_SYS_RATE_SHIFT 4 /* CLK_SYS_RATE - [7:4] */
287 #define WM9081_CLK_SYS_RATE_WIDTH 290 #define WM9081_CLK_SYS_RATE_WIDTH 4 /* CLK_SYS_RATE - [7:4] */
288 #define WM9081_SAMPLE_RATE_MASK 291 #define WM9081_SAMPLE_RATE_MASK 0x000F /* SAMPLE_RATE - [3:0] */
289 #define WM9081_SAMPLE_RATE_SHIFT 292 #define WM9081_SAMPLE_RATE_SHIFT 0 /* SAMPLE_RATE - [3:0] */
290 #define WM9081_SAMPLE_RATE_WIDTH 293 #define WM9081_SAMPLE_RATE_WIDTH 4 /* SAMPLE_RATE - [3:0] */
291 294
292 /* 295 /*
293 * R14 (0x0E) - Clock Control 3 296 * R14 (0x0E) - Clock Control 3
294 */ 297 */
295 #define WM9081_CLK_SRC_SEL 298 #define WM9081_CLK_SRC_SEL 0x2000 /* CLK_SRC_SEL */
296 #define WM9081_CLK_SRC_SEL_MASK 299 #define WM9081_CLK_SRC_SEL_MASK 0x2000 /* CLK_SRC_SEL */
297 #define WM9081_CLK_SRC_SEL_SHIFT 300 #define WM9081_CLK_SRC_SEL_SHIFT 13 /* CLK_SRC_SEL */
298 #define WM9081_CLK_SRC_SEL_WIDTH 301 #define WM9081_CLK_SRC_SEL_WIDTH 1 /* CLK_SRC_SEL */
299 #define WM9081_CLK_OP_ENA 302 #define WM9081_CLK_OP_ENA 0x0020 /* CLK_OP_ENA */
300 #define WM9081_CLK_OP_ENA_MASK 303 #define WM9081_CLK_OP_ENA_MASK 0x0020 /* CLK_OP_ENA */
301 #define WM9081_CLK_OP_ENA_SHIFT 304 #define WM9081_CLK_OP_ENA_SHIFT 5 /* CLK_OP_ENA */
302 #define WM9081_CLK_OP_ENA_WIDTH 305 #define WM9081_CLK_OP_ENA_WIDTH 1 /* CLK_OP_ENA */
303 #define WM9081_CLK_TO_ENA 306 #define WM9081_CLK_TO_ENA 0x0004 /* CLK_TO_ENA */
304 #define WM9081_CLK_TO_ENA_MASK 307 #define WM9081_CLK_TO_ENA_MASK 0x0004 /* CLK_TO_ENA */
305 #define WM9081_CLK_TO_ENA_SHIFT 308 #define WM9081_CLK_TO_ENA_SHIFT 2 /* CLK_TO_ENA */
306 #define WM9081_CLK_TO_ENA_WIDTH 309 #define WM9081_CLK_TO_ENA_WIDTH 1 /* CLK_TO_ENA */
307 #define WM9081_CLK_DSP_ENA 310 #define WM9081_CLK_DSP_ENA 0x0002 /* CLK_DSP_ENA */
308 #define WM9081_CLK_DSP_ENA_MASK 311 #define WM9081_CLK_DSP_ENA_MASK 0x0002 /* CLK_DSP_ENA */
309 #define WM9081_CLK_DSP_ENA_SHIFT 312 #define WM9081_CLK_DSP_ENA_SHIFT 1 /* CLK_DSP_ENA */
310 #define WM9081_CLK_DSP_ENA_WIDTH 313 #define WM9081_CLK_DSP_ENA_WIDTH 1 /* CLK_DSP_ENA */
311 #define WM9081_CLK_SYS_ENA 314 #define WM9081_CLK_SYS_ENA 0x0001 /* CLK_SYS_ENA */
312 #define WM9081_CLK_SYS_ENA_MASK 315 #define WM9081_CLK_SYS_ENA_MASK 0x0001 /* CLK_SYS_ENA */
313 #define WM9081_CLK_SYS_ENA_SHIFT 316 #define WM9081_CLK_SYS_ENA_SHIFT 0 /* CLK_SYS_ENA */
314 #define WM9081_CLK_SYS_ENA_WIDTH 317 #define WM9081_CLK_SYS_ENA_WIDTH 1 /* CLK_SYS_ENA */
315 318
316 /* 319 /*
317 * R16 (0x10) - FLL Control 1 320 * R16 (0x10) - FLL Control 1
318 */ 321 */
319 #define WM9081_FLL_HOLD 322 #define WM9081_FLL_HOLD 0x0008 /* FLL_HOLD */
320 #define WM9081_FLL_HOLD_MASK 323 #define WM9081_FLL_HOLD_MASK 0x0008 /* FLL_HOLD */
321 #define WM9081_FLL_HOLD_SHIFT 324 #define WM9081_FLL_HOLD_SHIFT 3 /* FLL_HOLD */
322 #define WM9081_FLL_HOLD_WIDTH 325 #define WM9081_FLL_HOLD_WIDTH 1 /* FLL_HOLD */
323 #define WM9081_FLL_FRAC 326 #define WM9081_FLL_FRAC 0x0004 /* FLL_FRAC */
324 #define WM9081_FLL_FRAC_MASK 327 #define WM9081_FLL_FRAC_MASK 0x0004 /* FLL_FRAC */
325 #define WM9081_FLL_FRAC_SHIFT 328 #define WM9081_FLL_FRAC_SHIFT 2 /* FLL_FRAC */
326 #define WM9081_FLL_FRAC_WIDTH 329 #define WM9081_FLL_FRAC_WIDTH 1 /* FLL_FRAC */
327 #define WM9081_FLL_ENA 330 #define WM9081_FLL_ENA 0x0001 /* FLL_ENA */
328 #define WM9081_FLL_ENA_MASK 331 #define WM9081_FLL_ENA_MASK 0x0001 /* FLL_ENA */
329 #define WM9081_FLL_ENA_SHIFT 332 #define WM9081_FLL_ENA_SHIFT 0 /* FLL_ENA */
330 #define WM9081_FLL_ENA_WIDTH 333 #define WM9081_FLL_ENA_WIDTH 1 /* FLL_ENA */
331 334
332 /* 335 /*
333 * R17 (0x11) - FLL Control 2 336 * R17 (0x11) - FLL Control 2
334 */ 337 */
335 #define WM9081_FLL_OUTDIV_MASK 338 #define WM9081_FLL_OUTDIV_MASK 0x0700 /* FLL_OUTDIV - [10:8] */
336 #define WM9081_FLL_OUTDIV_SHIFT 339 #define WM9081_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [10:8] */
337 #define WM9081_FLL_OUTDIV_WIDTH 340 #define WM9081_FLL_OUTDIV_WIDTH 3 /* FLL_OUTDIV - [10:8] */
338 #define WM9081_FLL_CTRL_RATE_MASK 341 #define WM9081_FLL_CTRL_RATE_MASK 0x0070 /* FLL_CTRL_RATE - [6:4] */
339 #define WM9081_FLL_CTRL_RATE_SHIFT 342 #define WM9081_FLL_CTRL_RATE_SHIFT 4 /* FLL_CTRL_RATE - [6:4] */
340 #define WM9081_FLL_CTRL_RATE_WIDTH 343 #define WM9081_FLL_CTRL_RATE_WIDTH 3 /* FLL_CTRL_RATE - [6:4] */
341 #define WM9081_FLL_FRATIO_MASK 344 #define WM9081_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */
342 #define WM9081_FLL_FRATIO_SHIFT 345 #define WM9081_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */
343 #define WM9081_FLL_FRATIO_WIDTH 346 #define WM9081_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */
344 347
345 /* 348 /*
346 * R18 (0x12) - FLL Control 3 349 * R18 (0x12) - FLL Control 3
347 */ 350 */
348 #define WM9081_FLL_K_MASK 351 #define WM9081_FLL_K_MASK 0xFFFF /* FLL_K - [15:0] */
349 #define WM9081_FLL_K_SHIFT 352 #define WM9081_FLL_K_SHIFT 0 /* FLL_K - [15:0] */
350 #define WM9081_FLL_K_WIDTH 353 #define WM9081_FLL_K_WIDTH 16 /* FLL_K - [15:0] */
351 354
352 /* 355 /*
353 * R19 (0x13) - FLL Control 4 356 * R19 (0x13) - FLL Control 4
354 */ 357 */
355 #define WM9081_FLL_N_MASK 358 #define WM9081_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */
356 #define WM9081_FLL_N_SHIFT 359 #define WM9081_FLL_N_SHIFT 5 /* FLL_N - [14:5] */
357 #define WM9081_FLL_N_WIDTH 360 #define WM9081_FLL_N_WIDTH 10 /* FLL_N - [14:5] */
358 #define WM9081_FLL_GAIN_MASK 361 #define WM9081_FLL_GAIN_MASK 0x000F /* FLL_GAIN - [3:0] */
359 #define WM9081_FLL_GAIN_SHIFT 362 #define WM9081_FLL_GAIN_SHIFT 0 /* FLL_GAIN - [3:0] */
360 #define WM9081_FLL_GAIN_WIDTH 363 #define WM9081_FLL_GAIN_WIDTH 4 /* FLL_GAIN - [3:0] */
361 364
362 /* 365 /*
363 * R20 (0x14) - FLL Control 5 366 * R20 (0x14) - FLL Control 5
364 */ 367 */
365 #define WM9081_FLL_CLK_REF_DIV_MASK 368 #define WM9081_FLL_CLK_REF_DIV_MASK 0x0018 /* FLL_CLK_REF_DIV - [4:3] */
366 #define WM9081_FLL_CLK_REF_DIV_SHIFT 369 #define WM9081_FLL_CLK_REF_DIV_SHIFT 3 /* FLL_CLK_REF_DIV - [4:3] */
367 #define WM9081_FLL_CLK_REF_DIV_WIDTH 370 #define WM9081_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [4:3] */
368 #define WM9081_FLL_CLK_SRC_MASK 371 #define WM9081_FLL_CLK_SRC_MASK 0x0003 /* FLL_CLK_SRC - [1:0] */
369 #define WM9081_FLL_CLK_SRC_SHIFT 372 #define WM9081_FLL_CLK_SRC_SHIFT 0 /* FLL_CLK_SRC - [1:0] */
370 #define WM9081_FLL_CLK_SRC_WIDTH 373 #define WM9081_FLL_CLK_SRC_WIDTH 2 /* FLL_CLK_SRC - [1:0] */
371 374
372 /* 375 /*
373 * R22 (0x16) - Audio Interface 1 376 * R22 (0x16) - Audio Interface 1
374 */ 377 */
375 #define WM9081_AIFDAC_CHAN 378 #define WM9081_AIFDAC_CHAN 0x0040 /* AIFDAC_CHAN */
376 #define WM9081_AIFDAC_CHAN_MASK 379 #define WM9081_AIFDAC_CHAN_MASK 0x0040 /* AIFDAC_CHAN */
377 #define WM9081_AIFDAC_CHAN_SHIFT 380 #define WM9081_AIFDAC_CHAN_SHIFT 6 /* AIFDAC_CHAN */
378 #define WM9081_AIFDAC_CHAN_WIDTH 381 #define WM9081_AIFDAC_CHAN_WIDTH 1 /* AIFDAC_CHAN */
379 #define WM9081_AIFDAC_TDM_SLOT_MASK 382 #define WM9081_AIFDAC_TDM_SLOT_MASK 0x0030 /* AIFDAC_TDM_SLOT - [5:4] */
380 #define WM9081_AIFDAC_TDM_SLOT_SHIFT 383 #define WM9081_AIFDAC_TDM_SLOT_SHIFT 4 /* AIFDAC_TDM_SLOT - [5:4] */
381 #define WM9081_AIFDAC_TDM_SLOT_WIDTH 384 #define WM9081_AIFDAC_TDM_SLOT_WIDTH 2 /* AIFDAC_TDM_SLOT - [5:4] */
382 #define WM9081_AIFDAC_TDM_MODE_MASK 385 #define WM9081_AIFDAC_TDM_MODE_MASK 0x000C /* AIFDAC_TDM_MODE - [3:2] */
383 #define WM9081_AIFDAC_TDM_MODE_SHIFT 386 #define WM9081_AIFDAC_TDM_MODE_SHIFT 2 /* AIFDAC_TDM_MODE - [3:2] */
384 #define WM9081_AIFDAC_TDM_MODE_WIDTH 387 #define WM9081_AIFDAC_TDM_MODE_WIDTH 2 /* AIFDAC_TDM_MODE - [3:2] */
385 #define WM9081_DAC_COMP 388 #define WM9081_DAC_COMP 0x0002 /* DAC_COMP */
386 #define WM9081_DAC_COMP_MASK 389 #define WM9081_DAC_COMP_MASK 0x0002 /* DAC_COMP */
387 #define WM9081_DAC_COMP_SHIFT 390 #define WM9081_DAC_COMP_SHIFT 1 /* DAC_COMP */
388 #define WM9081_DAC_COMP_WIDTH 391 #define WM9081_DAC_COMP_WIDTH 1 /* DAC_COMP */
389 #define WM9081_DAC_COMPMODE 392 #define WM9081_DAC_COMPMODE 0x0001 /* DAC_COMPMODE */
390 #define WM9081_DAC_COMPMODE_MASK 393 #define WM9081_DAC_COMPMODE_MASK 0x0001 /* DAC_COMPMODE */
391 #define WM9081_DAC_COMPMODE_SHIFT 394 #define WM9081_DAC_COMPMODE_SHIFT 0 /* DAC_COMPMODE */
392 #define WM9081_DAC_COMPMODE_WIDTH 395 #define WM9081_DAC_COMPMODE_WIDTH 1 /* DAC_COMPMODE */
393 396
394 /* 397 /*
395 * R23 (0x17) - Audio Interface 2 398 * R23 (0x17) - Audio Interface 2
396 */ 399 */
397 #define WM9081_AIF_TRIS 400 #define WM9081_AIF_TRIS 0x0200 /* AIF_TRIS */
398 #define WM9081_AIF_TRIS_MASK 401 #define WM9081_AIF_TRIS_MASK 0x0200 /* AIF_TRIS */
399 #define WM9081_AIF_TRIS_SHIFT 402 #define WM9081_AIF_TRIS_SHIFT 9 /* AIF_TRIS */
400 #define WM9081_AIF_TRIS_WIDTH 403 #define WM9081_AIF_TRIS_WIDTH 1 /* AIF_TRIS */
401 #define WM9081_DAC_DAT_INV 404 #define WM9081_DAC_DAT_INV 0x0100 /* DAC_DAT_INV */
402 #define WM9081_DAC_DAT_INV_MASK 405 #define WM9081_DAC_DAT_INV_MASK 0x0100 /* DAC_DAT_INV */
403 #define WM9081_DAC_DAT_INV_SHIFT 406 #define WM9081_DAC_DAT_INV_SHIFT 8 /* DAC_DAT_INV */
404 #define WM9081_DAC_DAT_INV_WIDTH 407 #define WM9081_DAC_DAT_INV_WIDTH 1 /* DAC_DAT_INV */
405 #define WM9081_AIF_BCLK_INV 408 #define WM9081_AIF_BCLK_INV 0x0080 /* AIF_BCLK_INV */
406 #define WM9081_AIF_BCLK_INV_MASK 409 #define WM9081_AIF_BCLK_INV_MASK 0x0080 /* AIF_BCLK_INV */
407 #define WM9081_AIF_BCLK_INV_SHIFT 410 #define WM9081_AIF_BCLK_INV_SHIFT 7 /* AIF_BCLK_INV */
408 #define WM9081_AIF_BCLK_INV_WIDTH 411 #define WM9081_AIF_BCLK_INV_WIDTH 1 /* AIF_BCLK_INV */
409 #define WM9081_BCLK_DIR 412 #define WM9081_BCLK_DIR 0x0040 /* BCLK_DIR */
410 #define WM9081_BCLK_DIR_MASK 413 #define WM9081_BCLK_DIR_MASK 0x0040 /* BCLK_DIR */
411 #define WM9081_BCLK_DIR_SHIFT 414 #define WM9081_BCLK_DIR_SHIFT 6 /* BCLK_DIR */
412 #define WM9081_BCLK_DIR_WIDTH 415 #define WM9081_BCLK_DIR_WIDTH 1 /* BCLK_DIR */
413 #define WM9081_LRCLK_DIR 416 #define WM9081_LRCLK_DIR 0x0020 /* LRCLK_DIR */
414 #define WM9081_LRCLK_DIR_MASK 417 #define WM9081_LRCLK_DIR_MASK 0x0020 /* LRCLK_DIR */
415 #define WM9081_LRCLK_DIR_SHIFT 418 #define WM9081_LRCLK_DIR_SHIFT 5 /* LRCLK_DIR */
416 #define WM9081_LRCLK_DIR_WIDTH 419 #define WM9081_LRCLK_DIR_WIDTH 1 /* LRCLK_DIR */
417 #define WM9081_AIF_LRCLK_INV 420 #define WM9081_AIF_LRCLK_INV 0x0010 /* AIF_LRCLK_INV */
418 #define WM9081_AIF_LRCLK_INV_MASK 421 #define WM9081_AIF_LRCLK_INV_MASK 0x0010 /* AIF_LRCLK_INV */
419 #define WM9081_AIF_LRCLK_INV_SHIFT 422 #define WM9081_AIF_LRCLK_INV_SHIFT 4 /* AIF_LRCLK_INV */
420 #define WM9081_AIF_LRCLK_INV_WIDTH 423 #define WM9081_AIF_LRCLK_INV_WIDTH 1 /* AIF_LRCLK_INV */
421 #define WM9081_AIF_WL_MASK 424 #define WM9081_AIF_WL_MASK 0x000C /* AIF_WL - [3:2] */
422 #define WM9081_AIF_WL_SHIFT 425 #define WM9081_AIF_WL_SHIFT 2 /* AIF_WL - [3:2] */
423 #define WM9081_AIF_WL_WIDTH 426 #define WM9081_AIF_WL_WIDTH 2 /* AIF_WL - [3:2] */
424 #define WM9081_AIF_FMT_MASK 427 #define WM9081_AIF_FMT_MASK 0x0003 /* AIF_FMT - [1:0] */
425 #define WM9081_AIF_FMT_SHIFT 428 #define WM9081_AIF_FMT_SHIFT 0 /* AIF_FMT - [1:0] */
426 #define WM9081_AIF_FMT_WIDTH 429 #define WM9081_AIF_FMT_WIDTH 2 /* AIF_FMT - [1:0] */
427 430
428 /* 431 /*
429 * R24 (0x18) - Audio Interface 3 432 * R24 (0x18) - Audio Interface 3
430 */ 433 */
431 #define WM9081_BCLK_DIV_MASK 434 #define WM9081_BCLK_DIV_MASK 0x001F /* BCLK_DIV - [4:0] */
432 #define WM9081_BCLK_DIV_SHIFT 435 #define WM9081_BCLK_DIV_SHIFT 0 /* BCLK_DIV - [4:0] */
433 #define WM9081_BCLK_DIV_WIDTH 436 #define WM9081_BCLK_DIV_WIDTH 5 /* BCLK_DIV - [4:0] */
434 437
435 /* 438 /*
436 * R25 (0x19) - Audio Interface 4 439 * R25 (0x19) - Audio Interface 4
437 */ 440 */
438 #define WM9081_LRCLK_RATE_MASK 441 #define WM9081_LRCLK_RATE_MASK 0x07FF /* LRCLK_RATE - [10:0] */
439 #define WM9081_LRCLK_RATE_SHIFT 442 #define WM9081_LRCLK_RATE_SHIFT 0 /* LRCLK_RATE - [10:0] */
440 #define WM9081_LRCLK_RATE_WIDTH 443 #define WM9081_LRCLK_RATE_WIDTH 11 /* LRCLK_RATE - [10:0] */
441 444
442 /* 445 /*
443 * R26 (0x1A) - Interrupt Status 446 * R26 (0x1A) - Interrupt Status
444 */ 447 */
445 #define WM9081_WSEQ_BUSY_EINT 448 #define WM9081_WSEQ_BUSY_EINT 0x0004 /* WSEQ_BUSY_EINT */
446 #define WM9081_WSEQ_BUSY_EINT_MASK 449 #define WM9081_WSEQ_BUSY_EINT_MASK 0x0004 /* WSEQ_BUSY_EINT */
447 #define WM9081_WSEQ_BUSY_EINT_SHIFT 450 #define WM9081_WSEQ_BUSY_EINT_SHIFT 2 /* WSEQ_BUSY_EINT */
448 #define WM9081_WSEQ_BUSY_EINT_WIDTH 451 #define WM9081_WSEQ_BUSY_EINT_WIDTH 1 /* WSEQ_BUSY_EINT */
449 #define WM9081_TSHUT_EINT 452 #define WM9081_TSHUT_EINT 0x0001 /* TSHUT_EINT */
450 #define WM9081_TSHUT_EINT_MASK 453 #define WM9081_TSHUT_EINT_MASK 0x0001 /* TSHUT_EINT */
451 #define WM9081_TSHUT_EINT_SHIFT 454 #define WM9081_TSHUT_EINT_SHIFT 0 /* TSHUT_EINT */
452 #define WM9081_TSHUT_EINT_WIDTH 455 #define WM9081_TSHUT_EINT_WIDTH 1 /* TSHUT_EINT */
453 456
454 /* 457 /*
455 * R27 (0x1B) - Interrupt Status Mask 458 * R27 (0x1B) - Interrupt Status Mask
456 */ 459 */
457 #define WM9081_IM_WSEQ_BUSY_EINT 460 #define WM9081_IM_WSEQ_BUSY_EINT 0x0004 /* IM_WSEQ_BUSY_EINT */
458 #define WM9081_IM_WSEQ_BUSY_EINT_MASK 461 #define WM9081_IM_WSEQ_BUSY_EINT_MASK 0x0004 /* IM_WSEQ_BUSY_EINT */
459 #define WM9081_IM_WSEQ_BUSY_EINT_SHIFT 462 #define WM9081_IM_WSEQ_BUSY_EINT_SHIFT 2 /* IM_WSEQ_BUSY_EINT */
460 #define WM9081_IM_WSEQ_BUSY_EINT_WIDTH 463 #define WM9081_IM_WSEQ_BUSY_EINT_WIDTH 1 /* IM_WSEQ_BUSY_EINT */
461 #define WM9081_IM_TSHUT_EINT 464 #define WM9081_IM_TSHUT_EINT 0x0001 /* IM_TSHUT_EINT */
462 #define WM9081_IM_TSHUT_EINT_MASK 465 #define WM9081_IM_TSHUT_EINT_MASK 0x0001 /* IM_TSHUT_EINT */
463 #define WM9081_IM_TSHUT_EINT_SHIFT 466 #define WM9081_IM_TSHUT_EINT_SHIFT 0 /* IM_TSHUT_EINT */
464 #define WM9081_IM_TSHUT_EINT_WIDTH 467 #define WM9081_IM_TSHUT_EINT_WIDTH 1 /* IM_TSHUT_EINT */
465 468
466 /* 469 /*
467 * R28 (0x1C) - Interrupt Polarity 470 * R28 (0x1C) - Interrupt Polarity
468 */ 471 */
469 #define WM9081_TSHUT_INV 472 #define WM9081_TSHUT_INV 0x0001 /* TSHUT_INV */
470 #define WM9081_TSHUT_INV_MASK 473 #define WM9081_TSHUT_INV_MASK 0x0001 /* TSHUT_INV */
471 #define WM9081_TSHUT_INV_SHIFT 474 #define WM9081_TSHUT_INV_SHIFT 0 /* TSHUT_INV */
472 #define WM9081_TSHUT_INV_WIDTH 475 #define WM9081_TSHUT_INV_WIDTH 1 /* TSHUT_INV */
473 476
474 /* 477 /*
475 * R29 (0x1D) - Interrupt Control 478 * R29 (0x1D) - Interrupt Control
476 */ 479 */
477 #define WM9081_IRQ_POL 480 #define WM9081_IRQ_POL 0x8000 /* IRQ_POL */
478 #define WM9081_IRQ_POL_MASK 481 #define WM9081_IRQ_POL_MASK 0x8000 /* IRQ_POL */
479 #define WM9081_IRQ_POL_SHIFT 482 #define WM9081_IRQ_POL_SHIFT 15 /* IRQ_POL */
480 #define WM9081_IRQ_POL_WIDTH 483 #define WM9081_IRQ_POL_WIDTH 1 /* IRQ_POL */
481 #define WM9081_IRQ_OP_CTRL 484 #define WM9081_IRQ_OP_CTRL 0x0001 /* IRQ_OP_CTRL */
482 #define WM9081_IRQ_OP_CTRL_MASK 485 #define WM9081_IRQ_OP_CTRL_MASK 0x0001 /* IRQ_OP_CTRL */
483 #define WM9081_IRQ_OP_CTRL_SHIFT 486 #define WM9081_IRQ_OP_CTRL_SHIFT 0 /* IRQ_OP_CTRL */
484 #define WM9081_IRQ_OP_CTRL_WIDTH 487 #define WM9081_IRQ_OP_CTRL_WIDTH 1 /* IRQ_OP_CTRL */
485 488
486 /* 489 /*
487 * R30 (0x1E) - DAC Digital 1 490 * R30 (0x1E) - DAC Digital 1
488 */ 491 */
489 #define WM9081_DAC_VOL_MASK 492 #define WM9081_DAC_VOL_MASK 0x00FF /* DAC_VOL - [7:0] */
490 #define WM9081_DAC_VOL_SHIFT 493 #define WM9081_DAC_VOL_SHIFT 0 /* DAC_VOL - [7:0] */
491 #define WM9081_DAC_VOL_WIDTH 494 #define WM9081_DAC_VOL_WIDTH 8 /* DAC_VOL - [7:0] */
492 495
493 /* 496 /*
494 * R31 (0x1F) - DAC Digital 2 497 * R31 (0x1F) - DAC Digital 2
495 */ 498 */
496 #define WM9081_DAC_MUTERATE 499 #define WM9081_DAC_MUTERATE 0x0400 /* DAC_MUTERATE */
497 #define WM9081_DAC_MUTERATE_MASK 500 #define WM9081_DAC_MUTERATE_MASK 0x0400 /* DAC_MUTERATE */
498 #define WM9081_DAC_MUTERATE_SHIFT 501 #define WM9081_DAC_MUTERATE_SHIFT 10 /* DAC_MUTERATE */
499 #define WM9081_DAC_MUTERATE_WIDTH 502 #define WM9081_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */
500 #define WM9081_DAC_MUTEMODE 503 #define WM9081_DAC_MUTEMODE 0x0200 /* DAC_MUTEMODE */
501 #define WM9081_DAC_MUTEMODE_MASK 504 #define WM9081_DAC_MUTEMODE_MASK 0x0200 /* DAC_MUTEMODE */
502 #define WM9081_DAC_MUTEMODE_SHIFT 505 #define WM9081_DAC_MUTEMODE_SHIFT 9 /* DAC_MUTEMODE */
503 #define WM9081_DAC_MUTEMODE_WIDTH 506 #define WM9081_DAC_MUTEMODE_WIDTH 1 /* DAC_MUTEMODE */
504 #define WM9081_DAC_MUTE 507 #define WM9081_DAC_MUTE 0x0008 /* DAC_MUTE */
505 #define WM9081_DAC_MUTE_MASK 508 #define WM9081_DAC_MUTE_MASK 0x0008 /* DAC_MUTE */
506 #define WM9081_DAC_MUTE_SHIFT 509 #define WM9081_DAC_MUTE_SHIFT 3 /* DAC_MUTE */
507 #define WM9081_DAC_MUTE_WIDTH 510 #define WM9081_DAC_MUTE_WIDTH 1 /* DAC_MUTE */
508 #define WM9081_DEEMPH_MASK 511 #define WM9081_DEEMPH_MASK 0x0006 /* DEEMPH - [2:1] */
509 #define WM9081_DEEMPH_SHIFT 512 #define WM9081_DEEMPH_SHIFT 1 /* DEEMPH - [2:1] */
510 #define WM9081_DEEMPH_WIDTH 513 #define WM9081_DEEMPH_WIDTH 2 /* DEEMPH - [2:1] */
511 514
512 /* 515 /*
513 * R32 (0x20) - DRC 1 516 * R32 (0x20) - DRC 1
514 */ 517 */
515 #define WM9081_DRC_ENA 518 #define WM9081_DRC_ENA 0x8000 /* DRC_ENA */
516 #define WM9081_DRC_ENA_MASK 519 #define WM9081_DRC_ENA_MASK 0x8000 /* DRC_ENA */
517 #define WM9081_DRC_ENA_SHIFT 520 #define WM9081_DRC_ENA_SHIFT 15 /* DRC_ENA */
518 #define WM9081_DRC_ENA_WIDTH 521 #define WM9081_DRC_ENA_WIDTH 1 /* DRC_ENA */
519 #define WM9081_DRC_STARTUP_GAIN_MASK 522 #define WM9081_DRC_STARTUP_GAIN_MASK 0x07C0 /* DRC_STARTUP_GAIN - [10:6] */
520 #define WM9081_DRC_STARTUP_GAIN_SHIFT 523 #define WM9081_DRC_STARTUP_GAIN_SHIFT 6 /* DRC_STARTUP_GAIN - [10:6] */
521 #define WM9081_DRC_STARTUP_GAIN_WIDTH 524 #define WM9081_DRC_STARTUP_GAIN_WIDTH 5 /* DRC_STARTUP_GAIN - [10:6] */
522 #define WM9081_DRC_FF_DLY 525 #define WM9081_DRC_FF_DLY 0x0020 /* DRC_FF_DLY */
523 #define WM9081_DRC_FF_DLY_MASK 526 #define WM9081_DRC_FF_DLY_MASK 0x0020 /* DRC_FF_DLY */
524 #define WM9081_DRC_FF_DLY_SHIFT 527 #define WM9081_DRC_FF_DLY_SHIFT 5 /* DRC_FF_DLY */
525 #define WM9081_DRC_FF_DLY_WIDTH 528 #define WM9081_DRC_FF_DLY_WIDTH 1 /* DRC_FF_DLY */
526 #define WM9081_DRC_QR 529 #define WM9081_DRC_QR 0x0004 /* DRC_QR */
527 #define WM9081_DRC_QR_MASK 530 #define WM9081_DRC_QR_MASK 0x0004 /* DRC_QR */
528 #define WM9081_DRC_QR_SHIFT 531 #define WM9081_DRC_QR_SHIFT 2 /* DRC_QR */
529 #define WM9081_DRC_QR_WIDTH 532 #define WM9081_DRC_QR_WIDTH 1 /* DRC_QR */
530 #define WM9081_DRC_ANTICLIP 533 #define WM9081_DRC_ANTICLIP 0x0002 /* DRC_ANTICLIP */
531 #define WM9081_DRC_ANTICLIP_MASK 534 #define WM9081_DRC_ANTICLIP_MASK 0x0002 /* DRC_ANTICLIP */
532 #define WM9081_DRC_ANTICLIP_SHIFT 535 #define WM9081_DRC_ANTICLIP_SHIFT 1 /* DRC_ANTICLIP */
533 #define WM9081_DRC_ANTICLIP_WIDTH 536 #define WM9081_DRC_ANTICLIP_WIDTH 1 /* DRC_ANTICLIP */
534 537
535 /* 538 /*
536 * R33 (0x21) - DRC 2 539 * R33 (0x21) - DRC 2
537 */ 540 */
538 #define WM9081_DRC_ATK_MASK 541 #define WM9081_DRC_ATK_MASK 0xF000 /* DRC_ATK - [15:12] */
539 #define WM9081_DRC_ATK_SHIFT 542 #define WM9081_DRC_ATK_SHIFT 12 /* DRC_ATK - [15:12] */
540 #define WM9081_DRC_ATK_WIDTH 543 #define WM9081_DRC_ATK_WIDTH 4 /* DRC_ATK - [15:12] */
541 #define WM9081_DRC_DCY_MASK 544 #define WM9081_DRC_DCY_MASK 0x0F00 /* DRC_DCY - [11:8] */
542 #define WM9081_DRC_DCY_SHIFT 545 #define WM9081_DRC_DCY_SHIFT 8 /* DRC_DCY - [11:8] */
543 #define WM9081_DRC_DCY_WIDTH 546 #define WM9081_DRC_DCY_WIDTH 4 /* DRC_DCY - [11:8] */
544 #define WM9081_DRC_QR_THR_MASK 547 #define WM9081_DRC_QR_THR_MASK 0x00C0 /* DRC_QR_THR - [7:6] */
545 #define WM9081_DRC_QR_THR_SHIFT 548 #define WM9081_DRC_QR_THR_SHIFT 6 /* DRC_QR_THR - [7:6] */
546 #define WM9081_DRC_QR_THR_WIDTH 549 #define WM9081_DRC_QR_THR_WIDTH 2 /* DRC_QR_THR - [7:6] */
547 #define WM9081_DRC_QR_DCY_MASK 550 #define WM9081_DRC_QR_DCY_MASK 0x0030 /* DRC_QR_DCY - [5:4] */
548 #define WM9081_DRC_QR_DCY_SHIFT 551 #define WM9081_DRC_QR_DCY_SHIFT 4 /* DRC_QR_DCY - [5:4] */
549 #define WM9081_DRC_QR_DCY_WIDTH 552 #define WM9081_DRC_QR_DCY_WIDTH 2 /* DRC_QR_DCY - [5:4] */
550 #define WM9081_DRC_MINGAIN_MASK 553 #define WM9081_DRC_MINGAIN_MASK 0x000C /* DRC_MINGAIN - [3:2] */
551 #define WM9081_DRC_MINGAIN_SHIFT 554 #define WM9081_DRC_MINGAIN_SHIFT 2 /* DRC_MINGAIN - [3:2] */
552 #define WM9081_DRC_MINGAIN_WIDTH 555 #define WM9081_DRC_MINGAIN_WIDTH 2 /* DRC_MINGAIN - [3:2] */
553 #define WM9081_DRC_MAXGAIN_MASK 556 #define WM9081_DRC_MAXGAIN_MASK 0x0003 /* DRC_MAXGAIN - [1:0] */
554 #define WM9081_DRC_MAXGAIN_SHIFT 557 #define WM9081_DRC_MAXGAIN_SHIFT 0 /* DRC_MAXGAIN - [1:0] */
555 #define WM9081_DRC_MAXGAIN_WIDTH 558 #define WM9081_DRC_MAXGAIN_WIDTH 2 /* DRC_MAXGAIN - [1:0] */
556 559
557 /* 560 /*
558 * R34 (0x22) - DRC 3 561 * R34 (0x22) - DRC 3
559 */ 562 */
560 #define WM9081_DRC_HI_COMP_MASK 563 #define WM9081_DRC_HI_COMP_MASK 0x0038 /* DRC_HI_COMP - [5:3] */
561 #define WM9081_DRC_HI_COMP_SHIFT 564 #define WM9081_DRC_HI_COMP_SHIFT 3 /* DRC_HI_COMP - [5:3] */
562 #define WM9081_DRC_HI_COMP_WIDTH 565 #define WM9081_DRC_HI_COMP_WIDTH 3 /* DRC_HI_COMP - [5:3] */
563 #define WM9081_DRC_LO_COMP_MASK 566 #define WM9081_DRC_LO_COMP_MASK 0x0007 /* DRC_LO_COMP - [2:0] */
564 #define WM9081_DRC_LO_COMP_SHIFT 567 #define WM9081_DRC_LO_COMP_SHIFT 0 /* DRC_LO_COMP - [2:0] */
565 #define WM9081_DRC_LO_COMP_WIDTH 568 #define WM9081_DRC_LO_COMP_WIDTH 3 /* DRC_LO_COMP - [2:0] */
566 569
567 /* 570 /*
568 * R35 (0x23) - DRC 4 571 * R35 (0x23) - DRC 4
569 */ 572 */
570 #define WM9081_DRC_KNEE_IP_MASK 573 #define WM9081_DRC_KNEE_IP_MASK 0x07E0 /* DRC_KNEE_IP - [10:5] */
571 #define WM9081_DRC_KNEE_IP_SHIFT 574 #define WM9081_DRC_KNEE_IP_SHIFT 5 /* DRC_KNEE_IP - [10:5] */
572 #define WM9081_DRC_KNEE_IP_WIDTH 575 #define WM9081_DRC_KNEE_IP_WIDTH 6 /* DRC_KNEE_IP - [10:5] */
573 #define WM9081_DRC_KNEE_OP_MASK 576 #define WM9081_DRC_KNEE_OP_MASK 0x001F /* DRC_KNEE_OP - [4:0] */
574 #define WM9081_DRC_KNEE_OP_SHIFT 577 #define WM9081_DRC_KNEE_OP_SHIFT 0 /* DRC_KNEE_OP - [4:0] */
575 #define WM9081_DRC_KNEE_OP_WIDTH 578 #define WM9081_DRC_KNEE_OP_WIDTH 5 /* DRC_KNEE_OP - [4:0] */
576 579
577 /* 580 /*
578 * R38 (0x26) - Write Sequencer 1 581 * R38 (0x26) - Write Sequencer 1
579 */ 582 */
580 #define WM9081_WSEQ_ENA 583 #define WM9081_WSEQ_ENA 0x8000 /* WSEQ_ENA */
581 #define WM9081_WSEQ_ENA_MASK 584 #define WM9081_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */
582 #define WM9081_WSEQ_ENA_SHIFT 585 #define WM9081_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */
583 #define WM9081_WSEQ_ENA_WIDTH 586 #define WM9081_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */
584 #define WM9081_WSEQ_ABORT 587 #define WM9081_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */
585 #define WM9081_WSEQ_ABORT_MASK 588 #define WM9081_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */
586 #define WM9081_WSEQ_ABORT_SHIFT 589 #define WM9081_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */
587 #define WM9081_WSEQ_ABORT_WIDTH 590 #define WM9081_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */
588 #define WM9081_WSEQ_START 591 #define WM9081_WSEQ_START 0x0100 /* WSEQ_START */
589 #define WM9081_WSEQ_START_MASK 592 #define WM9081_WSEQ_START_MASK 0x0100 /* WSEQ_START */
590 #define WM9081_WSEQ_START_SHIFT 593 #define WM9081_WSEQ_START_SHIFT 8 /* WSEQ_START */
591 #define WM9081_WSEQ_START_WIDTH 594 #define WM9081_WSEQ_START_WIDTH 1 /* WSEQ_START */
592 #define WM9081_WSEQ_START_INDEX_MASK 595 #define WM9081_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */
593 #define WM9081_WSEQ_START_INDEX_SHIFT 596 #define WM9081_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */
594 #define WM9081_WSEQ_START_INDEX_WIDTH 597 #define WM9081_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */
595 598
596 /* 599 /*
597 * R39 (0x27) - Write Sequencer 2 600 * R39 (0x27) - Write Sequencer 2
598 */ 601 */
599 #define WM9081_WSEQ_CURRENT_INDEX_MASK 602 #define WM9081_WSEQ_CURRENT_INDEX_MASK 0x07F0 /* WSEQ_CURRENT_INDEX - [10:4] */
600 #define WM9081_WSEQ_CURRENT_INDEX_SHIFT 603 #define WM9081_WSEQ_CURRENT_INDEX_SHIFT 4 /* WSEQ_CURRENT_INDEX - [10:4] */
601 #define WM9081_WSEQ_CURRENT_INDEX_WIDTH 604 #define WM9081_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [10:4] */
602 #define WM9081_WSEQ_BUSY 605 #define WM9081_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */
603 #define WM9081_WSEQ_BUSY_MASK 606 #define WM9081_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */
604 #define WM9081_WSEQ_BUSY_SHIFT 607 #define WM9081_WSEQ_BUSY_SHIFT 0 /* WSEQ_BUSY */
605 #define WM9081_WSEQ_BUSY_WIDTH 608 #define WM9081_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */
606 609
607 /* 610 /*
608 * R40 (0x28) - MW Slave 1 611 * R40 (0x28) - MW Slave 1
609 */ 612 */
610 #define WM9081_SPI_CFG 613 #define WM9081_SPI_CFG 0x0020 /* SPI_CFG */
611 #define WM9081_SPI_CFG_MASK 614 #define WM9081_SPI_CFG_MASK 0x0020 /* SPI_CFG */
612 #define WM9081_SPI_CFG_SHIFT 615 #define WM9081_SPI_CFG_SHIFT 5 /* SPI_CFG */
613 #define WM9081_SPI_CFG_WIDTH 616 #define WM9081_SPI_CFG_WIDTH 1 /* SPI_CFG */
614 #define WM9081_SPI_4WIRE 617 #define WM9081_SPI_4WIRE 0x0010 /* SPI_4WIRE */
615 #define WM9081_SPI_4WIRE_MASK 618 #define WM9081_SPI_4WIRE_MASK 0x0010 /* SPI_4WIRE */
616 #define WM9081_SPI_4WIRE_SHIFT 619 #define WM9081_SPI_4WIRE_SHIFT 4 /* SPI_4WIRE */
617 #define WM9081_SPI_4WIRE_WIDTH 620 #define WM9081_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */
618 #define WM9081_ARA_ENA 621 #define WM9081_ARA_ENA 0x0008 /* ARA_ENA */
619 #define WM9081_ARA_ENA_MASK 622 #define WM9081_ARA_ENA_MASK 0x0008 /* ARA_ENA */
620 #define WM9081_ARA_ENA_SHIFT 623 #define WM9081_ARA_ENA_SHIFT 3 /* ARA_ENA */
621 #define WM9081_ARA_ENA_WIDTH 624 #define WM9081_ARA_ENA_WIDTH 1 /* ARA_ENA */
622 #define WM9081_AUTO_INC 625 #define WM9081_AUTO_INC 0x0002 /* AUTO_INC */
623 #define WM9081_AUTO_INC_MASK 626 #define WM9081_AUTO_INC_MASK 0x0002 /* AUTO_INC */
624 #define WM9081_AUTO_INC_SHIFT 627 #define WM9081_AUTO_INC_SHIFT 1 /* AUTO_INC */
625 #define WM9081_AUTO_INC_WIDTH 628 #define WM9081_AUTO_INC_WIDTH 1 /* AUTO_INC */
626 629
627 /* 630 /*
628 * R42 (0x2A) - EQ 1 631 * R42 (0x2A) - EQ 1
629 */ 632 */
630 #define WM9081_EQ_B1_GAIN_MASK 633 #define WM9081_EQ_B1_GAIN_MASK 0xF800 /* EQ_B1_GAIN - [15:11] */
631 #define WM9081_EQ_B1_GAIN_SHIFT 634 #define WM9081_EQ_B1_GAIN_SHIFT 11 /* EQ_B1_GAIN - [15:11] */
632 #define WM9081_EQ_B1_GAIN_WIDTH 635 #define WM9081_EQ_B1_GAIN_WIDTH 5 /* EQ_B1_GAIN - [15:11] */
633 #define WM9081_EQ_B2_GAIN_MASK 636 #define WM9081_EQ_B2_GAIN_MASK 0x07C0 /* EQ_B2_GAIN - [10:6] */
634 #define WM9081_EQ_B2_GAIN_SHIFT 637 #define WM9081_EQ_B2_GAIN_SHIFT 6 /* EQ_B2_GAIN - [10:6] */
635 #define WM9081_EQ_B2_GAIN_WIDTH 638 #define WM9081_EQ_B2_GAIN_WIDTH 5 /* EQ_B2_GAIN - [10:6] */
636 #define WM9081_EQ_B4_GAIN_MASK 639 #define WM9081_EQ_B4_GAIN_MASK 0x003E /* EQ_B4_GAIN - [5:1] */
637 #define WM9081_EQ_B4_GAIN_SHIFT 640 #define WM9081_EQ_B4_GAIN_SHIFT 1 /* EQ_B4_GAIN - [5:1] */
638 #define WM9081_EQ_B4_GAIN_WIDTH 641 #define WM9081_EQ_B4_GAIN_WIDTH 5 /* EQ_B4_GAIN - [5:1] */
639 #define WM9081_EQ_ENA 642 #define WM9081_EQ_ENA 0x0001 /* EQ_ENA */
640 #define WM9081_EQ_ENA_MASK 643 #define WM9081_EQ_ENA_MASK 0x0001 /* EQ_ENA */
641 #define WM9081_EQ_ENA_SHIFT 644 #define WM9081_EQ_ENA_SHIFT 0 /* EQ_ENA */
642 #define WM9081_EQ_ENA_WIDTH 645 #define WM9081_EQ_ENA_WIDTH 1 /* EQ_ENA */
643 646
644 /* 647 /*
645 * R43 (0x2B) - EQ 2 648 * R43 (0x2B) - EQ 2
646 */ 649 */
647 #define WM9081_EQ_B3_GAIN_MASK 650 #define WM9081_EQ_B3_GAIN_MASK 0xF800 /* EQ_B3_GAIN - [15:11] */
648 #define WM9081_EQ_B3_GAIN_SHIFT 651 #define WM9081_EQ_B3_GAIN_SHIFT 11 /* EQ_B3_GAIN - [15:11] */
649 #define WM9081_EQ_B3_GAIN_WIDTH 652 #define WM9081_EQ_B3_GAIN_WIDTH 5 /* EQ_B3_GAIN - [15:11] */
650 #define WM9081_EQ_B5_GAIN_MASK 653 #define WM9081_EQ_B5_GAIN_MASK 0x07C0 /* EQ_B5_GAIN - [10:6] */
651 #define WM9081_EQ_B5_GAIN_SHIFT 654 #define WM9081_EQ_B5_GAIN_SHIFT 6 /* EQ_B5_GAIN - [10:6] */
652 #define WM9081_EQ_B5_GAIN_WIDTH 655 #define WM9081_EQ_B5_GAIN_WIDTH 5 /* EQ_B5_GAIN - [10:6] */
653 656
654 /* 657 /*
655 * R44 (0x2C) - EQ 3 658 * R44 (0x2C) - EQ 3
656 */ 659 */
657 #define WM9081_EQ_B1_A_MASK 660 #define WM9081_EQ_B1_A_MASK 0xFFFF /* EQ_B1_A - [15:0] */
658 #define WM9081_EQ_B1_A_SHIFT 661 #define WM9081_EQ_B1_A_SHIFT 0 /* EQ_B1_A - [15:0] */
659 #define WM9081_EQ_B1_A_WIDTH 662 #define WM9081_EQ_B1_A_WIDTH 16 /* EQ_B1_A - [15:0] */
660 663
661 /* 664 /*
662 * R45 (0x2D) - EQ 4 665 * R45 (0x2D) - EQ 4
663 */ 666 */
664 #define WM9081_EQ_B1_B_MASK 667 #define WM9081_EQ_B1_B_MASK 0xFFFF /* EQ_B1_B - [15:0] */
665 #define WM9081_EQ_B1_B_SHIFT 668 #define WM9081_EQ_B1_B_SHIFT 0 /* EQ_B1_B - [15:0] */
666 #define WM9081_EQ_B1_B_WIDTH 669 #define WM9081_EQ_B1_B_WIDTH 16 /* EQ_B1_B - [15:0] */
667 670
668 /* 671 /*
669 * R46 (0x2E) - EQ 5 672 * R46 (0x2E) - EQ 5
670 */ 673 */
671 #define WM9081_EQ_B1_PG_MASK 674 #define WM9081_EQ_B1_PG_MASK 0xFFFF /* EQ_B1_PG - [15:0] */
672 #define WM9081_EQ_B1_PG_SHIFT 675 #define WM9081_EQ_B1_PG_SHIFT 0 /* EQ_B1_PG - [15:0] */
673 #define WM9081_EQ_B1_PG_WIDTH 676 #define WM9081_EQ_B1_PG_WIDTH 16 /* EQ_B1_PG - [15:0] */
674 677
675 /* 678 /*
676 * R47 (0x2F) - EQ 6 679 * R47 (0x2F) - EQ 6
677 */ 680 */
678 #define WM9081_EQ_B2_A_MASK 681 #define WM9081_EQ_B2_A_MASK 0xFFFF /* EQ_B2_A - [15:0] */
679 #define WM9081_EQ_B2_A_SHIFT 682 #define WM9081_EQ_B2_A_SHIFT 0 /* EQ_B2_A - [15:0] */
680 #define WM9081_EQ_B2_A_WIDTH 683 #define WM9081_EQ_B2_A_WIDTH 16 /* EQ_B2_A - [15:0] */
681 684
682 /* 685 /*
683 * R48 (0x30) - EQ 7 686 * R48 (0x30) - EQ 7
684 */ 687 */
685 #define WM9081_EQ_B2_B_MASK 688 #define WM9081_EQ_B2_B_MASK 0xFFFF /* EQ_B2_B - [15:0] */
686 #define WM9081_EQ_B2_B_SHIFT 689 #define WM9081_EQ_B2_B_SHIFT 0 /* EQ_B2_B - [15:0] */
687 #define WM9081_EQ_B2_B_WIDTH 690 #define WM9081_EQ_B2_B_WIDTH 16 /* EQ_B2_B - [15:0] */
688 691
689 /* 692 /*
690 * R49 (0x31) - EQ 8 693 * R49 (0x31) - EQ 8
691 */ 694 */
692 #define WM9081_EQ_B2_C_MASK 695 #define WM9081_EQ_B2_C_MASK 0xFFFF /* EQ_B2_C - [15:0] */
693 #define WM9081_EQ_B2_C_SHIFT 696 #define WM9081_EQ_B2_C_SHIFT 0 /* EQ_B2_C - [15:0] */
694 #define WM9081_EQ_B2_C_WIDTH 697 #define WM9081_EQ_B2_C_WIDTH 16 /* EQ_B2_C - [15:0] */
695 698
696 /* 699 /*
697 * R50 (0x32) - EQ 9 700 * R50 (0x32) - EQ 9
698 */ 701 */
699 #define WM9081_EQ_B2_PG_MASK 702 #define WM9081_EQ_B2_PG_MASK 0xFFFF /* EQ_B2_PG - [15:0] */
700 #define WM9081_EQ_B2_PG_SHIFT 703 #define WM9081_EQ_B2_PG_SHIFT 0 /* EQ_B2_PG - [15:0] */
701 #define WM9081_EQ_B2_PG_WIDTH 704 #define WM9081_EQ_B2_PG_WIDTH 16 /* EQ_B2_PG - [15:0] */
702 705
703 /* 706 /*
704 * R51 (0x33) - EQ 10 707 * R51 (0x33) - EQ 10
705 */ 708 */
706 #define WM9081_EQ_B4_A_MASK 709 #define WM9081_EQ_B4_A_MASK 0xFFFF /* EQ_B4_A - [15:0] */
707 #define WM9081_EQ_B4_A_SHIFT 710 #define WM9081_EQ_B4_A_SHIFT 0 /* EQ_B4_A - [15:0] */
708 #define WM9081_EQ_B4_A_WIDTH 711 #define WM9081_EQ_B4_A_WIDTH 16 /* EQ_B4_A - [15:0] */
709 712
710 /* 713 /*
711 * R52 (0x34) - EQ 11 714 * R52 (0x34) - EQ 11
712 */ 715 */
713 #define WM9081_EQ_B4_B_MASK 716 #define WM9081_EQ_B4_B_MASK 0xFFFF /* EQ_B4_B - [15:0] */
714 #define WM9081_EQ_B4_B_SHIFT 717 #define WM9081_EQ_B4_B_SHIFT 0 /* EQ_B4_B - [15:0] */
715 #define WM9081_EQ_B4_B_WIDTH 718 #define WM9081_EQ_B4_B_WIDTH 16 /* EQ_B4_B - [15:0] */
716 719
717 /* 720 /*
718 * R53 (0x35) - EQ 12 721 * R53 (0x35) - EQ 12
719 */ 722 */
720 #define WM9081_EQ_B4_C_MASK 723 #define WM9081_EQ_B4_C_MASK 0xFFFF /* EQ_B4_C - [15:0] */
721 #define WM9081_EQ_B4_C_SHIFT 724 #define WM9081_EQ_B4_C_SHIFT 0 /* EQ_B4_C - [15:0] */
722 #define WM9081_EQ_B4_C_WIDTH 725 #define WM9081_EQ_B4_C_WIDTH 16 /* EQ_B4_C - [15:0] */
723 726
724 /* 727 /*
725 * R54 (0x36) - EQ 13 728 * R54 (0x36) - EQ 13
726 */ 729 */
727 #define WM9081_EQ_B4_PG_MASK 730 #define WM9081_EQ_B4_PG_MASK 0xFFFF /* EQ_B4_PG - [15:0] */
728 #define WM9081_EQ_B4_PG_SHIFT 731 #define WM9081_EQ_B4_PG_SHIFT 0 /* EQ_B4_PG - [15:0] */
729 #define WM9081_EQ_B4_PG_WIDTH 732 #define WM9081_EQ_B4_PG_WIDTH 16 /* EQ_B4_PG - [15:0] */
730 733
731 /* 734 /*
732 * R55 (0x37) - EQ 14 735 * R55 (0x37) - EQ 14
733 */ 736 */
734 #define WM9081_EQ_B3_A_MASK 737 #define WM9081_EQ_B3_A_MASK 0xFFFF /* EQ_B3_A - [15:0] */
735 #define WM9081_EQ_B3_A_SHIFT 738 #define WM9081_EQ_B3_A_SHIFT 0 /* EQ_B3_A - [15:0] */
736 #define WM9081_EQ_B3_A_WIDTH 739 #define WM9081_EQ_B3_A_WIDTH 16 /* EQ_B3_A - [15:0] */
737 740
738 /* 741 /*
739 * R56 (0x38) - EQ 15 742 * R56 (0x38) - EQ 15
740 */ 743 */
741 #define WM9081_EQ_B3_B_MASK 744 #define WM9081_EQ_B3_B_MASK 0xFFFF /* EQ_B3_B - [15:0] */
742 #define WM9081_EQ_B3_B_SHIFT 745 #define WM9081_EQ_B3_B_SHIFT 0 /* EQ_B3_B - [15:0] */
743 #define WM9081_EQ_B3_B_WIDTH 746 #define WM9081_EQ_B3_B_WIDTH 16 /* EQ_B3_B - [15:0] */
744 747
745 /* 748 /*
746 * R57 (0x39) - EQ 16 749 * R57 (0x39) - EQ 16
747 */ 750 */
748 #define WM9081_EQ_B3_C_MASK 751 #define WM9081_EQ_B3_C_MASK 0xFFFF /* EQ_B3_C - [15:0] */
749 #define WM9081_EQ_B3_C_SHIFT 752 #define WM9081_EQ_B3_C_SHIFT 0 /* EQ_B3_C - [15:0] */
750 #define WM9081_EQ_B3_C_WIDTH 753 #define WM9081_EQ_B3_C_WIDTH 16 /* EQ_B3_C - [15:0] */
751 754
752 /* 755 /*
753 * R58 (0x3A) - EQ 17 756 * R58 (0x3A) - EQ 17
754 */ 757 */
755 #define WM9081_EQ_B3_PG_MASK 758 #define WM9081_EQ_B3_PG_MASK 0xFFFF /* EQ_B3_PG - [15:0] */
756 #define WM9081_EQ_B3_PG_SHIFT 759 #define WM9081_EQ_B3_PG_SHIFT 0 /* EQ_B3_PG - [15:0] */
757 #define WM9081_EQ_B3_PG_WIDTH 760 #define WM9081_EQ_B3_PG_WIDTH 16 /* EQ_B3_PG - [15:0] */
758 761
759 /* 762 /*
760 * R59 (0x3B) - EQ 18 763 * R59 (0x3B) - EQ 18
761 */ 764 */
762 #define WM9081_EQ_B5_A_MASK 765 #define WM9081_EQ_B5_A_MASK 0xFFFF /* EQ_B5_A - [15:0] */
763 #define WM9081_EQ_B5_A_SHIFT 766 #define WM9081_EQ_B5_A_SHIFT 0 /* EQ_B5_A - [15:0] */
764 #define WM9081_EQ_B5_A_WIDTH 767 #define WM9081_EQ_B5_A_WIDTH 16 /* EQ_B5_A - [15:0] */
765 768
766 /* 769 /*
767 * R60 (0x3C) - EQ 19 770 * R60 (0x3C) - EQ 19
768 */ 771 */
769 #define WM9081_EQ_B5_B_MASK 772 #define WM9081_EQ_B5_B_MASK 0xFFFF /* EQ_B5_B - [15:0] */
770 #define WM9081_EQ_B5_B_SHIFT 773 #define WM9081_EQ_B5_B_SHIFT 0 /* EQ_B5_B - [15:0] */
771 #define WM9081_EQ_B5_B_WIDTH 774 #define WM9081_EQ_B5_B_WIDTH 16 /* EQ_B5_B - [15:0] */
772 775
773 /* 776 /*
774 * R61 (0x3D) - EQ 20 777 * R61 (0x3D) - EQ 20
775 */ 778 */
776 #define WM9081_EQ_B5_PG_MASK 779 #define WM9081_EQ_B5_PG_MASK 0xFFFF /* EQ_B5_PG - [15:0] */
777 #define WM9081_EQ_B5_PG_SHIFT 780 #define WM9081_EQ_B5_PG_SHIFT 0 /* EQ_B5_PG - [15:0] */
778 #define WM9081_EQ_B5_PG_WIDTH 781 #define WM9081_EQ_B5_PG_WIDTH 16 /* EQ_B5_PG - [15:0] */
779 782
780 783
781 #endif 784 #endif
782 785
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