1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 2 #ifndef WM9081_H 3 #define WM9081_H 4 5 /* 6 * wm9081.c -- WM9081 ALSA SoC Audio driver 7 * 8 * Author: Mark Brown 9 * 10 * Copyright 2009 Wolfson Microelectronics plc 11 */ 12 13 #include <sound/soc.h> 14 15 /* 16 * SYSCLK sources 17 */ 18 #define WM9081_SYSCLK_MCLK 1 /* Use MCL 19 #define WM9081_SYSCLK_FLL_MCLK 2 /* Use MCL 20 21 /* 22 * Register values. 23 */ 24 #define WM9081_SOFTWARE_RESET 25 #define WM9081_ANALOGUE_LINEOUT 26 #define WM9081_ANALOGUE_SPEAKER_PGA 27 #define WM9081_VMID_CONTROL 28 #define WM9081_BIAS_CONTROL_1 29 #define WM9081_ANALOGUE_MIXER 30 #define WM9081_ANTI_POP_CONTROL 31 #define WM9081_ANALOGUE_SPEAKER_1 32 #define WM9081_ANALOGUE_SPEAKER_2 33 #define WM9081_POWER_MANAGEMENT 34 #define WM9081_CLOCK_CONTROL_1 35 #define WM9081_CLOCK_CONTROL_2 36 #define WM9081_CLOCK_CONTROL_3 37 #define WM9081_FLL_CONTROL_1 38 #define WM9081_FLL_CONTROL_2 39 #define WM9081_FLL_CONTROL_3 40 #define WM9081_FLL_CONTROL_4 41 #define WM9081_FLL_CONTROL_5 42 #define WM9081_AUDIO_INTERFACE_1 43 #define WM9081_AUDIO_INTERFACE_2 44 #define WM9081_AUDIO_INTERFACE_3 45 #define WM9081_AUDIO_INTERFACE_4 46 #define WM9081_INTERRUPT_STATUS 47 #define WM9081_INTERRUPT_STATUS_MASK 48 #define WM9081_INTERRUPT_POLARITY 49 #define WM9081_INTERRUPT_CONTROL 50 #define WM9081_DAC_DIGITAL_1 51 #define WM9081_DAC_DIGITAL_2 52 #define WM9081_DRC_1 53 #define WM9081_DRC_2 54 #define WM9081_DRC_3 55 #define WM9081_DRC_4 56 #define WM9081_WRITE_SEQUENCER_1 57 #define WM9081_WRITE_SEQUENCER_2 58 #define WM9081_MW_SLAVE_1 59 #define WM9081_EQ_1 60 #define WM9081_EQ_2 61 #define WM9081_EQ_3 62 #define WM9081_EQ_4 63 #define WM9081_EQ_5 64 #define WM9081_EQ_6 65 #define WM9081_EQ_7 66 #define WM9081_EQ_8 67 #define WM9081_EQ_9 68 #define WM9081_EQ_10 69 #define WM9081_EQ_11 70 #define WM9081_EQ_12 71 #define WM9081_EQ_13 72 #define WM9081_EQ_14 73 #define WM9081_EQ_15 74 #define WM9081_EQ_16 75 #define WM9081_EQ_17 76 #define WM9081_EQ_18 77 #define WM9081_EQ_19 78 #define WM9081_EQ_20 79 80 #define WM9081_REGISTER_COUNT 81 #define WM9081_MAX_REGISTER 82 83 /* 84 * Field Definitions. 85 */ 86 87 /* 88 * R0 (0x00) - Software Reset 89 */ 90 #define WM9081_SW_RST_DEV_ID1_MASK 91 #define WM9081_SW_RST_DEV_ID1_SHIFT 92 #define WM9081_SW_RST_DEV_ID1_WIDTH 93 94 /* 95 * R2 (0x02) - Analogue Lineout 96 */ 97 #define WM9081_LINEOUT_MUTE 98 #define WM9081_LINEOUT_MUTE_MASK 99 #define WM9081_LINEOUT_MUTE_SHIFT 100 #define WM9081_LINEOUT_MUTE_WIDTH 101 #define WM9081_LINEOUTZC 102 #define WM9081_LINEOUTZC_MASK 103 #define WM9081_LINEOUTZC_SHIFT 104 #define WM9081_LINEOUTZC_WIDTH 105 #define WM9081_LINEOUT_VOL_MASK 106 #define WM9081_LINEOUT_VOL_SHIFT 107 #define WM9081_LINEOUT_VOL_WIDTH 108 109 /* 110 * R3 (0x03) - Analogue Speaker PGA 111 */ 112 #define WM9081_SPKPGA_MUTE 113 #define WM9081_SPKPGA_MUTE_MASK 114 #define WM9081_SPKPGA_MUTE_SHIFT 115 #define WM9081_SPKPGA_MUTE_WIDTH 116 #define WM9081_SPKPGAZC 117 #define WM9081_SPKPGAZC_MASK 118 #define WM9081_SPKPGAZC_SHIFT 119 #define WM9081_SPKPGAZC_WIDTH 120 #define WM9081_SPKPGA_VOL_MASK 121 #define WM9081_SPKPGA_VOL_SHIFT 122 #define WM9081_SPKPGA_VOL_WIDTH 123 124 /* 125 * R4 (0x04) - VMID Control 126 */ 127 #define WM9081_VMID_BUF_ENA 128 #define WM9081_VMID_BUF_ENA_MASK 129 #define WM9081_VMID_BUF_ENA_SHIFT 130 #define WM9081_VMID_BUF_ENA_WIDTH 131 #define WM9081_VMID_RAMP 132 #define WM9081_VMID_RAMP_MASK 133 #define WM9081_VMID_RAMP_SHIFT 134 #define WM9081_VMID_RAMP_WIDTH 135 #define WM9081_VMID_SEL_MASK 136 #define WM9081_VMID_SEL_SHIFT 137 #define WM9081_VMID_SEL_WIDTH 138 #define WM9081_VMID_FAST_ST 139 #define WM9081_VMID_FAST_ST_MASK 140 #define WM9081_VMID_FAST_ST_SHIFT 141 #define WM9081_VMID_FAST_ST_WIDTH 142 143 /* 144 * R5 (0x05) - Bias Control 1 145 */ 146 #define WM9081_BIAS_SRC 147 #define WM9081_BIAS_SRC_MASK 148 #define WM9081_BIAS_SRC_SHIFT 149 #define WM9081_BIAS_SRC_WIDTH 150 #define WM9081_STBY_BIAS_LVL 151 #define WM9081_STBY_BIAS_LVL_MASK 152 #define WM9081_STBY_BIAS_LVL_SHIFT 153 #define WM9081_STBY_BIAS_LVL_WIDTH 154 #define WM9081_STBY_BIAS_ENA 155 #define WM9081_STBY_BIAS_ENA_MASK 156 #define WM9081_STBY_BIAS_ENA_SHIFT 157 #define WM9081_STBY_BIAS_ENA_WIDTH 158 #define WM9081_BIAS_LVL_MASK 159 #define WM9081_BIAS_LVL_SHIFT 160 #define WM9081_BIAS_LVL_WIDTH 161 #define WM9081_BIAS_ENA 162 #define WM9081_BIAS_ENA_MASK 163 #define WM9081_BIAS_ENA_SHIFT 164 #define WM9081_BIAS_ENA_WIDTH 165 #define WM9081_STARTUP_BIAS_ENA 166 #define WM9081_STARTUP_BIAS_ENA_MASK 167 #define WM9081_STARTUP_BIAS_ENA_SHIFT 168 #define WM9081_STARTUP_BIAS_ENA_WIDTH 169 170 /* 171 * R7 (0x07) - Analogue Mixer 172 */ 173 #define WM9081_DAC_SEL 174 #define WM9081_DAC_SEL_MASK 175 #define WM9081_DAC_SEL_SHIFT 176 #define WM9081_DAC_SEL_WIDTH 177 #define WM9081_IN2_VOL 178 #define WM9081_IN2_VOL_MASK 179 #define WM9081_IN2_VOL_SHIFT 180 #define WM9081_IN2_VOL_WIDTH 181 #define WM9081_IN2_ENA 182 #define WM9081_IN2_ENA_MASK 183 #define WM9081_IN2_ENA_SHIFT 184 #define WM9081_IN2_ENA_WIDTH 185 #define WM9081_IN1_VOL 186 #define WM9081_IN1_VOL_MASK 187 #define WM9081_IN1_VOL_SHIFT 188 #define WM9081_IN1_VOL_WIDTH 189 #define WM9081_IN1_ENA 190 #define WM9081_IN1_ENA_MASK 191 #define WM9081_IN1_ENA_SHIFT 192 #define WM9081_IN1_ENA_WIDTH 193 194 /* 195 * R8 (0x08) - Anti Pop Control 196 */ 197 #define WM9081_LINEOUT_DISCH 198 #define WM9081_LINEOUT_DISCH_MASK 199 #define WM9081_LINEOUT_DISCH_SHIFT 200 #define WM9081_LINEOUT_DISCH_WIDTH 201 #define WM9081_LINEOUT_VROI 202 #define WM9081_LINEOUT_VROI_MASK 203 #define WM9081_LINEOUT_VROI_SHIFT 204 #define WM9081_LINEOUT_VROI_WIDTH 205 #define WM9081_LINEOUT_CLAMP 206 #define WM9081_LINEOUT_CLAMP_MASK 207 #define WM9081_LINEOUT_CLAMP_SHIFT 208 #define WM9081_LINEOUT_CLAMP_WIDTH 209 210 /* 211 * R9 (0x09) - Analogue Speaker 1 212 */ 213 #define WM9081_SPK_DCGAIN_MASK 214 #define WM9081_SPK_DCGAIN_SHIFT 215 #define WM9081_SPK_DCGAIN_WIDTH 216 #define WM9081_SPK_ACGAIN_MASK 217 #define WM9081_SPK_ACGAIN_SHIFT 218 #define WM9081_SPK_ACGAIN_WIDTH 219 220 /* 221 * R10 (0x0A) - Analogue Speaker 2 222 */ 223 #define WM9081_SPK_MODE 224 #define WM9081_SPK_MODE_MASK 225 #define WM9081_SPK_MODE_SHIFT 226 #define WM9081_SPK_MODE_WIDTH 227 #define WM9081_SPK_INV_MUTE 228 #define WM9081_SPK_INV_MUTE_MASK 229 #define WM9081_SPK_INV_MUTE_SHIFT 230 #define WM9081_SPK_INV_MUTE_WIDTH 231 #define WM9081_OUT_SPK_CTRL 232 #define WM9081_OUT_SPK_CTRL_MASK 233 #define WM9081_OUT_SPK_CTRL_SHIFT 234 #define WM9081_OUT_SPK_CTRL_WIDTH 235 236 /* 237 * R11 (0x0B) - Power Management 238 */ 239 #define WM9081_TSHUT_ENA 240 #define WM9081_TSHUT_ENA_MASK 241 #define WM9081_TSHUT_ENA_SHIFT 242 #define WM9081_TSHUT_ENA_WIDTH 243 #define WM9081_TSENSE_ENA 244 #define WM9081_TSENSE_ENA_MASK 245 #define WM9081_TSENSE_ENA_SHIFT 246 #define WM9081_TSENSE_ENA_WIDTH 247 #define WM9081_TEMP_SHUT 248 #define WM9081_TEMP_SHUT_MASK 249 #define WM9081_TEMP_SHUT_SHIFT 250 #define WM9081_TEMP_SHUT_WIDTH 251 #define WM9081_LINEOUT_ENA 252 #define WM9081_LINEOUT_ENA_MASK 253 #define WM9081_LINEOUT_ENA_SHIFT 254 #define WM9081_LINEOUT_ENA_WIDTH 255 #define WM9081_SPKPGA_ENA 256 #define WM9081_SPKPGA_ENA_MASK 257 #define WM9081_SPKPGA_ENA_SHIFT 258 #define WM9081_SPKPGA_ENA_WIDTH 259 #define WM9081_SPK_ENA 260 #define WM9081_SPK_ENA_MASK 261 #define WM9081_SPK_ENA_SHIFT 262 #define WM9081_SPK_ENA_WIDTH 263 #define WM9081_DAC_ENA 264 #define WM9081_DAC_ENA_MASK 265 #define WM9081_DAC_ENA_SHIFT 266 #define WM9081_DAC_ENA_WIDTH 267 268 /* 269 * R12 (0x0C) - Clock Control 1 270 */ 271 #define WM9081_CLK_OP_DIV_MASK 272 #define WM9081_CLK_OP_DIV_SHIFT 273 #define WM9081_CLK_OP_DIV_WIDTH 274 #define WM9081_CLK_TO_DIV_MASK 275 #define WM9081_CLK_TO_DIV_SHIFT 276 #define WM9081_CLK_TO_DIV_WIDTH 277 #define WM9081_MCLKDIV2 278 #define WM9081_MCLKDIV2_MASK 279 #define WM9081_MCLKDIV2_SHIFT 280 #define WM9081_MCLKDIV2_WIDTH 281 282 /* 283 * R13 (0x0D) - Clock Control 2 284 */ 285 #define WM9081_CLK_SYS_RATE_MASK 286 #define WM9081_CLK_SYS_RATE_SHIFT 287 #define WM9081_CLK_SYS_RATE_WIDTH 288 #define WM9081_SAMPLE_RATE_MASK 289 #define WM9081_SAMPLE_RATE_SHIFT 290 #define WM9081_SAMPLE_RATE_WIDTH 291 292 /* 293 * R14 (0x0E) - Clock Control 3 294 */ 295 #define WM9081_CLK_SRC_SEL 296 #define WM9081_CLK_SRC_SEL_MASK 297 #define WM9081_CLK_SRC_SEL_SHIFT 298 #define WM9081_CLK_SRC_SEL_WIDTH 299 #define WM9081_CLK_OP_ENA 300 #define WM9081_CLK_OP_ENA_MASK 301 #define WM9081_CLK_OP_ENA_SHIFT 302 #define WM9081_CLK_OP_ENA_WIDTH 303 #define WM9081_CLK_TO_ENA 304 #define WM9081_CLK_TO_ENA_MASK 305 #define WM9081_CLK_TO_ENA_SHIFT 306 #define WM9081_CLK_TO_ENA_WIDTH 307 #define WM9081_CLK_DSP_ENA 308 #define WM9081_CLK_DSP_ENA_MASK 309 #define WM9081_CLK_DSP_ENA_SHIFT 310 #define WM9081_CLK_DSP_ENA_WIDTH 311 #define WM9081_CLK_SYS_ENA 312 #define WM9081_CLK_SYS_ENA_MASK 313 #define WM9081_CLK_SYS_ENA_SHIFT 314 #define WM9081_CLK_SYS_ENA_WIDTH 315 316 /* 317 * R16 (0x10) - FLL Control 1 318 */ 319 #define WM9081_FLL_HOLD 320 #define WM9081_FLL_HOLD_MASK 321 #define WM9081_FLL_HOLD_SHIFT 322 #define WM9081_FLL_HOLD_WIDTH 323 #define WM9081_FLL_FRAC 324 #define WM9081_FLL_FRAC_MASK 325 #define WM9081_FLL_FRAC_SHIFT 326 #define WM9081_FLL_FRAC_WIDTH 327 #define WM9081_FLL_ENA 328 #define WM9081_FLL_ENA_MASK 329 #define WM9081_FLL_ENA_SHIFT 330 #define WM9081_FLL_ENA_WIDTH 331 332 /* 333 * R17 (0x11) - FLL Control 2 334 */ 335 #define WM9081_FLL_OUTDIV_MASK 336 #define WM9081_FLL_OUTDIV_SHIFT 337 #define WM9081_FLL_OUTDIV_WIDTH 338 #define WM9081_FLL_CTRL_RATE_MASK 339 #define WM9081_FLL_CTRL_RATE_SHIFT 340 #define WM9081_FLL_CTRL_RATE_WIDTH 341 #define WM9081_FLL_FRATIO_MASK 342 #define WM9081_FLL_FRATIO_SHIFT 343 #define WM9081_FLL_FRATIO_WIDTH 344 345 /* 346 * R18 (0x12) - FLL Control 3 347 */ 348 #define WM9081_FLL_K_MASK 349 #define WM9081_FLL_K_SHIFT 350 #define WM9081_FLL_K_WIDTH 351 352 /* 353 * R19 (0x13) - FLL Control 4 354 */ 355 #define WM9081_FLL_N_MASK 356 #define WM9081_FLL_N_SHIFT 357 #define WM9081_FLL_N_WIDTH 358 #define WM9081_FLL_GAIN_MASK 359 #define WM9081_FLL_GAIN_SHIFT 360 #define WM9081_FLL_GAIN_WIDTH 361 362 /* 363 * R20 (0x14) - FLL Control 5 364 */ 365 #define WM9081_FLL_CLK_REF_DIV_MASK 366 #define WM9081_FLL_CLK_REF_DIV_SHIFT 367 #define WM9081_FLL_CLK_REF_DIV_WIDTH 368 #define WM9081_FLL_CLK_SRC_MASK 369 #define WM9081_FLL_CLK_SRC_SHIFT 370 #define WM9081_FLL_CLK_SRC_WIDTH 371 372 /* 373 * R22 (0x16) - Audio Interface 1 374 */ 375 #define WM9081_AIFDAC_CHAN 376 #define WM9081_AIFDAC_CHAN_MASK 377 #define WM9081_AIFDAC_CHAN_SHIFT 378 #define WM9081_AIFDAC_CHAN_WIDTH 379 #define WM9081_AIFDAC_TDM_SLOT_MASK 380 #define WM9081_AIFDAC_TDM_SLOT_SHIFT 381 #define WM9081_AIFDAC_TDM_SLOT_WIDTH 382 #define WM9081_AIFDAC_TDM_MODE_MASK 383 #define WM9081_AIFDAC_TDM_MODE_SHIFT 384 #define WM9081_AIFDAC_TDM_MODE_WIDTH 385 #define WM9081_DAC_COMP 386 #define WM9081_DAC_COMP_MASK 387 #define WM9081_DAC_COMP_SHIFT 388 #define WM9081_DAC_COMP_WIDTH 389 #define WM9081_DAC_COMPMODE 390 #define WM9081_DAC_COMPMODE_MASK 391 #define WM9081_DAC_COMPMODE_SHIFT 392 #define WM9081_DAC_COMPMODE_WIDTH 393 394 /* 395 * R23 (0x17) - Audio Interface 2 396 */ 397 #define WM9081_AIF_TRIS 398 #define WM9081_AIF_TRIS_MASK 399 #define WM9081_AIF_TRIS_SHIFT 400 #define WM9081_AIF_TRIS_WIDTH 401 #define WM9081_DAC_DAT_INV 402 #define WM9081_DAC_DAT_INV_MASK 403 #define WM9081_DAC_DAT_INV_SHIFT 404 #define WM9081_DAC_DAT_INV_WIDTH 405 #define WM9081_AIF_BCLK_INV 406 #define WM9081_AIF_BCLK_INV_MASK 407 #define WM9081_AIF_BCLK_INV_SHIFT 408 #define WM9081_AIF_BCLK_INV_WIDTH 409 #define WM9081_BCLK_DIR 410 #define WM9081_BCLK_DIR_MASK 411 #define WM9081_BCLK_DIR_SHIFT 412 #define WM9081_BCLK_DIR_WIDTH 413 #define WM9081_LRCLK_DIR 414 #define WM9081_LRCLK_DIR_MASK 415 #define WM9081_LRCLK_DIR_SHIFT 416 #define WM9081_LRCLK_DIR_WIDTH 417 #define WM9081_AIF_LRCLK_INV 418 #define WM9081_AIF_LRCLK_INV_MASK 419 #define WM9081_AIF_LRCLK_INV_SHIFT 420 #define WM9081_AIF_LRCLK_INV_WIDTH 421 #define WM9081_AIF_WL_MASK 422 #define WM9081_AIF_WL_SHIFT 423 #define WM9081_AIF_WL_WIDTH 424 #define WM9081_AIF_FMT_MASK 425 #define WM9081_AIF_FMT_SHIFT 426 #define WM9081_AIF_FMT_WIDTH 427 428 /* 429 * R24 (0x18) - Audio Interface 3 430 */ 431 #define WM9081_BCLK_DIV_MASK 432 #define WM9081_BCLK_DIV_SHIFT 433 #define WM9081_BCLK_DIV_WIDTH 434 435 /* 436 * R25 (0x19) - Audio Interface 4 437 */ 438 #define WM9081_LRCLK_RATE_MASK 439 #define WM9081_LRCLK_RATE_SHIFT 440 #define WM9081_LRCLK_RATE_WIDTH 441 442 /* 443 * R26 (0x1A) - Interrupt Status 444 */ 445 #define WM9081_WSEQ_BUSY_EINT 446 #define WM9081_WSEQ_BUSY_EINT_MASK 447 #define WM9081_WSEQ_BUSY_EINT_SHIFT 448 #define WM9081_WSEQ_BUSY_EINT_WIDTH 449 #define WM9081_TSHUT_EINT 450 #define WM9081_TSHUT_EINT_MASK 451 #define WM9081_TSHUT_EINT_SHIFT 452 #define WM9081_TSHUT_EINT_WIDTH 453 454 /* 455 * R27 (0x1B) - Interrupt Status Mask 456 */ 457 #define WM9081_IM_WSEQ_BUSY_EINT 458 #define WM9081_IM_WSEQ_BUSY_EINT_MASK 459 #define WM9081_IM_WSEQ_BUSY_EINT_SHIFT 460 #define WM9081_IM_WSEQ_BUSY_EINT_WIDTH 461 #define WM9081_IM_TSHUT_EINT 462 #define WM9081_IM_TSHUT_EINT_MASK 463 #define WM9081_IM_TSHUT_EINT_SHIFT 464 #define WM9081_IM_TSHUT_EINT_WIDTH 465 466 /* 467 * R28 (0x1C) - Interrupt Polarity 468 */ 469 #define WM9081_TSHUT_INV 470 #define WM9081_TSHUT_INV_MASK 471 #define WM9081_TSHUT_INV_SHIFT 472 #define WM9081_TSHUT_INV_WIDTH 473 474 /* 475 * R29 (0x1D) - Interrupt Control 476 */ 477 #define WM9081_IRQ_POL 478 #define WM9081_IRQ_POL_MASK 479 #define WM9081_IRQ_POL_SHIFT 480 #define WM9081_IRQ_POL_WIDTH 481 #define WM9081_IRQ_OP_CTRL 482 #define WM9081_IRQ_OP_CTRL_MASK 483 #define WM9081_IRQ_OP_CTRL_SHIFT 484 #define WM9081_IRQ_OP_CTRL_WIDTH 485 486 /* 487 * R30 (0x1E) - DAC Digital 1 488 */ 489 #define WM9081_DAC_VOL_MASK 490 #define WM9081_DAC_VOL_SHIFT 491 #define WM9081_DAC_VOL_WIDTH 492 493 /* 494 * R31 (0x1F) - DAC Digital 2 495 */ 496 #define WM9081_DAC_MUTERATE 497 #define WM9081_DAC_MUTERATE_MASK 498 #define WM9081_DAC_MUTERATE_SHIFT 499 #define WM9081_DAC_MUTERATE_WIDTH 500 #define WM9081_DAC_MUTEMODE 501 #define WM9081_DAC_MUTEMODE_MASK 502 #define WM9081_DAC_MUTEMODE_SHIFT 503 #define WM9081_DAC_MUTEMODE_WIDTH 504 #define WM9081_DAC_MUTE 505 #define WM9081_DAC_MUTE_MASK 506 #define WM9081_DAC_MUTE_SHIFT 507 #define WM9081_DAC_MUTE_WIDTH 508 #define WM9081_DEEMPH_MASK 509 #define WM9081_DEEMPH_SHIFT 510 #define WM9081_DEEMPH_WIDTH 511 512 /* 513 * R32 (0x20) - DRC 1 514 */ 515 #define WM9081_DRC_ENA 516 #define WM9081_DRC_ENA_MASK 517 #define WM9081_DRC_ENA_SHIFT 518 #define WM9081_DRC_ENA_WIDTH 519 #define WM9081_DRC_STARTUP_GAIN_MASK 520 #define WM9081_DRC_STARTUP_GAIN_SHIFT 521 #define WM9081_DRC_STARTUP_GAIN_WIDTH 522 #define WM9081_DRC_FF_DLY 523 #define WM9081_DRC_FF_DLY_MASK 524 #define WM9081_DRC_FF_DLY_SHIFT 525 #define WM9081_DRC_FF_DLY_WIDTH 526 #define WM9081_DRC_QR 527 #define WM9081_DRC_QR_MASK 528 #define WM9081_DRC_QR_SHIFT 529 #define WM9081_DRC_QR_WIDTH 530 #define WM9081_DRC_ANTICLIP 531 #define WM9081_DRC_ANTICLIP_MASK 532 #define WM9081_DRC_ANTICLIP_SHIFT 533 #define WM9081_DRC_ANTICLIP_WIDTH 534 535 /* 536 * R33 (0x21) - DRC 2 537 */ 538 #define WM9081_DRC_ATK_MASK 539 #define WM9081_DRC_ATK_SHIFT 540 #define WM9081_DRC_ATK_WIDTH 541 #define WM9081_DRC_DCY_MASK 542 #define WM9081_DRC_DCY_SHIFT 543 #define WM9081_DRC_DCY_WIDTH 544 #define WM9081_DRC_QR_THR_MASK 545 #define WM9081_DRC_QR_THR_SHIFT 546 #define WM9081_DRC_QR_THR_WIDTH 547 #define WM9081_DRC_QR_DCY_MASK 548 #define WM9081_DRC_QR_DCY_SHIFT 549 #define WM9081_DRC_QR_DCY_WIDTH 550 #define WM9081_DRC_MINGAIN_MASK 551 #define WM9081_DRC_MINGAIN_SHIFT 552 #define WM9081_DRC_MINGAIN_WIDTH 553 #define WM9081_DRC_MAXGAIN_MASK 554 #define WM9081_DRC_MAXGAIN_SHIFT 555 #define WM9081_DRC_MAXGAIN_WIDTH 556 557 /* 558 * R34 (0x22) - DRC 3 559 */ 560 #define WM9081_DRC_HI_COMP_MASK 561 #define WM9081_DRC_HI_COMP_SHIFT 562 #define WM9081_DRC_HI_COMP_WIDTH 563 #define WM9081_DRC_LO_COMP_MASK 564 #define WM9081_DRC_LO_COMP_SHIFT 565 #define WM9081_DRC_LO_COMP_WIDTH 566 567 /* 568 * R35 (0x23) - DRC 4 569 */ 570 #define WM9081_DRC_KNEE_IP_MASK 571 #define WM9081_DRC_KNEE_IP_SHIFT 572 #define WM9081_DRC_KNEE_IP_WIDTH 573 #define WM9081_DRC_KNEE_OP_MASK 574 #define WM9081_DRC_KNEE_OP_SHIFT 575 #define WM9081_DRC_KNEE_OP_WIDTH 576 577 /* 578 * R38 (0x26) - Write Sequencer 1 579 */ 580 #define WM9081_WSEQ_ENA 581 #define WM9081_WSEQ_ENA_MASK 582 #define WM9081_WSEQ_ENA_SHIFT 583 #define WM9081_WSEQ_ENA_WIDTH 584 #define WM9081_WSEQ_ABORT 585 #define WM9081_WSEQ_ABORT_MASK 586 #define WM9081_WSEQ_ABORT_SHIFT 587 #define WM9081_WSEQ_ABORT_WIDTH 588 #define WM9081_WSEQ_START 589 #define WM9081_WSEQ_START_MASK 590 #define WM9081_WSEQ_START_SHIFT 591 #define WM9081_WSEQ_START_WIDTH 592 #define WM9081_WSEQ_START_INDEX_MASK 593 #define WM9081_WSEQ_START_INDEX_SHIFT 594 #define WM9081_WSEQ_START_INDEX_WIDTH 595 596 /* 597 * R39 (0x27) - Write Sequencer 2 598 */ 599 #define WM9081_WSEQ_CURRENT_INDEX_MASK 600 #define WM9081_WSEQ_CURRENT_INDEX_SHIFT 601 #define WM9081_WSEQ_CURRENT_INDEX_WIDTH 602 #define WM9081_WSEQ_BUSY 603 #define WM9081_WSEQ_BUSY_MASK 604 #define WM9081_WSEQ_BUSY_SHIFT 605 #define WM9081_WSEQ_BUSY_WIDTH 606 607 /* 608 * R40 (0x28) - MW Slave 1 609 */ 610 #define WM9081_SPI_CFG 611 #define WM9081_SPI_CFG_MASK 612 #define WM9081_SPI_CFG_SHIFT 613 #define WM9081_SPI_CFG_WIDTH 614 #define WM9081_SPI_4WIRE 615 #define WM9081_SPI_4WIRE_MASK 616 #define WM9081_SPI_4WIRE_SHIFT 617 #define WM9081_SPI_4WIRE_WIDTH 618 #define WM9081_ARA_ENA 619 #define WM9081_ARA_ENA_MASK 620 #define WM9081_ARA_ENA_SHIFT 621 #define WM9081_ARA_ENA_WIDTH 622 #define WM9081_AUTO_INC 623 #define WM9081_AUTO_INC_MASK 624 #define WM9081_AUTO_INC_SHIFT 625 #define WM9081_AUTO_INC_WIDTH 626 627 /* 628 * R42 (0x2A) - EQ 1 629 */ 630 #define WM9081_EQ_B1_GAIN_MASK 631 #define WM9081_EQ_B1_GAIN_SHIFT 632 #define WM9081_EQ_B1_GAIN_WIDTH 633 #define WM9081_EQ_B2_GAIN_MASK 634 #define WM9081_EQ_B2_GAIN_SHIFT 635 #define WM9081_EQ_B2_GAIN_WIDTH 636 #define WM9081_EQ_B4_GAIN_MASK 637 #define WM9081_EQ_B4_GAIN_SHIFT 638 #define WM9081_EQ_B4_GAIN_WIDTH 639 #define WM9081_EQ_ENA 640 #define WM9081_EQ_ENA_MASK 641 #define WM9081_EQ_ENA_SHIFT 642 #define WM9081_EQ_ENA_WIDTH 643 644 /* 645 * R43 (0x2B) - EQ 2 646 */ 647 #define WM9081_EQ_B3_GAIN_MASK 648 #define WM9081_EQ_B3_GAIN_SHIFT 649 #define WM9081_EQ_B3_GAIN_WIDTH 650 #define WM9081_EQ_B5_GAIN_MASK 651 #define WM9081_EQ_B5_GAIN_SHIFT 652 #define WM9081_EQ_B5_GAIN_WIDTH 653 654 /* 655 * R44 (0x2C) - EQ 3 656 */ 657 #define WM9081_EQ_B1_A_MASK 658 #define WM9081_EQ_B1_A_SHIFT 659 #define WM9081_EQ_B1_A_WIDTH 660 661 /* 662 * R45 (0x2D) - EQ 4 663 */ 664 #define WM9081_EQ_B1_B_MASK 665 #define WM9081_EQ_B1_B_SHIFT 666 #define WM9081_EQ_B1_B_WIDTH 667 668 /* 669 * R46 (0x2E) - EQ 5 670 */ 671 #define WM9081_EQ_B1_PG_MASK 672 #define WM9081_EQ_B1_PG_SHIFT 673 #define WM9081_EQ_B1_PG_WIDTH 674 675 /* 676 * R47 (0x2F) - EQ 6 677 */ 678 #define WM9081_EQ_B2_A_MASK 679 #define WM9081_EQ_B2_A_SHIFT 680 #define WM9081_EQ_B2_A_WIDTH 681 682 /* 683 * R48 (0x30) - EQ 7 684 */ 685 #define WM9081_EQ_B2_B_MASK 686 #define WM9081_EQ_B2_B_SHIFT 687 #define WM9081_EQ_B2_B_WIDTH 688 689 /* 690 * R49 (0x31) - EQ 8 691 */ 692 #define WM9081_EQ_B2_C_MASK 693 #define WM9081_EQ_B2_C_SHIFT 694 #define WM9081_EQ_B2_C_WIDTH 695 696 /* 697 * R50 (0x32) - EQ 9 698 */ 699 #define WM9081_EQ_B2_PG_MASK 700 #define WM9081_EQ_B2_PG_SHIFT 701 #define WM9081_EQ_B2_PG_WIDTH 702 703 /* 704 * R51 (0x33) - EQ 10 705 */ 706 #define WM9081_EQ_B4_A_MASK 707 #define WM9081_EQ_B4_A_SHIFT 708 #define WM9081_EQ_B4_A_WIDTH 709 710 /* 711 * R52 (0x34) - EQ 11 712 */ 713 #define WM9081_EQ_B4_B_MASK 714 #define WM9081_EQ_B4_B_SHIFT 715 #define WM9081_EQ_B4_B_WIDTH 716 717 /* 718 * R53 (0x35) - EQ 12 719 */ 720 #define WM9081_EQ_B4_C_MASK 721 #define WM9081_EQ_B4_C_SHIFT 722 #define WM9081_EQ_B4_C_WIDTH 723 724 /* 725 * R54 (0x36) - EQ 13 726 */ 727 #define WM9081_EQ_B4_PG_MASK 728 #define WM9081_EQ_B4_PG_SHIFT 729 #define WM9081_EQ_B4_PG_WIDTH 730 731 /* 732 * R55 (0x37) - EQ 14 733 */ 734 #define WM9081_EQ_B3_A_MASK 735 #define WM9081_EQ_B3_A_SHIFT 736 #define WM9081_EQ_B3_A_WIDTH 737 738 /* 739 * R56 (0x38) - EQ 15 740 */ 741 #define WM9081_EQ_B3_B_MASK 742 #define WM9081_EQ_B3_B_SHIFT 743 #define WM9081_EQ_B3_B_WIDTH 744 745 /* 746 * R57 (0x39) - EQ 16 747 */ 748 #define WM9081_EQ_B3_C_MASK 749 #define WM9081_EQ_B3_C_SHIFT 750 #define WM9081_EQ_B3_C_WIDTH 751 752 /* 753 * R58 (0x3A) - EQ 17 754 */ 755 #define WM9081_EQ_B3_PG_MASK 756 #define WM9081_EQ_B3_PG_SHIFT 757 #define WM9081_EQ_B3_PG_WIDTH 758 759 /* 760 * R59 (0x3B) - EQ 18 761 */ 762 #define WM9081_EQ_B5_A_MASK 763 #define WM9081_EQ_B5_A_SHIFT 764 #define WM9081_EQ_B5_A_WIDTH 765 766 /* 767 * R60 (0x3C) - EQ 19 768 */ 769 #define WM9081_EQ_B5_B_MASK 770 #define WM9081_EQ_B5_B_SHIFT 771 #define WM9081_EQ_B5_B_WIDTH 772 773 /* 774 * R61 (0x3D) - EQ 20 775 */ 776 #define WM9081_EQ_B5_PG_MASK 777 #define WM9081_EQ_B5_PG_SHIFT 778 #define WM9081_EQ_B5_PG_WIDTH 779 780 781 #endif 782
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