1 /* SPDX-License-Identifier: GPL-2.0 */ 1
2 /*
3 * Copyright 2017-2021 NXP
4 */
5
6 #ifndef __FSL_RPMSG_H
7 #define __FSL_RPMSG_H
8
9 /*
10 * struct fsl_rpmsg_soc_data
11 * @rates: supported rates
12 * @formats: supported formats
13 */
14 struct fsl_rpmsg_soc_data {
15 int rates;
16 u64 formats;
17 };
18
19 /*
20 * struct fsl_rpmsg - rpmsg private data
21 *
22 * @ipg: ipg clock for cpu dai (SAI)
23 * @mclk: master clock for cpu dai (SAI)
24 * @dma: clock for dma device
25 * @pll8k: parent clock for multiple of 8kHz f
26 * @pll11k: parent clock for multiple of 11kHz
27 * @card_pdev: Platform_device pointer to regi
28 * @soc_data: soc specific data
29 * @mclk_streams: Active streams that are usin
30 * @force_lpa: force enable low power audio ro
31 * @enable_lpa: enable low power audio routine
32 * @buffer_size: pre allocated dma buffer size
33 */
34 struct fsl_rpmsg {
35 struct clk *ipg;
36 struct clk *mclk;
37 struct clk *dma;
38 struct clk *pll8k;
39 struct clk *pll11k;
40 struct platform_device *card_pdev;
41 const struct fsl_rpmsg_soc_data *soc_d
42 unsigned int mclk_streams;
43 int force_lpa;
44 int enable_lpa;
45 int buffer_size;
46 };
47 #endif /* __FSL_RPMSG_H */
48
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