1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 // 2 //
3 // Copyright(c) 2021-2024 Intel Corporation 3 // Copyright(c) 2021-2024 Intel Corporation
4 // 4 //
5 // Authors: Cezary Rojewski <cezary.rojewski@i 5 // Authors: Cezary Rojewski <cezary.rojewski@intel.com>
6 // Amadeusz Slawinski <amadeuszx.slaw 6 // Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
7 // 7 //
8 8
9 #include "avs.h" 9 #include "avs.h"
10 10
11 static int avs_tgl_dsp_core_power(struct avs_d 11 static int avs_tgl_dsp_core_power(struct avs_dev *adev, u32 core_mask, bool power)
12 { 12 {
13 core_mask &= AVS_MAIN_CORE_MASK; 13 core_mask &= AVS_MAIN_CORE_MASK;
14 14
15 if (!core_mask) 15 if (!core_mask)
16 return 0; 16 return 0;
17 return avs_dsp_core_power(adev, core_m 17 return avs_dsp_core_power(adev, core_mask, power);
18 } 18 }
19 19
20 static int avs_tgl_dsp_core_reset(struct avs_d 20 static int avs_tgl_dsp_core_reset(struct avs_dev *adev, u32 core_mask, bool reset)
21 { 21 {
22 core_mask &= AVS_MAIN_CORE_MASK; 22 core_mask &= AVS_MAIN_CORE_MASK;
23 23
24 if (!core_mask) 24 if (!core_mask)
25 return 0; 25 return 0;
26 return avs_dsp_core_reset(adev, core_m 26 return avs_dsp_core_reset(adev, core_mask, reset);
27 } 27 }
28 28
29 static int avs_tgl_dsp_core_stall(struct avs_d 29 static int avs_tgl_dsp_core_stall(struct avs_dev *adev, u32 core_mask, bool stall)
30 { 30 {
31 core_mask &= AVS_MAIN_CORE_MASK; 31 core_mask &= AVS_MAIN_CORE_MASK;
32 32
33 if (!core_mask) 33 if (!core_mask)
34 return 0; 34 return 0;
35 return avs_dsp_core_stall(adev, core_m 35 return avs_dsp_core_stall(adev, core_mask, stall);
36 } 36 }
37 37
38 const struct avs_dsp_ops avs_tgl_dsp_ops = { 38 const struct avs_dsp_ops avs_tgl_dsp_ops = {
39 .power = avs_tgl_dsp_core_power, 39 .power = avs_tgl_dsp_core_power,
40 .reset = avs_tgl_dsp_core_reset, 40 .reset = avs_tgl_dsp_core_reset,
41 .stall = avs_tgl_dsp_core_stall, 41 .stall = avs_tgl_dsp_core_stall,
42 .dsp_interrupt = avs_cnl_dsp_interrupt 42 .dsp_interrupt = avs_cnl_dsp_interrupt,
43 .int_control = avs_dsp_interrupt_contr 43 .int_control = avs_dsp_interrupt_control,
44 .load_basefw = avs_icl_load_basefw, 44 .load_basefw = avs_icl_load_basefw,
45 .load_lib = avs_hda_load_library, 45 .load_lib = avs_hda_load_library,
46 .transfer_mods = avs_hda_transfer_modu 46 .transfer_mods = avs_hda_transfer_modules,
47 .log_buffer_offset = avs_icl_log_buffe 47 .log_buffer_offset = avs_icl_log_buffer_offset,
48 .log_buffer_status = avs_apl_log_buffe 48 .log_buffer_status = avs_apl_log_buffer_status,
49 .coredump = avs_apl_coredump, 49 .coredump = avs_apl_coredump,
50 .d0ix_toggle = avs_icl_d0ix_toggle, 50 .d0ix_toggle = avs_icl_d0ix_toggle,
51 .set_d0ix = avs_icl_set_d0ix, 51 .set_d0ix = avs_icl_set_d0ix,
52 AVS_SET_ENABLE_LOGS_OP(icl) 52 AVS_SET_ENABLE_LOGS_OP(icl)
53 }; 53 };
54 54
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