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Linux/sound/soc/loongson/loongson_i2s.h

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Diff markup

Differences between /sound/soc/loongson/loongson_i2s.h (Architecture mips) and /sound/soc/loongson/loongson_i2s.h (Architecture alpha)


  1 /* SPDX-License-Identifier: GPL-2.0 */              1 /* SPDX-License-Identifier: GPL-2.0 */
  2 /*                                                  2 /*
  3  * ALSA I2S interface for the Loongson platfor      3  * ALSA I2S interface for the Loongson platform
  4  *                                                  4  *
  5  * Copyright (C) 2023 Loongson Technology Corp      5  * Copyright (C) 2023 Loongson Technology Corporation Limited
  6  * Author: Yingkun Meng <mengyingkun@loongson.      6  * Author: Yingkun Meng <mengyingkun@loongson.cn>
  7  */                                                 7  */
  8                                                     8 
  9 #ifndef _LOONGSON_I2S_H                             9 #ifndef _LOONGSON_I2S_H
 10 #define _LOONGSON_I2S_H                            10 #define _LOONGSON_I2S_H
 11                                                    11 
 12 #include <linux/regmap.h>                          12 #include <linux/regmap.h>
 13 #include <sound/dmaengine_pcm.h>                   13 #include <sound/dmaengine_pcm.h>
 14                                                    14 
 15 /* I2S Common Registers */                         15 /* I2S Common Registers */
 16 #define LS_I2S_VER      0x00 /* I2S Version */     16 #define LS_I2S_VER      0x00 /* I2S Version */
 17 #define LS_I2S_CFG      0x04 /* I2S Config */      17 #define LS_I2S_CFG      0x04 /* I2S Config */
 18 #define LS_I2S_CTRL     0x08 /* I2S Control */     18 #define LS_I2S_CTRL     0x08 /* I2S Control */
 19 #define LS_I2S_RX_DATA  0x0C /* I2S DMA RX Add     19 #define LS_I2S_RX_DATA  0x0C /* I2S DMA RX Address */
 20 #define LS_I2S_TX_DATA  0x10 /* I2S DMA TX Add     20 #define LS_I2S_TX_DATA  0x10 /* I2S DMA TX Address */
 21                                                    21 
 22 /* 2K2000 I2S Specify Registers */                 22 /* 2K2000 I2S Specify Registers */
 23 #define LS_I2S_CFG1     0x14 /* I2S Config1 */     23 #define LS_I2S_CFG1     0x14 /* I2S Config1 */
 24                                                    24 
 25 /* 7A2000 I2S Specify Registers */                 25 /* 7A2000 I2S Specify Registers */
 26 #define LS_I2S_TX_ORDER 0x100 /* TX DMA Order      26 #define LS_I2S_TX_ORDER 0x100 /* TX DMA Order */
 27 #define LS_I2S_RX_ORDER 0x110 /* RX DMA Order      27 #define LS_I2S_RX_ORDER 0x110 /* RX DMA Order */
 28                                                    28 
 29 /* Loongson I2S Control Register */                29 /* Loongson I2S Control Register */
 30 #define I2S_CTRL_MCLK_READY     BIT(16) /* MCL     30 #define I2S_CTRL_MCLK_READY     BIT(16) /* MCLK ready */
 31 #define I2S_CTRL_MASTER         BIT(15) /* Mas     31 #define I2S_CTRL_MASTER         BIT(15) /* Master mode */
 32 #define I2S_CTRL_MSB            BIT(14) /* MSB     32 #define I2S_CTRL_MSB            BIT(14) /* MSB bit order */
 33 #define I2S_CTRL_RX_EN          BIT(13) /* RX      33 #define I2S_CTRL_RX_EN          BIT(13) /* RX enable */
 34 #define I2S_CTRL_TX_EN          BIT(12) /* TX      34 #define I2S_CTRL_TX_EN          BIT(12) /* TX enable */
 35 #define I2S_CTRL_RX_DMA_EN      BIT(11) /* DMA     35 #define I2S_CTRL_RX_DMA_EN      BIT(11) /* DMA RX enable */
 36 #define I2S_CTRL_CLK_READY      BIT(8)  /* BCL     36 #define I2S_CTRL_CLK_READY      BIT(8)  /* BCLK ready */
 37 #define I2S_CTRL_TX_DMA_EN      BIT(7)  /* DMA     37 #define I2S_CTRL_TX_DMA_EN      BIT(7)  /* DMA TX enable */
 38 #define I2S_CTRL_RESET          BIT(4)  /* Con     38 #define I2S_CTRL_RESET          BIT(4)  /* Controller soft reset */
 39 #define I2S_CTRL_MCLK_EN        BIT(3)  /* Ena     39 #define I2S_CTRL_MCLK_EN        BIT(3)  /* Enable MCLK */
 40 #define I2S_CTRL_RX_INT_EN      BIT(1)  /* RX      40 #define I2S_CTRL_RX_INT_EN      BIT(1)  /* RX interrupt enable */
 41 #define I2S_CTRL_TX_INT_EN      BIT(0)  /* TX      41 #define I2S_CTRL_TX_INT_EN      BIT(0)  /* TX interrupt enable */
 42                                                    42 
 43 #define LS_I2S_DRVNAME          "loongson-i2s"     43 #define LS_I2S_DRVNAME          "loongson-i2s"
 44                                                    44 
 45 struct loongson_dma_data {                         45 struct loongson_dma_data {
 46         dma_addr_t dev_addr;            /* dev     46         dma_addr_t dev_addr;            /* device physical address for DMA */
 47         void __iomem *order_addr;       /* DMA     47         void __iomem *order_addr;       /* DMA order register */
 48         int irq;                        /* DMA     48         int irq;                        /* DMA irq */
 49 };                                                 49 };
 50                                                    50 
 51 struct loongson_i2s {                              51 struct loongson_i2s {
 52         struct device *dev;                        52         struct device *dev;
 53         union {                                    53         union {
 54                 struct snd_dmaengine_dai_dma_d     54                 struct snd_dmaengine_dai_dma_data playback_dma_data;
 55                 struct loongson_dma_data tx_dm     55                 struct loongson_dma_data tx_dma_data;
 56         };                                         56         };
 57         union {                                    57         union {
 58                 struct snd_dmaengine_dai_dma_d     58                 struct snd_dmaengine_dai_dma_data capture_dma_data;
 59                 struct loongson_dma_data rx_dm     59                 struct loongson_dma_data rx_dma_data;
 60         };                                         60         };
 61         struct regmap *regmap;                     61         struct regmap *regmap;
 62         void __iomem *reg_base;                    62         void __iomem *reg_base;
 63         u32 rev_id;                                63         u32 rev_id;
 64         u32 clk_rate;                              64         u32 clk_rate;
 65         u32 sysclk;                                65         u32 sysclk;
 66 };                                                 66 };
 67                                                    67 
 68 extern const struct dev_pm_ops loongson_i2s_pm     68 extern const struct dev_pm_ops loongson_i2s_pm;
 69 extern struct snd_soc_dai_driver loongson_i2s_     69 extern struct snd_soc_dai_driver loongson_i2s_dai;
 70                                                    70 
 71 #endif                                             71 #endif
 72                                                    72 

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