1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 /* 3 * mt6797-reg.h -- Mediatek 6797 audio drive 4 * 5 * Copyright (c) 2018 MediaTek Inc. 6 * Author: KaiChieh Chuang <kaichieh.chuang@me 7 */ 8 9 #ifndef _MT6797_REG_H_ 10 #define _MT6797_REG_H_ 11 12 #define AUDIO_TOP_CON0 0x0000 13 #define AUDIO_TOP_CON1 0x0004 14 #define AUDIO_TOP_CON3 0x000c 15 #define AFE_DAC_CON0 0x0010 16 #define AFE_DAC_CON1 0x0014 17 #define AFE_I2S_CON 0x0018 18 #define AFE_DAIBT_CON0 0x001c 19 #define AFE_CONN0 0x0020 20 #define AFE_CONN1 0x0024 21 #define AFE_CONN2 0x0028 22 #define AFE_CONN3 0x002c 23 #define AFE_CONN4 0x0030 24 #define AFE_I2S_CON1 0x0034 25 #define AFE_I2S_CON2 0x0038 26 #define AFE_MRGIF_CON 0x003c 27 #define AFE_DL1_BASE 0x0040 28 #define AFE_DL1_CUR 0x0044 29 #define AFE_DL1_END 0x0048 30 #define AFE_I2S_CON3 0x004c 31 #define AFE_DL2_BASE 0x0050 32 #define AFE_DL2_CUR 0x0054 33 #define AFE_DL2_END 0x0058 34 #define AFE_CONN5 0x005c 35 #define AFE_CONN_24BIT 0x006c 36 #define AFE_AWB_BASE 0x0070 37 #define AFE_AWB_END 0x0078 38 #define AFE_AWB_CUR 0x007c 39 #define AFE_VUL_BASE 0x0080 40 #define AFE_VUL_END 0x0088 41 #define AFE_VUL_CUR 0x008c 42 #define AFE_DAI_BASE 0x0090 43 #define AFE_DAI_END 0x0098 44 #define AFE_DAI_CUR 0x009c 45 #define AFE_CONN6 0x00bc 46 #define AFE_MEMIF_MSB 0x00cc 47 #define AFE_MEMIF_MON0 0x00d0 48 #define AFE_MEMIF_MON1 0x00d4 49 #define AFE_MEMIF_MON2 0x00d8 50 #define AFE_MEMIF_MON4 0x00e0 51 #define AFE_ADDA_DL_SRC2_CON0 0x0108 52 #define AFE_ADDA_DL_SRC2_CON1 0x010c 53 #define AFE_ADDA_UL_SRC_CON0 0x0114 54 #define AFE_ADDA_UL_SRC_CON1 0x0118 55 #define AFE_ADDA_TOP_CON0 0x0120 56 #define AFE_ADDA_UL_DL_CON0 0x0124 57 #define AFE_ADDA_SRC_DEBUG 0x012c 58 #define AFE_ADDA_SRC_DEBUG_MON0 0x0130 59 #define AFE_ADDA_SRC_DEBUG_MON1 0x0134 60 #define AFE_ADDA_NEWIF_CFG0 0x0138 61 #define AFE_ADDA_NEWIF_CFG1 0x013c 62 #define AFE_ADDA_NEWIF_CFG2 0x0140 63 #define AFE_DMA_CTL 0x0150 64 #define AFE_DMA_MON0 0x0154 65 #define AFE_DMA_MON1 0x0158 66 #define AFE_SIDETONE_DEBUG 0x01d0 67 #define AFE_SIDETONE_MON 0x01d4 68 #define AFE_SIDETONE_CON0 0x01e0 69 #define AFE_SIDETONE_COEFF 0x01e4 70 #define AFE_SIDETONE_CON1 0x01e8 71 #define AFE_SIDETONE_GAIN 0x01ec 72 #define AFE_SGEN_CON0 0x01f0 73 #define AFE_SINEGEN_CON_TDM 0x01fc 74 #define AFE_TOP_CON0 0x0200 75 #define AFE_ADDA_PREDIS_CON0 0x0260 76 #define AFE_ADDA_PREDIS_CON1 0x0264 77 #define AFE_MRGIF_MON0 0x0270 78 #define AFE_MRGIF_MON1 0x0274 79 #define AFE_MRGIF_MON2 0x0278 80 #define AFE_I2S_MON 0x027c 81 #define AFE_MOD_DAI_BASE 0x0330 82 #define AFE_MOD_DAI_END 0x0338 83 #define AFE_MOD_DAI_CUR 0x033c 84 #define AFE_VUL_D2_BASE 0x0350 85 #define AFE_VUL_D2_END 0x0358 86 #define AFE_VUL_D2_CUR 0x035c 87 #define AFE_DL3_BASE 0x0360 88 #define AFE_DL3_CUR 0x0364 89 #define AFE_DL3_END 0x0368 90 #define AFE_HDMI_OUT_CON0 0x0370 91 #define AFE_HDMI_BASE 0x0374 92 #define AFE_HDMI_CUR 0x0378 93 #define AFE_HDMI_END 0x037c 94 #define AFE_HDMI_CONN0 0x0390 95 #define AFE_IRQ3_MCU_CNT_MON 0x0398 96 #define AFE_IRQ4_MCU_CNT_MON 0x039c 97 #define AFE_IRQ_MCU_CON 0x03a0 98 #define AFE_IRQ_MCU_STATUS 0x03a4 99 #define AFE_IRQ_MCU_CLR 0x03a8 100 #define AFE_IRQ_MCU_CNT1 0x03ac 101 #define AFE_IRQ_MCU_CNT2 0x03b0 102 #define AFE_IRQ_MCU_EN 0x03b4 103 #define AFE_IRQ_MCU_MON2 0x03b8 104 #define AFE_IRQ_MCU_CNT5 0x03bc 105 #define AFE_IRQ1_MCU_CNT_MON 0x03c0 106 #define AFE_IRQ2_MCU_CNT_MON 0x03c4 107 #define AFE_IRQ1_MCU_EN_CNT_MON 0x03c8 108 #define AFE_IRQ5_MCU_CNT_MON 0x03cc 109 #define AFE_MEMIF_MINLEN 0x03d0 110 #define AFE_MEMIF_MAXLEN 0x03d4 111 #define AFE_MEMIF_PBUF_SIZE 0x03d8 112 #define AFE_IRQ_MCU_CNT7 0x03dc 113 #define AFE_IRQ7_MCU_CNT_MON 0x03e0 114 #define AFE_IRQ_MCU_CNT3 0x03e4 115 #define AFE_IRQ_MCU_CNT4 0x03e8 116 #define AFE_APLL1_TUNER_CFG 0x03f0 117 #define AFE_APLL2_TUNER_CFG 0x03f4 118 #define AFE_MEMIF_HD_MODE 0x03f8 119 #define AFE_MEMIF_HDALIGN 0x03fc 120 #define AFE_GAIN1_CON0 0x0410 121 #define AFE_GAIN1_CON1 0x0414 122 #define AFE_GAIN1_CON2 0x0418 123 #define AFE_GAIN1_CON3 0x041c 124 #define AFE_CONN7 0x0420 125 #define AFE_GAIN1_CUR 0x0424 126 #define AFE_GAIN2_CON0 0x0428 127 #define AFE_GAIN2_CON1 0x042c 128 #define AFE_GAIN2_CON2 0x0430 129 #define AFE_GAIN2_CON3 0x0434 130 #define AFE_CONN8 0x0438 131 #define AFE_GAIN2_CUR 0x043c 132 #define AFE_CONN9 0x0440 133 #define AFE_CONN10 0x0444 134 #define AFE_CONN11 0x0448 135 #define AFE_CONN12 0x044c 136 #define AFE_CONN13 0x0450 137 #define AFE_CONN14 0x0454 138 #define AFE_CONN15 0x0458 139 #define AFE_CONN16 0x045c 140 #define AFE_CONN17 0x0460 141 #define AFE_CONN18 0x0464 142 #define AFE_CONN19 0x0468 143 #define AFE_CONN20 0x046c 144 #define AFE_CONN21 0x0470 145 #define AFE_CONN22 0x0474 146 #define AFE_CONN23 0x0478 147 #define AFE_CONN24 0x047c 148 #define AFE_CONN_RS 0x0494 149 #define AFE_CONN_DI 0x0498 150 #define AFE_CONN25 0x04b0 151 #define AFE_CONN26 0x04b4 152 #define AFE_CONN27 0x04b8 153 #define AFE_CONN28 0x04bc 154 #define AFE_CONN29 0x04c0 155 #define AFE_SRAM_DELSEL_CON0 0x04f0 156 #define AFE_SRAM_DELSEL_CON1 0x04f4 157 #define AFE_ASRC_CON0 0x0500 158 #define AFE_ASRC_CON1 0x0504 159 #define AFE_ASRC_CON2 0x0508 160 #define AFE_ASRC_CON3 0x050c 161 #define AFE_ASRC_CON4 0x0510 162 #define AFE_ASRC_CON5 0x0514 163 #define AFE_ASRC_CON6 0x0518 164 #define AFE_ASRC_CON7 0x051c 165 #define AFE_ASRC_CON8 0x0520 166 #define AFE_ASRC_CON9 0x0524 167 #define AFE_ASRC_CON10 0x0528 168 #define AFE_ASRC_CON11 0x052c 169 #define PCM_INTF_CON1 0x0530 170 #define PCM_INTF_CON2 0x0538 171 #define PCM2_INTF_CON 0x053c 172 #define AFE_TDM_CON1 0x0548 173 #define AFE_TDM_CON2 0x054c 174 #define AFE_ASRC_CON13 0x0550 175 #define AFE_ASRC_CON14 0x0554 176 #define AFE_ASRC_CON15 0x0558 177 #define AFE_ASRC_CON16 0x055c 178 #define AFE_ASRC_CON17 0x0560 179 #define AFE_ASRC_CON18 0x0564 180 #define AFE_ASRC_CON19 0x0568 181 #define AFE_ASRC_CON20 0x056c 182 #define AFE_ASRC_CON21 0x0570 183 #define CLK_AUDDIV_0 0x05a0 184 #define CLK_AUDDIV_1 0x05a4 185 #define CLK_AUDDIV_2 0x05a8 186 #define CLK_AUDDIV_3 0x05ac 187 #define AUDIO_TOP_DBG_CON 0x05c8 188 #define AUDIO_TOP_DBG_MON0 0x05cc 189 #define AUDIO_TOP_DBG_MON1 0x05d0 190 #define AUDIO_TOP_DBG_MON2 0x05d4 191 #define AFE_ADDA2_TOP_CON0 0x0600 192 #define AFE_ASRC4_CON0 0x06c0 193 #define AFE_ASRC4_CON1 0x06c4 194 #define AFE_ASRC4_CON2 0x06c8 195 #define AFE_ASRC4_CON3 0x06cc 196 #define AFE_ASRC4_CON4 0x06d0 197 #define AFE_ASRC4_CON5 0x06d4 198 #define AFE_ASRC4_CON6 0x06d8 199 #define AFE_ASRC4_CON7 0x06dc 200 #define AFE_ASRC4_CON8 0x06e0 201 #define AFE_ASRC4_CON9 0x06e4 202 #define AFE_ASRC4_CON10 0x06e8 203 #define AFE_ASRC4_CON11 0x06ec 204 #define AFE_ASRC4_CON12 0x06f0 205 #define AFE_ASRC4_CON13 0x06f4 206 #define AFE_ASRC4_CON14 0x06f8 207 #define AFE_ASRC2_CON0 0x0700 208 #define AFE_ASRC2_CON1 0x0704 209 #define AFE_ASRC2_CON2 0x0708 210 #define AFE_ASRC2_CON3 0x070c 211 #define AFE_ASRC2_CON4 0x0710 212 #define AFE_ASRC2_CON5 0x0714 213 #define AFE_ASRC2_CON6 0x0718 214 #define AFE_ASRC2_CON7 0x071c 215 #define AFE_ASRC2_CON8 0x0720 216 #define AFE_ASRC2_CON9 0x0724 217 #define AFE_ASRC2_CON10 0x0728 218 #define AFE_ASRC2_CON11 0x072c 219 #define AFE_ASRC2_CON12 0x0730 220 #define AFE_ASRC2_CON13 0x0734 221 #define AFE_ASRC2_CON14 0x0738 222 #define AFE_ASRC3_CON0 0x0740 223 #define AFE_ASRC3_CON1 0x0744 224 #define AFE_ASRC3_CON2 0x0748 225 #define AFE_ASRC3_CON3 0x074c 226 #define AFE_ASRC3_CON4 0x0750 227 #define AFE_ASRC3_CON5 0x0754 228 #define AFE_ASRC3_CON6 0x0758 229 #define AFE_ASRC3_CON7 0x075c 230 #define AFE_ASRC3_CON8 0x0760 231 #define AFE_ASRC3_CON9 0x0764 232 #define AFE_ASRC3_CON10 0x0768 233 #define AFE_ASRC3_CON11 0x076c 234 #define AFE_ASRC3_CON12 0x0770 235 #define AFE_ASRC3_CON13 0x0774 236 #define AFE_ASRC3_CON14 0x0778 237 #define AFE_GENERAL_REG0 0x0800 238 #define AFE_GENERAL_REG1 0x0804 239 #define AFE_GENERAL_REG2 0x0808 240 #define AFE_GENERAL_REG3 0x080c 241 #define AFE_GENERAL_REG4 0x0810 242 #define AFE_GENERAL_REG5 0x0814 243 #define AFE_GENERAL_REG6 0x0818 244 #define AFE_GENERAL_REG7 0x081c 245 #define AFE_GENERAL_REG8 0x0820 246 #define AFE_GENERAL_REG9 0x0824 247 #define AFE_GENERAL_REG10 0x0828 248 #define AFE_GENERAL_REG11 0x082c 249 #define AFE_GENERAL_REG12 0x0830 250 #define AFE_GENERAL_REG13 0x0834 251 #define AFE_GENERAL_REG14 0x0838 252 #define AFE_GENERAL_REG15 0x083c 253 #define AFE_CBIP_CFG0 0x0840 254 #define AFE_CBIP_MON0 0x0844 255 #define AFE_CBIP_SLV_MUX_MON0 0x0848 256 #define AFE_CBIP_SLV_DECODER_MON0 0x084c 257 258 #define AFE_MAX_REGISTER AFE_CBIP_SLV_DECODER_ 259 #define AFE_IRQ_STATUS_BITS 0x5f 260 261 /* AUDIO_TOP_CON0 */ 262 #define AHB_IDLE_EN_INT_SFT 263 #define AHB_IDLE_EN_INT_MASK 264 #define AHB_IDLE_EN_INT_MASK_SFT 265 #define AHB_IDLE_EN_EXT_SFT 266 #define AHB_IDLE_EN_EXT_MASK 267 #define AHB_IDLE_EN_EXT_MASK_SFT 268 #define PDN_TML_SFT 269 #define PDN_TML_MASK 270 #define PDN_TML_MASK_SFT 271 #define PDN_DAC_PREDIS_SFT 272 #define PDN_DAC_PREDIS_MASK 273 #define PDN_DAC_PREDIS_MASK_SFT 274 #define PDN_DAC_SFT 275 #define PDN_DAC_MASK 276 #define PDN_DAC_MASK_SFT 277 #define PDN_ADC_SFT 278 #define PDN_ADC_MASK 279 #define PDN_ADC_MASK_SFT 280 #define PDN_TDM_CK_SFT 281 #define PDN_TDM_CK_MASK 282 #define PDN_TDM_CK_MASK_SFT 283 #define PDN_APLL_TUNER_SFT 284 #define PDN_APLL_TUNER_MASK 285 #define PDN_APLL_TUNER_MASK_SFT 286 #define PDN_APLL2_TUNER_SFT 287 #define PDN_APLL2_TUNER_MASK 288 #define PDN_APLL2_TUNER_MASK_SFT 289 #define APB3_SEL_SFT 290 #define APB3_SEL_MASK 291 #define APB3_SEL_MASK_SFT 292 #define APB_R2T_SFT 293 #define APB_R2T_MASK 294 #define APB_R2T_MASK_SFT 295 #define APB_W2T_SFT 296 #define APB_W2T_MASK 297 #define APB_W2T_MASK_SFT 298 #define PDN_24M_SFT 299 #define PDN_24M_MASK 300 #define PDN_24M_MASK_SFT 301 #define PDN_22M_SFT 302 #define PDN_22M_MASK 303 #define PDN_22M_MASK_SFT 304 #define PDN_ADDA4_ADC_SFT 305 #define PDN_ADDA4_ADC_MASK 306 #define PDN_ADDA4_ADC_MASK_SFT 307 #define PDN_I2S_SFT 308 #define PDN_I2S_MASK 309 #define PDN_I2S_MASK_SFT 310 #define PDN_AFE_SFT 311 #define PDN_AFE_MASK 312 #define PDN_AFE_MASK_SFT 313 314 /* AUDIO_TOP_CON1 */ 315 #define PDN_ADC_HIRES_TML_SFT 316 #define PDN_ADC_HIRES_TML_MASK 317 #define PDN_ADC_HIRES_TML_MASK_SFT 318 #define PDN_ADC_HIRES_SFT 319 #define PDN_ADC_HIRES_MASK 320 #define PDN_ADC_HIRES_MASK_SFT 321 #define I2S4_BCLK_SW_CG_SFT 322 #define I2S4_BCLK_SW_CG_MASK 323 #define I2S4_BCLK_SW_CG_MASK_SFT 324 #define I2S3_BCLK_SW_CG_SFT 325 #define I2S3_BCLK_SW_CG_MASK 326 #define I2S3_BCLK_SW_CG_MASK_SFT 327 #define I2S2_BCLK_SW_CG_SFT 328 #define I2S2_BCLK_SW_CG_MASK 329 #define I2S2_BCLK_SW_CG_MASK_SFT 330 #define I2S1_BCLK_SW_CG_SFT 331 #define I2S1_BCLK_SW_CG_MASK 332 #define I2S1_BCLK_SW_CG_MASK_SFT 333 #define I2S_SOFT_RST2_SFT 334 #define I2S_SOFT_RST2_MASK 335 #define I2S_SOFT_RST2_MASK_SFT 336 #define I2S_SOFT_RST_SFT 337 #define I2S_SOFT_RST_MASK 338 #define I2S_SOFT_RST_MASK_SFT 339 340 /* AFE_DAC_CON0 */ 341 #define AFE_AWB_RETM_SFT 342 #define AFE_AWB_RETM_MASK 343 #define AFE_AWB_RETM_MASK_SFT 344 #define AFE_DL1_DATA2_RETM_SFT 345 #define AFE_DL1_DATA2_RETM_MASK 346 #define AFE_DL1_DATA2_RETM_MASK_SFT 347 #define AFE_DL2_RETM_SFT 348 #define AFE_DL2_RETM_MASK 349 #define AFE_DL2_RETM_MASK_SFT 350 #define AFE_DL1_RETM_SFT 351 #define AFE_DL1_RETM_MASK 352 #define AFE_DL1_RETM_MASK_SFT 353 #define AFE_ON_RETM_SFT 354 #define AFE_ON_RETM_MASK 355 #define AFE_ON_RETM_MASK_SFT 356 #define MOD_DAI_DUP_WR_SFT 357 #define MOD_DAI_DUP_WR_MASK 358 #define MOD_DAI_DUP_WR_MASK_SFT 359 #define DAI_MODE_SFT 360 #define DAI_MODE_MASK 361 #define DAI_MODE_MASK_SFT 362 #define VUL_DATA2_MODE_SFT 363 #define VUL_DATA2_MODE_MASK 364 #define VUL_DATA2_MODE_MASK_SFT 365 #define DL1_DATA2_MODE_SFT 366 #define DL1_DATA2_MODE_MASK 367 #define DL1_DATA2_MODE_MASK_SFT 368 #define DL3_MODE_SFT 369 #define DL3_MODE_MASK 370 #define DL3_MODE_MASK_SFT 371 #define VUL_DATA2_R_MONO_SFT 372 #define VUL_DATA2_R_MONO_MASK 373 #define VUL_DATA2_R_MONO_MASK_SFT 374 #define VUL_DATA2_DATA_SFT 375 #define VUL_DATA2_DATA_MASK 376 #define VUL_DATA2_DATA_MASK_SFT 377 #define VUL_DATA2_ON_SFT 378 #define VUL_DATA2_ON_MASK 379 #define VUL_DATA2_ON_MASK_SFT 380 #define DL1_DATA2_ON_SFT 381 #define DL1_DATA2_ON_MASK 382 #define DL1_DATA2_ON_MASK_SFT 383 #define MOD_DAI_ON_SFT 384 #define MOD_DAI_ON_MASK 385 #define MOD_DAI_ON_MASK_SFT 386 #define AWB_ON_SFT 387 #define AWB_ON_MASK 388 #define AWB_ON_MASK_SFT 389 #define DL3_ON_SFT 390 #define DL3_ON_MASK 391 #define DL3_ON_MASK_SFT 392 #define DAI_ON_SFT 393 #define DAI_ON_MASK 394 #define DAI_ON_MASK_SFT 395 #define VUL_ON_SFT 396 #define VUL_ON_MASK 397 #define VUL_ON_MASK_SFT 398 #define DL2_ON_SFT 399 #define DL2_ON_MASK 400 #define DL2_ON_MASK_SFT 401 #define DL1_ON_SFT 402 #define DL1_ON_MASK 403 #define DL1_ON_MASK_SFT 404 #define AFE_ON_SFT 405 #define AFE_ON_MASK 406 #define AFE_ON_MASK_SFT 407 408 /* AFE_DAC_CON1 */ 409 #define MOD_DAI_MODE_SFT 410 #define MOD_DAI_MODE_MASK 411 #define MOD_DAI_MODE_MASK_SFT 412 #define DAI_DUP_WR_SFT 413 #define DAI_DUP_WR_MASK 414 #define DAI_DUP_WR_MASK_SFT 415 #define VUL_R_MONO_SFT 416 #define VUL_R_MONO_MASK 417 #define VUL_R_MONO_MASK_SFT 418 #define VUL_DATA_SFT 419 #define VUL_DATA_MASK 420 #define VUL_DATA_MASK_SFT 421 #define AXI_2X1_CG_DISABLE_SFT 422 #define AXI_2X1_CG_DISABLE_MASK 423 #define AXI_2X1_CG_DISABLE_MASK_SFT 424 #define AWB_R_MONO_SFT 425 #define AWB_R_MONO_MASK 426 #define AWB_R_MONO_MASK_SFT 427 #define AWB_DATA_SFT 428 #define AWB_DATA_MASK 429 #define AWB_DATA_MASK_SFT 430 #define DL3_DATA_SFT 431 #define DL3_DATA_MASK 432 #define DL3_DATA_MASK_SFT 433 #define DL2_DATA_SFT 434 #define DL2_DATA_MASK 435 #define DL2_DATA_MASK_SFT 436 #define DL1_DATA_SFT 437 #define DL1_DATA_MASK 438 #define DL1_DATA_MASK_SFT 439 #define DL1_DATA2_DATA_SFT 440 #define DL1_DATA2_DATA_MASK 441 #define DL1_DATA2_DATA_MASK_SFT 442 #define VUL_MODE_SFT 443 #define VUL_MODE_MASK 444 #define VUL_MODE_MASK_SFT 445 #define AWB_MODE_SFT 446 #define AWB_MODE_MASK 447 #define AWB_MODE_MASK_SFT 448 #define I2S_MODE_SFT 449 #define I2S_MODE_MASK 450 #define I2S_MODE_MASK_SFT 451 #define DL2_MODE_SFT 452 #define DL2_MODE_MASK 453 #define DL2_MODE_MASK_SFT 454 #define DL1_MODE_SFT 455 #define DL1_MODE_MASK 456 #define DL1_MODE_MASK_SFT 457 458 /* AFE_ADDA_DL_SRC2_CON0 */ 459 #define DL_2_INPUT_MODE_CTL_SFT 460 #define DL_2_INPUT_MODE_CTL_MASK 461 #define DL_2_INPUT_MODE_CTL_MASK_SFT 462 #define DL_2_CH1_SATURATION_EN_CTL_SFT 463 #define DL_2_CH1_SATURATION_EN_CTL_MASK 464 #define DL_2_CH1_SATURATION_EN_CTL_MASK_SFT 465 #define DL_2_CH2_SATURATION_EN_CTL_SFT 466 #define DL_2_CH2_SATURATION_EN_CTL_MASK 467 #define DL_2_CH2_SATURATION_EN_CTL_MASK_SFT 468 #define DL_2_OUTPUT_SEL_CTL_SFT 469 #define DL_2_OUTPUT_SEL_CTL_MASK 470 #define DL_2_OUTPUT_SEL_CTL_MASK_SFT 471 #define DL_2_FADEIN_0START_EN_SFT 472 #define DL_2_FADEIN_0START_EN_MASK 473 #define DL_2_FADEIN_0START_EN_MASK_SFT 474 #define DL_DISABLE_HW_CG_CTL_SFT 475 #define DL_DISABLE_HW_CG_CTL_MASK 476 #define DL_DISABLE_HW_CG_CTL_MASK_SFT 477 #define C_DATA_EN_SEL_CTL_PRE_SFT 478 #define C_DATA_EN_SEL_CTL_PRE_MASK 479 #define C_DATA_EN_SEL_CTL_PRE_MASK_SFT 480 #define DL_2_SIDE_TONE_ON_CTL_PRE_SFT 481 #define DL_2_SIDE_TONE_ON_CTL_PRE_MASK 482 #define DL_2_SIDE_TONE_ON_CTL_PRE_MASK_SFT 483 #define DL_2_MUTE_CH1_OFF_CTL_PRE_SFT 484 #define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK 485 #define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK_SFT 486 #define DL_2_MUTE_CH2_OFF_CTL_PRE_SFT 487 #define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK 488 #define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK_SFT 489 #define DL2_ARAMPSP_CTL_PRE_SFT 490 #define DL2_ARAMPSP_CTL_PRE_MASK 491 #define DL2_ARAMPSP_CTL_PRE_MASK_SFT 492 #define DL_2_IIRMODE_CTL_PRE_SFT 493 #define DL_2_IIRMODE_CTL_PRE_MASK 494 #define DL_2_IIRMODE_CTL_PRE_MASK_SFT 495 #define DL_2_VOICE_MODE_CTL_PRE_SFT 496 #define DL_2_VOICE_MODE_CTL_PRE_MASK 497 #define DL_2_VOICE_MODE_CTL_PRE_MASK_SFT 498 #define D2_2_MUTE_CH1_ON_CTL_PRE_SFT 499 #define D2_2_MUTE_CH1_ON_CTL_PRE_MASK 500 #define D2_2_MUTE_CH1_ON_CTL_PRE_MASK_SFT 501 #define D2_2_MUTE_CH2_ON_CTL_PRE_SFT 502 #define D2_2_MUTE_CH2_ON_CTL_PRE_MASK 503 #define D2_2_MUTE_CH2_ON_CTL_PRE_MASK_SFT 504 #define DL_2_IIR_ON_CTL_PRE_SFT 505 #define DL_2_IIR_ON_CTL_PRE_MASK 506 #define DL_2_IIR_ON_CTL_PRE_MASK_SFT 507 #define DL_2_GAIN_ON_CTL_PRE_SFT 508 #define DL_2_GAIN_ON_CTL_PRE_MASK 509 #define DL_2_GAIN_ON_CTL_PRE_MASK_SFT 510 #define DL_2_SRC_ON_TMP_CTL_PRE_SFT 511 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK 512 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT 513 514 /* AFE_ADDA_DL_SRC2_CON1 */ 515 #define DL_2_GAIN_CTL_PRE_SFT 516 #define DL_2_GAIN_CTL_PRE_MASK 517 #define DL_2_GAIN_CTL_PRE_MASK_SFT 518 #define DL_2_GAIN_MODE_CTL_SFT 519 #define DL_2_GAIN_MODE_CTL_MASK 520 #define DL_2_GAIN_MODE_CTL_MASK_SFT 521 522 /* AFE_ADDA_UL_SRC_CON0 */ 523 #define C_COMB_OUT_SIN_GEN_CTL_SFT 524 #define C_COMB_OUT_SIN_GEN_CTL_MASK 525 #define C_COMB_OUT_SIN_GEN_CTL_MASK_SFT 526 #define C_BASEBAND_SIN_GEN_CTL_SFT 527 #define C_BASEBAND_SIN_GEN_CTL_MASK 528 #define C_BASEBAND_SIN_GEN_CTL_MASK_SFT 529 #define C_DIGMIC_PHASE_SEL_CH1_CTL_SFT 530 #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK 531 #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK_SFT 532 #define C_DIGMIC_PHASE_SEL_CH2_CTL_SFT 533 #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK 534 #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK_SFT 535 #define C_TWO_DIGITAL_MIC_CTL_SFT 536 #define C_TWO_DIGITAL_MIC_CTL_MASK 537 #define C_TWO_DIGITAL_MIC_CTL_MASK_SFT 538 #define UL_MODE_3P25M_CH2_CTL_SFT 539 #define UL_MODE_3P25M_CH2_CTL_MASK 540 #define UL_MODE_3P25M_CH2_CTL_MASK_SFT 541 #define UL_MODE_3P25M_CH1_CTL_SFT 542 #define UL_MODE_3P25M_CH1_CTL_MASK 543 #define UL_MODE_3P25M_CH1_CTL_MASK_SFT 544 #define UL_SRC_USE_CIC_OUT_CTL_SFT 545 #define UL_SRC_USE_CIC_OUT_CTL_MASK 546 #define UL_SRC_USE_CIC_OUT_CTL_MASK_SFT 547 #define UL_VOICE_MODE_CH1_CH2_CTL_SFT 548 #define UL_VOICE_MODE_CH1_CH2_CTL_MASK 549 #define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT 550 #define DMIC_LOW_POWER_MODE_CTL_SFT 551 #define DMIC_LOW_POWER_MODE_CTL_MASK 552 #define DMIC_LOW_POWER_MODE_CTL_MASK_SFT 553 #define DMIC_48K_SEL_CTL_SFT 554 #define DMIC_48K_SEL_CTL_MASK 555 #define DMIC_48K_SEL_CTL_MASK_SFT 556 #define UL_DISABLE_HW_CG_CTL_SFT 557 #define UL_DISABLE_HW_CG_CTL_MASK 558 #define UL_DISABLE_HW_CG_CTL_MASK_SFT 559 #define UL_IIR_ON_TMP_CTL_SFT 560 #define UL_IIR_ON_TMP_CTL_MASK 561 #define UL_IIR_ON_TMP_CTL_MASK_SFT 562 #define UL_IIRMODE_CTL_SFT 563 #define UL_IIRMODE_CTL_MASK 564 #define UL_IIRMODE_CTL_MASK_SFT 565 #define DIGMIC_3P25M_1P625M_SEL_CTL_SFT 566 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 567 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT 568 #define AGC_260K_SEL_CH2_CTL_SFT 569 #define AGC_260K_SEL_CH2_CTL_MASK 570 #define AGC_260K_SEL_CH2_CTL_MASK_SFT 571 #define AGC_260K_SEL_CH1_CTL_SFT 572 #define AGC_260K_SEL_CH1_CTL_MASK 573 #define AGC_260K_SEL_CH1_CTL_MASK_SFT 574 #define UL_LOOP_BACK_MODE_CTL_SFT 575 #define UL_LOOP_BACK_MODE_CTL_MASK 576 #define UL_LOOP_BACK_MODE_CTL_MASK_SFT 577 #define UL_SDM_3_LEVEL_CTL_SFT 578 #define UL_SDM_3_LEVEL_CTL_MASK 579 #define UL_SDM_3_LEVEL_CTL_MASK_SFT 580 #define UL_SRC_ON_TMP_CTL_SFT 581 #define UL_SRC_ON_TMP_CTL_MASK 582 #define UL_SRC_ON_TMP_CTL_MASK_SFT 583 584 /* AFE_ADDA_UL_SRC_CON1 */ 585 #define C_SDM_RESET_CTL_SFT 586 #define C_SDM_RESET_CTL_MASK 587 #define C_SDM_RESET_CTL_MASK_SFT 588 #define ADITHON_CTL_SFT 589 #define ADITHON_CTL_MASK 590 #define ADITHON_CTL_MASK_SFT 591 #define ADITHVAL_CTL_SFT 592 #define ADITHVAL_CTL_MASK 593 #define ADITHVAL_CTL_MASK_SFT 594 #define C_DAC_EN_CTL_SFT 595 #define C_DAC_EN_CTL_MASK 596 #define C_DAC_EN_CTL_MASK_SFT 597 #define C_MUTE_SW_CTL_SFT 598 #define C_MUTE_SW_CTL_MASK 599 #define C_MUTE_SW_CTL_MASK_SFT 600 #define ASDM_SRC_SEL_CTL_SFT 601 #define ASDM_SRC_SEL_CTL_MASK 602 #define ASDM_SRC_SEL_CTL_MASK_SFT 603 #define C_AMP_DIV_CH2_CTL_SFT 604 #define C_AMP_DIV_CH2_CTL_MASK 605 #define C_AMP_DIV_CH2_CTL_MASK_SFT 606 #define C_FREQ_DIV_CH2_CTL_SFT 607 #define C_FREQ_DIV_CH2_CTL_MASK 608 #define C_FREQ_DIV_CH2_CTL_MASK_SFT 609 #define C_SINE_MODE_CH2_CTL_SFT 610 #define C_SINE_MODE_CH2_CTL_MASK 611 #define C_SINE_MODE_CH2_CTL_MASK_SFT 612 #define C_AMP_DIV_CH1_CTL_SFT 613 #define C_AMP_DIV_CH1_CTL_MASK 614 #define C_AMP_DIV_CH1_CTL_MASK_SFT 615 #define C_FREQ_DIV_CH1_CTL_SFT 616 #define C_FREQ_DIV_CH1_CTL_MASK 617 #define C_FREQ_DIV_CH1_CTL_MASK_SFT 618 #define C_SINE_MODE_CH1_CTL_SFT 619 #define C_SINE_MODE_CH1_CTL_MASK 620 #define C_SINE_MODE_CH1_CTL_MASK_SFT 621 622 /* AFE_ADDA_TOP_CON0 */ 623 #define C_LOOP_BACK_MODE_CTL_SFT 624 #define C_LOOP_BACK_MODE_CTL_MASK 625 #define C_LOOP_BACK_MODE_CTL_MASK_SFT 626 #define C_EXT_ADC_CTL_SFT 627 #define C_EXT_ADC_CTL_MASK 628 #define C_EXT_ADC_CTL_MASK_SFT 629 630 /* AFE_ADDA_UL_DL_CON0 */ 631 #define AFE_UL_DL_CON0_RESERVED_SFT 632 #define AFE_UL_DL_CON0_RESERVED_MASK 633 #define AFE_UL_DL_CON0_RESERVED_MASK_SFT 634 #define ADDA_AFE_ON_SFT 635 #define ADDA_AFE_ON_MASK 636 #define ADDA_AFE_ON_MASK_SFT 637 638 /* AFE_IRQ_MCU_CON */ 639 #define IRQ7_MCU_MODE_SFT 640 #define IRQ7_MCU_MODE_MASK 641 #define IRQ7_MCU_MODE_MASK_SFT 642 #define IRQ4_MCU_MODE_SFT 643 #define IRQ4_MCU_MODE_MASK 644 #define IRQ4_MCU_MODE_MASK_SFT 645 #define IRQ3_MCU_MODE_SFT 646 #define IRQ3_MCU_MODE_MASK 647 #define IRQ3_MCU_MODE_MASK_SFT 648 #define IRQ7_MCU_ON_SFT 649 #define IRQ7_MCU_ON_MASK 650 #define IRQ7_MCU_ON_MASK_SFT 651 #define IRQ5_MCU_ON_SFT 652 #define IRQ5_MCU_ON_MASK 653 #define IRQ5_MCU_ON_MASK_SFT 654 #define IRQ2_MCU_MODE_SFT 655 #define IRQ2_MCU_MODE_MASK 656 #define IRQ2_MCU_MODE_MASK_SFT 657 #define IRQ1_MCU_MODE_SFT 658 #define IRQ1_MCU_MODE_MASK 659 #define IRQ1_MCU_MODE_MASK_SFT 660 #define IRQ4_MCU_ON_SFT 661 #define IRQ4_MCU_ON_MASK 662 #define IRQ4_MCU_ON_MASK_SFT 663 #define IRQ3_MCU_ON_SFT 664 #define IRQ3_MCU_ON_MASK 665 #define IRQ3_MCU_ON_MASK_SFT 666 #define IRQ2_MCU_ON_SFT 667 #define IRQ2_MCU_ON_MASK 668 #define IRQ2_MCU_ON_MASK_SFT 669 #define IRQ1_MCU_ON_SFT 670 #define IRQ1_MCU_ON_MASK 671 #define IRQ1_MCU_ON_MASK_SFT 672 673 /* AFE_IRQ_MCU_EN */ 674 #define AFE_IRQ_CM4_EN_SFT 675 #define AFE_IRQ_CM4_EN_MASK 676 #define AFE_IRQ_CM4_EN_MASK_SFT 677 #define AFE_IRQ_MD32_EN_SFT 678 #define AFE_IRQ_MD32_EN_MASK 679 #define AFE_IRQ_MD32_EN_MASK_SFT 680 #define AFE_IRQ_MCU_EN_SFT 681 #define AFE_IRQ_MCU_EN_MASK 682 #define AFE_IRQ_MCU_EN_MASK_SFT 683 684 /* AFE_IRQ_MCU_CLR */ 685 #define IRQ7_MCU_CLR_SFT 686 #define IRQ7_MCU_CLR_MASK 687 #define IRQ7_MCU_CLR_MASK_SFT 688 #define IRQ5_MCU_CLR_SFT 689 #define IRQ5_MCU_CLR_MASK 690 #define IRQ5_MCU_CLR_MASK_SFT 691 #define IRQ4_MCU_CLR_SFT 692 #define IRQ4_MCU_CLR_MASK 693 #define IRQ4_MCU_CLR_MASK_SFT 694 #define IRQ3_MCU_CLR_SFT 695 #define IRQ3_MCU_CLR_MASK 696 #define IRQ3_MCU_CLR_MASK_SFT 697 #define IRQ2_MCU_CLR_SFT 698 #define IRQ2_MCU_CLR_MASK 699 #define IRQ2_MCU_CLR_MASK_SFT 700 #define IRQ1_MCU_CLR_SFT 701 #define IRQ1_MCU_CLR_MASK 702 #define IRQ1_MCU_CLR_MASK_SFT 703 704 /* AFE_IRQ_MCU_CNT1 */ 705 #define AFE_IRQ_MCU_CNT1_SFT 706 #define AFE_IRQ_MCU_CNT1_MASK 707 #define AFE_IRQ_MCU_CNT1_MASK_SFT 708 709 /* AFE_IRQ_MCU_CNT2 */ 710 #define AFE_IRQ_MCU_CNT2_SFT 711 #define AFE_IRQ_MCU_CNT2_MASK 712 #define AFE_IRQ_MCU_CNT2_MASK_SFT 713 714 /* AFE_IRQ_MCU_CNT3 */ 715 #define AFE_IRQ_MCU_CNT3_SFT 716 #define AFE_IRQ_MCU_CNT3_MASK 717 #define AFE_IRQ_MCU_CNT3_MASK_SFT 718 719 /* AFE_IRQ_MCU_CNT4 */ 720 #define AFE_IRQ_MCU_CNT4_SFT 721 #define AFE_IRQ_MCU_CNT4_MASK 722 #define AFE_IRQ_MCU_CNT4_MASK_SFT 723 724 /* AFE_IRQ_MCU_CNT5 */ 725 #define AFE_IRQ_MCU_CNT5_SFT 726 #define AFE_IRQ_MCU_CNT5_MASK 727 #define AFE_IRQ_MCU_CNT5_MASK_SFT 728 729 /* AFE_IRQ_MCU_CNT7 */ 730 #define AFE_IRQ_MCU_CNT7_SFT 731 #define AFE_IRQ_MCU_CNT7_MASK 732 #define AFE_IRQ_MCU_CNT7_MASK_SFT 733 734 /* AFE_MEMIF_MSB */ 735 #define CPU_COMPACT_MODE_SFT 736 #define CPU_COMPACT_MODE_MASK 737 #define CPU_COMPACT_MODE_MASK_SFT 738 #define CPU_HD_ALIGN_SFT 739 #define CPU_HD_ALIGN_MASK 740 #define CPU_HD_ALIGN_MASK_SFT 741 742 /* AFE_MEMIF_HD_MODE */ 743 #define HDMI_HD_SFT 744 #define HDMI_HD_MASK 745 #define HDMI_HD_MASK_SFT 746 #define MOD_DAI_HD_SFT 747 #define MOD_DAI_HD_MASK 748 #define MOD_DAI_HD_MASK_SFT 749 #define DAI_HD_SFT 750 #define DAI_HD_MASK 751 #define DAI_HD_MASK_SFT 752 #define VUL_DATA2_HD_SFT 753 #define VUL_DATA2_HD_MASK 754 #define VUL_DATA2_HD_MASK_SFT 755 #define VUL_HD_SFT 756 #define VUL_HD_MASK 757 #define VUL_HD_MASK_SFT 758 #define AWB_HD_SFT 759 #define AWB_HD_MASK 760 #define AWB_HD_MASK_SFT 761 #define DL3_HD_SFT 762 #define DL3_HD_MASK 763 #define DL3_HD_MASK_SFT 764 #define DL2_HD_SFT 765 #define DL2_HD_MASK 766 #define DL2_HD_MASK_SFT 767 #define DL1_DATA2_HD_SFT 768 #define DL1_DATA2_HD_MASK 769 #define DL1_DATA2_HD_MASK_SFT 770 #define DL1_HD_SFT 771 #define DL1_HD_MASK 772 #define DL1_HD_MASK_SFT 773 774 /* AFE_MEMIF_HDALIGN */ 775 #define HDMI_NORMAL_MODE_SFT 776 #define HDMI_NORMAL_MODE_MASK 777 #define HDMI_NORMAL_MODE_MASK_SFT 778 #define MOD_DAI_NORMAL_MODE_SFT 779 #define MOD_DAI_NORMAL_MODE_MASK 780 #define MOD_DAI_NORMAL_MODE_MASK_SFT 781 #define DAI_NORMAL_MODE_SFT 782 #define DAI_NORMAL_MODE_MASK 783 #define DAI_NORMAL_MODE_MASK_SFT 784 #define VUL_DATA2_NORMAL_MODE_SFT 785 #define VUL_DATA2_NORMAL_MODE_MASK 786 #define VUL_DATA2_NORMAL_MODE_MASK_SFT 787 #define VUL_NORMAL_MODE_SFT 788 #define VUL_NORMAL_MODE_MASK 789 #define VUL_NORMAL_MODE_MASK_SFT 790 #define AWB_NORMAL_MODE_SFT 791 #define AWB_NORMAL_MODE_MASK 792 #define AWB_NORMAL_MODE_MASK_SFT 793 #define DL3_NORMAL_MODE_SFT 794 #define DL3_NORMAL_MODE_MASK 795 #define DL3_NORMAL_MODE_MASK_SFT 796 #define DL2_NORMAL_MODE_SFT 797 #define DL2_NORMAL_MODE_MASK 798 #define DL2_NORMAL_MODE_MASK_SFT 799 #define DL1_DATA2_NORMAL_MODE_SFT 800 #define DL1_DATA2_NORMAL_MODE_MASK 801 #define DL1_DATA2_NORMAL_MODE_MASK_SFT 802 #define DL1_NORMAL_MODE_SFT 803 #define DL1_NORMAL_MODE_MASK 804 #define DL1_NORMAL_MODE_MASK_SFT 805 #define HDMI_HD_ALIGN_SFT 806 #define HDMI_HD_ALIGN_MASK 807 #define HDMI_HD_ALIGN_MASK_SFT 808 #define MOD_DAI_HD_ALIGN_SFT 809 #define MOD_DAI_HD_ALIGN_MASK 810 #define MOD_DAI_HD_ALIGN_MASK_SFT 811 #define DAI_ALIGN_SFT 812 #define DAI_ALIGN_MASK 813 #define DAI_ALIGN_MASK_SFT 814 #define VUL2_HD_ALIGN_SFT 815 #define VUL2_HD_ALIGN_MASK 816 #define VUL2_HD_ALIGN_MASK_SFT 817 #define VUL_DATA2_HD_ALIGN_SFT 818 #define VUL_DATA2_HD_ALIGN_MASK 819 #define VUL_DATA2_HD_ALIGN_MASK_SFT 820 #define VUL_HD_ALIGN_SFT 821 #define VUL_HD_ALIGN_MASK 822 #define VUL_HD_ALIGN_MASK_SFT 823 #define AWB_HD_ALIGN_SFT 824 #define AWB_HD_ALIGN_MASK 825 #define AWB_HD_ALIGN_MASK_SFT 826 #define DL3_HD_ALIGN_SFT 827 #define DL3_HD_ALIGN_MASK 828 #define DL3_HD_ALIGN_MASK_SFT 829 #define DL2_HD_ALIGN_SFT 830 #define DL2_HD_ALIGN_MASK 831 #define DL2_HD_ALIGN_MASK_SFT 832 #define DL1_DATA2_HD_ALIGN_SFT 833 #define DL1_DATA2_HD_ALIGN_MASK 834 #define DL1_DATA2_HD_ALIGN_MASK_SFT 835 #define DL1_HD_ALIGN_SFT 836 #define DL1_HD_ALIGN_MASK 837 #define DL1_HD_ALIGN_MASK_SFT 838 839 /* PCM_INTF_CON1 */ 840 #define PCM_FIX_VALUE_SEL_SFT 841 #define PCM_FIX_VALUE_SEL_MASK 842 #define PCM_FIX_VALUE_SEL_MASK_SFT 843 #define PCM_BUFFER_LOOPBACK_SFT 844 #define PCM_BUFFER_LOOPBACK_MASK 845 #define PCM_BUFFER_LOOPBACK_MASK_SFT 846 #define PCM_PARALLEL_LOOPBACK_SFT 847 #define PCM_PARALLEL_LOOPBACK_MASK 848 #define PCM_PARALLEL_LOOPBACK_MASK_SFT 849 #define PCM_SERIAL_LOOPBACK_SFT 850 #define PCM_SERIAL_LOOPBACK_MASK 851 #define PCM_SERIAL_LOOPBACK_MASK_SFT 852 #define PCM_DAI_PCM_LOOPBACK_SFT 853 #define PCM_DAI_PCM_LOOPBACK_MASK 854 #define PCM_DAI_PCM_LOOPBACK_MASK_SFT 855 #define PCM_I2S_PCM_LOOPBACK_SFT 856 #define PCM_I2S_PCM_LOOPBACK_MASK 857 #define PCM_I2S_PCM_LOOPBACK_MASK_SFT 858 #define PCM_SYNC_DELSEL_SFT 859 #define PCM_SYNC_DELSEL_MASK 860 #define PCM_SYNC_DELSEL_MASK_SFT 861 #define PCM_TX_LR_SWAP_SFT 862 #define PCM_TX_LR_SWAP_MASK 863 #define PCM_TX_LR_SWAP_MASK_SFT 864 #define PCM_SYNC_OUT_INV_SFT 865 #define PCM_SYNC_OUT_INV_MASK 866 #define PCM_SYNC_OUT_INV_MASK_SFT 867 #define PCM_BCLK_OUT_INV_SFT 868 #define PCM_BCLK_OUT_INV_MASK 869 #define PCM_BCLK_OUT_INV_MASK_SFT 870 #define PCM_SYNC_IN_INV_SFT 871 #define PCM_SYNC_IN_INV_MASK 872 #define PCM_SYNC_IN_INV_MASK_SFT 873 #define PCM_BCLK_IN_INV_SFT 874 #define PCM_BCLK_IN_INV_MASK 875 #define PCM_BCLK_IN_INV_MASK_SFT 876 #define PCM_TX_LCH_RPT_SFT 877 #define PCM_TX_LCH_RPT_MASK 878 #define PCM_TX_LCH_RPT_MASK_SFT 879 #define PCM_VBT_16K_MODE_SFT 880 #define PCM_VBT_16K_MODE_MASK 881 #define PCM_VBT_16K_MODE_MASK_SFT 882 #define PCM_EXT_MODEM_SFT 883 #define PCM_EXT_MODEM_MASK 884 #define PCM_EXT_MODEM_MASK_SFT 885 #define PCM_24BIT_SFT 886 #define PCM_24BIT_MASK 887 #define PCM_24BIT_MASK_SFT 888 #define PCM_WLEN_SFT 889 #define PCM_WLEN_MASK 890 #define PCM_WLEN_MASK_SFT 891 #define PCM_SYNC_LENGTH_SFT 892 #define PCM_SYNC_LENGTH_MASK 893 #define PCM_SYNC_LENGTH_MASK_SFT 894 #define PCM_SYNC_TYPE_SFT 895 #define PCM_SYNC_TYPE_MASK 896 #define PCM_SYNC_TYPE_MASK_SFT 897 #define PCM_BT_MODE_SFT 898 #define PCM_BT_MODE_MASK 899 #define PCM_BT_MODE_MASK_SFT 900 #define PCM_BYP_ASRC_SFT 901 #define PCM_BYP_ASRC_MASK 902 #define PCM_BYP_ASRC_MASK_SFT 903 #define PCM_SLAVE_SFT 904 #define PCM_SLAVE_MASK 905 #define PCM_SLAVE_MASK_SFT 906 #define PCM_MODE_SFT 907 #define PCM_MODE_MASK 908 #define PCM_MODE_MASK_SFT 909 #define PCM_FMT_SFT 910 #define PCM_FMT_MASK 911 #define PCM_FMT_MASK_SFT 912 #define PCM_EN_SFT 913 #define PCM_EN_MASK 914 #define PCM_EN_MASK_SFT 915 916 /* PCM_INTF_CON2 */ 917 #define PCM1_TX_FIFO_OV_SFT 918 #define PCM1_TX_FIFO_OV_MASK 919 #define PCM1_TX_FIFO_OV_MASK_SFT 920 #define PCM1_RX_FIFO_OV_SFT 921 #define PCM1_RX_FIFO_OV_MASK 922 #define PCM1_RX_FIFO_OV_MASK_SFT 923 #define PCM2_TX_FIFO_OV_SFT 924 #define PCM2_TX_FIFO_OV_MASK 925 #define PCM2_TX_FIFO_OV_MASK_SFT 926 #define PCM2_RX_FIFO_OV_SFT 927 #define PCM2_RX_FIFO_OV_MASK 928 #define PCM2_RX_FIFO_OV_MASK_SFT 929 #define PCM1_SYNC_GLITCH_SFT 930 #define PCM1_SYNC_GLITCH_MASK 931 #define PCM1_SYNC_GLITCH_MASK_SFT 932 #define PCM2_SYNC_GLITCH_SFT 933 #define PCM2_SYNC_GLITCH_MASK 934 #define PCM2_SYNC_GLITCH_MASK_SFT 935 #define PCM1_PCM2_LOOPBACK_SFT 936 #define PCM1_PCM2_LOOPBACK_MASK 937 #define PCM1_PCM2_LOOPBACK_MASK_SFT 938 #define DAI_PCM_LOOPBACK_CH_SFT 939 #define DAI_PCM_LOOPBACK_CH_MASK 940 #define DAI_PCM_LOOPBACK_CH_MASK_SFT 941 #define I2S_PCM_LOOPBACK_CH_SFT 942 #define I2S_PCM_LOOPBACK_CH_MASK 943 #define I2S_PCM_LOOPBACK_CH_MASK_SFT 944 #define PCM_USE_MD3_SFT 945 #define PCM_USE_MD3_MASK 946 #define PCM_USE_MD3_MASK_SFT 947 #define TX_FIX_VALUE_SFT 948 #define TX_FIX_VALUE_MASK 949 #define TX_FIX_VALUE_MASK_SFT 950 951 /* PCM2_INTF_CON */ 952 #define PCM2_TX_FIX_VALUE_SFT 953 #define PCM2_TX_FIX_VALUE_MASK 954 #define PCM2_TX_FIX_VALUE_MASK_SFT 955 #define PCM2_FIX_VALUE_SEL_SFT 956 #define PCM2_FIX_VALUE_SEL_MASK 957 #define PCM2_FIX_VALUE_SEL_MASK_SFT 958 #define PCM2_BUFFER_LOOPBACK_SFT 959 #define PCM2_BUFFER_LOOPBACK_MASK 960 #define PCM2_BUFFER_LOOPBACK_MASK_SFT 961 #define PCM2_PARALLEL_LOOPBACK_SFT 962 #define PCM2_PARALLEL_LOOPBACK_MASK 963 #define PCM2_PARALLEL_LOOPBACK_MASK_SFT 964 #define PCM2_SERIAL_LOOPBACK_SFT 965 #define PCM2_SERIAL_LOOPBACK_MASK 966 #define PCM2_SERIAL_LOOPBACK_MASK_SFT 967 #define PCM2_DAI_PCM_LOOPBACK_SFT 968 #define PCM2_DAI_PCM_LOOPBACK_MASK 969 #define PCM2_DAI_PCM_LOOPBACK_MASK_SFT 970 #define PCM2_I2S_PCM_LOOPBACK_SFT 971 #define PCM2_I2S_PCM_LOOPBACK_MASK 972 #define PCM2_I2S_PCM_LOOPBACK_MASK_SFT 973 #define PCM2_SYNC_DELSEL_SFT 974 #define PCM2_SYNC_DELSEL_MASK 975 #define PCM2_SYNC_DELSEL_MASK_SFT 976 #define PCM2_TX_LR_SWAP_SFT 977 #define PCM2_TX_LR_SWAP_MASK 978 #define PCM2_TX_LR_SWAP_MASK_SFT 979 #define PCM2_SYNC_IN_INV_SFT 980 #define PCM2_SYNC_IN_INV_MASK 981 #define PCM2_SYNC_IN_INV_MASK_SFT 982 #define PCM2_BCLK_IN_INV_SFT 983 #define PCM2_BCLK_IN_INV_MASK 984 #define PCM2_BCLK_IN_INV_MASK_SFT 985 #define PCM2_TX_LCH_RPT_SFT 986 #define PCM2_TX_LCH_RPT_MASK 987 #define PCM2_TX_LCH_RPT_MASK_SFT 988 #define PCM2_VBT_16K_MODE_SFT 989 #define PCM2_VBT_16K_MODE_MASK 990 #define PCM2_VBT_16K_MODE_MASK_SFT 991 #define PCM2_LOOPBACK_CH_SEL_SFT 992 #define PCM2_LOOPBACK_CH_SEL_MASK 993 #define PCM2_LOOPBACK_CH_SEL_MASK_SFT 994 #define PCM2_TX2_BT_MODE_SFT 995 #define PCM2_TX2_BT_MODE_MASK 996 #define PCM2_TX2_BT_MODE_MASK_SFT 997 #define PCM2_BT_MODE_SFT 998 #define PCM2_BT_MODE_MASK 999 #define PCM2_BT_MODE_MASK_SFT 1000 #define PCM2_AFIFO_SFT 1001 #define PCM2_AFIFO_MASK 1002 #define PCM2_AFIFO_MASK_SFT 1003 #define PCM2_WLEN_SFT 1004 #define PCM2_WLEN_MASK 1005 #define PCM2_WLEN_MASK_SFT 1006 #define PCM2_MODE_SFT 1007 #define PCM2_MODE_MASK 1008 #define PCM2_MODE_MASK_SFT 1009 #define PCM2_FMT_SFT 1010 #define PCM2_FMT_MASK 1011 #define PCM2_FMT_MASK_SFT 1012 #define PCM2_EN_SFT 1013 #define PCM2_EN_MASK 1014 #define PCM2_EN_MASK_SFT 1015 #endif 1016
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.