1 /* SPDX-License-Identifier: GPL-2.0-only */ <<
2 /* 1 /*
3 * Copyright (c) 2010-2011,2013-2015 The Linux 2 * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
>> 3 *
>> 4 * This program is free software; you can redistribute it and/or modify
>> 5 * it under the terms of the GNU General Public License version 2 and
>> 6 * only version 2 as published by the Free Software Foundation.
>> 7 *
>> 8 * This program is distributed in the hope that it will be useful,
>> 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 11 * GNU General Public License for more details.
4 */ 12 */
5 13
6 #ifndef __LPASS_LPAIF_REG_H__ 14 #ifndef __LPASS_LPAIF_REG_H__
7 #define __LPASS_LPAIF_REG_H__ 15 #define __LPASS_LPAIF_REG_H__
8 16
9 /* LPAIF I2S */ 17 /* LPAIF I2S */
10 18
11 #define LPAIF_I2SCTL_REG_ADDR(v, addr, port) \ 19 #define LPAIF_I2SCTL_REG_ADDR(v, addr, port) \
12 (v->i2sctrl_reg_base + (addr) + v->i2s 20 (v->i2sctrl_reg_base + (addr) + v->i2sctrl_reg_stride * (port))
13 21
14 #define LPAIF_I2SCTL_REG(v, port) LPAIF_ 22 #define LPAIF_I2SCTL_REG(v, port) LPAIF_I2SCTL_REG_ADDR(v, 0x0, (port))
15 !! 23 #define LPAIF_I2SCTL_LOOPBACK_MASK 0x8000
16 #define LPAIF_I2SCTL_LOOPBACK_DISABLE 0 !! 24 #define LPAIF_I2SCTL_LOOPBACK_SHIFT 15
17 #define LPAIF_I2SCTL_LOOPBACK_ENABLE 1 !! 25 #define LPAIF_I2SCTL_LOOPBACK_DISABLE (0 << LPAIF_I2SCTL_LOOPBACK_SHIFT)
18 !! 26 #define LPAIF_I2SCTL_LOOPBACK_ENABLE (1 << LPAIF_I2SCTL_LOOPBACK_SHIFT)
19 #define LPAIF_I2SCTL_SPKEN_DISABLE 0 !! 27
20 #define LPAIF_I2SCTL_SPKEN_ENABLE 1 !! 28 #define LPAIF_I2SCTL_SPKEN_MASK 0x4000
21 !! 29 #define LPAIF_I2SCTL_SPKEN_SHIFT 14
22 #define LPAIF_I2SCTL_MODE_NONE 0 !! 30 #define LPAIF_I2SCTL_SPKEN_DISABLE (0 << LPAIF_I2SCTL_SPKEN_SHIFT)
23 #define LPAIF_I2SCTL_MODE_SD0 1 !! 31 #define LPAIF_I2SCTL_SPKEN_ENABLE (1 << LPAIF_I2SCTL_SPKEN_SHIFT)
24 #define LPAIF_I2SCTL_MODE_SD1 2 !! 32
25 #define LPAIF_I2SCTL_MODE_SD2 3 !! 33 #define LPAIF_I2SCTL_SPKMODE_MASK 0x3C00
26 #define LPAIF_I2SCTL_MODE_SD3 4 !! 34 #define LPAIF_I2SCTL_SPKMODE_SHIFT 10
27 #define LPAIF_I2SCTL_MODE_QUAD01 5 !! 35 #define LPAIF_I2SCTL_SPKMODE_NONE (0 << LPAIF_I2SCTL_SPKMODE_SHIFT)
28 #define LPAIF_I2SCTL_MODE_QUAD23 6 !! 36 #define LPAIF_I2SCTL_SPKMODE_SD0 (1 << LPAIF_I2SCTL_SPKMODE_SHIFT)
29 #define LPAIF_I2SCTL_MODE_6CH 7 !! 37 #define LPAIF_I2SCTL_SPKMODE_SD1 (2 << LPAIF_I2SCTL_SPKMODE_SHIFT)
30 #define LPAIF_I2SCTL_MODE_8CH 8 !! 38 #define LPAIF_I2SCTL_SPKMODE_SD2 (3 << LPAIF_I2SCTL_SPKMODE_SHIFT)
31 #define LPAIF_I2SCTL_MODE_10CH 9 !! 39 #define LPAIF_I2SCTL_SPKMODE_SD3 (4 << LPAIF_I2SCTL_SPKMODE_SHIFT)
32 #define LPAIF_I2SCTL_MODE_12CH 10 !! 40 #define LPAIF_I2SCTL_SPKMODE_QUAD01 (5 << LPAIF_I2SCTL_SPKMODE_SHIFT)
33 #define LPAIF_I2SCTL_MODE_14CH 11 !! 41 #define LPAIF_I2SCTL_SPKMODE_QUAD23 (6 << LPAIF_I2SCTL_SPKMODE_SHIFT)
34 #define LPAIF_I2SCTL_MODE_16CH 12 !! 42 #define LPAIF_I2SCTL_SPKMODE_6CH (7 << LPAIF_I2SCTL_SPKMODE_SHIFT)
35 #define LPAIF_I2SCTL_MODE_SD4 13 !! 43 #define LPAIF_I2SCTL_SPKMODE_8CH (8 << LPAIF_I2SCTL_SPKMODE_SHIFT)
36 #define LPAIF_I2SCTL_MODE_SD5 14 !! 44
37 #define LPAIF_I2SCTL_MODE_SD6 15 !! 45 #define LPAIF_I2SCTL_SPKMONO_MASK 0x0200
38 #define LPAIF_I2SCTL_MODE_SD7 16 !! 46 #define LPAIF_I2SCTL_SPKMONO_SHIFT 9
39 #define LPAIF_I2SCTL_MODE_QUAD45 17 !! 47 #define LPAIF_I2SCTL_SPKMONO_STEREO (0 << LPAIF_I2SCTL_SPKMONO_SHIFT)
40 #define LPAIF_I2SCTL_MODE_QUAD47 18 !! 48 #define LPAIF_I2SCTL_SPKMONO_MONO (1 << LPAIF_I2SCTL_SPKMONO_SHIFT)
41 #define LPAIF_I2SCTL_MODE_8CH_2 19 !! 49
42 !! 50 #define LPAIF_I2SCTL_MICEN_MASK GENMASK(8, 8)
43 #define LPAIF_I2SCTL_SPKMODE(mode) mode !! 51 #define LPAIF_I2SCTL_MICEN_SHIFT 8
44 !! 52 #define LPAIF_I2SCTL_MICEN_DISABLE (0 << LPAIF_I2SCTL_MICEN_SHIFT)
45 #define LPAIF_I2SCTL_SPKMONO_STEREO 0 !! 53 #define LPAIF_I2SCTL_MICEN_ENABLE (1 << LPAIF_I2SCTL_MICEN_SHIFT)
46 #define LPAIF_I2SCTL_SPKMONO_MONO 1 !! 54
47 !! 55 #define LPAIF_I2SCTL_MICMODE_MASK GENMASK(7, 4)
48 #define LPAIF_I2SCTL_MICEN_DISABLE 0 !! 56 #define LPAIF_I2SCTL_MICMODE_SHIFT 4
49 #define LPAIF_I2SCTL_MICEN_ENABLE 1 !! 57 #define LPAIF_I2SCTL_MICMODE_NONE (0 << LPAIF_I2SCTL_MICMODE_SHIFT)
50 !! 58 #define LPAIF_I2SCTL_MICMODE_SD0 (1 << LPAIF_I2SCTL_MICMODE_SHIFT)
51 #define LPAIF_I2SCTL_MICMODE(mode) mode !! 59 #define LPAIF_I2SCTL_MICMODE_SD1 (2 << LPAIF_I2SCTL_MICMODE_SHIFT)
52 !! 60 #define LPAIF_I2SCTL_MICMODE_SD2 (3 << LPAIF_I2SCTL_MICMODE_SHIFT)
53 #define LPAIF_I2SCTL_MICMONO_STEREO 0 !! 61 #define LPAIF_I2SCTL_MICMODE_SD3 (4 << LPAIF_I2SCTL_MICMODE_SHIFT)
54 #define LPAIF_I2SCTL_MICMONO_MONO 1 !! 62 #define LPAIF_I2SCTL_MICMODE_QUAD01 (5 << LPAIF_I2SCTL_MICMODE_SHIFT)
55 !! 63 #define LPAIF_I2SCTL_MICMODE_QUAD23 (6 << LPAIF_I2SCTL_MICMODE_SHIFT)
56 #define LPAIF_I2SCTL_WSSRC_INTERNAL 0 !! 64 #define LPAIF_I2SCTL_MICMODE_6CH (7 << LPAIF_I2SCTL_MICMODE_SHIFT)
57 #define LPAIF_I2SCTL_WSSRC_EXTERNAL 1 !! 65 #define LPAIF_I2SCTL_MICMODE_8CH (8 << LPAIF_I2SCTL_MICMODE_SHIFT)
58 !! 66
59 #define LPAIF_I2SCTL_BITWIDTH_16 0 !! 67 #define LPAIF_I2SCTL_MIMONO_MASK GENMASK(3, 3)
60 #define LPAIF_I2SCTL_BITWIDTH_24 1 !! 68 #define LPAIF_I2SCTL_MICMONO_SHIFT 3
61 #define LPAIF_I2SCTL_BITWIDTH_32 2 !! 69 #define LPAIF_I2SCTL_MICMONO_STEREO (0 << LPAIF_I2SCTL_MICMONO_SHIFT)
62 !! 70 #define LPAIF_I2SCTL_MICMONO_MONO (1 << LPAIF_I2SCTL_MICMONO_SHIFT)
63 #define LPAIF_I2SCTL_RESET_STATE 0x003C !! 71
64 #define LPAIF_DMACTL_RESET_STATE 0x0020 !! 72 #define LPAIF_I2SCTL_WSSRC_MASK 0x0004
65 !! 73 #define LPAIF_I2SCTL_WSSRC_SHIFT 2
>> 74 #define LPAIF_I2SCTL_WSSRC_INTERNAL (0 << LPAIF_I2SCTL_WSSRC_SHIFT)
>> 75 #define LPAIF_I2SCTL_WSSRC_EXTERNAL (1 << LPAIF_I2SCTL_WSSRC_SHIFT)
>> 76
>> 77 #define LPAIF_I2SCTL_BITWIDTH_MASK 0x0003
>> 78 #define LPAIF_I2SCTL_BITWIDTH_SHIFT 0
>> 79 #define LPAIF_I2SCTL_BITWIDTH_16 (0 << LPAIF_I2SCTL_BITWIDTH_SHIFT)
>> 80 #define LPAIF_I2SCTL_BITWIDTH_24 (1 << LPAIF_I2SCTL_BITWIDTH_SHIFT)
>> 81 #define LPAIF_I2SCTL_BITWIDTH_32 (2 << LPAIF_I2SCTL_BITWIDTH_SHIFT)
66 82
67 /* LPAIF IRQ */ 83 /* LPAIF IRQ */
68 #define LPAIF_IRQ_REG_ADDR(v, addr, port) \ 84 #define LPAIF_IRQ_REG_ADDR(v, addr, port) \
69 (v->irq_reg_base + (addr) + v->irq_reg 85 (v->irq_reg_base + (addr) + v->irq_reg_stride * (port))
70 86
71 #define LPAIF_IRQ_PORT_HOST 0 87 #define LPAIF_IRQ_PORT_HOST 0
72 88
73 #define LPAIF_IRQEN_REG(v, port) LPAIF_ 89 #define LPAIF_IRQEN_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x0, (port))
74 #define LPAIF_IRQSTAT_REG(v, port) LPAIF_ 90 #define LPAIF_IRQSTAT_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x4, (port))
75 #define LPAIF_IRQCLEAR_REG(v, port) LPAIF_ 91 #define LPAIF_IRQCLEAR_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0xC, (port))
76 92
77 /* LPAIF RXTX IRQ */ <<
78 #define LPAIF_RXTX_IRQ_REG_ADDR(v, addr, port) <<
79 (v->rxtx_irq_reg_base + (addr) <<
80 <<
81 #define LPAIF_RXTX_IRQEN_REG(v, port) LPAIF_RX <<
82 #define LPAIF_RXTX_IRQSTAT_REG(v, port) LPAIF_ <<
83 #define LPAIF_RXTX_IRQCLEAR_REG(v, port) LPAIF <<
84 <<
85 /* LPAIF VA IRQ */ <<
86 #define LPAIF_VA_IRQ_REG_ADDR(v, addr, port) \ <<
87 (v->va_irq_reg_base + (addr) + <<
88 <<
89 #define LPAIF_VA_IRQEN_REG(v, port) LPAIF_VA_I <<
90 #define LPAIF_VA_IRQSTAT_REG(v, port) LPAIF_VA <<
91 #define LPAIF_VA_IRQCLEAR_REG(v, port) LPAIF_V <<
92 <<
93 #define LPASS_HDMITX_APP_IRQ_REG_ADDR(v, addr) <<
94 ((v->hdmi_irq_reg_base) + (addr)) <<
95 <<
96 #define LPASS_HDMITX_APP_IRQEN_REG(v) <<
97 #define LPASS_HDMITX_APP_IRQSTAT_REG(v) <<
98 #define LPASS_HDMITX_APP_IRQCLEAR_REG(v) <<
99 <<
100 #define LPAIF_IRQ_BITSTRIDE 3 93 #define LPAIF_IRQ_BITSTRIDE 3
101 94
102 #define LPAIF_IRQ_PER(chan) (1 << 95 #define LPAIF_IRQ_PER(chan) (1 << (LPAIF_IRQ_BITSTRIDE * (chan)))
103 #define LPAIF_IRQ_XRUN(chan) (2 << 96 #define LPAIF_IRQ_XRUN(chan) (2 << (LPAIF_IRQ_BITSTRIDE * (chan)))
104 #define LPAIF_IRQ_ERR(chan) (4 << 97 #define LPAIF_IRQ_ERR(chan) (4 << (LPAIF_IRQ_BITSTRIDE * (chan)))
105 98
106 #define LPAIF_IRQ_ALL(chan) (7 << 99 #define LPAIF_IRQ_ALL(chan) (7 << (LPAIF_IRQ_BITSTRIDE * (chan)))
107 #define LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(chan) <<
108 #define LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(chan) <<
109 #define LPAIF_IRQ_HDMI_METADONE BIT(23 <<
110 100
111 /* LPAIF DMA */ 101 /* LPAIF DMA */
112 #define LPAIF_HDMI_RDMA_REG_ADDR(v, addr, chan <<
113 (v->hdmi_rdma_reg_base + (addr) + v->h <<
114 <<
115 #define LPAIF_HDMI_RDMACTL_AUDINTF(id) (id << <<
116 <<
117 #define LPAIF_HDMI_RDMACTL_REG(v, chan) <<
118 #define LPAIF_HDMI_RDMABASE_REG(v, chan) <<
119 #define LPAIF_HDMI_RDMABUFF_REG(v, chan) <<
120 #define LPAIF_HDMI_RDMACURR_REG(v, chan) <<
121 #define LPAIF_HDMI_RDMAPER_REG(v, chan) <<
122 #define LPAIF_HDMI_RDMAPERCNT_REG(v, chan) <<
123 102
124 #define LPAIF_RDMA_REG_ADDR(v, addr, chan) \ 103 #define LPAIF_RDMA_REG_ADDR(v, addr, chan) \
125 (v->rdma_reg_base + (addr) + v->rdma_r 104 (v->rdma_reg_base + (addr) + v->rdma_reg_stride * (chan))
126 105
127 #define LPAIF_RDMACTL_AUDINTF(id) (id << 106 #define LPAIF_RDMACTL_AUDINTF(id) (id << LPAIF_RDMACTL_AUDINTF_SHIFT)
128 107
129 #define LPAIF_RDMACTL_REG(v, chan) LPAIF_ 108 #define LPAIF_RDMACTL_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x00, (chan))
130 #define LPAIF_RDMABASE_REG(v, chan) LPAIF_ 109 #define LPAIF_RDMABASE_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x04, (chan))
131 #define LPAIF_RDMABUFF_REG(v, chan) LPAIF_ 110 #define LPAIF_RDMABUFF_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x08, (chan))
132 #define LPAIF_RDMACURR_REG(v, chan) LPAIF_ 111 #define LPAIF_RDMACURR_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x0C, (chan))
133 #define LPAIF_RDMAPER_REG(v, chan) LPAIF_ 112 #define LPAIF_RDMAPER_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x10, (chan))
134 #define LPAIF_RDMAPERCNT_REG(v, chan) LPAIF_ 113 #define LPAIF_RDMAPERCNT_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x14, (chan))
135 114
136 #define LPAIF_WRDMA_REG_ADDR(v, addr, chan) \ 115 #define LPAIF_WRDMA_REG_ADDR(v, addr, chan) \
137 (v->wrdma_reg_base + (addr) + \ 116 (v->wrdma_reg_base + (addr) + \
138 v->wrdma_reg_stride * (chan - v->wrdm 117 v->wrdma_reg_stride * (chan - v->wrdma_channel_start))
139 118
140 #define LPAIF_WRDMACTL_REG(v, chan) LPAIF_ 119 #define LPAIF_WRDMACTL_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x00, (chan))
141 #define LPAIF_WRDMABASE_REG(v, chan) LPAIF_ 120 #define LPAIF_WRDMABASE_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x04, (chan))
142 #define LPAIF_WRDMABUFF_REG(v, chan) LPAIF_ 121 #define LPAIF_WRDMABUFF_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x08, (chan))
143 #define LPAIF_WRDMACURR_REG(v, chan) LPAIF_ 122 #define LPAIF_WRDMACURR_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x0C, (chan))
144 #define LPAIF_WRDMAPER_REG(v, chan) LPAIF_ 123 #define LPAIF_WRDMAPER_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x10, (chan))
145 #define LPAIF_WRDMAPERCNT_REG(v, chan) LPAIF_ 124 #define LPAIF_WRDMAPERCNT_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x14, (chan))
146 125
147 #define LPAIF_INTFDMA_REG(v, chan, reg, dai_id !! 126 #define __LPAIF_DMA_REG(v, chan, dir, reg) \
148 ((dai_id == LPASS_DP_RX) ? \ !! 127 (dir == SNDRV_PCM_STREAM_PLAYBACK) ? \
149 LPAIF_HDMI_RDMA##reg##_REG(v, !! 128 LPAIF_RDMA##reg##_REG(v, chan) : \
150 LPAIF_RDMA##reg##_REG(v, chan !! 129 LPAIF_WRDMA##reg##_REG(v, chan)
151 !! 130
152 #define __LPAIF_DMA_REG(v, chan, dir, reg, dai !! 131 #define LPAIF_DMACTL_REG(v, chan, dir) __LPAIF_DMA_REG(v, chan, dir, CTL)
153 ((dir == SNDRV_PCM_STREAM_PLAYBACK) ? !! 132 #define LPAIF_DMABASE_REG(v, chan, dir) __LPAIF_DMA_REG(v, chan, dir, BASE)
154 (LPAIF_INTFDMA_REG(v, chan, re !! 133 #define LPAIF_DMABUFF_REG(v, chan, dir) __LPAIF_DMA_REG(v, chan, dir, BUFF)
155 LPAIF_WRDMA##reg##_REG(v, chan !! 134 #define LPAIF_DMACURR_REG(v, chan, dir) __LPAIF_DMA_REG(v, chan, dir, CURR)
156 !! 135 #define LPAIF_DMAPER_REG(v, chan, dir) __LPAIF_DMA_REG(v, chan, dir, PER)
157 #define LPAIF_DMACTL_REG(v, chan, dir, dai_id) !! 136 #define LPAIF_DMAPERCNT_REG(v, chan, dir) __LPAIF_DMA_REG(v, chan, dir, PERCNT)
158 (is_cdc_dma_port(dai_id) ? \ !! 137
159 __LPAIF_CDC_DMA_REG(v, chan, dir, CTL, !! 138 #define LPAIF_DMACTL_BURSTEN_MASK 0x800
160 __LPAIF_DMA_REG(v, chan, dir, CTL, dai !! 139 #define LPAIF_DMACTL_BURSTEN_SHIFT 11
161 #define LPAIF_DMABASE_REG(v, chan, dir, dai_id !! 140 #define LPAIF_DMACTL_BURSTEN_SINGLE (0 << LPAIF_DMACTL_BURSTEN_SHIFT)
162 (is_cdc_dma_port(dai_id) ? \ !! 141 #define LPAIF_DMACTL_BURSTEN_INCR4 (1 << LPAIF_DMACTL_BURSTEN_SHIFT)
163 __LPAIF_CDC_DMA_REG(v, chan, dir, BASE !! 142
164 __LPAIF_DMA_REG(v, chan, dir, BASE, da !! 143 #define LPAIF_DMACTL_WPSCNT_MASK 0x700
165 #define LPAIF_DMABUFF_REG(v, chan, dir, dai_id !! 144 #define LPAIF_DMACTL_WPSCNT_SHIFT 8
166 (is_cdc_dma_port(dai_id) ? \ !! 145 #define LPAIF_DMACTL_WPSCNT_ONE (0 << LPAIF_DMACTL_WPSCNT_SHIFT)
167 __LPAIF_CDC_DMA_REG(v, chan, dir, BUFF !! 146 #define LPAIF_DMACTL_WPSCNT_TWO (1 << LPAIF_DMACTL_WPSCNT_SHIFT)
168 __LPAIF_DMA_REG(v, chan, dir, BUFF, da !! 147 #define LPAIF_DMACTL_WPSCNT_THREE (2 << LPAIF_DMACTL_WPSCNT_SHIFT)
169 #define LPAIF_DMACURR_REG(v, chan, dir, dai_id !! 148 #define LPAIF_DMACTL_WPSCNT_FOUR (3 << LPAIF_DMACTL_WPSCNT_SHIFT)
170 (is_cdc_dma_port(dai_id) ? \ !! 149 #define LPAIF_DMACTL_WPSCNT_SIX (5 << LPAIF_DMACTL_WPSCNT_SHIFT)
171 __LPAIF_CDC_DMA_REG(v, chan, dir, CURR !! 150 #define LPAIF_DMACTL_WPSCNT_EIGHT (7 << LPAIF_DMACTL_WPSCNT_SHIFT)
172 __LPAIF_DMA_REG(v, chan, dir, CURR, da !! 151
173 #define LPAIF_DMAPER_REG(v, chan, dir, dai_id) !! 152 #define LPAIF_DMACTL_AUDINTF_MASK 0x0F0
174 (is_cdc_dma_port(dai_id) ? \ !! 153 #define LPAIF_DMACTL_AUDINTF_SHIFT 4
175 __LPAIF_CDC_DMA_REG(v, chan, dir, PER, !! 154 #define LPAIF_DMACTL_AUDINTF(id) (id << LPAIF_DMACTL_AUDINTF_SHIFT)
176 __LPAIF_DMA_REG(v, chan, dir, PER, dai !! 155
177 #define LPAIF_DMAPERCNT_REG(v, chan, dir, dai_ !! 156 #define LPAIF_DMACTL_FIFOWM_MASK 0x00E
178 (is_cdc_dma_port(dai_id) ? \ !! 157 #define LPAIF_DMACTL_FIFOWM_SHIFT 1
179 __LPAIF_CDC_DMA_REG(v, chan, dir, PERC !! 158 #define LPAIF_DMACTL_FIFOWM_1 (0 << LPAIF_DMACTL_FIFOWM_SHIFT)
180 __LPAIF_DMA_REG(v, chan, dir, PERCNT, !! 159 #define LPAIF_DMACTL_FIFOWM_2 (1 << LPAIF_DMACTL_FIFOWM_SHIFT)
181 !! 160 #define LPAIF_DMACTL_FIFOWM_3 (2 << LPAIF_DMACTL_FIFOWM_SHIFT)
182 #define LPAIF_CDC_RDMA_REG_ADDR(v, addr, chan, !! 161 #define LPAIF_DMACTL_FIFOWM_4 (3 << LPAIF_DMACTL_FIFOWM_SHIFT)
183 (is_rxtx_cdc_dma_port(dai_id) ? \ !! 162 #define LPAIF_DMACTL_FIFOWM_5 (4 << LPAIF_DMACTL_FIFOWM_SHIFT)
184 (v->rxtx_rdma_reg_base + (addr) + v->r !! 163 #define LPAIF_DMACTL_FIFOWM_6 (5 << LPAIF_DMACTL_FIFOWM_SHIFT)
185 (v->va_rdma_reg_base + (addr) + v->va_ !! 164 #define LPAIF_DMACTL_FIFOWM_7 (6 << LPAIF_DMACTL_FIFOWM_SHIFT)
186 !! 165 #define LPAIF_DMACTL_FIFOWM_8 (7 << LPAIF_DMACTL_FIFOWM_SHIFT)
187 #define LPAIF_CDC_RXTX_RDMACTL_REG(v, chan, da !! 166
188 LPAIF_CDC_RDMA_REG_ADDR(v, 0x0 !! 167 #define LPAIF_DMACTL_ENABLE_MASK 0x1
189 #define LPAIF_CDC_RXTX_RDMABASE_REG(v, chan, d !! 168 #define LPAIF_DMACTL_ENABLE_SHIFT 0
190 LPAIF_CDC_RDMA_REG_ADDR(v, 0x0 !! 169 #define LPAIF_DMACTL_ENABLE_OFF (0 << LPAIF_DMACTL_ENABLE_SHIFT)
191 #define LPAIF_CDC_RXTX_RDMABUFF_REG(v, chan, d !! 170 #define LPAIF_DMACTL_ENABLE_ON (1 << LPAIF_DMACTL_ENABLE_SHIFT)
192 LPAIF_CDC_RDMA_REG_ADDR(v, 0x0 !! 171
193 #define LPAIF_CDC_RXTX_RDMACURR_REG(v, chan, d !! 172 #define LPAIF_DMACTL_DYNCLK_MASK BIT(12)
194 LPAIF_CDC_RDMA_REG_ADDR(v, 0x0 !! 173 #define LPAIF_DMACTL_DYNCLK_SHIFT 12
195 #define LPAIF_CDC_RXTX_RDMAPER_REG(v, chan, da !! 174 #define LPAIF_DMACTL_DYNCLK_OFF (0 << LPAIF_DMACTL_DYNCLK_SHIFT)
196 LPAIF_CDC_RDMA_REG_ADDR(v, 0x1 !! 175 #define LPAIF_DMACTL_DYNCLK_ON (1 << LPAIF_DMACTL_DYNCLK_SHIFT)
197 #define LPAIF_CDC_RXTX_RDMA_INTF_REG(v, chan, <<
198 LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan <<
199 <<
200 #define LPAIF_CDC_VA_RDMACTL_REG(v, chan, dai_ <<
201 #define LPAIF_CDC_VA_RDMABASE_REG(v, chan, dai <<
202 #define LPAIF_CDC_VA_RDMABUFF_REG(v, chan, dai <<
203 #define LPAIF_CDC_VA_RDMACURR_REG(v, chan, dai <<
204 #define LPAIF_CDC_VA_RDMAPER_REG(v, chan, dai_ <<
205 #define LPAIF_CDC_VA_RDMA_INTF_REG(v, chan, da <<
206 LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan <<
207 <<
208 #define LPAIF_CDC_WRDMA_REG_ADDR(v, addr, chan <<
209 (is_rxtx_cdc_dma_port(dai_id) ? \ <<
210 (v->rxtx_wrdma_reg_base + (addr) + \ <<
211 v->rxtx_wrdma_reg_stride * (ch <<
212 (v->va_wrdma_reg_base + (addr) + \ <<
213 v->va_wrdma_reg_stride * (chan <<
214 <<
215 #define LPAIF_CDC_RXTX_WRDMACTL_REG(v, chan, d <<
216 LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (cha <<
217 #define LPAIF_CDC_RXTX_WRDMABASE_REG(v, chan, <<
218 LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (cha <<
219 #define LPAIF_CDC_RXTX_WRDMABUFF_REG(v, chan, <<
220 LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (cha <<
221 #define LPAIF_CDC_RXTX_WRDMACURR_REG(v, chan, <<
222 LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (cha <<
223 #define LPAIF_CDC_RXTX_WRDMAPER_REG(v, chan, d <<
224 LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (cha <<
225 #define LPAIF_CDC_RXTX_WRDMA_INTF_REG(v, chan, <<
226 LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (cha <<
227 <<
228 #define LPAIF_CDC_VA_WRDMACTL_REG(v, chan, dai <<
229 LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (cha <<
230 #define LPAIF_CDC_VA_WRDMABASE_REG(v, chan, da <<
231 LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (cha <<
232 #define LPAIF_CDC_VA_WRDMABUFF_REG(v, chan, da <<
233 LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (cha <<
234 #define LPAIF_CDC_VA_WRDMACURR_REG(v, chan, da <<
235 LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (cha <<
236 #define LPAIF_CDC_VA_WRDMAPER_REG(v, chan, dai <<
237 LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (cha <<
238 #define LPAIF_CDC_VA_WRDMA_INTF_REG(v, chan, d <<
239 LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (cha <<
240 <<
241 #define __LPAIF_CDC_RDDMA_REG(v, chan, dir, re <<
242 (is_rxtx_cdc_dma_port(dai_id) <<
243 LPAIF_CDC_VA_RDMA##reg <<
244 <<
245 #define __LPAIF_CDC_WRDMA_REG(v, chan, dir, re <<
246 (is_rxtx_cdc_dma_port(dai_id) <<
247 LPAIF_CDC_VA_WRDMA##re <<
248 <<
249 #define __LPAIF_CDC_DMA_REG(v, chan, dir, reg, <<
250 ((dir == SNDRV_PCM_STREAM_PLA <<
251 __LPAIF_CDC_RDDMA_REG( <<
252 __LPAIF_CDC_WRDMA_REG( <<
253 <<
254 #define LPAIF_CDC_INTF_REG(v, chan, dir, dai_i <<
255 ((dir == SNDRV_PCM_STREAM_PLA <<
256 LPAIF_CDC_RDMA_INTF_REG(v, cha <<
257 LPAIF_CDC_WRDMA_INTF_REG(v, ch <<
258 <<
259 #define LPAIF_INTF_REG(v, chan, dir, dai_id) \ <<
260 (is_cdc_dma_port(dai_id) ? \ <<
261 LPAIF_CDC_INTF_REG(v, chan, di <<
262 LPAIF_DMACTL_REG(v, chan, dir, <<
263 <<
264 #define LPAIF_DMACTL_BURSTEN_SINGLE 0 <<
265 #define LPAIF_DMACTL_BURSTEN_INCR4 1 <<
266 <<
267 #define LPAIF_DMACTL_WPSCNT_ONE 0 <<
268 #define LPAIF_DMACTL_WPSCNT_TWO 1 <<
269 #define LPAIF_DMACTL_WPSCNT_THREE 2 <<
270 #define LPAIF_DMACTL_WPSCNT_FOUR 3 <<
271 #define LPAIF_DMACTL_WPSCNT_SIX 5 <<
272 #define LPAIF_DMACTL_WPSCNT_EIGHT 7 <<
273 #define LPAIF_DMACTL_WPSCNT_TEN 9 <<
274 #define LPAIF_DMACTL_WPSCNT_TWELVE 11 <<
275 #define LPAIF_DMACTL_WPSCNT_FOURTEEN 13 <<
276 #define LPAIF_DMACTL_WPSCNT_SIXTEEN 15 <<
277 <<
278 #define LPAIF_DMACTL_AUDINTF(id) id <<
279 <<
280 #define LPAIF_DMACTL_FIFOWM_1 0 <<
281 #define LPAIF_DMACTL_FIFOWM_2 1 <<
282 #define LPAIF_DMACTL_FIFOWM_3 2 <<
283 #define LPAIF_DMACTL_FIFOWM_4 3 <<
284 #define LPAIF_DMACTL_FIFOWM_5 4 <<
285 #define LPAIF_DMACTL_FIFOWM_6 5 <<
286 #define LPAIF_DMACTL_FIFOWM_7 6 <<
287 #define LPAIF_DMACTL_FIFOWM_8 7 <<
288 #define LPAIF_DMACTL_FIFOWM_9 8 <<
289 #define LPAIF_DMACTL_FIFOWM_10 9 <<
290 #define LPAIF_DMACTL_FIFOWM_11 10 <<
291 #define LPAIF_DMACTL_FIFOWM_12 11 <<
292 #define LPAIF_DMACTL_FIFOWM_13 12 <<
293 #define LPAIF_DMACTL_FIFOWM_14 13 <<
294 #define LPAIF_DMACTL_FIFOWM_15 14 <<
295 #define LPAIF_DMACTL_FIFOWM_16 15 <<
296 #define LPAIF_DMACTL_FIFOWM_17 16 <<
297 #define LPAIF_DMACTL_FIFOWM_18 17 <<
298 #define LPAIF_DMACTL_FIFOWM_19 18 <<
299 #define LPAIF_DMACTL_FIFOWM_20 19 <<
300 #define LPAIF_DMACTL_FIFOWM_21 20 <<
301 #define LPAIF_DMACTL_FIFOWM_22 21 <<
302 #define LPAIF_DMACTL_FIFOWM_23 22 <<
303 #define LPAIF_DMACTL_FIFOWM_24 23 <<
304 #define LPAIF_DMACTL_FIFOWM_25 24 <<
305 #define LPAIF_DMACTL_FIFOWM_26 25 <<
306 #define LPAIF_DMACTL_FIFOWM_27 26 <<
307 #define LPAIF_DMACTL_FIFOWM_28 27 <<
308 #define LPAIF_DMACTL_FIFOWM_29 28 <<
309 #define LPAIF_DMACTL_FIFOWM_30 29 <<
310 #define LPAIF_DMACTL_FIFOWM_31 30 <<
311 #define LPAIF_DMACTL_FIFOWM_32 31 <<
312 <<
313 #define LPAIF_DMACTL_ENABLE_OFF 0 <<
314 #define LPAIF_DMACTL_ENABLE_ON 1 <<
315 <<
316 #define LPAIF_DMACTL_DYNCLK_OFF 0 <<
317 #define LPAIF_DMACTL_DYNCLK_ON 1 <<
318 <<
319 #endif /* __LPASS_LPAIF_REG_H__ */ 176 #endif /* __LPASS_LPAIF_REG_H__ */
320 177
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