1 // SPDX-License-Identifier: GPL-2.0-only 1
2 /*
3 * Copyright (c) 2020, The Linux Foundation. A
4 *
5 * lpass-sc7180.c -- ALSA SoC platform-machine
6 */
7
8 #include <linux/clk.h>
9 #include <linux/device.h>
10 #include <linux/err.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm.h>
16 #include <dt-bindings/sound/sc7180-lpass.h>
17 #include <sound/pcm.h>
18 #include <sound/soc.h>
19
20 #include "lpass-lpaif-reg.h"
21 #include "lpass.h"
22
23 static struct snd_soc_dai_driver sc7180_lpass_
24 {
25 .id = MI2S_PRIMARY,
26 .name = "Primary MI2S",
27 .playback = {
28 .stream_name = "Primar
29 .formats = SNDR
30 .rates = SNDRV_PCM_RAT
31 .rate_min = 4800
32 .rate_max = 4800
33 .channels_min = 2,
34 .channels_max = 2,
35 },
36 .capture = {
37 .stream_name = "Primar
38 .formats = SNDRV_PCM_F
39 SNDRV_PCM_FMTB
40 .rates = SNDRV_PCM_RAT
41 .rate_min = 4800
42 .rate_max = 4800
43 .channels_min = 2,
44 .channels_max = 2,
45 },
46 .ops = &asoc_qcom_lpass_cpu
47 }, {
48 .id = MI2S_SECONDARY,
49 .name = "Secondary MI2S",
50 .playback = {
51 .stream_name = "Second
52 .formats = SNDR
53 .rates = SNDRV_PCM_RAT
54 .rate_min = 4800
55 .rate_max = 4800
56 .channels_min = 2,
57 .channels_max = 2,
58 },
59 .ops = &asoc_qcom_lpass_cpu
60 }, {
61 .id = LPASS_DP_RX,
62 .name = "Hdmi",
63 .playback = {
64 .stream_name = "Hdmi P
65 .formats = SNDR
66 .rates = SNDRV_PCM_RAT
67 .rate_min = 4800
68 .rate_max = 4800
69 .channels_min = 2,
70 .channels_max = 2,
71 },
72 .ops = &asoc_qcom_lpass_hdm
73 },
74 };
75
76 static int sc7180_lpass_alloc_dma_channel(stru
77 int
78 {
79 const struct lpass_variant *v = drvdat
80 int chan = 0;
81
82 if (dai_id == LPASS_DP_RX) {
83 if (direction == SNDRV_PCM_STR
84 chan = find_first_zero
85
86
87 if (chan >= v->hdmi_rd
88 return -EBUSY;
89 }
90 set_bit(chan, &drvdata->hdmi_d
91 } else {
92 if (direction == SNDRV_PCM_STR
93 chan = find_first_zero
94
95
96 if (chan >= v->rdma_ch
97 return -EBUSY;
98 } else {
99 chan = find_next_zero_
100 v->wrd
101 v->wrd
102 v->wrd
103
104 if (chan >= v->wrdma_
105 return -EBUSY;
106 }
107
108 set_bit(chan, &drvdata->dma_ch
109 }
110 return chan;
111 }
112
113 static int sc7180_lpass_free_dma_channel(struc
114 {
115 if (dai_id == LPASS_DP_RX)
116 clear_bit(chan, &drvdata->hdmi
117 else
118 clear_bit(chan, &drvdata->dma_
119
120 return 0;
121 }
122
123 static int sc7180_lpass_init(struct platform_d
124 {
125 struct lpass_data *drvdata = platform_
126 const struct lpass_variant *variant =
127 struct device *dev = &pdev->dev;
128 int ret, i;
129
130 drvdata->clks = devm_kcalloc(dev, vari
131 sizeof(*d
132 if (!drvdata->clks)
133 return -ENOMEM;
134
135 drvdata->num_clks = variant->num_clks;
136
137 for (i = 0; i < drvdata->num_clks; i++
138 drvdata->clks[i].id = variant-
139
140 ret = devm_clk_bulk_get(dev, drvdata->
141 if (ret) {
142 dev_err(dev, "Failed to get cl
143 return ret;
144 }
145
146 ret = clk_bulk_prepare_enable(drvdata-
147 if (ret) {
148 dev_err(dev, "sc7180 clk_enabl
149 return ret;
150 }
151
152 return 0;
153 }
154
155 static int sc7180_lpass_exit(struct platform_d
156 {
157 struct lpass_data *drvdata = platform_
158
159 clk_bulk_disable_unprepare(drvdata->nu
160 return 0;
161 }
162
163 static int __maybe_unused sc7180_lpass_dev_res
164 {
165 struct lpass_data *drvdata = dev_get_d
166
167 return clk_bulk_prepare_enable(drvdata
168 }
169
170 static int __maybe_unused sc7180_lpass_dev_sus
171 {
172 struct lpass_data *drvdata = dev_get_d
173
174 clk_bulk_disable_unprepare(drvdata->nu
175 return 0;
176 }
177
178 static const struct dev_pm_ops sc7180_lpass_pm
179 SET_SYSTEM_SLEEP_PM_OPS(sc7180_lpass_d
180 };
181
182 static const struct lpass_variant sc7180_data
183 .i2sctrl_reg_base = 0x1000,
184 .i2sctrl_reg_stride = 0x1000,
185 .i2s_ports = 3,
186 .irq_reg_base = 0x9000,
187 .irq_reg_stride = 0x1000,
188 .irq_ports = 3,
189 .rdma_reg_base = 0xC000,
190 .rdma_reg_stride = 0x1000,
191 .rdma_channels = 5,
192 .hdmi_rdma_reg_base = 0x64
193 .hdmi_rdma_reg_stride = 0x1000,
194 .hdmi_rdma_channels = 4,
195 .dmactl_audif_start = 1,
196 .wrdma_reg_base = 0x18000,
197 .wrdma_reg_stride = 0x1000,
198 .wrdma_channel_start = 5,
199 .wrdma_channels = 4,
200
201 .loopback = REG_FIELD_ID
202 .spken = REG_FIELD_ID
203 .spkmode = REG_FIELD_ID
204 .spkmono = REG_FIELD_ID
205 .micen = REG_FIELD_ID
206 .micmode = REG_FIELD_ID
207 .micmono = REG_FIELD_ID
208 .wssrc = REG_FIELD_ID
209 .bitwidth = REG_FIELD_ID
210
211 .rdma_dyncclk = REG_FIELD_ID
212 .rdma_bursten = REG_FIELD_ID
213 .rdma_wpscnt = REG_FIELD_ID
214 .rdma_intf = REG_
215 .rdma_fifowm = REG_FIELD_ID
216 .rdma_enable = REG_FIELD_ID
217
218 .wrdma_dyncclk = REG_FIELD_ID
219 .wrdma_bursten = REG_FIELD_ID
220 .wrdma_wpscnt = REG_FIELD_ID
221 .wrdma_intf = REG_FIELD_ID
222 .wrdma_fifowm = REG_FIELD_ID
223 .wrdma_enable = REG_FIELD_ID
224
225 .hdmi_tx_ctl_addr = 0x1000,
226 .hdmi_legacy_addr = 0x1008,
227 .hdmi_vbit_addr = 0x610c0,
228 .hdmi_ch_lsb_addr = 0x61048,
229 .hdmi_ch_msb_addr = 0x6104c,
230 .ch_stride = 0x8,
231 .hdmi_parity_addr = 0x61034,
232 .hdmi_dmactl_addr = 0x61038,
233 .hdmi_dma_stride = 0x4,
234 .hdmi_DP_addr = 0x610c8,
235 .hdmi_sstream_addr = 0x6101c,
236 .hdmi_irq_reg_base = 0x63
237 .hdmi_irq_ports = 1,
238
239 .hdmi_rdma_dyncclk = REG_
240 .hdmi_rdma_bursten = REG_
241 .hdmi_rdma_burst8 = REG_
242 .hdmi_rdma_burst16 = REG_
243 .hdmi_rdma_dynburst = REG_
244 .hdmi_rdma_wpscnt = REG_
245 .hdmi_rdma_fifowm = REG_
246 .hdmi_rdma_enable = REG_
247
248 .sstream_en = REG_FIELD(0x
249 .dma_sel = REG_
250 .auto_bbit_en = REG_FIELD(0x6101c, 3
251 .layout = REG_FIELD(0x
252 .layout_sp = REG_FIELD(0x
253 .set_sp_on_en = REG_FIELD(0x6101c, 1
254 .dp_audio = REG_FIELD(0x
255 .dp_staffing_en = REG_FIELD(0x6101c, 1
256 .dp_sp_b_hw_en = REG_FIELD(0x6101c, 1
257
258 .mute = REG_FIELD(0x
259 .as_sdp_cc = REG_FIELD(0x
260 .as_sdp_ct = REG_FIELD(0x
261 .aif_db4 = REG_
262 .frequency = REG_FIELD(0x
263 .mst_index = REG_FIELD(0x
264 .dptx_index = REG_FIELD(0x
265
266 .soft_reset = REG_FIELD(0x
267 .force_reset = REG_FIELD(0x1000, 30
268
269 .use_hw_chs = REG_FIELD(0x
270 .use_hw_usr = REG_FIELD(0x
271 .hw_chs_sel = REG_FIELD(0x
272 .hw_usr_sel = REG_FIELD(0x
273
274 .replace_vbit = REG_FIELD(0x610c0, 0
275 .vbit_stream = REG_FIELD(0x610c0, 1
276
277 .legacy_en = REG_FIELD(0
278 .calc_en = REG_FIELD(0
279 .lsb_bits = REG_FIELD(0
280 .msb_bits = REG_FIELD(0
281
282
283 .clk_name = (const char*
284 "pcnoc-sway
285 "audio-core
286 "pcnoc-mpor
287 },
288 .num_clks = 3,
289 .dai_driver = sc7180_lpass
290 .num_dai = ARRAY_SIZE(s
291 .dai_osr_clk_names = (const char
292 "mclk0",
293 "null",
294 },
295 .dai_bit_clk_names = (const char
296 "mi2s-bit-c
297 "mi2s-bit-c
298 },
299 .init = sc7180_lpass
300 .exit = sc7180_lpass
301 .alloc_dma_channel = sc7180_lpass
302 .free_dma_channel = sc7180_lpass
303 };
304
305 static const struct of_device_id sc7180_lpass_
306 {.compatible = "qcom,sc7180-lpass-cpu"
307 {}
308 };
309 MODULE_DEVICE_TABLE(of, sc7180_lpass_cpu_devic
310
311 static struct platform_driver sc7180_lpass_cpu
312 .driver = {
313 .name = "sc7180-lpass-cpu",
314 .of_match_table = of_match_ptr
315 .pm = &sc7180_lpass_pm_ops,
316 },
317 .probe = asoc_qcom_lpass_cpu_platform_
318 .remove = asoc_qcom_lpass_cpu_platform
319 .shutdown = asoc_qcom_lpass_cpu_platfo
320 };
321
322 module_platform_driver(sc7180_lpass_cpu_platfo
323
324 MODULE_DESCRIPTION("SC7180 LPASS CPU DRIVER");
325 MODULE_LICENSE("GPL");
326
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.