1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2020, Linaro Limited 2 // Copyright (c) 2020, Linaro Limited
3 3
4 #include <dt-bindings/sound/qcom,q6afe.h> <<
5 #include <linux/err.h> 4 #include <linux/err.h>
6 #include <linux/init.h> 5 #include <linux/init.h>
7 #include <linux/clk-provider.h> 6 #include <linux/clk-provider.h>
8 #include <linux/module.h> 7 #include <linux/module.h>
9 #include <linux/device.h> 8 #include <linux/device.h>
10 #include <linux/platform_device.h> 9 #include <linux/platform_device.h>
11 #include "q6dsp-lpass-clocks.h" !! 10 #include <linux/of.h>
>> 11 #include <linux/slab.h>
12 #include "q6afe.h" 12 #include "q6afe.h"
13 13
14 #define Q6AFE_CLK(id) { 14 #define Q6AFE_CLK(id) { \
15 .clk_id = id, 15 .clk_id = id, \
16 .q6dsp_clk_id = Q6AFE_##id, !! 16 .afe_clk_id = Q6AFE_##id, \
17 .name = #id, 17 .name = #id, \
18 .rate = 19200000, 18 .rate = 19200000, \
19 } 19 }
20 20
>> 21 #define Q6AFE_VOTE_CLK(id, blkid, n) { \
>> 22 .clk_id = id, \
>> 23 .afe_clk_id = blkid, \
>> 24 .name = n, \
>> 25 }
>> 26
>> 27 struct q6afe_clk_init {
>> 28 int clk_id;
>> 29 int afe_clk_id;
>> 30 char *name;
>> 31 int rate;
>> 32 };
>> 33
>> 34 struct q6afe_clk {
>> 35 struct device *dev;
>> 36 int afe_clk_id;
>> 37 int attributes;
>> 38 int rate;
>> 39 uint32_t handle;
>> 40 struct clk_hw hw;
>> 41 };
>> 42
>> 43 #define to_q6afe_clk(_hw) container_of(_hw, struct q6afe_clk, hw)
>> 44
>> 45 struct q6afe_cc {
>> 46 struct device *dev;
>> 47 struct q6afe_clk *clks[Q6AFE_MAX_CLK_ID];
>> 48 };
>> 49
>> 50 static int clk_q6afe_prepare(struct clk_hw *hw)
>> 51 {
>> 52 struct q6afe_clk *clk = to_q6afe_clk(hw);
>> 53
>> 54 return q6afe_set_lpass_clock(clk->dev, clk->afe_clk_id, clk->attributes,
>> 55 Q6AFE_LPASS_CLK_ROOT_DEFAULT, clk->rate);
>> 56 }
>> 57
>> 58 static void clk_q6afe_unprepare(struct clk_hw *hw)
>> 59 {
>> 60 struct q6afe_clk *clk = to_q6afe_clk(hw);
>> 61
>> 62 q6afe_set_lpass_clock(clk->dev, clk->afe_clk_id, clk->attributes,
>> 63 Q6AFE_LPASS_CLK_ROOT_DEFAULT, 0);
>> 64 }
>> 65
>> 66 static int clk_q6afe_set_rate(struct clk_hw *hw, unsigned long rate,
>> 67 unsigned long parent_rate)
>> 68 {
>> 69 struct q6afe_clk *clk = to_q6afe_clk(hw);
>> 70
>> 71 clk->rate = rate;
>> 72
>> 73 return 0;
>> 74 }
>> 75
>> 76 static unsigned long clk_q6afe_recalc_rate(struct clk_hw *hw,
>> 77 unsigned long parent_rate)
>> 78 {
>> 79 struct q6afe_clk *clk = to_q6afe_clk(hw);
>> 80
>> 81 return clk->rate;
>> 82 }
>> 83
>> 84 static long clk_q6afe_round_rate(struct clk_hw *hw, unsigned long rate,
>> 85 unsigned long *parent_rate)
>> 86 {
>> 87 return rate;
>> 88 }
>> 89
>> 90 static const struct clk_ops clk_q6afe_ops = {
>> 91 .prepare = clk_q6afe_prepare,
>> 92 .unprepare = clk_q6afe_unprepare,
>> 93 .set_rate = clk_q6afe_set_rate,
>> 94 .round_rate = clk_q6afe_round_rate,
>> 95 .recalc_rate = clk_q6afe_recalc_rate,
>> 96 };
>> 97
>> 98 static int clk_vote_q6afe_block(struct clk_hw *hw)
>> 99 {
>> 100 struct q6afe_clk *clk = to_q6afe_clk(hw);
>> 101
>> 102 return q6afe_vote_lpass_core_hw(clk->dev, clk->afe_clk_id,
>> 103 clk_hw_get_name(&clk->hw), &clk->handle);
>> 104 }
21 105
22 static const struct q6dsp_clk_init q6afe_clks[ !! 106 static void clk_unvote_q6afe_block(struct clk_hw *hw)
>> 107 {
>> 108 struct q6afe_clk *clk = to_q6afe_clk(hw);
>> 109
>> 110 q6afe_unvote_lpass_core_hw(clk->dev, clk->afe_clk_id, clk->handle);
>> 111 }
>> 112
>> 113 static const struct clk_ops clk_vote_q6afe_ops = {
>> 114 .prepare = clk_vote_q6afe_block,
>> 115 .unprepare = clk_unvote_q6afe_block,
>> 116 };
>> 117
>> 118 static const struct q6afe_clk_init q6afe_clks[] = {
23 Q6AFE_CLK(LPASS_CLK_ID_PRI_MI2S_IBIT), 119 Q6AFE_CLK(LPASS_CLK_ID_PRI_MI2S_IBIT),
24 Q6AFE_CLK(LPASS_CLK_ID_PRI_MI2S_EBIT), 120 Q6AFE_CLK(LPASS_CLK_ID_PRI_MI2S_EBIT),
25 Q6AFE_CLK(LPASS_CLK_ID_SEC_MI2S_IBIT), 121 Q6AFE_CLK(LPASS_CLK_ID_SEC_MI2S_IBIT),
26 Q6AFE_CLK(LPASS_CLK_ID_SEC_MI2S_EBIT), 122 Q6AFE_CLK(LPASS_CLK_ID_SEC_MI2S_EBIT),
27 Q6AFE_CLK(LPASS_CLK_ID_TER_MI2S_IBIT), 123 Q6AFE_CLK(LPASS_CLK_ID_TER_MI2S_IBIT),
28 Q6AFE_CLK(LPASS_CLK_ID_TER_MI2S_EBIT), 124 Q6AFE_CLK(LPASS_CLK_ID_TER_MI2S_EBIT),
29 Q6AFE_CLK(LPASS_CLK_ID_QUAD_MI2S_IBIT) 125 Q6AFE_CLK(LPASS_CLK_ID_QUAD_MI2S_IBIT),
30 Q6AFE_CLK(LPASS_CLK_ID_QUAD_MI2S_EBIT) 126 Q6AFE_CLK(LPASS_CLK_ID_QUAD_MI2S_EBIT),
31 Q6AFE_CLK(LPASS_CLK_ID_SPEAKER_I2S_IBI 127 Q6AFE_CLK(LPASS_CLK_ID_SPEAKER_I2S_IBIT),
32 Q6AFE_CLK(LPASS_CLK_ID_SPEAKER_I2S_EBI 128 Q6AFE_CLK(LPASS_CLK_ID_SPEAKER_I2S_EBIT),
33 Q6AFE_CLK(LPASS_CLK_ID_SPEAKER_I2S_OSR 129 Q6AFE_CLK(LPASS_CLK_ID_SPEAKER_I2S_OSR),
34 Q6AFE_CLK(LPASS_CLK_ID_QUI_MI2S_IBIT), 130 Q6AFE_CLK(LPASS_CLK_ID_QUI_MI2S_IBIT),
35 Q6AFE_CLK(LPASS_CLK_ID_QUI_MI2S_EBIT), 131 Q6AFE_CLK(LPASS_CLK_ID_QUI_MI2S_EBIT),
36 Q6AFE_CLK(LPASS_CLK_ID_SEN_MI2S_IBIT), 132 Q6AFE_CLK(LPASS_CLK_ID_SEN_MI2S_IBIT),
37 Q6AFE_CLK(LPASS_CLK_ID_SEN_MI2S_EBIT), 133 Q6AFE_CLK(LPASS_CLK_ID_SEN_MI2S_EBIT),
38 Q6AFE_CLK(LPASS_CLK_ID_INT0_MI2S_IBIT) 134 Q6AFE_CLK(LPASS_CLK_ID_INT0_MI2S_IBIT),
39 Q6AFE_CLK(LPASS_CLK_ID_INT1_MI2S_IBIT) 135 Q6AFE_CLK(LPASS_CLK_ID_INT1_MI2S_IBIT),
40 Q6AFE_CLK(LPASS_CLK_ID_INT2_MI2S_IBIT) 136 Q6AFE_CLK(LPASS_CLK_ID_INT2_MI2S_IBIT),
41 Q6AFE_CLK(LPASS_CLK_ID_INT3_MI2S_IBIT) 137 Q6AFE_CLK(LPASS_CLK_ID_INT3_MI2S_IBIT),
42 Q6AFE_CLK(LPASS_CLK_ID_INT4_MI2S_IBIT) 138 Q6AFE_CLK(LPASS_CLK_ID_INT4_MI2S_IBIT),
43 Q6AFE_CLK(LPASS_CLK_ID_INT5_MI2S_IBIT) 139 Q6AFE_CLK(LPASS_CLK_ID_INT5_MI2S_IBIT),
44 Q6AFE_CLK(LPASS_CLK_ID_INT6_MI2S_IBIT) 140 Q6AFE_CLK(LPASS_CLK_ID_INT6_MI2S_IBIT),
45 Q6AFE_CLK(LPASS_CLK_ID_QUI_MI2S_OSR), 141 Q6AFE_CLK(LPASS_CLK_ID_QUI_MI2S_OSR),
46 Q6AFE_CLK(LPASS_CLK_ID_PRI_PCM_IBIT), 142 Q6AFE_CLK(LPASS_CLK_ID_PRI_PCM_IBIT),
47 Q6AFE_CLK(LPASS_CLK_ID_PRI_PCM_EBIT), 143 Q6AFE_CLK(LPASS_CLK_ID_PRI_PCM_EBIT),
48 Q6AFE_CLK(LPASS_CLK_ID_SEC_PCM_IBIT), 144 Q6AFE_CLK(LPASS_CLK_ID_SEC_PCM_IBIT),
49 Q6AFE_CLK(LPASS_CLK_ID_SEC_PCM_EBIT), 145 Q6AFE_CLK(LPASS_CLK_ID_SEC_PCM_EBIT),
50 Q6AFE_CLK(LPASS_CLK_ID_TER_PCM_IBIT), 146 Q6AFE_CLK(LPASS_CLK_ID_TER_PCM_IBIT),
51 Q6AFE_CLK(LPASS_CLK_ID_TER_PCM_EBIT), 147 Q6AFE_CLK(LPASS_CLK_ID_TER_PCM_EBIT),
52 Q6AFE_CLK(LPASS_CLK_ID_QUAD_PCM_IBIT), 148 Q6AFE_CLK(LPASS_CLK_ID_QUAD_PCM_IBIT),
53 Q6AFE_CLK(LPASS_CLK_ID_QUAD_PCM_EBIT), 149 Q6AFE_CLK(LPASS_CLK_ID_QUAD_PCM_EBIT),
54 Q6AFE_CLK(LPASS_CLK_ID_QUIN_PCM_IBIT), 150 Q6AFE_CLK(LPASS_CLK_ID_QUIN_PCM_IBIT),
55 Q6AFE_CLK(LPASS_CLK_ID_QUIN_PCM_EBIT), 151 Q6AFE_CLK(LPASS_CLK_ID_QUIN_PCM_EBIT),
56 Q6AFE_CLK(LPASS_CLK_ID_QUI_PCM_OSR), 152 Q6AFE_CLK(LPASS_CLK_ID_QUI_PCM_OSR),
57 Q6AFE_CLK(LPASS_CLK_ID_PRI_TDM_IBIT), 153 Q6AFE_CLK(LPASS_CLK_ID_PRI_TDM_IBIT),
58 Q6AFE_CLK(LPASS_CLK_ID_PRI_TDM_EBIT), 154 Q6AFE_CLK(LPASS_CLK_ID_PRI_TDM_EBIT),
59 Q6AFE_CLK(LPASS_CLK_ID_SEC_TDM_IBIT), 155 Q6AFE_CLK(LPASS_CLK_ID_SEC_TDM_IBIT),
60 Q6AFE_CLK(LPASS_CLK_ID_SEC_TDM_EBIT), 156 Q6AFE_CLK(LPASS_CLK_ID_SEC_TDM_EBIT),
61 Q6AFE_CLK(LPASS_CLK_ID_TER_TDM_IBIT), 157 Q6AFE_CLK(LPASS_CLK_ID_TER_TDM_IBIT),
62 Q6AFE_CLK(LPASS_CLK_ID_TER_TDM_EBIT), 158 Q6AFE_CLK(LPASS_CLK_ID_TER_TDM_EBIT),
63 Q6AFE_CLK(LPASS_CLK_ID_QUAD_TDM_IBIT), 159 Q6AFE_CLK(LPASS_CLK_ID_QUAD_TDM_IBIT),
64 Q6AFE_CLK(LPASS_CLK_ID_QUAD_TDM_EBIT), 160 Q6AFE_CLK(LPASS_CLK_ID_QUAD_TDM_EBIT),
65 Q6AFE_CLK(LPASS_CLK_ID_QUIN_TDM_IBIT), 161 Q6AFE_CLK(LPASS_CLK_ID_QUIN_TDM_IBIT),
66 Q6AFE_CLK(LPASS_CLK_ID_QUIN_TDM_EBIT), 162 Q6AFE_CLK(LPASS_CLK_ID_QUIN_TDM_EBIT),
67 Q6AFE_CLK(LPASS_CLK_ID_QUIN_TDM_OSR), 163 Q6AFE_CLK(LPASS_CLK_ID_QUIN_TDM_OSR),
68 Q6AFE_CLK(LPASS_CLK_ID_MCLK_1), 164 Q6AFE_CLK(LPASS_CLK_ID_MCLK_1),
69 Q6AFE_CLK(LPASS_CLK_ID_MCLK_2), 165 Q6AFE_CLK(LPASS_CLK_ID_MCLK_2),
70 Q6AFE_CLK(LPASS_CLK_ID_MCLK_3), 166 Q6AFE_CLK(LPASS_CLK_ID_MCLK_3),
71 Q6AFE_CLK(LPASS_CLK_ID_MCLK_4), 167 Q6AFE_CLK(LPASS_CLK_ID_MCLK_4),
72 Q6AFE_CLK(LPASS_CLK_ID_INTERNAL_DIGITA 168 Q6AFE_CLK(LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE),
73 Q6AFE_CLK(LPASS_CLK_ID_INT_MCLK_0), 169 Q6AFE_CLK(LPASS_CLK_ID_INT_MCLK_0),
74 Q6AFE_CLK(LPASS_CLK_ID_INT_MCLK_1), 170 Q6AFE_CLK(LPASS_CLK_ID_INT_MCLK_1),
75 Q6AFE_CLK(LPASS_CLK_ID_WSA_CORE_MCLK), 171 Q6AFE_CLK(LPASS_CLK_ID_WSA_CORE_MCLK),
76 Q6AFE_CLK(LPASS_CLK_ID_WSA_CORE_NPL_MC 172 Q6AFE_CLK(LPASS_CLK_ID_WSA_CORE_NPL_MCLK),
77 Q6AFE_CLK(LPASS_CLK_ID_VA_CORE_MCLK), 173 Q6AFE_CLK(LPASS_CLK_ID_VA_CORE_MCLK),
78 Q6AFE_CLK(LPASS_CLK_ID_TX_CORE_MCLK), 174 Q6AFE_CLK(LPASS_CLK_ID_TX_CORE_MCLK),
79 Q6AFE_CLK(LPASS_CLK_ID_TX_CORE_NPL_MCL 175 Q6AFE_CLK(LPASS_CLK_ID_TX_CORE_NPL_MCLK),
80 Q6AFE_CLK(LPASS_CLK_ID_RX_CORE_MCLK), 176 Q6AFE_CLK(LPASS_CLK_ID_RX_CORE_MCLK),
81 Q6AFE_CLK(LPASS_CLK_ID_RX_CORE_NPL_MCL 177 Q6AFE_CLK(LPASS_CLK_ID_RX_CORE_NPL_MCLK),
82 Q6AFE_CLK(LPASS_CLK_ID_VA_CORE_2X_MCLK 178 Q6AFE_CLK(LPASS_CLK_ID_VA_CORE_2X_MCLK),
83 Q6DSP_VOTE_CLK(LPASS_HW_AVTIMER_VOTE, !! 179 Q6AFE_VOTE_CLK(LPASS_HW_AVTIMER_VOTE,
84 Q6AFE_LPASS_CORE_AVTIME 180 Q6AFE_LPASS_CORE_AVTIMER_BLOCK,
85 "LPASS_AVTIMER_MACRO"), 181 "LPASS_AVTIMER_MACRO"),
86 Q6DSP_VOTE_CLK(LPASS_HW_MACRO_VOTE, !! 182 Q6AFE_VOTE_CLK(LPASS_HW_MACRO_VOTE,
87 Q6AFE_LPASS_CORE_HW_MAC 183 Q6AFE_LPASS_CORE_HW_MACRO_BLOCK,
88 "LPASS_HW_MACRO"), 184 "LPASS_HW_MACRO"),
89 Q6DSP_VOTE_CLK(LPASS_HW_DCODEC_VOTE, !! 185 Q6AFE_VOTE_CLK(LPASS_HW_DCODEC_VOTE,
90 Q6AFE_LPASS_CORE_HW_DCO 186 Q6AFE_LPASS_CORE_HW_DCODEC_BLOCK,
91 "LPASS_HW_DCODEC"), 187 "LPASS_HW_DCODEC"),
92 }; 188 };
93 189
94 static const struct q6dsp_clk_desc q6dsp_clk_q !! 190 static struct clk_hw *q6afe_of_clk_hw_get(struct of_phandle_args *clkspec,
95 .clks = q6afe_clks, !! 191 void *data)
96 .num_clks = ARRAY_SIZE(q6afe_clks), !! 192 {
97 .lpass_set_clk = q6afe_set_lpass_clock !! 193 struct q6afe_cc *cc = data;
98 .lpass_vote_clk = q6afe_vote_lpass_cor !! 194 unsigned int idx = clkspec->args[0];
99 .lpass_unvote_clk = q6afe_unvote_lpass !! 195 unsigned int attr = clkspec->args[1];
100 }; !! 196
>> 197 if (idx >= Q6AFE_MAX_CLK_ID || attr > LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR) {
>> 198 dev_err(cc->dev, "Invalid clk specifier (%d, %d)\n", idx, attr);
>> 199 return ERR_PTR(-EINVAL);
>> 200 }
>> 201
>> 202 if (cc->clks[idx]) {
>> 203 cc->clks[idx]->attributes = attr;
>> 204 return &cc->clks[idx]->hw;
>> 205 }
>> 206
>> 207 return ERR_PTR(-ENOENT);
>> 208 }
>> 209
>> 210 static int q6afe_clock_dev_probe(struct platform_device *pdev)
>> 211 {
>> 212 struct q6afe_cc *cc;
>> 213 struct device *dev = &pdev->dev;
>> 214 int i, ret;
>> 215
>> 216 cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
>> 217 if (!cc)
>> 218 return -ENOMEM;
>> 219
>> 220 cc->dev = dev;
>> 221 for (i = 0; i < ARRAY_SIZE(q6afe_clks); i++) {
>> 222 unsigned int id = q6afe_clks[i].clk_id;
>> 223 struct clk_init_data init = {
>> 224 .name = q6afe_clks[i].name,
>> 225 };
>> 226 struct q6afe_clk *clk;
>> 227
>> 228 clk = devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL);
>> 229 if (!clk)
>> 230 return -ENOMEM;
>> 231
>> 232 clk->dev = dev;
>> 233 clk->afe_clk_id = q6afe_clks[i].afe_clk_id;
>> 234 clk->rate = q6afe_clks[i].rate;
>> 235 clk->hw.init = &init;
>> 236
>> 237 if (clk->rate)
>> 238 init.ops = &clk_q6afe_ops;
>> 239 else
>> 240 init.ops = &clk_vote_q6afe_ops;
>> 241
>> 242 cc->clks[id] = clk;
>> 243
>> 244 ret = devm_clk_hw_register(dev, &clk->hw);
>> 245 if (ret)
>> 246 return ret;
>> 247 }
>> 248
>> 249 ret = devm_of_clk_add_hw_provider(dev, q6afe_of_clk_hw_get, cc);
>> 250 if (ret)
>> 251 return ret;
>> 252
>> 253 dev_set_drvdata(dev, cc);
>> 254
>> 255 return 0;
>> 256 }
101 257
102 #ifdef CONFIG_OF 258 #ifdef CONFIG_OF
103 static const struct of_device_id q6afe_clock_d 259 static const struct of_device_id q6afe_clock_device_id[] = {
104 { .compatible = "qcom,q6afe-clocks", . !! 260 { .compatible = "qcom,q6afe-clocks" },
105 {}, 261 {},
106 }; 262 };
107 MODULE_DEVICE_TABLE(of, q6afe_clock_device_id) 263 MODULE_DEVICE_TABLE(of, q6afe_clock_device_id);
108 #endif 264 #endif
109 265
110 static struct platform_driver q6afe_clock_plat 266 static struct platform_driver q6afe_clock_platform_driver = {
111 .driver = { 267 .driver = {
112 .name = "q6afe-clock", 268 .name = "q6afe-clock",
113 .of_match_table = of_match_ptr 269 .of_match_table = of_match_ptr(q6afe_clock_device_id),
114 }, 270 },
115 .probe = q6dsp_clock_dev_probe, !! 271 .probe = q6afe_clock_dev_probe,
116 }; 272 };
117 module_platform_driver(q6afe_clock_platform_dr 273 module_platform_driver(q6afe_clock_platform_driver);
118 274
119 MODULE_DESCRIPTION("Q6 Audio Frontend clock dr 275 MODULE_DESCRIPTION("Q6 Audio Frontend clock driver");
120 MODULE_LICENSE("GPL v2"); 276 MODULE_LICENSE("GPL v2");
121 277
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