1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */
2 2
3 #ifndef __Q6AFE_H__ 3 #ifndef __Q6AFE_H__
4 #define __Q6AFE_H__ 4 #define __Q6AFE_H__
5 5
6 #define AFE_PORT_MAX 129 6 #define AFE_PORT_MAX 129
7 7
8 #define MSM_AFE_PORT_TYPE_RX 0 8 #define MSM_AFE_PORT_TYPE_RX 0
9 #define MSM_AFE_PORT_TYPE_TX 1 9 #define MSM_AFE_PORT_TYPE_TX 1
10 #define AFE_MAX_PORTS AFE_PORT_MAX 10 #define AFE_MAX_PORTS AFE_PORT_MAX
11 11
12 #define Q6AFE_MAX_MI2S_LINES 4 12 #define Q6AFE_MAX_MI2S_LINES 4
13 13
14 #define AFE_MAX_CHAN_COUNT 8 14 #define AFE_MAX_CHAN_COUNT 8
15 #define AFE_PORT_MAX_AUDIO_CHAN_CNT 0x8 15 #define AFE_PORT_MAX_AUDIO_CHAN_CNT 0x8
16 16
17 #define Q6AFE_LPASS_CLK_SRC_INTERNAL 1 17 #define Q6AFE_LPASS_CLK_SRC_INTERNAL 1
18 #define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0 18 #define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0
19 19
20 #define LPAIF_DIG_CLK 1 20 #define LPAIF_DIG_CLK 1
21 #define LPAIF_BIT_CLK 2 21 #define LPAIF_BIT_CLK 2
22 #define LPAIF_OSR_CLK 3 22 #define LPAIF_OSR_CLK 3
23 23
24 /* Clock ID for Primary I2S IBIT */ 24 /* Clock ID for Primary I2S IBIT */
25 #define Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT 25 #define Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT 0x100
26 /* Clock ID for Primary I2S EBIT */ 26 /* Clock ID for Primary I2S EBIT */
27 #define Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT 27 #define Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT 0x101
28 /* Clock ID for Secondary I2S IBIT */ 28 /* Clock ID for Secondary I2S IBIT */
29 #define Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT 29 #define Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT 0x102
30 /* Clock ID for Secondary I2S EBIT */ 30 /* Clock ID for Secondary I2S EBIT */
31 #define Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT 31 #define Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT 0x103
32 /* Clock ID for Tertiary I2S IBIT */ 32 /* Clock ID for Tertiary I2S IBIT */
33 #define Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT 33 #define Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT 0x104
34 /* Clock ID for Tertiary I2S EBIT */ 34 /* Clock ID for Tertiary I2S EBIT */
35 #define Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT 35 #define Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT 0x105
36 /* Clock ID for Quartnery I2S IBIT */ 36 /* Clock ID for Quartnery I2S IBIT */
37 #define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT 37 #define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT 0x106
38 /* Clock ID for Quartnery I2S EBIT */ 38 /* Clock ID for Quartnery I2S EBIT */
39 #define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT 39 #define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT 0x107
40 /* Clock ID for Speaker I2S IBIT */ 40 /* Clock ID for Speaker I2S IBIT */
41 #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_IBIT 41 #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_IBIT 0x108
42 /* Clock ID for Speaker I2S EBIT */ 42 /* Clock ID for Speaker I2S EBIT */
43 #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_EBIT 43 #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_EBIT 0x109
44 /* Clock ID for Speaker I2S OSR */ 44 /* Clock ID for Speaker I2S OSR */
45 #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_OSR 45 #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_OSR 0x10A
46 46
47 /* Clock ID for QUINARY I2S IBIT */ 47 /* Clock ID for QUINARY I2S IBIT */
48 #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT 48 #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT 0x10B
49 /* Clock ID for QUINARY I2S EBIT */ 49 /* Clock ID for QUINARY I2S EBIT */
50 #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT 50 #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT 0x10C
51 /* Clock ID for SENARY I2S IBIT */ 51 /* Clock ID for SENARY I2S IBIT */
52 #define Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT 52 #define Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT 0x10D
53 /* Clock ID for SENARY I2S EBIT */ 53 /* Clock ID for SENARY I2S EBIT */
54 #define Q6AFE_LPASS_CLK_ID_SEN_MI2S_EBIT 54 #define Q6AFE_LPASS_CLK_ID_SEN_MI2S_EBIT 0x10E
55 /* Clock ID for INT0 I2S IBIT */ 55 /* Clock ID for INT0 I2S IBIT */
56 #define Q6AFE_LPASS_CLK_ID_INT0_MI2S_IBIT 56 #define Q6AFE_LPASS_CLK_ID_INT0_MI2S_IBIT 0x10F
57 /* Clock ID for INT1 I2S IBIT */ 57 /* Clock ID for INT1 I2S IBIT */
58 #define Q6AFE_LPASS_CLK_ID_INT1_MI2S_IBIT 58 #define Q6AFE_LPASS_CLK_ID_INT1_MI2S_IBIT 0x110
59 /* Clock ID for INT2 I2S IBIT */ 59 /* Clock ID for INT2 I2S IBIT */
60 #define Q6AFE_LPASS_CLK_ID_INT2_MI2S_IBIT 60 #define Q6AFE_LPASS_CLK_ID_INT2_MI2S_IBIT 0x111
61 /* Clock ID for INT3 I2S IBIT */ 61 /* Clock ID for INT3 I2S IBIT */
62 #define Q6AFE_LPASS_CLK_ID_INT3_MI2S_IBIT 62 #define Q6AFE_LPASS_CLK_ID_INT3_MI2S_IBIT 0x112
63 /* Clock ID for INT4 I2S IBIT */ 63 /* Clock ID for INT4 I2S IBIT */
64 #define Q6AFE_LPASS_CLK_ID_INT4_MI2S_IBIT 64 #define Q6AFE_LPASS_CLK_ID_INT4_MI2S_IBIT 0x113
65 /* Clock ID for INT5 I2S IBIT */ 65 /* Clock ID for INT5 I2S IBIT */
66 #define Q6AFE_LPASS_CLK_ID_INT5_MI2S_IBIT 66 #define Q6AFE_LPASS_CLK_ID_INT5_MI2S_IBIT 0x114
67 /* Clock ID for INT6 I2S IBIT */ 67 /* Clock ID for INT6 I2S IBIT */
68 #define Q6AFE_LPASS_CLK_ID_INT6_MI2S_IBIT 68 #define Q6AFE_LPASS_CLK_ID_INT6_MI2S_IBIT 0x115
69 69
70 /* Clock ID for QUINARY MI2S OSR CLK */ 70 /* Clock ID for QUINARY MI2S OSR CLK */
71 #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR 71 #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR 0x116
72 72
73 /* Clock ID for Primary PCM IBIT */ 73 /* Clock ID for Primary PCM IBIT */
74 #define Q6AFE_LPASS_CLK_ID_PRI_PCM_IBIT 74 #define Q6AFE_LPASS_CLK_ID_PRI_PCM_IBIT 0x200
75 /* Clock ID for Primary PCM EBIT */ 75 /* Clock ID for Primary PCM EBIT */
76 #define Q6AFE_LPASS_CLK_ID_PRI_PCM_EBIT 76 #define Q6AFE_LPASS_CLK_ID_PRI_PCM_EBIT 0x201
77 /* Clock ID for Secondary PCM IBIT */ 77 /* Clock ID for Secondary PCM IBIT */
78 #define Q6AFE_LPASS_CLK_ID_SEC_PCM_IBIT 78 #define Q6AFE_LPASS_CLK_ID_SEC_PCM_IBIT 0x202
79 /* Clock ID for Secondary PCM EBIT */ 79 /* Clock ID for Secondary PCM EBIT */
80 #define Q6AFE_LPASS_CLK_ID_SEC_PCM_EBIT 80 #define Q6AFE_LPASS_CLK_ID_SEC_PCM_EBIT 0x203
81 /* Clock ID for Tertiary PCM IBIT */ 81 /* Clock ID for Tertiary PCM IBIT */
82 #define Q6AFE_LPASS_CLK_ID_TER_PCM_IBIT 82 #define Q6AFE_LPASS_CLK_ID_TER_PCM_IBIT 0x204
83 /* Clock ID for Tertiary PCM EBIT */ 83 /* Clock ID for Tertiary PCM EBIT */
84 #define Q6AFE_LPASS_CLK_ID_TER_PCM_EBIT 84 #define Q6AFE_LPASS_CLK_ID_TER_PCM_EBIT 0x205
85 /* Clock ID for Quartery PCM IBIT */ 85 /* Clock ID for Quartery PCM IBIT */
86 #define Q6AFE_LPASS_CLK_ID_QUAD_PCM_IBIT 86 #define Q6AFE_LPASS_CLK_ID_QUAD_PCM_IBIT 0x206
87 /* Clock ID for Quartery PCM EBIT */ 87 /* Clock ID for Quartery PCM EBIT */
88 #define Q6AFE_LPASS_CLK_ID_QUAD_PCM_EBIT 88 #define Q6AFE_LPASS_CLK_ID_QUAD_PCM_EBIT 0x207
89 /* Clock ID for Quinary PCM IBIT */ 89 /* Clock ID for Quinary PCM IBIT */
90 #define Q6AFE_LPASS_CLK_ID_QUIN_PCM_IBIT 90 #define Q6AFE_LPASS_CLK_ID_QUIN_PCM_IBIT 0x208
91 /* Clock ID for Quinary PCM EBIT */ 91 /* Clock ID for Quinary PCM EBIT */
92 #define Q6AFE_LPASS_CLK_ID_QUIN_PCM_EBIT 92 #define Q6AFE_LPASS_CLK_ID_QUIN_PCM_EBIT 0x209
93 /* Clock ID for QUINARY PCM OSR */ 93 /* Clock ID for QUINARY PCM OSR */
94 #define Q6AFE_LPASS_CLK_ID_QUI_PCM_OSR 94 #define Q6AFE_LPASS_CLK_ID_QUI_PCM_OSR 0x20A
95 95
96 /** Clock ID for Primary TDM IBIT */ 96 /** Clock ID for Primary TDM IBIT */
97 #define Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT 97 #define Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT 0x200
98 /** Clock ID for Primary TDM EBIT */ 98 /** Clock ID for Primary TDM EBIT */
99 #define Q6AFE_LPASS_CLK_ID_PRI_TDM_EBIT 99 #define Q6AFE_LPASS_CLK_ID_PRI_TDM_EBIT 0x201
100 /** Clock ID for Secondary TDM IBIT */ 100 /** Clock ID for Secondary TDM IBIT */
101 #define Q6AFE_LPASS_CLK_ID_SEC_TDM_IBIT 101 #define Q6AFE_LPASS_CLK_ID_SEC_TDM_IBIT 0x202
102 /** Clock ID for Secondary TDM EBIT */ 102 /** Clock ID for Secondary TDM EBIT */
103 #define Q6AFE_LPASS_CLK_ID_SEC_TDM_EBIT 103 #define Q6AFE_LPASS_CLK_ID_SEC_TDM_EBIT 0x203
104 /** Clock ID for Tertiary TDM IBIT */ 104 /** Clock ID for Tertiary TDM IBIT */
105 #define Q6AFE_LPASS_CLK_ID_TER_TDM_IBIT 105 #define Q6AFE_LPASS_CLK_ID_TER_TDM_IBIT 0x204
106 /** Clock ID for Tertiary TDM EBIT */ 106 /** Clock ID for Tertiary TDM EBIT */
107 #define Q6AFE_LPASS_CLK_ID_TER_TDM_EBIT 107 #define Q6AFE_LPASS_CLK_ID_TER_TDM_EBIT 0x205
108 /** Clock ID for Quartery TDM IBIT */ 108 /** Clock ID for Quartery TDM IBIT */
109 #define Q6AFE_LPASS_CLK_ID_QUAD_TDM_IBIT 109 #define Q6AFE_LPASS_CLK_ID_QUAD_TDM_IBIT 0x206
110 /** Clock ID for Quartery TDM EBIT */ 110 /** Clock ID for Quartery TDM EBIT */
111 #define Q6AFE_LPASS_CLK_ID_QUAD_TDM_EBIT 111 #define Q6AFE_LPASS_CLK_ID_QUAD_TDM_EBIT 0x207
112 /** Clock ID for Quinary TDM IBIT */ 112 /** Clock ID for Quinary TDM IBIT */
113 #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_IBIT 113 #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_IBIT 0x208
114 /** Clock ID for Quinary TDM EBIT */ 114 /** Clock ID for Quinary TDM EBIT */
115 #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT 115 #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT 0x209
116 /** Clock ID for Quinary TDM OSR */ 116 /** Clock ID for Quinary TDM OSR */
117 #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_OSR 117 #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_OSR 0x20A
118 118
119 /* Clock ID for MCLK1 */ 119 /* Clock ID for MCLK1 */
120 #define Q6AFE_LPASS_CLK_ID_MCLK_1 120 #define Q6AFE_LPASS_CLK_ID_MCLK_1 0x300
121 /* Clock ID for MCLK2 */ 121 /* Clock ID for MCLK2 */
122 #define Q6AFE_LPASS_CLK_ID_MCLK_2 122 #define Q6AFE_LPASS_CLK_ID_MCLK_2 0x301
123 /* Clock ID for MCLK3 */ 123 /* Clock ID for MCLK3 */
124 #define Q6AFE_LPASS_CLK_ID_MCLK_3 124 #define Q6AFE_LPASS_CLK_ID_MCLK_3 0x302
125 /* Clock ID for MCLK4 */ 125 /* Clock ID for MCLK4 */
126 #define Q6AFE_LPASS_CLK_ID_MCLK_4 126 #define Q6AFE_LPASS_CLK_ID_MCLK_4 0x304
127 /* Clock ID for Internal Digital Codec Core */ 127 /* Clock ID for Internal Digital Codec Core */
128 #define Q6AFE_LPASS_CLK_ID_INTERNAL_DIGITAL_CO 128 #define Q6AFE_LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 0x303
129 /* Clock ID for INT MCLK0 */ 129 /* Clock ID for INT MCLK0 */
130 #define Q6AFE_LPASS_CLK_ID_INT_MCLK_0 130 #define Q6AFE_LPASS_CLK_ID_INT_MCLK_0 0x305
131 /* Clock ID for INT MCLK1 */ 131 /* Clock ID for INT MCLK1 */
132 #define Q6AFE_LPASS_CLK_ID_INT_MCLK_1 132 #define Q6AFE_LPASS_CLK_ID_INT_MCLK_1 0x306
133 133
134 #define Q6AFE_LPASS_CLK_ID_WSA_CORE_MCLK 134 #define Q6AFE_LPASS_CLK_ID_WSA_CORE_MCLK 0x309
135 #define Q6AFE_LPASS_CLK_ID_WSA_CORE_NPL_MCLK 135 #define Q6AFE_LPASS_CLK_ID_WSA_CORE_NPL_MCLK 0x30a
136 #define Q6AFE_LPASS_CLK_ID_TX_CORE_MCLK 136 #define Q6AFE_LPASS_CLK_ID_TX_CORE_MCLK 0x30c
137 #define Q6AFE_LPASS_CLK_ID_TX_CORE_NPL_MCLK 137 #define Q6AFE_LPASS_CLK_ID_TX_CORE_NPL_MCLK 0x30d
138 #define Q6AFE_LPASS_CLK_ID_RX_CORE_MCLK 138 #define Q6AFE_LPASS_CLK_ID_RX_CORE_MCLK 0x30e
139 #define Q6AFE_LPASS_CLK_ID_RX_CORE_NPL_MCLK 139 #define Q6AFE_LPASS_CLK_ID_RX_CORE_NPL_MCLK 0x30f
140 #define Q6AFE_LPASS_CLK_ID_VA_CORE_MCLK 140 #define Q6AFE_LPASS_CLK_ID_VA_CORE_MCLK 0x30b
141 #define Q6AFE_LPASS_CLK_ID_VA_CORE_2X_MCLK 141 #define Q6AFE_LPASS_CLK_ID_VA_CORE_2X_MCLK 0x310
142 142
143 #define Q6AFE_LPASS_CORE_AVTIMER_BLOCK 143 #define Q6AFE_LPASS_CORE_AVTIMER_BLOCK 0x2
144 #define Q6AFE_LPASS_CORE_HW_MACRO_BLOCK 144 #define Q6AFE_LPASS_CORE_HW_MACRO_BLOCK 0x3
145 #define Q6AFE_LPASS_CORE_HW_DCODEC_BLOCK 145 #define Q6AFE_LPASS_CORE_HW_DCODEC_BLOCK 0x4
146 146
147 /* Clock attribute for invalid use (reserved f 147 /* Clock attribute for invalid use (reserved for internal usage) */
148 #define Q6AFE_LPASS_CLK_ATTRIBUTE_INVALID 148 #define Q6AFE_LPASS_CLK_ATTRIBUTE_INVALID 0x0
149 /* Clock attribute for no couple case */ 149 /* Clock attribute for no couple case */
150 #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO 150 #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1
151 /* Clock attribute for dividend couple case */ 151 /* Clock attribute for dividend couple case */
152 #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVID 152 #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2
153 /* Clock attribute for divisor couple case */ 153 /* Clock attribute for divisor couple case */
154 #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVIS 154 #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3
155 /* Clock attribute for invert and no couple ca 155 /* Clock attribute for invert and no couple case */
156 #define Q6AFE_LPASS_CLK_ATTRIBUTE_INVERT_COUPL 156 #define Q6AFE_LPASS_CLK_ATTRIBUTE_INVERT_COUPLE_NO 0x4
157 157
158 #define Q6AFE_CMAP_INVALID 0xFFFF 158 #define Q6AFE_CMAP_INVALID 0xFFFF
159 159
160 struct q6afe_hdmi_cfg { 160 struct q6afe_hdmi_cfg {
161 u16 datatype; 161 u16 datatype;
162 u16 channel_allocatio 162 u16 channel_allocation;
163 u32 sample_rate; 163 u32 sample_rate;
164 u16 bit_width; 164 u16 bit_width;
165 }; 165 };
166 166
167 struct q6afe_slim_cfg { 167 struct q6afe_slim_cfg {
168 u32 sample_rate; 168 u32 sample_rate;
169 u16 bit_width; 169 u16 bit_width;
170 u16 data_format; 170 u16 data_format;
171 u16 num_channels; 171 u16 num_channels;
172 u8 ch_mapping[AFE_MAX_CHAN_COUNT] 172 u8 ch_mapping[AFE_MAX_CHAN_COUNT];
173 }; 173 };
174 174
175 struct q6afe_i2s_cfg { 175 struct q6afe_i2s_cfg {
176 u32 sample_rate; 176 u32 sample_rate;
177 u16 bit_width; 177 u16 bit_width;
178 u16 data_format; 178 u16 data_format;
179 u16 num_channels; 179 u16 num_channels;
180 u32 sd_line_mask; 180 u32 sd_line_mask;
181 int fmt; 181 int fmt;
182 }; 182 };
183 183
184 struct q6afe_tdm_cfg { 184 struct q6afe_tdm_cfg {
185 u16 num_channels; 185 u16 num_channels;
186 u32 sample_rate; 186 u32 sample_rate;
187 u16 bit_width; 187 u16 bit_width;
188 u16 data_format; 188 u16 data_format;
189 u16 sync_mode; 189 u16 sync_mode;
190 u16 sync_src; 190 u16 sync_src;
191 u16 nslots_per_frame; 191 u16 nslots_per_frame;
192 u16 slot_width; 192 u16 slot_width;
193 u16 slot_mask; 193 u16 slot_mask;
194 u32 data_align_type; 194 u32 data_align_type;
195 u16 ch_mapping[AFE_MAX_CHAN_COUNT] 195 u16 ch_mapping[AFE_MAX_CHAN_COUNT];
196 }; 196 };
197 197
198 struct q6afe_cdc_dma_cfg { 198 struct q6afe_cdc_dma_cfg {
199 u16 sample_rate; 199 u16 sample_rate;
200 u16 bit_width; 200 u16 bit_width;
201 u16 data_format; 201 u16 data_format;
202 u16 num_channels; 202 u16 num_channels;
203 u16 active_channels_mask; 203 u16 active_channels_mask;
204 }; 204 };
205 205
206 206
207 struct q6afe_port_config { 207 struct q6afe_port_config {
208 struct q6afe_hdmi_cfg hdmi; 208 struct q6afe_hdmi_cfg hdmi;
209 struct q6afe_slim_cfg slim; 209 struct q6afe_slim_cfg slim;
210 struct q6afe_i2s_cfg i2s_cfg; 210 struct q6afe_i2s_cfg i2s_cfg;
211 struct q6afe_tdm_cfg tdm; 211 struct q6afe_tdm_cfg tdm;
212 struct q6afe_cdc_dma_cfg dma_cfg; 212 struct q6afe_cdc_dma_cfg dma_cfg;
213 }; 213 };
214 214
215 struct q6afe_port; 215 struct q6afe_port;
216 216
217 struct q6afe_port *q6afe_port_get_from_id(stru 217 struct q6afe_port *q6afe_port_get_from_id(struct device *dev, int id);
218 int q6afe_port_start(struct q6afe_port *port); 218 int q6afe_port_start(struct q6afe_port *port);
219 int q6afe_port_stop(struct q6afe_port *port); 219 int q6afe_port_stop(struct q6afe_port *port);
220 void q6afe_port_put(struct q6afe_port *port); 220 void q6afe_port_put(struct q6afe_port *port);
221 int q6afe_get_port_id(int index); 221 int q6afe_get_port_id(int index);
222 void q6afe_hdmi_port_prepare(struct q6afe_port 222 void q6afe_hdmi_port_prepare(struct q6afe_port *port,
223 struct q6afe_hdmi_ 223 struct q6afe_hdmi_cfg *cfg);
224 void q6afe_slim_port_prepare(struct q6afe_port 224 void q6afe_slim_port_prepare(struct q6afe_port *port,
225 struct q6afe_slim_cf 225 struct q6afe_slim_cfg *cfg);
226 int q6afe_i2s_port_prepare(struct q6afe_port * 226 int q6afe_i2s_port_prepare(struct q6afe_port *port, struct q6afe_i2s_cfg *cfg);
227 void q6afe_tdm_port_prepare(struct q6afe_port 227 void q6afe_tdm_port_prepare(struct q6afe_port *port, struct q6afe_tdm_cfg *cfg);
228 void q6afe_cdc_dma_port_prepare(struct q6afe_p 228 void q6afe_cdc_dma_port_prepare(struct q6afe_port *port,
229 struct q6afe_c 229 struct q6afe_cdc_dma_cfg *cfg);
230 230
231 int q6afe_port_set_sysclk(struct q6afe_port *p 231 int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id,
232 int clk_src, int clk 232 int clk_src, int clk_root,
233 unsigned int freq, i 233 unsigned int freq, int dir);
234 int q6afe_set_lpass_clock(struct device *dev, 234 int q6afe_set_lpass_clock(struct device *dev, int clk_id, int attri,
235 int clk_root, unsign 235 int clk_root, unsigned int freq);
236 int q6afe_vote_lpass_core_hw(struct device *de 236 int q6afe_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
237 const char *clien 237 const char *client_name, uint32_t *client_handle);
238 int q6afe_unvote_lpass_core_hw(struct device * 238 int q6afe_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
239 uint32_t client 239 uint32_t client_handle);
240 #endif /* __Q6AFE_H__ */ 240 #endif /* __Q6AFE_H__ */
241 241
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