1 /* SPDX-License-Identifier: GPL-2.0 */ 1
2
3 #ifndef __Q6AFE_H__
4 #define __Q6AFE_H__
5
6 #define AFE_PORT_MAX 129
7
8 #define MSM_AFE_PORT_TYPE_RX 0
9 #define MSM_AFE_PORT_TYPE_TX 1
10 #define AFE_MAX_PORTS AFE_PORT_MAX
11
12 #define Q6AFE_MAX_MI2S_LINES 4
13
14 #define AFE_MAX_CHAN_COUNT 8
15 #define AFE_PORT_MAX_AUDIO_CHAN_CNT 0x8
16
17 #define Q6AFE_LPASS_CLK_SRC_INTERNAL 1
18 #define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0
19
20 #define LPAIF_DIG_CLK 1
21 #define LPAIF_BIT_CLK 2
22 #define LPAIF_OSR_CLK 3
23
24 /* Clock ID for Primary I2S IBIT */
25 #define Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT
26 /* Clock ID for Primary I2S EBIT */
27 #define Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT
28 /* Clock ID for Secondary I2S IBIT */
29 #define Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT
30 /* Clock ID for Secondary I2S EBIT */
31 #define Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT
32 /* Clock ID for Tertiary I2S IBIT */
33 #define Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT
34 /* Clock ID for Tertiary I2S EBIT */
35 #define Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT
36 /* Clock ID for Quartnery I2S IBIT */
37 #define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT
38 /* Clock ID for Quartnery I2S EBIT */
39 #define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT
40 /* Clock ID for Speaker I2S IBIT */
41 #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_IBIT
42 /* Clock ID for Speaker I2S EBIT */
43 #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_EBIT
44 /* Clock ID for Speaker I2S OSR */
45 #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_OSR
46
47 /* Clock ID for QUINARY I2S IBIT */
48 #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT
49 /* Clock ID for QUINARY I2S EBIT */
50 #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT
51 /* Clock ID for SENARY I2S IBIT */
52 #define Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT
53 /* Clock ID for SENARY I2S EBIT */
54 #define Q6AFE_LPASS_CLK_ID_SEN_MI2S_EBIT
55 /* Clock ID for INT0 I2S IBIT */
56 #define Q6AFE_LPASS_CLK_ID_INT0_MI2S_IBIT
57 /* Clock ID for INT1 I2S IBIT */
58 #define Q6AFE_LPASS_CLK_ID_INT1_MI2S_IBIT
59 /* Clock ID for INT2 I2S IBIT */
60 #define Q6AFE_LPASS_CLK_ID_INT2_MI2S_IBIT
61 /* Clock ID for INT3 I2S IBIT */
62 #define Q6AFE_LPASS_CLK_ID_INT3_MI2S_IBIT
63 /* Clock ID for INT4 I2S IBIT */
64 #define Q6AFE_LPASS_CLK_ID_INT4_MI2S_IBIT
65 /* Clock ID for INT5 I2S IBIT */
66 #define Q6AFE_LPASS_CLK_ID_INT5_MI2S_IBIT
67 /* Clock ID for INT6 I2S IBIT */
68 #define Q6AFE_LPASS_CLK_ID_INT6_MI2S_IBIT
69
70 /* Clock ID for QUINARY MI2S OSR CLK */
71 #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR
72
73 /* Clock ID for Primary PCM IBIT */
74 #define Q6AFE_LPASS_CLK_ID_PRI_PCM_IBIT
75 /* Clock ID for Primary PCM EBIT */
76 #define Q6AFE_LPASS_CLK_ID_PRI_PCM_EBIT
77 /* Clock ID for Secondary PCM IBIT */
78 #define Q6AFE_LPASS_CLK_ID_SEC_PCM_IBIT
79 /* Clock ID for Secondary PCM EBIT */
80 #define Q6AFE_LPASS_CLK_ID_SEC_PCM_EBIT
81 /* Clock ID for Tertiary PCM IBIT */
82 #define Q6AFE_LPASS_CLK_ID_TER_PCM_IBIT
83 /* Clock ID for Tertiary PCM EBIT */
84 #define Q6AFE_LPASS_CLK_ID_TER_PCM_EBIT
85 /* Clock ID for Quartery PCM IBIT */
86 #define Q6AFE_LPASS_CLK_ID_QUAD_PCM_IBIT
87 /* Clock ID for Quartery PCM EBIT */
88 #define Q6AFE_LPASS_CLK_ID_QUAD_PCM_EBIT
89 /* Clock ID for Quinary PCM IBIT */
90 #define Q6AFE_LPASS_CLK_ID_QUIN_PCM_IBIT
91 /* Clock ID for Quinary PCM EBIT */
92 #define Q6AFE_LPASS_CLK_ID_QUIN_PCM_EBIT
93 /* Clock ID for QUINARY PCM OSR */
94 #define Q6AFE_LPASS_CLK_ID_QUI_PCM_OSR
95
96 /** Clock ID for Primary TDM IBIT */
97 #define Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT
98 /** Clock ID for Primary TDM EBIT */
99 #define Q6AFE_LPASS_CLK_ID_PRI_TDM_EBIT
100 /** Clock ID for Secondary TDM IBIT */
101 #define Q6AFE_LPASS_CLK_ID_SEC_TDM_IBIT
102 /** Clock ID for Secondary TDM EBIT */
103 #define Q6AFE_LPASS_CLK_ID_SEC_TDM_EBIT
104 /** Clock ID for Tertiary TDM IBIT */
105 #define Q6AFE_LPASS_CLK_ID_TER_TDM_IBIT
106 /** Clock ID for Tertiary TDM EBIT */
107 #define Q6AFE_LPASS_CLK_ID_TER_TDM_EBIT
108 /** Clock ID for Quartery TDM IBIT */
109 #define Q6AFE_LPASS_CLK_ID_QUAD_TDM_IBIT
110 /** Clock ID for Quartery TDM EBIT */
111 #define Q6AFE_LPASS_CLK_ID_QUAD_TDM_EBIT
112 /** Clock ID for Quinary TDM IBIT */
113 #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_IBIT
114 /** Clock ID for Quinary TDM EBIT */
115 #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT
116 /** Clock ID for Quinary TDM OSR */
117 #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_OSR
118
119 /* Clock ID for MCLK1 */
120 #define Q6AFE_LPASS_CLK_ID_MCLK_1
121 /* Clock ID for MCLK2 */
122 #define Q6AFE_LPASS_CLK_ID_MCLK_2
123 /* Clock ID for MCLK3 */
124 #define Q6AFE_LPASS_CLK_ID_MCLK_3
125 /* Clock ID for MCLK4 */
126 #define Q6AFE_LPASS_CLK_ID_MCLK_4
127 /* Clock ID for Internal Digital Codec Core */
128 #define Q6AFE_LPASS_CLK_ID_INTERNAL_DIGITAL_CO
129 /* Clock ID for INT MCLK0 */
130 #define Q6AFE_LPASS_CLK_ID_INT_MCLK_0
131 /* Clock ID for INT MCLK1 */
132 #define Q6AFE_LPASS_CLK_ID_INT_MCLK_1
133
134 #define Q6AFE_LPASS_CLK_ID_WSA_CORE_MCLK
135 #define Q6AFE_LPASS_CLK_ID_WSA_CORE_NPL_MCLK
136 #define Q6AFE_LPASS_CLK_ID_TX_CORE_MCLK
137 #define Q6AFE_LPASS_CLK_ID_TX_CORE_NPL_MCLK
138 #define Q6AFE_LPASS_CLK_ID_RX_CORE_MCLK
139 #define Q6AFE_LPASS_CLK_ID_RX_CORE_NPL_MCLK
140 #define Q6AFE_LPASS_CLK_ID_VA_CORE_MCLK
141 #define Q6AFE_LPASS_CLK_ID_VA_CORE_2X_MCLK
142
143 #define Q6AFE_LPASS_CORE_AVTIMER_BLOCK
144 #define Q6AFE_LPASS_CORE_HW_MACRO_BLOCK
145 #define Q6AFE_LPASS_CORE_HW_DCODEC_BLOCK
146
147 /* Clock attribute for invalid use (reserved f
148 #define Q6AFE_LPASS_CLK_ATTRIBUTE_INVALID
149 /* Clock attribute for no couple case */
150 #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO
151 /* Clock attribute for dividend couple case */
152 #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVID
153 /* Clock attribute for divisor couple case */
154 #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVIS
155 /* Clock attribute for invert and no couple ca
156 #define Q6AFE_LPASS_CLK_ATTRIBUTE_INVERT_COUPL
157
158 #define Q6AFE_CMAP_INVALID 0xFFFF
159
160 struct q6afe_hdmi_cfg {
161 u16 datatype;
162 u16 channel_allocatio
163 u32 sample_rate;
164 u16 bit_width;
165 };
166
167 struct q6afe_slim_cfg {
168 u32 sample_rate;
169 u16 bit_width;
170 u16 data_format;
171 u16 num_channels;
172 u8 ch_mapping[AFE_MAX_CHAN_COUNT]
173 };
174
175 struct q6afe_i2s_cfg {
176 u32 sample_rate;
177 u16 bit_width;
178 u16 data_format;
179 u16 num_channels;
180 u32 sd_line_mask;
181 int fmt;
182 };
183
184 struct q6afe_tdm_cfg {
185 u16 num_channels;
186 u32 sample_rate;
187 u16 bit_width;
188 u16 data_format;
189 u16 sync_mode;
190 u16 sync_src;
191 u16 nslots_per_frame;
192 u16 slot_width;
193 u16 slot_mask;
194 u32 data_align_type;
195 u16 ch_mapping[AFE_MAX_CHAN_COUNT]
196 };
197
198 struct q6afe_cdc_dma_cfg {
199 u16 sample_rate;
200 u16 bit_width;
201 u16 data_format;
202 u16 num_channels;
203 u16 active_channels_mask;
204 };
205
206
207 struct q6afe_port_config {
208 struct q6afe_hdmi_cfg hdmi;
209 struct q6afe_slim_cfg slim;
210 struct q6afe_i2s_cfg i2s_cfg;
211 struct q6afe_tdm_cfg tdm;
212 struct q6afe_cdc_dma_cfg dma_cfg;
213 };
214
215 struct q6afe_port;
216
217 struct q6afe_port *q6afe_port_get_from_id(stru
218 int q6afe_port_start(struct q6afe_port *port);
219 int q6afe_port_stop(struct q6afe_port *port);
220 void q6afe_port_put(struct q6afe_port *port);
221 int q6afe_get_port_id(int index);
222 void q6afe_hdmi_port_prepare(struct q6afe_port
223 struct q6afe_hdmi_
224 void q6afe_slim_port_prepare(struct q6afe_port
225 struct q6afe_slim_cf
226 int q6afe_i2s_port_prepare(struct q6afe_port *
227 void q6afe_tdm_port_prepare(struct q6afe_port
228 void q6afe_cdc_dma_port_prepare(struct q6afe_p
229 struct q6afe_c
230
231 int q6afe_port_set_sysclk(struct q6afe_port *p
232 int clk_src, int clk
233 unsigned int freq, i
234 int q6afe_set_lpass_clock(struct device *dev,
235 int clk_root, unsign
236 int q6afe_vote_lpass_core_hw(struct device *de
237 const char *clien
238 int q6afe_unvote_lpass_core_hw(struct device *
239 uint32_t client
240 #endif /* __Q6AFE_H__ */
241
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