1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */
2 2
3 #ifndef __Q6AFE_H__ 3 #ifndef __Q6AFE_H__
4 #define __Q6AFE_H__ 4 #define __Q6AFE_H__
5 5
6 #define AFE_PORT_MAX 129 !! 6 #include <dt-bindings/sound/qcom,q6afe.h>
>> 7
>> 8 #define AFE_PORT_MAX 105
7 9
8 #define MSM_AFE_PORT_TYPE_RX 0 10 #define MSM_AFE_PORT_TYPE_RX 0
9 #define MSM_AFE_PORT_TYPE_TX 1 11 #define MSM_AFE_PORT_TYPE_TX 1
10 #define AFE_MAX_PORTS AFE_PORT_MAX 12 #define AFE_MAX_PORTS AFE_PORT_MAX
11 13
12 #define Q6AFE_MAX_MI2S_LINES 4 14 #define Q6AFE_MAX_MI2S_LINES 4
13 15
14 #define AFE_MAX_CHAN_COUNT 8 16 #define AFE_MAX_CHAN_COUNT 8
15 #define AFE_PORT_MAX_AUDIO_CHAN_CNT 0x8 17 #define AFE_PORT_MAX_AUDIO_CHAN_CNT 0x8
16 18
17 #define Q6AFE_LPASS_CLK_SRC_INTERNAL 1 19 #define Q6AFE_LPASS_CLK_SRC_INTERNAL 1
18 #define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0 20 #define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0
19 21
20 #define LPAIF_DIG_CLK 1 22 #define LPAIF_DIG_CLK 1
21 #define LPAIF_BIT_CLK 2 23 #define LPAIF_BIT_CLK 2
22 #define LPAIF_OSR_CLK 3 24 #define LPAIF_OSR_CLK 3
23 25
24 /* Clock ID for Primary I2S IBIT */ 26 /* Clock ID for Primary I2S IBIT */
25 #define Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT 27 #define Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT 0x100
26 /* Clock ID for Primary I2S EBIT */ 28 /* Clock ID for Primary I2S EBIT */
27 #define Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT 29 #define Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT 0x101
28 /* Clock ID for Secondary I2S IBIT */ 30 /* Clock ID for Secondary I2S IBIT */
29 #define Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT 31 #define Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT 0x102
30 /* Clock ID for Secondary I2S EBIT */ 32 /* Clock ID for Secondary I2S EBIT */
31 #define Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT 33 #define Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT 0x103
32 /* Clock ID for Tertiary I2S IBIT */ 34 /* Clock ID for Tertiary I2S IBIT */
33 #define Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT 35 #define Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT 0x104
34 /* Clock ID for Tertiary I2S EBIT */ 36 /* Clock ID for Tertiary I2S EBIT */
35 #define Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT 37 #define Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT 0x105
36 /* Clock ID for Quartnery I2S IBIT */ 38 /* Clock ID for Quartnery I2S IBIT */
37 #define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT 39 #define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT 0x106
38 /* Clock ID for Quartnery I2S EBIT */ 40 /* Clock ID for Quartnery I2S EBIT */
39 #define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT 41 #define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT 0x107
40 /* Clock ID for Speaker I2S IBIT */ 42 /* Clock ID for Speaker I2S IBIT */
41 #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_IBIT 43 #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_IBIT 0x108
42 /* Clock ID for Speaker I2S EBIT */ 44 /* Clock ID for Speaker I2S EBIT */
43 #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_EBIT 45 #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_EBIT 0x109
44 /* Clock ID for Speaker I2S OSR */ 46 /* Clock ID for Speaker I2S OSR */
45 #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_OSR 47 #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_OSR 0x10A
46 48
47 /* Clock ID for QUINARY I2S IBIT */ 49 /* Clock ID for QUINARY I2S IBIT */
48 #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT 50 #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT 0x10B
49 /* Clock ID for QUINARY I2S EBIT */ 51 /* Clock ID for QUINARY I2S EBIT */
50 #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT 52 #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT 0x10C
51 /* Clock ID for SENARY I2S IBIT */ 53 /* Clock ID for SENARY I2S IBIT */
52 #define Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT 54 #define Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT 0x10D
53 /* Clock ID for SENARY I2S EBIT */ 55 /* Clock ID for SENARY I2S EBIT */
54 #define Q6AFE_LPASS_CLK_ID_SEN_MI2S_EBIT 56 #define Q6AFE_LPASS_CLK_ID_SEN_MI2S_EBIT 0x10E
55 /* Clock ID for INT0 I2S IBIT */ 57 /* Clock ID for INT0 I2S IBIT */
56 #define Q6AFE_LPASS_CLK_ID_INT0_MI2S_IBIT 58 #define Q6AFE_LPASS_CLK_ID_INT0_MI2S_IBIT 0x10F
57 /* Clock ID for INT1 I2S IBIT */ 59 /* Clock ID for INT1 I2S IBIT */
58 #define Q6AFE_LPASS_CLK_ID_INT1_MI2S_IBIT 60 #define Q6AFE_LPASS_CLK_ID_INT1_MI2S_IBIT 0x110
59 /* Clock ID for INT2 I2S IBIT */ 61 /* Clock ID for INT2 I2S IBIT */
60 #define Q6AFE_LPASS_CLK_ID_INT2_MI2S_IBIT 62 #define Q6AFE_LPASS_CLK_ID_INT2_MI2S_IBIT 0x111
61 /* Clock ID for INT3 I2S IBIT */ 63 /* Clock ID for INT3 I2S IBIT */
62 #define Q6AFE_LPASS_CLK_ID_INT3_MI2S_IBIT 64 #define Q6AFE_LPASS_CLK_ID_INT3_MI2S_IBIT 0x112
63 /* Clock ID for INT4 I2S IBIT */ 65 /* Clock ID for INT4 I2S IBIT */
64 #define Q6AFE_LPASS_CLK_ID_INT4_MI2S_IBIT 66 #define Q6AFE_LPASS_CLK_ID_INT4_MI2S_IBIT 0x113
65 /* Clock ID for INT5 I2S IBIT */ 67 /* Clock ID for INT5 I2S IBIT */
66 #define Q6AFE_LPASS_CLK_ID_INT5_MI2S_IBIT 68 #define Q6AFE_LPASS_CLK_ID_INT5_MI2S_IBIT 0x114
67 /* Clock ID for INT6 I2S IBIT */ 69 /* Clock ID for INT6 I2S IBIT */
68 #define Q6AFE_LPASS_CLK_ID_INT6_MI2S_IBIT 70 #define Q6AFE_LPASS_CLK_ID_INT6_MI2S_IBIT 0x115
69 71
70 /* Clock ID for QUINARY MI2S OSR CLK */ 72 /* Clock ID for QUINARY MI2S OSR CLK */
71 #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR 73 #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR 0x116
72 74
73 /* Clock ID for Primary PCM IBIT */ 75 /* Clock ID for Primary PCM IBIT */
74 #define Q6AFE_LPASS_CLK_ID_PRI_PCM_IBIT 76 #define Q6AFE_LPASS_CLK_ID_PRI_PCM_IBIT 0x200
75 /* Clock ID for Primary PCM EBIT */ 77 /* Clock ID for Primary PCM EBIT */
76 #define Q6AFE_LPASS_CLK_ID_PRI_PCM_EBIT 78 #define Q6AFE_LPASS_CLK_ID_PRI_PCM_EBIT 0x201
77 /* Clock ID for Secondary PCM IBIT */ 79 /* Clock ID for Secondary PCM IBIT */
78 #define Q6AFE_LPASS_CLK_ID_SEC_PCM_IBIT 80 #define Q6AFE_LPASS_CLK_ID_SEC_PCM_IBIT 0x202
79 /* Clock ID for Secondary PCM EBIT */ 81 /* Clock ID for Secondary PCM EBIT */
80 #define Q6AFE_LPASS_CLK_ID_SEC_PCM_EBIT 82 #define Q6AFE_LPASS_CLK_ID_SEC_PCM_EBIT 0x203
81 /* Clock ID for Tertiary PCM IBIT */ 83 /* Clock ID for Tertiary PCM IBIT */
82 #define Q6AFE_LPASS_CLK_ID_TER_PCM_IBIT 84 #define Q6AFE_LPASS_CLK_ID_TER_PCM_IBIT 0x204
83 /* Clock ID for Tertiary PCM EBIT */ 85 /* Clock ID for Tertiary PCM EBIT */
84 #define Q6AFE_LPASS_CLK_ID_TER_PCM_EBIT 86 #define Q6AFE_LPASS_CLK_ID_TER_PCM_EBIT 0x205
85 /* Clock ID for Quartery PCM IBIT */ 87 /* Clock ID for Quartery PCM IBIT */
86 #define Q6AFE_LPASS_CLK_ID_QUAD_PCM_IBIT 88 #define Q6AFE_LPASS_CLK_ID_QUAD_PCM_IBIT 0x206
87 /* Clock ID for Quartery PCM EBIT */ 89 /* Clock ID for Quartery PCM EBIT */
88 #define Q6AFE_LPASS_CLK_ID_QUAD_PCM_EBIT 90 #define Q6AFE_LPASS_CLK_ID_QUAD_PCM_EBIT 0x207
89 /* Clock ID for Quinary PCM IBIT */ 91 /* Clock ID for Quinary PCM IBIT */
90 #define Q6AFE_LPASS_CLK_ID_QUIN_PCM_IBIT 92 #define Q6AFE_LPASS_CLK_ID_QUIN_PCM_IBIT 0x208
91 /* Clock ID for Quinary PCM EBIT */ 93 /* Clock ID for Quinary PCM EBIT */
92 #define Q6AFE_LPASS_CLK_ID_QUIN_PCM_EBIT 94 #define Q6AFE_LPASS_CLK_ID_QUIN_PCM_EBIT 0x209
93 /* Clock ID for QUINARY PCM OSR */ 95 /* Clock ID for QUINARY PCM OSR */
94 #define Q6AFE_LPASS_CLK_ID_QUI_PCM_OSR 96 #define Q6AFE_LPASS_CLK_ID_QUI_PCM_OSR 0x20A
95 97
96 /** Clock ID for Primary TDM IBIT */ 98 /** Clock ID for Primary TDM IBIT */
97 #define Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT 99 #define Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT 0x200
98 /** Clock ID for Primary TDM EBIT */ 100 /** Clock ID for Primary TDM EBIT */
99 #define Q6AFE_LPASS_CLK_ID_PRI_TDM_EBIT 101 #define Q6AFE_LPASS_CLK_ID_PRI_TDM_EBIT 0x201
100 /** Clock ID for Secondary TDM IBIT */ 102 /** Clock ID for Secondary TDM IBIT */
101 #define Q6AFE_LPASS_CLK_ID_SEC_TDM_IBIT 103 #define Q6AFE_LPASS_CLK_ID_SEC_TDM_IBIT 0x202
102 /** Clock ID for Secondary TDM EBIT */ 104 /** Clock ID for Secondary TDM EBIT */
103 #define Q6AFE_LPASS_CLK_ID_SEC_TDM_EBIT 105 #define Q6AFE_LPASS_CLK_ID_SEC_TDM_EBIT 0x203
104 /** Clock ID for Tertiary TDM IBIT */ 106 /** Clock ID for Tertiary TDM IBIT */
105 #define Q6AFE_LPASS_CLK_ID_TER_TDM_IBIT 107 #define Q6AFE_LPASS_CLK_ID_TER_TDM_IBIT 0x204
106 /** Clock ID for Tertiary TDM EBIT */ 108 /** Clock ID for Tertiary TDM EBIT */
107 #define Q6AFE_LPASS_CLK_ID_TER_TDM_EBIT 109 #define Q6AFE_LPASS_CLK_ID_TER_TDM_EBIT 0x205
108 /** Clock ID for Quartery TDM IBIT */ 110 /** Clock ID for Quartery TDM IBIT */
109 #define Q6AFE_LPASS_CLK_ID_QUAD_TDM_IBIT 111 #define Q6AFE_LPASS_CLK_ID_QUAD_TDM_IBIT 0x206
110 /** Clock ID for Quartery TDM EBIT */ 112 /** Clock ID for Quartery TDM EBIT */
111 #define Q6AFE_LPASS_CLK_ID_QUAD_TDM_EBIT 113 #define Q6AFE_LPASS_CLK_ID_QUAD_TDM_EBIT 0x207
112 /** Clock ID for Quinary TDM IBIT */ 114 /** Clock ID for Quinary TDM IBIT */
113 #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_IBIT 115 #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_IBIT 0x208
114 /** Clock ID for Quinary TDM EBIT */ 116 /** Clock ID for Quinary TDM EBIT */
115 #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT 117 #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT 0x209
116 /** Clock ID for Quinary TDM OSR */ 118 /** Clock ID for Quinary TDM OSR */
117 #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_OSR 119 #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_OSR 0x20A
118 120
119 /* Clock ID for MCLK1 */ 121 /* Clock ID for MCLK1 */
120 #define Q6AFE_LPASS_CLK_ID_MCLK_1 122 #define Q6AFE_LPASS_CLK_ID_MCLK_1 0x300
121 /* Clock ID for MCLK2 */ 123 /* Clock ID for MCLK2 */
122 #define Q6AFE_LPASS_CLK_ID_MCLK_2 124 #define Q6AFE_LPASS_CLK_ID_MCLK_2 0x301
123 /* Clock ID for MCLK3 */ 125 /* Clock ID for MCLK3 */
124 #define Q6AFE_LPASS_CLK_ID_MCLK_3 126 #define Q6AFE_LPASS_CLK_ID_MCLK_3 0x302
125 /* Clock ID for MCLK4 */ 127 /* Clock ID for MCLK4 */
126 #define Q6AFE_LPASS_CLK_ID_MCLK_4 128 #define Q6AFE_LPASS_CLK_ID_MCLK_4 0x304
127 /* Clock ID for Internal Digital Codec Core */ 129 /* Clock ID for Internal Digital Codec Core */
128 #define Q6AFE_LPASS_CLK_ID_INTERNAL_DIGITAL_CO 130 #define Q6AFE_LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 0x303
129 /* Clock ID for INT MCLK0 */ 131 /* Clock ID for INT MCLK0 */
130 #define Q6AFE_LPASS_CLK_ID_INT_MCLK_0 132 #define Q6AFE_LPASS_CLK_ID_INT_MCLK_0 0x305
131 /* Clock ID for INT MCLK1 */ 133 /* Clock ID for INT MCLK1 */
132 #define Q6AFE_LPASS_CLK_ID_INT_MCLK_1 134 #define Q6AFE_LPASS_CLK_ID_INT_MCLK_1 0x306
133 135
134 #define Q6AFE_LPASS_CLK_ID_WSA_CORE_MCLK <<
135 #define Q6AFE_LPASS_CLK_ID_WSA_CORE_NPL_MCLK <<
136 #define Q6AFE_LPASS_CLK_ID_TX_CORE_MCLK <<
137 #define Q6AFE_LPASS_CLK_ID_TX_CORE_NPL_MCLK <<
138 #define Q6AFE_LPASS_CLK_ID_RX_CORE_MCLK <<
139 #define Q6AFE_LPASS_CLK_ID_RX_CORE_NPL_MCLK <<
140 #define Q6AFE_LPASS_CLK_ID_VA_CORE_MCLK <<
141 #define Q6AFE_LPASS_CLK_ID_VA_CORE_2X_MCLK <<
142 <<
143 #define Q6AFE_LPASS_CORE_AVTIMER_BLOCK <<
144 #define Q6AFE_LPASS_CORE_HW_MACRO_BLOCK <<
145 #define Q6AFE_LPASS_CORE_HW_DCODEC_BLOCK <<
146 <<
147 /* Clock attribute for invalid use (reserved f 136 /* Clock attribute for invalid use (reserved for internal usage) */
148 #define Q6AFE_LPASS_CLK_ATTRIBUTE_INVALID 137 #define Q6AFE_LPASS_CLK_ATTRIBUTE_INVALID 0x0
149 /* Clock attribute for no couple case */ 138 /* Clock attribute for no couple case */
150 #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO 139 #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1
151 /* Clock attribute for dividend couple case */ 140 /* Clock attribute for dividend couple case */
152 #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVID 141 #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2
153 /* Clock attribute for divisor couple case */ 142 /* Clock attribute for divisor couple case */
154 #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVIS 143 #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3
155 /* Clock attribute for invert and no couple ca 144 /* Clock attribute for invert and no couple case */
156 #define Q6AFE_LPASS_CLK_ATTRIBUTE_INVERT_COUPL 145 #define Q6AFE_LPASS_CLK_ATTRIBUTE_INVERT_COUPLE_NO 0x4
157 146
158 #define Q6AFE_CMAP_INVALID 0xFFFF 147 #define Q6AFE_CMAP_INVALID 0xFFFF
159 148
160 struct q6afe_hdmi_cfg { 149 struct q6afe_hdmi_cfg {
161 u16 datatype; 150 u16 datatype;
162 u16 channel_allocatio 151 u16 channel_allocation;
163 u32 sample_rate; 152 u32 sample_rate;
164 u16 bit_width; 153 u16 bit_width;
165 }; 154 };
166 155
167 struct q6afe_slim_cfg { 156 struct q6afe_slim_cfg {
168 u32 sample_rate; 157 u32 sample_rate;
169 u16 bit_width; 158 u16 bit_width;
170 u16 data_format; 159 u16 data_format;
171 u16 num_channels; 160 u16 num_channels;
172 u8 ch_mapping[AFE_MAX_CHAN_COUNT] 161 u8 ch_mapping[AFE_MAX_CHAN_COUNT];
173 }; 162 };
174 163
175 struct q6afe_i2s_cfg { 164 struct q6afe_i2s_cfg {
176 u32 sample_rate; 165 u32 sample_rate;
177 u16 bit_width; 166 u16 bit_width;
178 u16 data_format; 167 u16 data_format;
179 u16 num_channels; 168 u16 num_channels;
180 u32 sd_line_mask; 169 u32 sd_line_mask;
181 int fmt; 170 int fmt;
182 }; 171 };
183 172
184 struct q6afe_tdm_cfg { 173 struct q6afe_tdm_cfg {
185 u16 num_channels; 174 u16 num_channels;
186 u32 sample_rate; 175 u32 sample_rate;
187 u16 bit_width; 176 u16 bit_width;
188 u16 data_format; 177 u16 data_format;
189 u16 sync_mode; 178 u16 sync_mode;
190 u16 sync_src; 179 u16 sync_src;
191 u16 nslots_per_frame; 180 u16 nslots_per_frame;
192 u16 slot_width; 181 u16 slot_width;
193 u16 slot_mask; 182 u16 slot_mask;
194 u32 data_align_type; 183 u32 data_align_type;
195 u16 ch_mapping[AFE_MAX_CHAN_COUNT] 184 u16 ch_mapping[AFE_MAX_CHAN_COUNT];
196 }; 185 };
197 186
198 struct q6afe_cdc_dma_cfg { <<
199 u16 sample_rate; <<
200 u16 bit_width; <<
201 u16 data_format; <<
202 u16 num_channels; <<
203 u16 active_channels_mask; <<
204 }; <<
205 <<
206 <<
207 struct q6afe_port_config { 187 struct q6afe_port_config {
208 struct q6afe_hdmi_cfg hdmi; 188 struct q6afe_hdmi_cfg hdmi;
209 struct q6afe_slim_cfg slim; 189 struct q6afe_slim_cfg slim;
210 struct q6afe_i2s_cfg i2s_cfg; 190 struct q6afe_i2s_cfg i2s_cfg;
211 struct q6afe_tdm_cfg tdm; 191 struct q6afe_tdm_cfg tdm;
212 struct q6afe_cdc_dma_cfg dma_cfg; <<
213 }; 192 };
214 193
215 struct q6afe_port; 194 struct q6afe_port;
216 195
217 struct q6afe_port *q6afe_port_get_from_id(stru 196 struct q6afe_port *q6afe_port_get_from_id(struct device *dev, int id);
218 int q6afe_port_start(struct q6afe_port *port); 197 int q6afe_port_start(struct q6afe_port *port);
219 int q6afe_port_stop(struct q6afe_port *port); 198 int q6afe_port_stop(struct q6afe_port *port);
220 void q6afe_port_put(struct q6afe_port *port); 199 void q6afe_port_put(struct q6afe_port *port);
221 int q6afe_get_port_id(int index); 200 int q6afe_get_port_id(int index);
>> 201 int q6afe_is_rx_port(int index);
222 void q6afe_hdmi_port_prepare(struct q6afe_port 202 void q6afe_hdmi_port_prepare(struct q6afe_port *port,
223 struct q6afe_hdmi_ 203 struct q6afe_hdmi_cfg *cfg);
224 void q6afe_slim_port_prepare(struct q6afe_port 204 void q6afe_slim_port_prepare(struct q6afe_port *port,
225 struct q6afe_slim_cf 205 struct q6afe_slim_cfg *cfg);
226 int q6afe_i2s_port_prepare(struct q6afe_port * 206 int q6afe_i2s_port_prepare(struct q6afe_port *port, struct q6afe_i2s_cfg *cfg);
227 void q6afe_tdm_port_prepare(struct q6afe_port 207 void q6afe_tdm_port_prepare(struct q6afe_port *port, struct q6afe_tdm_cfg *cfg);
228 void q6afe_cdc_dma_port_prepare(struct q6afe_p <<
229 struct q6afe_c <<
230 208
231 int q6afe_port_set_sysclk(struct q6afe_port *p 209 int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id,
232 int clk_src, int clk 210 int clk_src, int clk_root,
233 unsigned int freq, i 211 unsigned int freq, int dir);
234 int q6afe_set_lpass_clock(struct device *dev, <<
235 int clk_root, unsign <<
236 int q6afe_vote_lpass_core_hw(struct device *de <<
237 const char *clien <<
238 int q6afe_unvote_lpass_core_hw(struct device * <<
239 uint32_t client <<
240 #endif /* __Q6AFE_H__ */ 212 #endif /* __Q6AFE_H__ */
241 213
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