1 /* SPDX-License-Identifier: GPL-2.0-only */ 1
2 /*
3 * sound/soc/rockchip/rockchip_i2s.h
4 *
5 * ALSA SoC Audio Layer - Rockchip I2S Control
6 *
7 * Copyright (c) 2014 Rockchip Electronics Co.
8 * Author: Jianqun xu <jay.xu@rock-chips.com>
9 */
10
11 #ifndef _ROCKCHIP_IIS_H
12 #define _ROCKCHIP_IIS_H
13
14 /*
15 * TXCR
16 * transmit operation control register
17 */
18 #define I2S_TXCR_RCNT_SHIFT 17
19 #define I2S_TXCR_RCNT_MASK (0x3f << I2S_T
20 #define I2S_TXCR_CSR_SHIFT 15
21 #define I2S_TXCR_CSR(x) (x << I2S_TXCR
22 #define I2S_TXCR_CSR_MASK (3 << I2S_TXCR
23 #define I2S_TXCR_HWT BIT(14)
24 #define I2S_TXCR_SJM_SHIFT 12
25 #define I2S_TXCR_SJM_R (0 << I2S_TXCR
26 #define I2S_TXCR_SJM_L (1 << I2S_TXCR
27 #define I2S_TXCR_FBM_SHIFT 11
28 #define I2S_TXCR_FBM_MSB (0 << I2S_TXCR
29 #define I2S_TXCR_FBM_LSB (1 << I2S_TXCR
30 #define I2S_TXCR_IBM_SHIFT 9
31 #define I2S_TXCR_IBM_NORMAL (0 << I2S_TXCR
32 #define I2S_TXCR_IBM_LSJM (1 << I2S_TXCR
33 #define I2S_TXCR_IBM_RSJM (2 << I2S_TXCR
34 #define I2S_TXCR_IBM_MASK (3 << I2S_TXCR
35 #define I2S_TXCR_PBM_SHIFT 7
36 #define I2S_TXCR_PBM_MODE(x) (x << I2S_TXCR
37 #define I2S_TXCR_PBM_MASK (3 << I2S_TXCR
38 #define I2S_TXCR_TFS_SHIFT 5
39 #define I2S_TXCR_TFS_I2S (0 << I2S_TXCR
40 #define I2S_TXCR_TFS_PCM (1 << I2S_TXCR
41 #define I2S_TXCR_TFS_MASK (1 << I2S_TXCR
42 #define I2S_TXCR_VDW_SHIFT 0
43 #define I2S_TXCR_VDW(x) ((x - 1) << I2
44 #define I2S_TXCR_VDW_MASK (0x1f << I2S_T
45
46 /*
47 * RXCR
48 * receive operation control register
49 */
50 #define I2S_RXCR_CSR_SHIFT 15
51 #define I2S_RXCR_CSR(x) (x << I2S_RXCR
52 #define I2S_RXCR_CSR_MASK (3 << I2S_RXCR
53 #define I2S_RXCR_HWT BIT(14)
54 #define I2S_RXCR_SJM_SHIFT 12
55 #define I2S_RXCR_SJM_R (0 << I2S_RXCR
56 #define I2S_RXCR_SJM_L (1 << I2S_RXCR
57 #define I2S_RXCR_FBM_SHIFT 11
58 #define I2S_RXCR_FBM_MSB (0 << I2S_RXCR
59 #define I2S_RXCR_FBM_LSB (1 << I2S_RXCR
60 #define I2S_RXCR_IBM_SHIFT 9
61 #define I2S_RXCR_IBM_NORMAL (0 << I2S_RXCR
62 #define I2S_RXCR_IBM_LSJM (1 << I2S_RXCR
63 #define I2S_RXCR_IBM_RSJM (2 << I2S_RXCR
64 #define I2S_RXCR_IBM_MASK (3 << I2S_RXCR
65 #define I2S_RXCR_PBM_SHIFT 7
66 #define I2S_RXCR_PBM_MODE(x) (x << I2S_RXCR
67 #define I2S_RXCR_PBM_MASK (3 << I2S_RXCR
68 #define I2S_RXCR_TFS_SHIFT 5
69 #define I2S_RXCR_TFS_I2S (0 << I2S_RXCR
70 #define I2S_RXCR_TFS_PCM (1 << I2S_RXCR
71 #define I2S_RXCR_TFS_MASK (1 << I2S_RXCR
72 #define I2S_RXCR_VDW_SHIFT 0
73 #define I2S_RXCR_VDW(x) ((x - 1) << I2
74 #define I2S_RXCR_VDW_MASK (0x1f << I2S_R
75
76 /*
77 * CKR
78 * clock generation register
79 */
80 #define I2S_CKR_TRCM_SHIFT 28
81 #define I2S_CKR_TRCM(x) (x << I2S_CKR_TRCM_SHI
82 #define I2S_CKR_TRCM_TXRX (0 << I2S_CKR_
83 #define I2S_CKR_TRCM_TXONLY (1 << I2S_CKR_
84 #define I2S_CKR_TRCM_RXONLY (2 << I2S_CKR_
85 #define I2S_CKR_TRCM_MASK (3 << I2S_CKR_
86 #define I2S_CKR_MSS_SHIFT 27
87 #define I2S_CKR_MSS_MASTER (0 << I2S_CKR_
88 #define I2S_CKR_MSS_SLAVE (1 << I2S_CKR_
89 #define I2S_CKR_MSS_MASK (1 << I2S_CKR_
90 #define I2S_CKR_CKP_SHIFT 26
91 #define I2S_CKR_CKP_NORMAL (0 << I2S_CKR_
92 #define I2S_CKR_CKP_INVERTED (1 << I2S_CKR_
93 #define I2S_CKR_CKP_MASK (1 << I2S_CKR_
94 #define I2S_CKR_RLP_SHIFT 25
95 #define I2S_CKR_RLP_NORMAL (0 << I2S_CKR_
96 #define I2S_CKR_RLP_INVERTED (1 << I2S_CKR_
97 #define I2S_CKR_RLP_MASK (1 << I2S_CKR_
98 #define I2S_CKR_TLP_SHIFT 24
99 #define I2S_CKR_TLP_NORMAL (0 << I2S_CKR_
100 #define I2S_CKR_TLP_INVERTED (1 << I2S_CKR_
101 #define I2S_CKR_TLP_MASK (1 << I2S_CKR_
102 #define I2S_CKR_MDIV_SHIFT 16
103 #define I2S_CKR_MDIV(x) ((x - 1) << I2
104 #define I2S_CKR_MDIV_MASK (0xff << I2S_C
105 #define I2S_CKR_RSD_SHIFT 8
106 #define I2S_CKR_RSD(x) ((x - 1) << I2
107 #define I2S_CKR_RSD_MASK (0xff << I2S_C
108 #define I2S_CKR_TSD_SHIFT 0
109 #define I2S_CKR_TSD(x) ((x - 1) << I2
110 #define I2S_CKR_TSD_MASK (0xff << I2S_C
111
112 /*
113 * FIFOLR
114 * FIFO level register
115 */
116 #define I2S_FIFOLR_RFL_SHIFT 24
117 #define I2S_FIFOLR_RFL_MASK (0x3f << I2S_F
118 #define I2S_FIFOLR_TFL3_SHIFT 18
119 #define I2S_FIFOLR_TFL3_MASK (0x3f << I2S_F
120 #define I2S_FIFOLR_TFL2_SHIFT 12
121 #define I2S_FIFOLR_TFL2_MASK (0x3f << I2S_F
122 #define I2S_FIFOLR_TFL1_SHIFT 6
123 #define I2S_FIFOLR_TFL1_MASK (0x3f << I2S_F
124 #define I2S_FIFOLR_TFL0_SHIFT 0
125 #define I2S_FIFOLR_TFL0_MASK (0x3f << I2S_F
126
127 /*
128 * DMACR
129 * DMA control register
130 */
131 #define I2S_DMACR_RDE_SHIFT 24
132 #define I2S_DMACR_RDE_DISABLE (0 << I2S_DMAC
133 #define I2S_DMACR_RDE_ENABLE (1 << I2S_DMAC
134 #define I2S_DMACR_RDL_SHIFT 16
135 #define I2S_DMACR_RDL(x) ((x - 1) << I2
136 #define I2S_DMACR_RDL_MASK (0x1f << I2S_D
137 #define I2S_DMACR_TDE_SHIFT 8
138 #define I2S_DMACR_TDE_DISABLE (0 << I2S_DMAC
139 #define I2S_DMACR_TDE_ENABLE (1 << I2S_DMAC
140 #define I2S_DMACR_TDL_SHIFT 0
141 #define I2S_DMACR_TDL(x) ((x) << I2S_DM
142 #define I2S_DMACR_TDL_MASK (0x1f << I2S_D
143
144 /*
145 * INTCR
146 * interrupt control register
147 */
148 #define I2S_INTCR_RFT_SHIFT 20
149 #define I2S_INTCR_RFT(x) ((x - 1) << I2
150 #define I2S_INTCR_RXOIC BIT(18)
151 #define I2S_INTCR_RXOIE_SHIFT 17
152 #define I2S_INTCR_RXOIE_DISABLE (0 << I2S_INTC
153 #define I2S_INTCR_RXOIE_ENABLE (1 << I2S_INTC
154 #define I2S_INTCR_RXFIE_SHIFT 16
155 #define I2S_INTCR_RXFIE_DISABLE (0 << I2S_INTC
156 #define I2S_INTCR_RXFIE_ENABLE (1 << I2S_INTC
157 #define I2S_INTCR_TFT_SHIFT 4
158 #define I2S_INTCR_TFT(x) ((x - 1) << I2
159 #define I2S_INTCR_TFT_MASK (0x1f << I2S_I
160 #define I2S_INTCR_TXUIC BIT(2)
161 #define I2S_INTCR_TXUIE_SHIFT 1
162 #define I2S_INTCR_TXUIE_DISABLE (0 << I2S_INTC
163 #define I2S_INTCR_TXUIE_ENABLE (1 << I2S_INTC
164
165 /*
166 * INTSR
167 * interrupt status register
168 */
169 #define I2S_INTSR_TXEIE_SHIFT 0
170 #define I2S_INTSR_TXEIE_DISABLE (0 << I2S_INTS
171 #define I2S_INTSR_TXEIE_ENABLE (1 << I2S_INTS
172 #define I2S_INTSR_RXOI_SHIFT 17
173 #define I2S_INTSR_RXOI_INA (0 << I2S_INTS
174 #define I2S_INTSR_RXOI_ACT (1 << I2S_INTS
175 #define I2S_INTSR_RXFI_SHIFT 16
176 #define I2S_INTSR_RXFI_INA (0 << I2S_INTS
177 #define I2S_INTSR_RXFI_ACT (1 << I2S_INTS
178 #define I2S_INTSR_TXUI_SHIFT 1
179 #define I2S_INTSR_TXUI_INA (0 << I2S_INTS
180 #define I2S_INTSR_TXUI_ACT (1 << I2S_INTS
181 #define I2S_INTSR_TXEI_SHIFT 0
182 #define I2S_INTSR_TXEI_INA (0 << I2S_INTS
183 #define I2S_INTSR_TXEI_ACT (1 << I2S_INTS
184
185 /*
186 * XFER
187 * Transfer start register
188 */
189 #define I2S_XFER_RXS_SHIFT 1
190 #define I2S_XFER_RXS_STOP (0 << I2S_XFER
191 #define I2S_XFER_RXS_START (1 << I2S_XFER
192 #define I2S_XFER_TXS_SHIFT 0
193 #define I2S_XFER_TXS_STOP (0 << I2S_XFER
194 #define I2S_XFER_TXS_START (1 << I2S_XFER
195
196 /*
197 * CLR
198 * clear SCLK domain logic register
199 */
200 #define I2S_CLR_RXC BIT(1)
201 #define I2S_CLR_TXC BIT(0)
202
203 /*
204 * TXDR
205 * Transimt FIFO data register, write only.
206 */
207 #define I2S_TXDR_MASK (0xff)
208
209 /*
210 * RXDR
211 * Receive FIFO data register, write only.
212 */
213 #define I2S_RXDR_MASK (0xff)
214
215 /* Clock divider id */
216 enum {
217 ROCKCHIP_DIV_MCLK = 0,
218 ROCKCHIP_DIV_BCLK,
219 };
220
221 /* channel select */
222 #define I2S_CSR_SHIFT 15
223 #define I2S_CHN_2 (0 << I2S_CSR_SHIFT)
224 #define I2S_CHN_4 (1 << I2S_CSR_SHIFT)
225 #define I2S_CHN_6 (2 << I2S_CSR_SHIFT)
226 #define I2S_CHN_8 (3 << I2S_CSR_SHIFT)
227
228 /* I2S REGS */
229 #define I2S_TXCR (0x0000)
230 #define I2S_RXCR (0x0004)
231 #define I2S_CKR (0x0008)
232 #define I2S_FIFOLR (0x000c)
233 #define I2S_DMACR (0x0010)
234 #define I2S_INTCR (0x0014)
235 #define I2S_INTSR (0x0018)
236 #define I2S_XFER (0x001c)
237 #define I2S_CLR (0x0020)
238 #define I2S_TXDR (0x0024)
239 #define I2S_RXDR (0x0028)
240
241 /* io direction cfg register */
242 #define I2S_IO_DIRECTION_MASK (7)
243 #define I2S_IO_8CH_OUT_2CH_IN (0)
244 #define I2S_IO_6CH_OUT_4CH_IN (4)
245 #define I2S_IO_4CH_OUT_6CH_IN (6)
246 #define I2S_IO_2CH_OUT_8CH_IN (7)
247
248 #endif /* _ROCKCHIP_IIS_H */
249
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