1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 2 /* 3 * ALSA SoC Audio Layer - Rockchip SPDIF trans 3 * ALSA SoC Audio Layer - Rockchip SPDIF transceiver driver 4 * 4 * 5 * Copyright (c) 2015 Collabora Ltd. 5 * Copyright (c) 2015 Collabora Ltd. 6 * Author: Sjoerd Simons <sjoerd.simons@collab 6 * Author: Sjoerd Simons <sjoerd.simons@collabora.co.uk> 7 */ 7 */ 8 8 9 #ifndef _ROCKCHIP_SPDIF_H 9 #ifndef _ROCKCHIP_SPDIF_H 10 #define _ROCKCHIP_SPDIF_H 10 #define _ROCKCHIP_SPDIF_H 11 11 12 /* 12 /* 13 * CFGR 13 * CFGR 14 * transfer configuration register 14 * transfer configuration register 15 */ 15 */ 16 #define SPDIF_CFGR_CLK_DIV_SHIFT (16) 16 #define SPDIF_CFGR_CLK_DIV_SHIFT (16) 17 #define SPDIF_CFGR_CLK_DIV_MASK (0xff 17 #define SPDIF_CFGR_CLK_DIV_MASK (0xff << SPDIF_CFGR_CLK_DIV_SHIFT) 18 #define SPDIF_CFGR_CLK_DIV(x) (x << 18 #define SPDIF_CFGR_CLK_DIV(x) (x << SPDIF_CFGR_CLK_DIV_SHIFT) 19 19 20 #define SPDIF_CFGR_HALFWORD_SHIFT 2 20 #define SPDIF_CFGR_HALFWORD_SHIFT 2 21 #define SPDIF_CFGR_HALFWORD_DISABLE (0 << 21 #define SPDIF_CFGR_HALFWORD_DISABLE (0 << SPDIF_CFGR_HALFWORD_SHIFT) 22 #define SPDIF_CFGR_HALFWORD_ENABLE (1 << 22 #define SPDIF_CFGR_HALFWORD_ENABLE (1 << SPDIF_CFGR_HALFWORD_SHIFT) 23 23 24 #define SPDIF_CFGR_VDW_SHIFT 0 24 #define SPDIF_CFGR_VDW_SHIFT 0 25 #define SPDIF_CFGR_VDW(x) (x << SPDIF_CF 25 #define SPDIF_CFGR_VDW(x) (x << SPDIF_CFGR_VDW_SHIFT) 26 #define SDPIF_CFGR_VDW_MASK (0xf << SPDIF_ 26 #define SDPIF_CFGR_VDW_MASK (0xf << SPDIF_CFGR_VDW_SHIFT) 27 27 28 #define SPDIF_CFGR_VDW_16 SPDIF_CFGR_VDW 28 #define SPDIF_CFGR_VDW_16 SPDIF_CFGR_VDW(0x0) 29 #define SPDIF_CFGR_VDW_20 SPDIF_CFGR_VDW 29 #define SPDIF_CFGR_VDW_20 SPDIF_CFGR_VDW(0x1) 30 #define SPDIF_CFGR_VDW_24 SPDIF_CFGR_VDW 30 #define SPDIF_CFGR_VDW_24 SPDIF_CFGR_VDW(0x2) 31 31 32 /* 32 /* 33 * DMACR 33 * DMACR 34 * DMA control register 34 * DMA control register 35 */ 35 */ 36 #define SPDIF_DMACR_TDE_SHIFT 5 36 #define SPDIF_DMACR_TDE_SHIFT 5 37 #define SPDIF_DMACR_TDE_DISABLE (0 << SPDIF_DM 37 #define SPDIF_DMACR_TDE_DISABLE (0 << SPDIF_DMACR_TDE_SHIFT) 38 #define SPDIF_DMACR_TDE_ENABLE (1 << SPDIF_DM 38 #define SPDIF_DMACR_TDE_ENABLE (1 << SPDIF_DMACR_TDE_SHIFT) 39 39 40 #define SPDIF_DMACR_TDL_SHIFT 0 40 #define SPDIF_DMACR_TDL_SHIFT 0 41 #define SPDIF_DMACR_TDL(x) ((x) << SPDIF_ 41 #define SPDIF_DMACR_TDL(x) ((x) << SPDIF_DMACR_TDL_SHIFT) 42 #define SPDIF_DMACR_TDL_MASK (0x1f << SPDIF 42 #define SPDIF_DMACR_TDL_MASK (0x1f << SPDIF_DMACR_TDL_SHIFT) 43 43 44 /* 44 /* 45 * XFER 45 * XFER 46 * Transfer control register 46 * Transfer control register 47 */ 47 */ 48 #define SPDIF_XFER_TXS_SHIFT 0 48 #define SPDIF_XFER_TXS_SHIFT 0 49 #define SPDIF_XFER_TXS_STOP (0 << SPDIF_XF 49 #define SPDIF_XFER_TXS_STOP (0 << SPDIF_XFER_TXS_SHIFT) 50 #define SPDIF_XFER_TXS_START (1 << SPDIF_XF 50 #define SPDIF_XFER_TXS_START (1 << SPDIF_XFER_TXS_SHIFT) 51 51 52 #define SPDIF_CFGR (0x0000) 52 #define SPDIF_CFGR (0x0000) 53 #define SPDIF_SDBLR (0x0004) 53 #define SPDIF_SDBLR (0x0004) 54 #define SPDIF_DMACR (0x0008) 54 #define SPDIF_DMACR (0x0008) 55 #define SPDIF_INTCR (0x000c) 55 #define SPDIF_INTCR (0x000c) 56 #define SPDIF_INTSR (0x0010) 56 #define SPDIF_INTSR (0x0010) 57 #define SPDIF_XFER (0x0018) 57 #define SPDIF_XFER (0x0018) 58 #define SPDIF_SMPDR (0x0020) 58 #define SPDIF_SMPDR (0x0020) 59 59 60 #endif /* _ROCKCHIP_SPDIF_H */ 60 #endif /* _ROCKCHIP_SPDIF_H */ 61 61
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