1 // SPDX-License-Identifier: (GPL-2.0-only OR B 1
2 //
3 // Copyright (c) 2022 Mediatek Corporation. Al
4 //
5 // Author: Allen-KH Cheng <allen-kh.cheng@medi
6 // Tinghan Shen <tinghan.shen@mediatek
7 //
8 // Hardware interface for mt8186 DSP code load
9
10 #include <sound/sof.h>
11 #include "mt8186.h"
12 #include "../../ops.h"
13
14 void mt8186_sof_hifixdsp_boot_sequence(struct
15 {
16 /* set RUNSTALL to stop core */
17 snd_sof_dsp_update_bits(sdev, DSP_REG_
18 RUNSTALL, RUNS
19
20 /* enable mbox 0 & 1 IRQ */
21 snd_sof_dsp_update_bits(sdev, DSP_REG_
22 DSP_MBOX0_IRQ_
23 DSP_MBOX0_IRQ_
24
25 /* set core boot address */
26 snd_sof_dsp_write(sdev, DSP_SECREG_BAR
27 snd_sof_dsp_write(sdev, DSP_SECREG_BAR
28
29 /* assert core reset */
30 snd_sof_dsp_update_bits(sdev, DSP_REG_
31 SW_RSTN_C0 | S
32 SW_RSTN_C0 | S
33
34 /* hardware requirement */
35 udelay(1);
36
37 /* release core reset */
38 snd_sof_dsp_update_bits(sdev, DSP_REG_
39 SW_RSTN_C0 | S
40 0);
41
42 /* clear RUNSTALL (bit31) to start cor
43 snd_sof_dsp_update_bits(sdev, DSP_REG_
44 RUNSTALL, 0);
45 }
46
47 void mt8186_sof_hifixdsp_shutdown(struct snd_s
48 {
49 /* set RUNSTALL to stop core */
50 snd_sof_dsp_update_bits(sdev, DSP_REG_
51 RUNSTALL, RUNS
52
53 /* assert core reset */
54 snd_sof_dsp_update_bits(sdev, DSP_REG_
55 SW_RSTN_C0 | S
56 SW_RSTN_C0 | S
57 }
58
59
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